JP2006190376A - Nonvolatile semiconductor storage apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage apparatus in which it is suppressed that a resistance value of a valuable resistance element included in a memory cell is changed by a voltage pulse applied to the memory cell and defective read-out is caused at the time of read-out of a memory cell array. <P>SOLUTION: The apparatus is provided with a memory cell selecting circuit 17 selecting a memory cell out of a memory cell array 15, a read-out voltage applying circuit 22a applying read-out voltage to the variable resistance element of a selected memory cell, and a read-out circuit 23a detecting magnitude of a read-out current flowing in accordance with a resistance value of the variable resistance element of the memory cell to be read in the selected memory cell and performing read-out operation of information stored in the memory cell to be read out, the read-out voltage applying circuit 22a is constituted so that polarity of applied read-out voltage can be changed, the read-out circuit 23a performs read-out operation in accordance with a current direction of the read-out current in accordance with the polarity of read-out voltage applied to the variable resistance element to be read out. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device having a memory cell array in which a plurality of memory cells each including a variable resistance element that stores information according to a change in electrical resistance are arranged in a row direction and a column direction. The present invention relates to a technique for preventing and suppressing deterioration of stored data accompanying a cell array read operation.

  In recent years, next-generation non-volatile random access memory (NVRAM) capable of high-speed operation, which replaces flash memory, includes FeRAM (Ferroelectric RAM), MRAM (Magnetic RAM), OUM (Ovonic Unified Memory), etc. A device structure has been proposed, and intense development competition is taking place from the viewpoint of high performance, high reliability, low cost, and process consistency.

In addition to these existing technologies, the method of reversibly changing the electrical resistance by applying a voltage pulse to a perovskite material known for its giant magnetoresistive effect by Shanqing Liu, Alex Ignatiev, etc. of the University of Houston, USA is as follows. It is disclosed in Patent Literature 1 and Non-Patent Literature 1. This is an extremely epoch-making phenomenon in which a perovskite material known for its giant magnetoresistive effect is used, and a resistance change of several orders of magnitude appears even at room temperature without applying a magnetic field. Unlike a MRAM, a resistive non-volatile memory RRAM (Resistance Random Access Memory) using a variable resistance element utilizing this phenomenon does not require a magnetic field at all, so it consumes very little power and is easy to miniaturize and highly integrate. Since the dynamic range of resistance change is much wider than that of MRAM, it has an excellent feature that multi-value storage is possible. The basic structure of an actual device is very simple, and is a structure in which a lower electrode material, a perovskite metal oxide, and an upper electrode material are stacked in this order in the direction perpendicular to the substrate. In the element structure exemplified in Patent Document 1, the lower electrode material is yttrium / barium / copper oxide YBa ₂ Cu ₃ O ₇ (YBCO) deposited on a lanthanum / aluminum oxide LaAlO ₃ (LAO) single crystal substrate. ) Film, the perovskite type metal oxide is a crystalline praseodymium / calcium / manganese oxide Pr _1-x Ca _x MnO ₃ (PCMO) film, and the upper electrode material is an Ag film deposited by sputtering. It has been reported that the operation of this memory element can reversibly change the resistance by applying a positive or negative voltage pulse applied between the upper and lower electrodes to 51 volts. It means that a novel nonvolatile semiconductor memory device is possible by reading the resistance value in this reversible resistance change operation (hereinafter referred to as “switching operation” as appropriate).

  A memory cell array is formed by arranging a plurality of memory cells in the matrix in the row direction and the column direction, each having a variable resistance element composed of the PCMO film or the like and storing information by changing the electric resistance of the variable resistance element. A circuit for controlling data writing, erasing, and reading with respect to each memory cell of the memory cell array can be arranged around the memory cell array to constitute a nonvolatile semiconductor memory device.

  As a configuration of the memory cell including the variable resistance element, when each memory cell is configured by a series circuit in which a variable resistance element and a selection transistor are connected in series, or when configured by only a variable resistance element, etc. There is. A memory cell having the former configuration is referred to as a 1T / 1R type memory cell, and a memory cell having the latter configuration is referred to as a 1R type memory cell.

  A configuration example in which a memory cell array is formed by 1T / 1R type memory cells to configure a large-capacity nonvolatile semiconductor memory device will be described with reference to the drawings.

  FIG. 1 schematically shows a configuration example of a memory cell array of 1T / 1R type memory cells. A similar memory cell array configuration is proposed in the patent application (Japanese Patent Application No. 2003-168223) by the present applicant. Yes. In this memory cell array configuration, the memory cell array 1 includes m × n memory cells 2 at intersections of m bit lines (BL1 to BLm) extending in the column direction and n word lines (WL1 to WLn) extending in the row direction. The arrangement is arranged. In addition, n source lines (SL1 to SLn) are arranged in parallel with the word lines. In each memory cell, the upper electrode of the variable resistance element 3 and the drain electrode of the selection transistor 4 are connected, the lower electrode of the variable resistance element 3 is connected to the bit line, the gate electrode of the selection transistor 4 is connected to the word line, The source electrode of the selection transistor 4 is connected to the source line. The lower electrode of the variable resistance element 3 and the drain electrode of the selection transistor 4 are connected, the upper electrode of the variable resistance element 3 is connected to the bit line, and the relationship between the upper electrode and the lower electrode of the variable resistance element 3 is inverted. It doesn't matter.

  Thus, by configuring the memory cell 2 with the series circuit of the selection transistor 4 and the variable resistance element 3, the selection transistor 4 of the memory cell 2 selected by the potential of the word line is turned on, and further, the bit line A write or erase voltage is selectively applied only to the variable resistance element 3 of the memory cell 2 selected by the potential, so that the resistance value of the variable resistance element 3 can be changed.

  FIG. 2 shows a configuration example of a nonvolatile semiconductor memory device including the memory cell array 1 of 1T / 1R type memory cells. A specific memory cell in the memory cell array 1 corresponding to the address input input from the address line 8 to the control circuit 10 is selected by the bit line decoder 5, the source line decoder 6, and the word line decoder 7. Write, erase, and read operations are executed, and data is stored in and read from the selected memory cell. Data input / output to / from an external device (not shown) is performed via the data line 9.

  The word line decoder 7 selects a word line of the memory cell array 1 corresponding to the signal input to the address line 8, and the bit line decoder 5 selects the bit of the memory cell array 1 corresponding to the address signal input to the address line 8. Further, the source line decoder 6 selects the source line of the memory cell array 1 corresponding to the address signal input to the address line 8. The control circuit 10 performs control in each operation of writing, erasing, and reading of the memory cell array 1. Based on the address signal input from the address line 8, the data input input from the data line 9 (at the time of writing), and the control input signal input from the control signal line 11, the control circuit 10 The read, write, and erase operations of the line decoder 5, the source line decoder 6, the voltage switch circuit 12, and the memory cell array 1 are controlled. In the example shown in FIG. 2, the control circuit 10 has functions as a general address buffer circuit, data input / output buffer circuit, and control input buffer circuit (not shown).

  The voltage switch circuit 12 switches each word line, bit line, and source line voltage required for reading, writing, and erasing the memory cell array 1 according to the operation mode, and supplies the voltage to the memory cell array 1. Here, Vcc is a power supply voltage of the nonvolatile semiconductor memory device, Vss is a ground voltage, Vwrt and Vrst are voltages for writing and erasing, and Vr is a reading voltage. Data is read from the memory cell array 1 via the bit line decoder 5 and the read circuit 13. The read circuit 13 determines the data state, transfers the result to the control circuit 10, and outputs it to the data line 9.

  Next, a configuration example in which a memory cell array is formed by 1R type memory cells to configure a large-capacity nonvolatile semiconductor memory device will be described with reference to the drawings. As shown in FIG. 3, the memory cell 14 is not composed of a series circuit of selection transistors and variable resistance elements, but is composed of a single variable resistance element 3, and the 1R type memory cells 14 are arranged in a matrix. The memory cell array 15 is configured, for example, the same as that disclosed in Patent Document 2 below. Specifically, in the memory cell array 15, m × n memory cells 14 are arranged at intersections of m bit lines (BL1 to BLm) extending in the column direction and n word lines (WL1 to WLn) extending in the row direction. It has become the composition. In each memory cell 14, the upper electrode of the variable resistance element 3 is connected to the word line, and the lower electrode of the variable resistance element 3 is connected to the bit line. Note that the lower electrode of the variable resistance element 3 is connected to the word line, and the upper electrode of the variable resistance element 3 is connected to the bit line, so that the relationship between the upper electrode and the lower electrode of the variable resistance element 3 may be reversed. .

  In the memory cell array 1 (see FIGS. 1 and 2) configured by 1T / 1R type memory cells 2, when selecting a memory cell to be read, written, or erased, a selected word line and a selected bit line are selected. Read only to the variable resistance element included in the selected memory cell by applying a predetermined voltage and turning on only the selection transistor included in the selected memory cell connected to both the selected word line and the selected bit line. Current can flow. On the other hand, in the memory cell array 15 composed of 1R type memory cells 14, when selecting a memory cell from which data is to be read, the selected memory cell connected to the word line and bit line common to the read target memory cell is also used. Since the same bias voltage is applied, a read current flows also to other than the read target memory cell. A read current flowing through a selected memory cell selected in units of rows or columns is detected as a read current of a memory cell to be read by column selection or row selection. In the memory cell array 15 composed of the 1R type memory cells 14, a read current flows in addition to the read target memory cell. However, the memory cell structure is simple, and the memory cell area and the memory cell array area are reduced. There is.

  3 and 4 show a conventional example of a voltage application procedure to each part at the time of data read operation in the memory cell array 15 constituted by 1R type memory cells 14. When reading the data of the selected memory cell, the selected word line connected to the selected memory cell is maintained at the ground potential Vss, and the other unselected word lines and all the bit lines are all in the read period Tread. A read voltage Vr is applied. During the read period Tread, a voltage difference of the read voltage Vr occurs between the selected word line and all the bit lines, so that the electric resistance, that is, the read current corresponding to the storage state flows through the variable resistance element of the selected memory cell. The data stored in the selected memory cell can be read out. In this case, since a read current according to the storage state of the selected memory cell connected to the selected word line flows through each bit line, on the bit line side, by selectively reading the read current flowing through the predetermined selected bit line, Data of a specific selected memory cell can be read out. Here, the relationship between the bit line and the word line may be exchanged so that the read current flowing through each word line is selectively read on the word line side.

  FIG. 5 shows a configuration example of a nonvolatile semiconductor memory device including the memory cell array 15 of the 1R type memory cell 14. A specific memory cell in the memory cell array 15 corresponding to the address input input from the address line 18 to the control circuit 20 is selected by the bit line decoder 16 and the word line decoder 17 to write, erase and read data. Each operation is executed, and data is stored in and read from the selected memory cell. Data is input / output to / from an external device (not shown) through the data line 19.

  The word line decoder 17 selects the word line of the memory cell array 15 corresponding to the signal input to the address line 18, and the bit line decoder 16 selects the bit of the memory cell array 15 corresponding to the address signal input to the address line 18. Select a line. The control circuit 20 performs control in each operation of writing, erasing, and reading of the memory cell array 15. Based on the address signal input from the address line 18, the data input input from the data line 19 (at the time of writing), and the control input signal input from the control signal line 21, the control circuit 20 includes the word line decoder 17, bit The read, write, and erase operations of the line decoder 16, the voltage switch circuit 22, and the memory cell array 15 are controlled. In the example shown in FIG. 5, the control circuit 20 has functions as a general address buffer circuit, data input / output buffer circuit, and control input buffer circuit (not shown).

  The voltage switch circuit 22 switches each voltage of the word line, bit line, and source line necessary for reading, writing, and erasing of the memory cell array 15 according to the operation mode, and supplies it to the memory cell array 15. Here, Vcc is a power supply voltage of the nonvolatile semiconductor memory device, Vss is a ground voltage, Vwrt and Vrst are voltages for writing and erasing, and Vr is a reading voltage. Data is read from the memory cell array 15 via the bit line decoder 16 and the read circuit 23. The read circuit 23 determines the data state, transfers the result to the control circuit 20, and outputs it to the data line 19.

  As a variable resistance element constituting the 1T / 1R type memory cell and the 1R type memory cell, a phase change memory element that changes a resistance value by a change in state of crystal / amorphization of a chalcogenide compound, a resistance change due to a tunnel magnetoresistance effect is used There are an MRAM element, a memory element of a polymer ferroelectric RAM (PFRAM) in which a resistance element is formed of a conductive polymer, an RRAM element that causes a resistance change by application of an electric pulse, and the like.

US Pat. No. 6,204,139 JP 2002-8369 A Liu, S .; Q. In addition, “Electrical-pulse-induced reversible resistance change effect in magnetosensitive films”, Applied Physics Letter, Vol. 76, pp. 2749-2751, 2000

  When data is read from a memory cell having a variable resistance element, a bias voltage is applied to the variable resistance element to cause a read current to flow, and the resistance value of the variable resistance element is determined based on the magnitude of the current to read the data. Accordingly, a predetermined bias voltage is applied to the variable resistance element in accordance with the read operation regardless of the configuration of the memory cell.

When the PCMO film (Pr _1-x Ca _x MnO ₃ ), which is a kind of perovskite-type metal oxide, is used as a variable resistance element, the inventors of the present application have an absolute value equal to or lower than a write voltage. It has been found that when the read voltage is applied as a continuous pulse of the same polarity, the resistance value of the variable resistance element changes. As shown in FIG. 6, when a positive voltage pulse (pulse width 100 ns) is continuously applied to the upper electrode of the variable resistance element, the resistance value of the variable resistance element whose initial state is in the high resistance state is It decreased as the number of times increased. When the negative voltage pulse (pulse width 100 ns) was continuously applied, the resistance value increased as the number of pulse applications increased. In the negative voltage pulse, the resistance value tends to increase as the number of pulse application increases. However, the difference from the low resistance state becomes more noticeable when the high resistance state becomes a higher resistance state. The resistance change does not cause a problem in characteristics. A decrease in resistance value when a positive voltage pulse is applied becomes a problem.

  Here, the positive voltage pulse refers to a state in which a reference ground voltage is applied to the lower electrode and a positive voltage pulse (for example, 1 V) is applied to the upper electrode. Further, the negative voltage pulse refers to a state in which a reference ground voltage is applied to the upper electrode and a positive voltage pulse (for example, 1 V) is applied to the lower electrode. The resistance value measurement conditions shown in FIG. 6 were calculated from the current value when a reference ground voltage was applied to the lower electrode and 0.5 V was applied to the upper electrode. In addition, the horizontal axis of FIG. 6 indicates the logarithm of the relative application number of voltage pulses.

  FIG. 7 shows the result of examining the resistance change when a positive voltage pulse is applied to the upper electrode of the variable resistance element that was in the low resistance state in the initial state. The resistance measurement conditions shown in FIG. 7 were calculated from the current value when a reference ground voltage was applied to the lower electrode and 0.5 V was applied to the upper electrode. In addition, the horizontal axis of FIG. 7 indicates the logarithmic display of the relative number of voltage pulses applied. From FIG. 7, it can be seen that the resistance change is smaller than that in the high resistance state in the initial state. In particular, the voltage applied to the variable resistance element at the time of reading is generally preferably about 1V, but the resistance change is small with a voltage pulse of 1V or -1V. In addition, when the voltage pulse is positive, when the voltage amplitude is 2 V, the resistance value tends to decrease as the number of pulse application increases. However, the low resistance state further becomes the low resistance state. This difference in resistance is not a problem in terms of characteristics.

  In summary, from the above experimental results, the read disturb phenomenon in which the data stored in the memory cell, that is, the resistance value changes according to the number of voltage pulses applied in accordance with the read operation, becomes clear. It was. In particular, when a read operation is performed by applying a positive voltage pulse to a variable resistance element whose resistance state during reading is a high resistance state, the resistance value of the variable resistance element decreases, and the resistance state of the variable resistance element is low. The resistance difference between the resistance states is reduced, and the read margin is reduced. Furthermore, repeated read operations on the same memory cell may cause the stored data to be completely lost and become impossible to read as a worst case.

  Further, in a memory cell array composed of 1R type memory cells, a read voltage is applied to a selected memory cell that is not to be read and shares a word line or bit line with the read target memory cell. It became clear that the phenomenon appears more prominently.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and an object of the present invention is to read errors due to a change in resistance value of a variable resistance element included in a memory cell due to a voltage pulse applied to the memory cell during reading from the memory cell array. It is an object of the present invention to provide a non-volatile semiconductor memory device with a large read margin, which is prevented from falling into the process.

  In order to achieve the above object, a non-volatile semiconductor memory device according to the present invention includes a memory cell array in which a plurality of memory cells each including a variable resistance element for storing information according to a change in electrical resistance are arranged in a row direction and a column direction. A memory cell selection circuit that selects the memory cells from the memory cell array in row units, column units, or memory cell units, and selected by the memory cell selection circuit A read voltage application circuit that applies a read voltage to the variable resistance element of the selected memory cell, and a magnitude of a read current that flows in accordance with the resistance value of the variable resistance element with respect to the memory cell to be read of the selected memory cell And a read circuit for performing a read operation of information stored in the read target memory cell. The read voltage application circuit is configured to change the polarity of the read voltage to be applied in order to select the direction of current flowing through the variable resistance element of the selected memory cell. The read operation is performed in accordance with the current direction of the read current according to the polarity of the read voltage applied to the variable resistance element of the memory cell to be read.

  According to the nonvolatile semiconductor memory device having the above characteristics, the read voltage application circuit selectively executes both the read voltage application to the selected memory cell and the read voltage application in which the read current flows in the opposite direction. Since the read voltage is applied, a read voltage that causes a reverse read current to flow during another read operation is applied to the variable resistance element of the selected memory cell whose resistance value may have increased or decreased. As a result, the resistance can be changed in a direction to cancel the resistance change due to the application of the read voltage, and the cumulative resistance change from the initial resistance state can be suppressed even if the number of times of applying the read voltage is increased. In addition, it suppresses the decrease in read margin, and further greatly improves the number of reads until the stored data is lost or cannot be read. Rukoto is possible.

  For example, according to the experimental results obtained by measuring the resistance change accompanying the voltage pulse application to the variable resistance element shown in FIG. 6, when the initial state is the high resistance state, only the positive voltage pulse (voltage amplitude 2 V, pulse width 100 ns) is obtained. When the positive and negative voltage pulses (voltage amplitude 2 V, pulse width 100 ns) are alternately applied, the positive and negative voltage pulses (the former is clearly It can be confirmed that the resistance change when the read voltage is applied and the latter is equivalent to the dummy read voltage is significantly suppressed, and the above-described effect is supported.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a nonvolatile semiconductor memory device according to the present invention (hereinafter referred to as “the present device” as appropriate) will be described below with reference to the drawings.

  In the present embodiment, the memory cells constituting the memory cell array of the nonvolatile semiconductor memory device are formed to include a variable resistance element that stores information by a change in electrical resistance. As an example of the variable resistance element, a PCMO film A description will be given assuming an RRAM element having a three-layer structure in which Pt electrodes are arranged on the upper and lower sides. Note that the present invention can be applied to any variable resistance element as long as the variable resistance element is an element in which a resistance change is caused by voltage application (or current application).

The inventors of the present application form a variable resistance element in which a PCMO film (Pr _1-x Ca _x MnO ₃ ), which is a kind of perovskite-type metal oxide, and a Pt electrode on the upper and lower sides thereof are formed. In addition, it has been found that when voltage pulses of the same polarity that cause current to flow in a certain direction are continuously applied, the resistance of the variable resistance element changes as the number of pulse applications increases. The PCMO film of the variable resistance element was formed at 500 ° C. using a sputtering method.

  As shown in FIG. 6, when a positive pulse (pulse width 100 ns) is continuously applied to the upper electrode of the variable resistance element, the variable resistance element in the initial state, that is, in the high resistance state when no pulse is applied. The resistance value decreased as the number of pulse applications increased. The initial high resistance state was formed by applying a write voltage pulse having a write voltage Vpp = 4 V and a pulse width of 3 μs to the lower electrode.

  When a negative pulse (pulse width 100 ns) having the same polarity as the write voltage pulse was continuously applied, the resistance value increased as the number of pulse applications increased. In addition, the greater the voltage amplitude of the applied voltage pulse, that is, the greater the current flowing through the variable resistance element, the greater the degree of resistance change, and the resistance increases or the resistance increases. It has been clarified that whether to change in a decreasing direction depends on the direction in which the current flows, that is, the polarity of the applied voltage pulse.

  The inventors of the present application pay attention to the fact that the direction of the resistance change of the variable resistive element depends on the direction of the current flowing through the variable resistive element due to the application of the voltage pulse. The inventors have devised a method for canceling resistance change by applying a voltage pulse for flowing current, and have tried to apply voltage pulses for flowing current in different directions alternately and continuously to the variable resistance element. FIG. 6 shows the state of resistance change in the case of applying a combination of reverse polarity pulses that flow current in the reverse direction when applying a continuous voltage pulse to a variable resistance element whose initial state is a high resistance state. This is a typical example. It has been verified that the resistance change is smaller when voltage pulses having different polarities are applied alternately in combination as compared with the case where voltage pulses having the same polarity are continuously applied. Therefore, when reading stored data in a memory cell including a variable resistance element, in addition to a read current that normally flows only in one direction, a current that flows in the opposite direction is also used as a read current. It became clear that the resistance change due to the pulse application can be suppressed, and that the number of times of reading can be increased.

  Next, the device of the present invention capable of suppressing the resistance change of the variable resistance element accompanying the read operation will be described based on the above new knowledge about the variable resistance element. First, the device of the present invention in the case where the memory cell is a 1R type memory cell composed of only variable resistance elements will be described.

<First Embodiment>
FIG. 8 shows an example of the configuration of the device of the present invention. In FIG. 8, portions common to the conventional nonvolatile semiconductor memory device are described with common reference numerals. As shown in FIG. 8, the device of the present invention has a bit line decoder 16, a word line decoder 17, a voltage switch circuit 22a, a read circuit around a memory cell array 15 in which 1R type memory cells (not shown) are arranged in a matrix. A circuit 23a and a control circuit 20a are provided. Basically, the configuration is the same as that of the conventional nonvolatile semiconductor memory device having the memory cell array of 1R type memory cells shown in FIG. The difference from the conventional nonvolatile semiconductor memory device of FIG. 5 is that a read number counter 30 comprising a 1-bit counter for determining whether the number of read times for the entire memory cell array is an odd number or an even number is added. The exchange is performed, and the read voltage applied to the memory cell array supplied from the voltage switch is changed depending on the state of the read number counter. This 1-bit counter has an initial value of 0, and is incremented by 1 each time reading to the memory cell array is completed. Since there is only 1 bit, 0 and 1 are inverted each time reading is completed. That is, it is possible to hold whether the cumulative read count is an even number or an odd number. This value will be called C. It is a feature of the device of the present invention that the read voltage applied to the memory cell array is changed by this value C.

  The configuration of memory cell array 15 is the same as that of memory cell array 15 of the conventional nonvolatile semiconductor memory device shown in FIG. Specifically, the memory cell array 15 includes m bit lines (corresponding to column selection lines) extending in the column direction (BL1 to BLm) and n word lines (corresponding to row selection lines) extending in the row direction (WL1 to WL1). WLn) has a configuration in which m × n memory cells 2 are arranged at intersections. In each memory cell 14, the upper electrode of the variable resistance element 3 is connected to the word line, and the lower electrode of the variable resistance element 3 is connected to the bit line. Note that the lower electrode of the variable resistance element 3 is connected to the word line, and the upper electrode of the variable resistance element 3 is connected to the bit line, so that the relationship between the upper electrode and the lower electrode of the variable resistance element 3 may be reversed. .

  The bit line decoder 16 and the word line decoder 17 select a memory cell to be read from the memory cell array 15 corresponding to the address input input from the address line 18 to the control circuit 20a. The word line decoder 17 selects the word line of the memory cell array 15 corresponding to the signal input to the address line 18, and the bit line decoder 16 selects the bit of the memory cell array 15 corresponding to the address signal input to the address line 18. Select a line. In the present embodiment, the word line decoder 17 functions as a memory cell selection circuit that selects memory cells from the memory cell array 15 in units of rows. The control circuit 20a performs control in each of write, erase, and read operations of the memory cell array 15. Based on the address signal input from the address line 18, the data input input from the data line 19 (during writing), and the control input signal input from the control signal line 21, the control circuit 20 a The read, write, and erase operations of the line decoder 16, voltage switch circuit 22a, and memory cell array 15 are controlled. In the example shown in FIG. 8, the control circuit 20a has functions as a general address buffer circuit, data input / output buffer circuit, and control input buffer circuit (not shown).

  The voltage switch circuit 22 a switches each voltage of the word line, the bit line, and the source line necessary for reading, writing, and erasing of the memory cell array 15 according to the operation mode, and supplies it to the memory cell array 15. In particular, in the read mode, the voltage switch circuit 22a functions as a read voltage application circuit that applies a predetermined read voltage to the bit lines and word lines connected to one row of selected memory cells selected by the word line decoder 17. In the present embodiment, a predetermined read voltage is applied with a memory cell connected to one selected word line selected by the word line decoder 17 as a selected memory cell. In the figure, Vcc is a power supply voltage of the device of the present invention, Vss is a ground voltage, Vwrt is a write voltage, Vrst is an erase voltage, and Vb is a bias voltage of the memory cell array. Vb + Vr and Vb−Vr are used at the time of reading, and Vb−Vr or Vb + Vr is applied to a selected word line in a memory cell array biased to Vb (Vb is applied to all word lines and bit lines). Read out. At this time, a voltage having an absolute value Vr is applied as a read voltage to the variable resistance element of the selected memory cell.

  The read circuit 23a converts the read current flowing through the selected bit line selected by the bit line decoder 16 among the read current flowing through the bit line connected to the selected memory cell, and converts the voltage in the selected memory cell in one row. The state of the storage data of the memory cell to be read connected to the selected bit line is determined, and the result is transferred to the control circuit 20a and output to the data line 19.

  In this embodiment, when Vb−Vr is applied to the selected word line and when Vb + Vr is applied, the current direction of the read current flowing through the selected memory cell is reversed. Therefore, even if the storage data of the memory cell to be read is the same, if the current direction of the read current is different, the voltage value obtained by voltage conversion of the read current is different. Therefore, in this embodiment, it is necessary to change the determination method of the voltage value obtained by voltage conversion according to the polarity of the read voltage. For example, when differentially amplifying the voltage value after voltage conversion with the reference voltage, use an appropriate reference voltage according to the polarity of the read voltage, and set the logic level of the differential amplification output according to the polarity of the read voltage. It is necessary to perform processing such as inversion.

  Next, a specific operation during the read operation will be described with reference to the drawing in the case of three word lines and three bit lines shown in FIG.

  In the present invention, the main feature is that two types of read currents in which the directions of the read currents flowing in the memory cells at the time of reading are opposite to each other are selectively used. Reading that flows into the memory cell is referred to as “+ reading”, and reading that causes the reading current to flow from the memory cell to the bit line is referred to as “−reading”, and the same applies in the following description.

  Whether to perform “+ read” or “−read” is determined by the count value C of the number-of-reads counter 30. It is assumed that “+ read” is performed when C = 0, and “−read” is performed when C = 1. Of course, the reverse setting may be used, but the description will be made on the assumption of the above correspondence. For example, assume that the word line WL2 is selected at the time of the first reading. At this time, since the memory cell array has not been read in the past, the count value C of the read count counter 30 is 0, so “+ read” is performed on the memory cells connected to the word line WL2. As shown in FIG. 9A, only the word line WL2 is biased to Vb−Vr, the other word lines and bit lines are biased to Vb, and a read current flows from the bit line to the memory cell. At the stage where this “+ reading” is completed, 1 is added to the read count counter 30, and C = 1. If WL2 is selected again in the next reading, since C = 1 at this time, “−reading” is performed. As shown in FIG. 9B, only the word line WL2 is biased to Vb + Vr, the other word lines and bit lines are biased to Vb, and a read current flows from the memory cell to the bit line. Therefore, both “+ read” and “−read” are performed on the same memory cells R21 to R23 connected to the word line WL2, and currents in opposite directions flow to the same memory cell, respectively. Is reduced. FIG. 10 shows a change in the count value C of the read number counter 30, the polarity of the read voltage, and the bias voltage applied to each word line and each bit line when several readings are performed. As can be seen from FIG. 10, every time reading is performed on the memory cell array, the count value C of the read counter 30 is rewritten, and the polarity of the read voltage is changed accordingly. In the example shown in FIG. 10, “+ read” and “−read” are performed the same number of times for the memory cells respectively connected to the word lines WL1 to WL3 in eight readings in the entire memory cell array. Disturbance is reduced.

  However, as shown in FIG. 10, whether or not a memory cell is accessed has to be relied upon by chance in the case of a random access memory. For example, the worst case as shown in FIG. In the example shown in FIG. 11, only “+ read” is performed on the memory cells connected to the word line W2, and only “−read” is performed on the memory cells connected to the word line W3. If such reading continues thereafter, the read disturb is not reduced at all.

  However, as shown in FIG. 11, whether or not a memory cell is accessed may be inevitably caused depending on the use of the device of the present invention, but is basically a coincidence. Therefore, it is considered that, by performing many readings, both “+ reading” and “−reading” are performed on each memory cell, and the read disturb can be reduced to some extent.

Second Embodiment
In the first embodiment, the read disturb reduction effect depends on the averaging by the multiple read-out accidentally, and depending on the application, there may be no read disturb reduction effect at all. A second embodiment of the device of the present invention that improves this point will now be described.

  As shown in FIG. 12, the configuration of the device of the present invention according to the second embodiment is basically the same as that of the first embodiment, but the read number counter 30 in the first embodiment is replaced with a binary random number. The configuration is replaced with the generation circuit 31. The binary random number generation circuit 31 randomly generates one of two values “0” or “1” and holds the value as a binary random value Q. The initial value of the binary random value Q may be either 0 or 1. Each time reading to the memory cell array 15 is completed once, a value of 0 or 1 is newly generated at random, and the binary random number value Q is rewritten to this value. The binary random value Q here is used in the same manner as the count value C of the read number counter 30 in the first embodiment. That is, “+ read” is performed when Q = 0, and “−read” is performed when Q = 1. Since the value of Q is randomly set to “0” or “1” at every reading, the direction of the reading current is randomly determined. In FIG. 13, as in the first embodiment, the binary random number generation circuit 31 performs binary disturbance when the memory cell array (see FIG. 9) having three word lines and three bit lines is read up to 16 times. The numerical value Q, the polarity of the read voltage, and the bias voltage applied to each word line and each bit line are shown. Note that the selected word line (word line connected to the selected memory cell) at each read count in FIG. 13 is appropriately selected. As can be seen from FIG. 13, since the binary random value Q is rewritten at random every time the memory cell array is read, “+ read” and “+” are read from the memory cells connected to the word lines WL1 to WL3. -The number of "reads" is approximately balanced. Here, for the sake of simplicity, description has been made up to reading up to 16 times, but the same is true even when the number of readings increases. As the number of readings increases, the degree of balance between the numbers of “+ reading” and “−reading” increases. Eventually, reading is performed so that “+ reading” and “−reading” are approximately the same number of times, and therefore, read currents flow in both forward and reverse directions in a balanced manner, so that read disturb can be reliably reduced.

<Third Embodiment>
Even in the second embodiment, the read disturb can be sufficiently reduced. However, in order to more positively equalize the number of “+ read” and “−read” with respect to the same memory cell, the second embodiment of the device of the present invention. Next, three embodiments will be described.

  As shown in FIG. 14, the configuration of the device of the present invention according to the third embodiment is basically the same as that of the first embodiment, but the read count counter 30 in the first embodiment is read by row. It is replaced with the number counter 32, and the number of readings can be counted in units of rows. In the first embodiment, the direction of the read current is determined depending on whether the number of reads to the entire memory cell array is an even number or an odd number. In the third embodiment, the read from the memory cells connected to the same word line is performed. The polarity of the read voltage is determined according to the number of times. “+ Read” and “−read” are alternated every p times of reading to the memory cells connected to the same word line. Note that p is set to a natural number of 1 or more. As a result, reading can be continued within a range in which the difference between the “+ read” count and the “−read” count to the same memory cell does not exceed p times. The row-by-row read counter 32 counts the number of times of reading for each word line in units of rows. In order to count the number of reads for each word line, the number of read counters 32 equal to the number of word lines is necessary. For example, the row-specific read counter 32 may be configured as shown in FIG. In order to switch between “+ read” and “−read” every time the number of reads to the memory cells connected to the same word line is 2 to the kth power, a (k + 1) -bit counter is used and the most significant bit (see FIG. The polarity of the read voltage may be determined by the bit values of C11 to Cn1).

  In FIG. 16, as in the first embodiment and the second embodiment, as an example, when the memory cell array (see FIG. 9) having three word lines and three bit lines is read up to 14 times, Reads the count value of the row-by-row read count counter 32 in each word line, the polarity of the read voltage, and the bias voltage applied to each word line and each bit line to the first power of 2 (p = 2, k = 1). It is assumed that the polarity of the read voltage is changed every time. In order to change the polarity of the reading voltage every two readings, a 2-bit row-by-row reading number counter 32 is required for three word lines. Note that the selected word line (word line connected to the selected memory cell) at each read count in FIG. 16 is appropriately selected. As shown in FIG. 16, every time the same word line is selected and reading is performed, 1 is added to the row-by-row read count counter 32, and the most significant bits (C11 to C31) of the row-by-row read count counter 32 are added. The polarity of the read voltage is determined by the bit value. Here, a general method for changing the polarity of the read voltage every time p times of reading to the memory cells connected to the same word line is shown by way of example in the case of p = 2. In this case, “+ read” and “−read” are performed every other time, and the row-by-row read count counter 32 is a 1-bit counter, and the circuit scale can be reduced. preferable.

<Fourth embodiment>
In the first to third embodiments, the case where the memory cell is the 1R type has been described, but an embodiment in which the memory cell is the 1T / 1R type is described below.

  FIG. 17 shows a block configuration example in the fourth embodiment of the device of the present invention. The configuration is basically the same as that of the conventional nonvolatile semiconductor memory device including the memory cell array of 1T / 1R type memory cells shown in FIG. The difference from the conventional nonvolatile semiconductor memory device of FIG. 2 is that the same read counter 30 in the first embodiment is added. As shown in the first embodiment, the read number counter 30 is composed of a 1-bit counter that determines whether the read number for the entire memory cell array 1 is odd or even. The count of the read number counter 30 of this 1-bit counter The bias voltage supplied from the voltage switch to each bit line and each source line is switched by the value C so that “+ read” and “−read” are switched, and the polarity of the read voltage applied to the memory cell array 1 is changed. . Even when a 1T / 1R type memory cell is used, “+ read” is performed so that the read current flows from the bit line described below to the memory cell, and read such that the read current flows from the memory cell to the bit line. Is referred to as “-read”.

  In FIG. 17, portions common to the conventional nonvolatile semiconductor memory device shown in FIG. 2 are described with common reference numerals. In the fourth embodiment, around the memory cell array 1 in which 1T / 1R type memory cells (not shown) are arranged in a matrix, a bit line decoder 5, a source line decoder 6, a word line decoder 7, a voltage switch circuit 12a, A read circuit 13 and a control circuit 10a are provided. A specific memory cell in the memory cell array 1 corresponding to the address input input from the address line 8 to the control circuit 10a is selected by the bit line decoder 5, the source line decoder 6, and the word line decoder 7, and the data Write, erase, and read operations are executed, and data is stored in and read from the selected memory cell. Data input / output to / from an external device (not shown) is performed via the data line 9.

  The configuration of the memory cell array 1 is also the same as the configuration of the memory cell array 1 of the conventional nonvolatile semiconductor memory device shown in FIG. Specifically, in the memory cell array 1, m × n memory cells 2 are arranged at intersections of m bit lines (BL1 to BLm) extending in the column direction and n word lines (WL1 to WLn) extending in the row direction. It has become the composition. In addition, n source lines (SL1 to SLn) are arranged in parallel with the word lines. In each memory cell, the upper electrode of the variable resistance element 3 and the drain electrode of the selection transistor 4 are connected, the lower electrode of the variable resistance element 3 is connected to the bit line, the gate electrode of the selection transistor 4 is connected to the word line, The source electrode of the selection transistor 4 is connected to the source line. The lower electrode of the variable resistance element 3 and the drain electrode of the selection transistor 4 are connected, the upper electrode of the variable resistance element 3 is connected to the bit line, and the relationship between the upper electrode and the lower electrode of the variable resistance element 3 is inverted. It doesn't matter.

  The word line decoder 7 selects a word line of the memory cell array 1 corresponding to the signal input to the address line 8, and the bit line decoder 5 selects the bit of the memory cell array 1 corresponding to the address signal input to the address line 8. Further, the source line decoder 6 selects the source line of the memory cell array 1 corresponding to the address signal input to the address line 8. The bit line decoder 5, the source line decoder 6, and the word line decoder 7 select at least one memory cell in the memory cell array 1 corresponding to the address input input from the address line 8 to the control circuit 10a in units of memory cells. Functions as a memory cell selection circuit.

  The control circuit 10a performs control in each of write, erase, and read operations of the memory cell array 1. Based on the address signal input from the address line 8, the data input input from the data line 9 (at the time of writing), and the control input signal input from the control signal line 11, the control circuit 10 a The line decoder 5, the source line decoder 6, the voltage switch circuit 12a, and the memory cell array 1 are controlled in reading, writing, and erasing operations. In the example shown in FIG. 17, the control circuit 10 has functions as a general address buffer circuit, data input / output buffer circuit, and control input buffer circuit (not shown).

  The voltage switch circuit 12 a switches each voltage of the word line, bit line, and source line necessary for reading, writing, and erasing of the memory cell array 1 according to the operation mode, and supplies it to the memory cell array 1. In particular, in the read mode, the voltage switch circuit 12a uses a bit line decoder 5, a source line decoder 6, and a word line decoder 7 to connect a predetermined bit line, word line, and source line connected to the selected memory cell. It functions as a read voltage application circuit for applying the read voltage. Here, Vcc is a power supply voltage of the device of the present invention, Vss is a ground voltage, Vwrt is a write voltage, Vrst is an erase voltage, and Vb is a bias voltage of the memory cell array. Vb + Vr and Vb−Vr are used at the time of reading, and Vb−Vr or Vb + Vr is applied to a selected bit line in a memory cell array biased to Vb (Vb is applied to all source lines and bit lines). Read out. At this time, a voltage having an absolute value Vr is applied as a read voltage to the variable resistance element of the selected memory cell.

  Data is read from the memory cell array 1 via the bit line decoder 5 and the read circuit 13a. The read circuit 13a determines the data state, transfers the result to the control circuit 10a, and outputs it to the data line 9.

  In this embodiment, when Vb−Vr is applied to the selected word line and when Vb + Vr is applied, the current direction of the read current flowing through the selected memory cell is reversed. Therefore, even if the storage data of the memory cell to be read is the same, if the current direction of the read current is different, the voltage value obtained by voltage conversion of the read current is different. Therefore, in this embodiment, it is necessary to change the determination method of the voltage value obtained by voltage conversion according to the polarity of the read voltage, as in the case of the first embodiment. For example, when differentially amplifying the voltage value after voltage conversion with the reference voltage, use an appropriate reference voltage according to the polarity of the read voltage, and set the logic level of the differential amplification output according to the polarity of the read voltage. It is necessary to perform processing such as inversion.

  Next, a specific operation during the read operation will be described. In the case of a 1T / 1R type memory cell, since there is a selection transistor, it is necessary to apply a control voltage for turning on and off the selection transistor. However, each bit line and each source line respectively connected to both ends of the variable resistance element. The voltage application method may be performed according to the first embodiment. However, the source line in this embodiment corresponds to the bit line in the first embodiment, and the bit line in this embodiment corresponds to the word line in the first embodiment.

  FIG. 18 assumes a case where the memory cell array has a matrix configuration of 2 rows × 2 columns as shown in FIG. 19 and includes two word lines, two source lines, and two bit lines. Changes in the count value C of the read number counter 30 when reading is performed a plurality of times (12 times), the ON / OFF state of each select transistor, the polarity of the read voltage, and the voltage applied to each source line and each bit line Indicates the bias voltage. As can be seen from FIG. 18, every time reading is performed on the memory cell array, the count value C of the read counter 30 is rewritten, and the polarity of the read voltage is changed accordingly. In the figure, which memory cell is selected at each read count is appropriately determined for the sake of simplicity. In the example shown in FIG. 18, the four memory cells are only subjected to “+ read” or “−read” (R11, R21), and “+ read” and “−read” are balanced. (R12, R22). If such a reading method is continuously performed in the future, there will be a memory cell in which the effect of reducing the read disturb does not occur at all. However, this is because the setting is intentionally made for the purpose of explanation. However, if the memory cell selection method is random to some extent, “+ read” and “−” are read into each memory cell. The number of “reads” is roughly balanced, and the read disturb is considered to be reduced to some extent. In the example shown in FIG. 18, the bias voltage Vb is always applied to both of the two source lines SL1 and SL2. However, since the selection transistor is off in the source line of the unselected row, the bias voltage Vb is not necessarily biased. The voltage Vb need not be applied.

<Fifth Embodiment>
In the fourth embodiment, as in the first embodiment, there is a problem that the disturbance reduction effect is relied on by chance to some extent. In the following, a fifth embodiment of the device of the present invention improved in the 1T / 1R type memory cell array by the same method as the second embodiment will be described.

  The configuration of the device of the present invention according to the fifth embodiment is basically the same as that of the fourth embodiment as shown in FIG. 20, but the read counter 30 in the fourth embodiment is a binary random number. The configuration is replaced with the generation circuit 31. As in the second embodiment, the binary random number generation circuit 31 randomly generates either “0” or “1”, and holds the value as a binary random value Q. The initial value of the binary random value Q may be either 0 or 1. Each time reading to the memory cell array 1 is completed once, a new value of 0 or 1 is randomly generated, and the binary random number value Q is rewritten to this value. The binary random value Q is used in the same manner as the count value C of the read number counter 30 in the fourth embodiment, and “+ read” is performed when Q = 0, and “−read” is performed when Q = 1. Shall. Since the value of Q is randomly set to “0” or “1” at every reading, the direction of the reading current is randomly determined. FIG. 21 shows a case where a matrix configuration of 2 rows × 2 columns as shown in FIG. 19 is provided with two word lines, two source lines, and two bit lines. Binary random number value Q of the binary random number generation circuit 31, the variable resistance element of the selected memory cell, the polarity of the read voltage, the on / off state of each select transistor, each source line and each The bias voltage applied to the bit line is shown. For convenience of explanation, the value of the binary random value Q and the selected memory cell are appropriately determined. As can be seen from FIG. 21, since the polarity of reading is determined at random, “+ reading” and “−reading” are balanced even if the number of readings increases, so “+ reading” or “−reading” is achieved. Only one of "" is not performed, and the read disturb is reliably reduced. In the example shown in FIG. 21, the bias voltage Vb is always applied to both of the two source lines SL1 and SL2. However, since the selection transistor is off in the source line of the unselected row, the bias voltage Vb is not necessarily biased. The voltage Vb need not be applied.

<Sixth Embodiment>
In the fifth embodiment as well, read disturb can be sufficiently reduced. However, as in the third embodiment, the number of “+ read” and “−read” for the same memory cell is more positively aligned. Next, a sixth embodiment of the device of the present invention will be described.

  The configuration of the device of the present invention according to the sixth embodiment is basically the same as that of the fourth embodiment as shown in FIG. 22, but the read count counter 30 in the fourth embodiment is read by row. It is replaced with the number counter 32, and the number of readings can be counted in units of rows. Similar to the third embodiment, the polarity of the read voltage is determined according to the number of read times to the memory cells connected to the same source line (corresponding to the word line in the third embodiment). “+ Read” and “−read” are alternated every p times of reading to the memory cells connected to the same source line. Note that p is set to a natural number of 1 or more. As a result, reading can be continued within a range in which the difference between the “+ read” count and the “−read” count to the same memory cell does not exceed p times. One row-by-row reading counter 32 is provided for each source line, and the number of times of reading for the same source line is counted.

  The 1T / 1R type memory cell array is characterized in that one memory cell can be selected and read out, which is an advantage. However, if a read number counter is provided for each memory cell, the same number of read times as the memory cell is provided. A counter is required, and the read count counter becomes larger than the memory cell array, making it impractical at all. Therefore, it is appropriate to provide a read count counter for each source line as a row-specific read count counter. However, in this configuration, it is necessary to change the memory cell selection method in which only one memory cell such as the conventional 1T / 1R type memory cell array is selected and read. Even if there is one memory cell to be read, it is necessary to pass a read current to all the other memory cells sharing the source line with that memory cell. This is because the number of read-out counters 32 for each row is one for each source line, and the history of “+ read” and “−read” for all the memory cells connected to the same source line needs to be aligned.

  In the case of the memory cell array as shown in FIG. 1, for example, when reading is performed on the variable resistance element R11, normally, the transistors TR11 to TR1m connected to WL1 are all turned on, and between the bit line BL1 and the source line SL1. The read voltage is applied only to the other bit line, and no potential difference is generated between the other bit lines BL2 to BLm and the source line SL1. However, in this embodiment, the read voltage is applied to all between the source line SL1 and the bit lines BL1 to BLm. Thereby, not only the read current flows through the variable resistance element R11, but also the current can flow through the variable resistance elements R12 to R1m of the memory cells that are not to be read. That is, by selecting all the memory cells connected to the same source line, the history of the currents flowing through the memory cells connected to the same source line is prepared, and the row-by-row read count counter 32 provided for each source line functions effectively. To come. FIG. 23 assumes a case where a matrix configuration of 2 rows × 2 columns as shown in FIG. 19 is provided with two word lines, two source lines, and two bit lines. Read) memory cell variable resistance element, selection transistor ON / OFF state, bias voltage applied to each source line and each bit line, read count and read voltage for each source line And the count value of the row-by-row read count counter for each source line. For convenience of explanation, the memory cell to be read at each number of times of reading is appropriately determined. When the most significant bit (C11, C21) of the count value of each row read counter 32 is “0”, “+ read” is performed, and when “1”, “−read” is performed. As can be seen from FIG. 23, “+ read” and “−read” are switched every two readings for the memory cells connected to the same source line, and “+ read” and “− Since “read” is performed in a balanced manner, only one of “+ read” and “−read” is not performed, and read disturb is reliably reduced. Here, a general method of changing the polarity of the read voltage every time p times of reading to the memory cells connected to the same source line is shown as an example, but p = 1. In this case, it is more preferable to set p = 1 because “+ read” and “−read” are performed every other time and the row-by-row read count counter 32 is a 1-bit counter, and the circuit scale can be reduced. In the example shown in FIG. 23, the bias voltage Vb is always applied to both of the two source lines SL1 and SL2. However, since the selection transistor is off in the source line of the unselected row, the bias voltage Vb is not necessarily biased. The voltage Vb need not be applied.

<Seventh embodiment>
In the sixth embodiment, read disturb can be surely reduced. However, in spite of the 1T / 1R type memory cell array, a memory cell that is not a read target is also selected, so that an excessive read current flows and read. Current consumption increases. Therefore, a seventh embodiment of the device of the present invention for suppressing an increase in current consumption during reading and for surely reducing reading disturb will be described below.

  The configuration of the device of the present invention according to the seventh embodiment is basically the same as that of the sixth embodiment as shown in FIG. 24, but in addition to the row-by-row reading number counter 32 in the sixth embodiment, A selected column address storage circuit 33 for storing a selected column address of a bit line connected to a memory cell to be read in each selected row is provided for each row. The row-by-row read count counter 32 is a 1-bit counter, and alternates between “+ read” and “−read” every read p times to the memory cells connected to the same source line.

  The bit line decoder 5 selects a bit line at the time of current reading in accordance with a column address for selecting a bit line to be read, and is stored in the selected column address storage circuit 33 in the same row as the selected source line. Based on the selected column address, the bit line to be read selected at the previous reading is also selected again. As a result, every time the same row is accessed, the memory cell accessed last time is also selected at the same time, and a read voltage having a polarity opposite to that at the previous read time is applied to the variable resistance element. In the two read operations for the line, “+ read” and “−read” are always performed on the memory cell to be read for the first time, and read disturb is reliably reduced.

  If the memory cell to be read for the first time is selected as the read target for the second time, the memory cell is deleted without being stored in the selected column address storage circuit 33, so that the same memory cell is read three times at the next reading. Continuous reading can be avoided.

  When this embodiment is applied to a serial read application, for example, when the column address is regularly incremented and read continuously, the selected column address storage circuit 33 is not necessarily provided, and the bit line decoder 5 is not provided. When the bit line to be read is selected, the adjacent previous bit line may be selected at the same time. When selecting the first bit line, the last bit line may be selected simultaneously.

  Next, another embodiment of the device of the present invention will be described.

  <1> In each of the above-described embodiments, the memory cell structure has been described by exemplifying the respective memory cell array configurations for two cases of 1R type memory cells and 1T / 1R type memory cells. Any structure other than the type memory cell and the 1T / 1R type memory cell may be used as long as the direction of the current flowing through the variable resistance element of the selected memory cell can be reversed. The selection transistor of the 1T / 1R type memory cell is not limited to the N-type MOSFET, but may be a P-type MOSFET.

  <2> In the fourth to seventh embodiments, the memory cell array configuration of the 1T / 1R type memory cell is exemplified by a configuration in which source lines extending in the row direction as shown in FIG. The memory cell array configuration of the 1R type memory cell is not limited to the configuration of the above embodiment. For example, it may be a source line extending in parallel with the bit line in the column direction.

  Further, the relationship between the bit line and the source line may be reversed with respect to the configuration shown in FIG. In this case, the read circuit 13 a is connected to the source line decoder 6, and the read number counter 32 is connected to the bit line decoder 5.

  <3> In the first to third embodiments, it is assumed that one word line is selected and a read current flowing through a selected memory cell connected to the selected word line is selected and read on the bit line side. However, the relation between the word line and the bit line is inverted, one bit line is selected, and the read current flowing through the selected memory cell connected to the selected bit line is selected on the word line side and read. It does not matter. In this case, the read circuit 23a is connected to the word line decoder 17 side.

  <4> In each of the embodiments described above, the voltage switch circuits 22a and 12a shown in FIGS. 8, 12, 14, 17, 20, 20, 22 and 24 set the voltages for the write, erase, and read operations. Although a form in which one circuit block is generated is shown, a circuit that individually generates the voltage for each operation may be provided. Furthermore, a read voltage application circuit during a read operation may be provided in each decoder.

  <5> In the third and sixth embodiments described above, a read count counter is provided for each row of the memory cell array. However, in the case where the data is always accessed with a certain data size, the memory Since the area is always read continuously, a read number counter may be provided for each area. That is, a read number counter may be provided for every two or more rows.

  <6> In the above embodiments, the description has been made on the assumption that the memory cell array is composed of one memory cell array. However, as shown in FIG. 25, the memory cell array 55 is divided into a plurality of subarray blocks 56, and a certain data In applications that are always accessed by size, if the data size and the capacity of the sub-array block 56 are the same, the sub-array block 56 is always read continuously, so reading is performed for each sub-array block area. Even if the number counter 54 is provided and “+ read” and “−read” are switched depending on the state of the counter, the read disturb can be reduced.

A circuit diagram schematically showing a configuration example of a memory cell array of a 1T / 1R type memory cell including a variable resistance element and a selection transistor. 1 is a block diagram showing a configuration example of a conventional nonvolatile semiconductor memory device including a memory cell array of 1T / 1R type memory cells. 1 is a circuit diagram schematically showing a configuration example of a memory cell array of 1R type memory cells composed only of variable resistance elements. Timing chart showing a conventional example of a procedure for applying a voltage to each word line and each bit line during a data read operation in a memory cell array composed of 1R type memory cells 1 is a block diagram showing a configuration example of a conventional nonvolatile semiconductor memory device having a memory cell array of 1R type memory cells. Characteristic diagram showing the relationship between voltage pulse application and resistance change for variable resistance elements whose initial state is high resistance Characteristic diagram showing the relationship between voltage pulse application and resistance change for variable resistance elements whose initial state is low resistance 1 is a block diagram showing a circuit configuration example in a first embodiment of a nonvolatile semiconductor memory device according to the present invention having a memory cell array of 1R type memory cells. FIG. 6 is a diagram for explaining a read method that alternatively uses two kinds of read currents having different current directions in a nonvolatile semiconductor memory device according to the present invention having a memory cell array of 1R type memory cells. Table showing an example of the polarity and application state of the read voltage in the first embodiment of the nonvolatile semiconductor memory device according to the present invention having a memory cell array of 1R type memory cells. Table showing another example of the polarity and application state of the read voltage in the first embodiment of the nonvolatile semiconductor memory device according to the present invention having a memory cell array of 1R type memory cells. 1 is a block diagram showing a circuit configuration example in a second embodiment of a nonvolatile semiconductor memory device according to the present invention having a memory cell array of 1R type memory cells. Table showing an example of the polarity and application state of the read voltage in the second embodiment of the nonvolatile semiconductor memory device according to the present invention having a memory cell array of 1R type memory cells. 1 is a block diagram showing a circuit configuration example in a third embodiment of a nonvolatile semiconductor memory device according to the present invention having a memory cell array of 1R type memory cells. The figure which shows the example of 1 structure of the reading frequency counter used with the non-volatile semiconductor memory device which concerns on this invention Table showing an example of the polarity and application state of the read voltage in the third embodiment of the nonvolatile semiconductor memory device according to the present invention having the memory cell array of 1R type memory cells. A block diagram showing an example of a circuit configuration in a fourth embodiment of a nonvolatile semiconductor memory device according to the present invention having a memory cell array of 1T / 1R type memory cells. A table showing an example of the polarity and application state of the read voltage in the fourth embodiment of the nonvolatile semiconductor memory device according to the present invention having a memory cell array of 1T / 1R type memory cells. FIG. 6 is a diagram for explaining a reading method that alternatively uses two types of reading currents having different current directions in a nonvolatile semiconductor memory device according to the present invention having a memory cell array of 1T / 1R type memory cells. A block diagram showing a circuit configuration example in a fifth embodiment of a nonvolatile semiconductor memory device according to the present invention having a memory cell array of 1T / 1R type memory cells. A table showing an example of the polarity and application state of the read voltage in the fifth embodiment of the nonvolatile semiconductor memory device having the memory cell array of 1T / 1R type memory cells A block diagram showing a circuit configuration example in a sixth embodiment of a nonvolatile semiconductor memory device according to the present invention having a memory cell array of 1T / 1R type memory cells. A table showing an example of the polarity and application state of the read voltage in the sixth embodiment of the nonvolatile semiconductor memory device according to the present invention having the memory cell array of 1T / 1R type memory cells. A block diagram showing a circuit configuration example in a seventh embodiment of a nonvolatile semiconductor memory device according to the present invention having a memory cell array of 1T / 1R type memory cells. The block diagram which shows the circuit structural example in another embodiment of the non-volatile semiconductor memory device based on this invention when a memory cell array is divided | segmented into a subarray block group

Explanation of symbols

1, 15, 55: Memory cell array 2, 14: Memory cell 3: Variable resistance element 4: Select transistor 5, 16: Bit line decoder 6: Source line decoder 7, 17: Word line decoder 8, 18, 58: Address line 9, 19, 59: Data line 10, 10a to 10c, 20, 20a to 20c, 50: Control circuit 11, 21, 51: Control signal line 12, 12a, 22, 22a, 52: Voltage switch circuit 13, 13a, 23, 23a, 53: Read circuit 30: Read number counter 31: Binary random number generation circuit 32: Read number counter for each row 33: Selected column address storage circuit 54: Read number counter for each block 56: Subarray blocks BL1 to BLm: Bits Line (column selection line)
WL1 to WLn: Word line (row selection line)
SL1 to SLn: Source lines R11 to Rnm: Variable resistance elements TR11 to TRnm: Selection transistor Tread: Read time Vcc: Power supply voltage Vss: Ground voltage Vwrt: Write voltage Vrst: Erase voltage Vb: Memory cell array bias voltage Vr: Read voltage Vb−Vr: Read applied voltage Vb + Vr: Read applied voltage

Claims (11)

A non-volatile semiconductor memory device having a memory cell array in which a plurality of memory cells each including a variable resistance element that stores information according to a change in electrical resistance are arranged in a row direction and a column direction,
A memory cell selection circuit for selecting the memory cells from the memory cell array in row units, column units, or memory cell units;
A read voltage application circuit for applying a read voltage to the variable resistance element of the selected memory cell selected by the memory cell selection circuit;
A read operation of information stored in the memory cell to be read is detected by detecting the magnitude of a read current flowing in the memory cell to be read of the selected memory cell according to the resistance value of the variable resistance element. A readout circuit for performing,
The read voltage application circuit is configured to be able to change the polarity of the read voltage to be applied in order to select the direction of current flowing through the variable resistance element of the selected memory cell.
The read circuit performs the read operation in accordance with a current direction of the read current according to a polarity of the read voltage applied to the variable resistance element of the memory cell to be read. Semiconductor memory device.   The read voltage application circuit determines the polarity of the read voltage so that the polarity of the read voltage to be applied is the same number in the forward / reverse direction or substantially the same number in the read operation for the same memory cell array a plurality of times. The nonvolatile semiconductor memory device according to claim 1.   2. The read voltage application circuit reverses the polarity of the read voltage to be applied in every one or more predetermined natural number of the read operations in the read operation for the same memory cell array. The non-volatile semiconductor memory device described in 1.   The read voltage application circuit determines the polarity of the read voltage to be applied based on a random value generated randomly or in advance for each read operation in the read operation for the same memory cell array. The nonvolatile semiconductor memory device according to claim 1.   The read voltage application circuit is configured to apply the read voltage so that the polarity of the read voltage to be applied is equal to or equal to the same number in the read operation for a plurality of times for the memory cells in the same row or column of the same memory cell array. The non-volatile semiconductor memory device according to claim 1, wherein the polarity is determined.   The read voltage application circuit reverses the polarity of the read voltage to be applied in the read operation for the same row or the same column of the same memory cell array at every one or more predetermined natural number of the read operations. The nonvolatile semiconductor memory device according to claim 1.   7. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell selection circuit selects the memory cell from the memory cell array in units of rows or columns.   The memory cell array includes a plurality of row selection lines extending in the row direction and a plurality of column selection lines extending in the column direction, and each of the memory cells in the same row has the one end side of the variable resistance element on the same row. 8. The memory cell in the same column is connected to a selection line, and each of the memory cells in the same column is configured by connecting the other end side of the variable resistance element to the same column selection line. Nonvolatile semiconductor memory device The memory cell includes a series circuit of the variable resistance element and a selection transistor,
The memory cell array includes a plurality of row selection lines extending in the row direction and a plurality of column selection lines extending in the column direction, and each of the memory cells in the same row has the same row selection line as the gate of the selection transistor. And each of the memory cells in the same column is configured by connecting one end of the series circuit to the same column selection line and each of the memory cells connecting the other end of the series circuit to a source line. And
7. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell selection circuit selects at least one of the memory cells in the same row from the memory cell array. The memory cell includes a series circuit of the variable resistance element and a selection transistor,
The memory cell array includes a plurality of row selection lines extending in the row direction and a plurality of column selection lines extending in the column direction, and each of the memory cells in the same row has the same row selection line as the gate of the selection transistor. And each of the memory cells in the same column is configured by connecting one end of the series circuit to the same column selection line and each of the memory cells connecting the other end of the series circuit to a source line. And
The memory cell selection circuit simultaneously selects the memory cell to be read at the time of the previous read of the same row as the memory cell to be read from the memory cell array,
The read voltage application circuit determines that the polarity of the read voltage to be applied is opposite to the polarity of the read voltage applied in the previous read of the same row. A nonvolatile semiconductor memory device.   The nonvolatile semiconductor memory device according to claim 1, wherein the variable resistance element is a perovskite metal oxide.

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