JP2006173186A - Semiconductor device, pattern layout creation method and exposure mask - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device equipped with a wiring pattern group including two or more wiring patterns which are effective in high integration. <P>SOLUTION: The semiconductor device comprises a semiconductor substrate 13 and the wiring pattern group which is arranged in the semiconductor substrate 13 and provided with wiring patterns P1-P4. Each of wiring patterns P1-P4 includes a fringe 2 for connecting electrically with a wiring pattern in a wiring group other than the wiring pattern group. The wiring patterns P1-P4 include the wiring pattern P1 and the wiring patterns P2-P4 (Pi) arranged in one direction different from the longitudinal direction of the wiring pattern P1. The wiring patterns P2-P4 are arranged in a position more distant from the wiring pattern P1 as a value (i) gets larger, and at the same time are provided with the wiring pattern group with a longer size in the longitudinal direction. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device including a wiring pattern group, a pattern layout creating method for a plurality of wiring patterns in the wiring pattern group, and an exposure mask.

  The progress of semiconductor manufacturing technology in recent years is very remarkable. Currently, semiconductor devices having a minimum processing dimension of 90 nm are mass-produced. The miniaturization of semiconductor devices has been realized by a dramatic advance in fine pattern formation technology. Typical fine pattern formation techniques include a mask process technique, a lithography process technique, and an etching process technique.

  When the pattern size is sufficiently large, create a mask with a mask pattern of the same shape as the design pattern, set the mask in the exposure device, and transfer the mask pattern onto the resist applied on the wafer As a result, a pattern as designed on the wafer could be formed relatively easily.

  However, now that the pattern size has been miniaturized, it has become difficult to form a pattern as designed on a wafer. The reason is that the influence of diffraction of exposure light on the size of the pattern on the wafer has increased, it has become difficult to manufacture a mask for accurately forming a fine pattern, and It is difficult to finely process a wafer or a film thereon (metal film, insulating film, semiconductor film).

  As techniques for improving the fidelity of a design pattern, there are known correction methods called optical proximity effect correction (OPC) and process proximity effect correction (Process Proximity Correction: PPC).

  OPC and PPC (hereinafter referred to as PPC including OPC) correction methods are roughly classified into rule-based OPC and model-rule OPC.

  The rule-based OPC defines the amount of movement of the edges constituting the design pattern as a rule (table) according to the width of the design pattern or the distance between the closest patterns of the patterns, and according to the rule (table), This is a method for obtaining an optimum edge movement amount (correction amount).

  On the other hand, the model rule OPC uses an lithography simulator that can predict the diffracted light intensity distribution of exposure light with high accuracy, so that the optimum edge movement amount (correction) is made so that the same pattern as the design pattern is formed on the wafer (Quantity) is obtained by calculation.

  There has also been proposed a correction method that realizes higher-precision correction by combining rule-based OPC and model-rule OPC.

  In recent years, not only OPC (technique for correcting a mask pattern) but also a technique for correcting a design pattern drawn by a designer according to a certain rule, a so-called correction method called target MDP (Mask Data Processing) processing has been proposed. Has been.

  In the target MDP process, for a specific pattern type that is predicted to be difficult to form on the wafer, the pattern type is corrected so that the pattern type can be easily formed on the wafer.

  In the target MDP process, the final design pattern is different from the pattern drawn by the original designer. For this reason, it is necessary to advance the target MDP process after agreeing in advance with the designer how to change the pattern. Therefore, the implementation of the target MDP process is complicated.

  In recent years, it has become difficult to ensure a process margin in a lithography process. Therefore, a technique for deforming the design pattern in a more complicated manner is required for the target MDP process. However, it is difficult to establish such a deformation technique.

  Incidentally, a NAND flash memory is known as one of nonvolatile semiconductor memory devices. The NAND flash memory includes a memory cell array in which a plurality of memory cells are connected in series. The memory cell has a MOS structure in which a floating gate and a control gate are stacked. The NAND flash memory has an advantage that it is suitable for high integration.

However, as described above, the progress of the lithography process has not sufficiently coped with the miniaturization of semiconductor devices, so that it is becoming difficult to achieve high integration of the NAND flash memory. Specifically, it is difficult to reduce the wiring pattern layout of the conventional NAND flash memory (Patent Document 1) as it is and achieve high integration.
JP 2002-64043 A

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device including a wiring pattern group including a plurality of wiring patterns effective for high integration, and a plurality of wiring patterns in the wiring pattern group. And providing an exposure mask for forming the wiring pattern group.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, a semiconductor device according to the present invention is a semiconductor substrate and a wiring pattern group provided on the semiconductor substrate and including N (N ≧ 2) wiring patterns, and each of the N wiring patterns. One end includes a connection region for electrically connecting to a wiring pattern in a wiring pattern group different from the wiring pattern group, and the N wiring patterns include a wiring pattern N1 and a length of the wiring pattern N1. Including at least one wiring pattern Ni (i ≧ 2) arranged in one direction different from the direction, and the at least one wiring pattern Ni increases from the wiring pattern N1 as the value of i increases. Of the at least one or more wiring patterns Ni that are arranged at a distance from each other, and the connection region is located at the end on the same side, the larger the value of i, Continued region is located farther with respect to the longitudinal direction, and characterized by being provided with said wiring pattern group.

  Another semiconductor device according to the present invention is a semiconductor substrate and a wiring pattern group including N (N ≧ 3) wiring patterns provided on the semiconductor substrate, wherein each of the N wiring patterns includes: The wiring pattern group includes a connection region for electrical connection with a wiring pattern in a wiring group different from the wiring pattern group, and the N wiring patterns are different from the wiring pattern N1 in the longitudinal direction of the wiring pattern N1. Two or more wiring patterns Ni (i ≧ 2) arranged in the direction, and the two or more wiring patterns Ni are arranged at a position farther from the wiring pattern N1 as the value of i increases. The two or more wiring patterns Ni include at least one wiring pattern Np (2 ≦ p <N) and at least one wiring pattern Nq (p <q ≦ N), At least one The wiring pattern Np has a longer dimension in the longitudinal direction as the value of p is larger, and the at least one wiring pattern Nq has a shorter dimension in the longitudinal direction as the value of q is larger. The wiring pattern group is provided.

  The pattern layout creating method according to the present invention is a step of defining a wiring pattern N1 which is a reference when arranging N (N ≧ 2) wiring patterns in a wiring pattern group, and the N wiring patterns Each includes a connection region for electrically connecting to a wiring pattern in a wiring group different from the wiring pattern group, and at least one in a direction different from the longitudinal direction of the wiring pattern N1. A step of arranging at least one wiring pattern Ni (i ≧ 2), the step of arranging the at least one wiring pattern Ni at a position farther from the wiring pattern N1 as the value of i increases. And a step of increasing the longitudinal dimension of the at least one wiring pattern Ni as the value of i increases.

  Another pattern layout creating method according to the present invention is a step of defining a wiring pattern N1 and a wiring pattern N1 ′ that are used as a reference when arranging N (N ≧ 3) wiring patterns in a wiring group. The wiring pattern N1 and the wiring pattern N1 ′ have the same longitudinal direction, and the wiring pattern N1 ′ is arranged at a certain distance from the wiring pattern N1 in one direction different from the longitudinal direction, and Each of the N wiring patterns includes a connection region for electrically connecting to a wiring pattern in a wiring group different from the wiring pattern group; and the N (N ≧ 3) wiring patterns In the step of arranging the remaining wiring pattern obtained by removing the wiring pattern N1 and the wiring pattern N1 ′ from the wiring pattern between the wiring pattern N1 and the wiring pattern N1 ′. Thus, after arranging at least one wiring pattern Np (2 ≦ p <N) at a position farther from the wiring pattern N1 as the value of p increases, the one or more wiring patterns Np are arranged. When at least one wiring pattern Nq (p <q <N) remains in the remaining wiring pattern, the larger the value of q, the farther from the wiring pattern N1 ′, and Placing the at least one wiring pattern Nq at a position away from the wiring pattern Np having the largest value of p by a certain distance; and as the value of p increases, the at least one wiring pattern When the longitudinal dimension of Np is increased and the at least one wiring pattern Nq remains, the larger the value of q, the more the at least one The dimension of the upper wiring pattern Nq in the longitudinal direction is reduced, and the dimension of the wiring pattern Nq in which the q value is the smallest is set to the longitudinal dimension of the wiring pattern Np in which the value of p is the largest. And a step of making it larger or smaller than a dimension in the direction.

  An exposure mask according to the present invention comprises a transparent substrate for exposure light, and a pattern corresponding to a plurality of wiring patterns provided on the transparent substrate and corresponding to a plurality of wiring patterns according to the present invention. To do.

  According to the present invention, a semiconductor device including a wiring pattern group including a plurality of wiring patterns effective for high integration, a pattern layout creation method for a plurality of wiring patterns in the wiring pattern group, and the wiring pattern group are formed. Therefore, an exposure mask can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows a layout of a control gate wiring pattern (CG wiring pattern) of a conventional NAND flash memory corresponding to the 65 nm generation. In FIG. 1, four CG wiring patterns 1 are shown.

  The CG wiring pattern 1 includes a portion (gate pattern portion) which is a main body of the CG wiring pattern, and a portion (gate leading portion) for electrically connecting the gate pattern portion to a wiring pattern of another layer. . In FIG. 1, the right side of the broken line is the gate pattern part (main pattern part), and the left side of the broken line is the gate lead-out part.

  The boundary between the gate pattern portion and the gate lead-out portion is generally determined based on the influence of exposure (exposure latitude). Generally, the gate pattern portion is provided in a region where the influence of exposure is less than that of the gate lead-out portion (region where the exposure tolerance is large).

  The gate lead portion includes a portion called a fringe 2. In the fringe 2, contact is made with the wiring patterns of other layers. In the figure, reference numeral 3 indicates a contact portion between the fringe 2 and a wiring pattern of another layer. Hereinafter, a portion of the gate lead portion excluding the fringe 2 is referred to as a lead wiring portion.

  If the fringe 2 has a small area, contact failure may occur due to misalignment during exposure. Accordingly, the area of the fringe 2 is required to have a certain size. However, this hinders miniaturization (high integration).

  As shown in FIG. 1, the gate lead portions of the four CG wiring patterns 1 have an irregular pattern layout. This is a result of determining the layout of the four CG wiring patterns 1 (CG wiring pattern layout) so that the fringe 2 having an area having a required size is arranged.

  On the other hand, in recent years, fine CG wiring patterns have been formed by a lithography process using modified illumination. For a lithography process using modified illumination, it is very difficult to form a pattern layout other than L & S, that is, an irregular pattern layout.

  As described above, the regularity of the CG wiring pattern layout shown in FIG. 1 is broken due to the arrangement of the fringes 2. Therefore, it is very difficult to form the gate lead portion shown in FIG. 1 by a lithography process using modified illumination. That is, the compatibility between the conventional lithography process using modified illumination and the conventional CG wiring pattern layout is poor.

  By the way, in the NAND flash memory, a state occurs in which a CG wiring pattern to which a high voltage is applied (first CG wiring pattern) and a CG wiring pattern to which no voltage is applied (second CG wiring pattern) are adjacent to each other. obtain.

  At this time, the high voltage applied to the first CG wiring pattern affects the second CG wiring pattern, or dielectric breakdown occurs between the first CG wiring pattern and the second CG wiring pattern. May happen.

  For this reason, the first CG wiring pattern is designed such that at least the interval between the portion to which the high voltage of the first CG wiring pattern is applied and the second CG wiring pattern does not cause the above inconvenience (such as dielectric breakdown). The wiring pattern and the second CG wiring pattern need to be arranged. However, this hinders miniaturization (high integration).

  Further, when misalignment occurs between the contact hole and the element isolation region (STI), a contact plug reaching the element isolation region may be formed. In this case, there is a disadvantage that a voltage is applied to the element isolation region.

  In order to prevent the above inconvenience, it is necessary to increase the fringe size by an amount corresponding to a possible misalignment. However, this hinders high integration.

  In the present embodiment, even if memory cells are highly integrated (miniaturized), a wiring pattern group including a plurality of wiring patterns (here, control CG wiring patterns) effective for realizing a semiconductor memory integrated circuit on a wafer. A NAND flash memory including the above will be described.

  Here, a 45 nm generation NAND flash memory will be described. Therefore, modified illumination is used in a photolithography process for manufacturing a NAND flash memory. The present embodiment can also be applied to a NAND flash memory of a generation in which miniaturization (high integration) is advanced more than the 65 nm generation, 55 nm generation, or 45 nm generation. Depending on the degree of miniaturization (high integration), it may not be necessary to use modified illumination. In general, it is necessary to use modified illumination in a generation in which miniaturization (high integration) has progressed.

  FIG. 2 is a plan view showing the CG wiring pattern layout of the present embodiment. A wiring pattern group including select gates 10, 11, and 32 CG wiring gate patterns P (P 1 -P 7, P 1 ′ -P 25 ′) is disposed above the semiconductor substrate (wafer) 13.

  The 32 CG wiring gate patterns P are arranged at a constant pitch between the select gates 10 and 11. The pitch does not necessarily have to be constant. The longitudinal directions of the 32 CG wiring gate patterns P are the same, and the 32 CG wiring gate patterns P are arranged in a direction perpendicular to the longitudinal direction. In FIG. 2, for the sake of simplicity, only P1 ', P2', P3 ', and P25' are shown among the reference symbols P1 'to P25'.

  As for the CG wiring patterns P1-P7 disposed under the selection gate 10, the dimension in the longitudinal direction of the gate pattern portion is longer as it is disposed at the lower side.

  The longitudinal dimension of the gate pattern portion of the CG wiring pattern P2 is longer than the longitudinal dimension of the gate pattern portion of the CG wiring pattern P1 by a fixed dimension. Similarly, the longitudinal dimension of the gate pattern portion of the CG wiring pattern P3 is longer than the longitudinal dimension of the gate pattern portion of the CG wiring pattern P2 by a certain dimension.

  In other words, the longitudinal dimension of the gate pattern portion of the CG wiring pattern Pi (i = 2-7) is longer than the longitudinal dimension of the gate pattern portion of the CG wiring pattern Pi-1 by a certain dimension.

  The difference (constant dimension) between the longitudinal dimension of the gate pattern portion of the CG wiring pattern Pi and the longitudinal dimension of the gate pattern portion of the CG wiring pattern Pi-1 is not necessarily the same for each i.

  On the portion of the CG wiring pattern P2 that is longer than the CG wiring pattern P1 by a certain dimension, the gate lead-out portion of the CG wiring pattern P1 is disposed. Similarly, the gate lead-out portion of the CG wiring pattern P2 is disposed on the portion of the CG wiring pattern P3 that is longer than the CG wiring pattern P2 by a certain dimension.

  That is, the gate lead-out portion of the CG wiring pattern Pi is arranged on the portion of the CG wiring pattern Pi that is longer than the CG wiring pattern Pi-1 by a certain dimension (in the open space). Therefore, the CG wiring patterns P1 to P7 are arranged so that the gate leading portion of the CG wiring pattern Pi-1 and the gate leading portion of the CG wiring pattern Pi do not overlap in the arrangement direction of the CG wiring pattern P. become.

  On the other hand, the CG wiring patterns P1'-P25 'arranged on the selection gate 11 have a longer dimension in the longitudinal direction of the gate pattern portion as they are arranged on the upper side.

  The longitudinal dimension of the gate pattern portion of the CG wiring pattern P2 'is longer than the longitudinal dimension of the gate pattern portion of the CG wiring pattern P1' by a fixed dimension. Similarly, the longitudinal dimension of the gate pattern portion of the CG wiring pattern P3 'is longer than the longitudinal dimension of the gate pattern portion of the CG wiring pattern P2' by a certain dimension.

  That is, the longitudinal dimension of the gate pattern portion of the CG wiring pattern Pj ′ (j = 2-25) is longer than the longitudinal dimension of the gate pattern portion of the CG wiring pattern Pj-1 ′ by a certain dimension. Yes.

  The difference (constant dimension) between the longitudinal dimension of the gate pattern portion of the CG wiring pattern Pj ′ and the longitudinal dimension of the gate pattern portion of the CG wiring pattern Pj−1 ′ is not necessarily the same for each j. .

  On the portion of the CG wiring pattern P2 'that is longer than the CG wiring pattern P1' by a certain dimension, a gate lead-out portion of the CG wiring pattern P1 'is disposed. Similarly, a gate lead-out portion of the CG wiring pattern P2 'is disposed on a portion of the CG wiring pattern P3' that is longer than the CG wiring pattern P2 'by a certain dimension.

  That is, the gate lead-out portion of the CG wiring pattern Pj is disposed on the portion of the CG wiring pattern Pj 'that is longer than the CG wiring pattern Pj-1' by a certain dimension (in the open space). Therefore, the CG wiring patterns P1′-P25 ′ are arranged so that the gate drawing portion of the CG wiring pattern Pj-1 ′ and the gate drawing portion of the CG wiring pattern Pj ′ do not overlap in the arrangement direction of the CG wiring pattern P. Will be placed.

  The CG wiring pattern layout of the present embodiment has an asymmetrical mountain pattern composed of seven gate lead portions arranged from the top to the bottom and 25 gate lead portions arranged from the bottom to the top. Has a layout. The reason for adopting such a pattern layout will be described below.

  FIG. 3 shows a symmetric chevron pattern layout in which the number of gate lead-out portions arranged from the top to the bottom is the same as the number of gate lead-out portions arranged from the bottom to the top. That is, a CG wiring pattern layout including a plurality of gate lead portions arranged vertically symmetrically about the CG wiring pattern P4 is shown.

  The fringes 2 of the adjacent CG wiring patterns P3 and P5 are arranged above and below the lead-out wiring portion of the CG wiring pattern P4. In this case, the lithography margin becomes insufficient, and the lead-out wiring portion of the CG wiring pattern P4 and the fringe 2 of the CG wiring patterns P3 and P5 may come into contact with each other.

FIG. 4 shows an asymmetric mountain-shaped pattern layout in which the number of gate lead portions arranged from the top to the bottom is different from the number of gate lead portions arranged from the bottom to the top. This corresponds to a simplified CG wiring pattern layout of FIG.
The fringe 2 of the CG wiring pattern P1 adjacent to the CG wiring pattern P2 is disposed on the leading wiring part of the CG wiring pattern P2. Is not arranged. The fringes 2 of the CG wiring patterns P3 and 5 adjacent thereto are not arranged above and below the lead-out wiring portion of the CG wiring pattern P3. The fringe 2 of the CG wiring pattern P5 adjacent to the CG wiring pattern P4 is disposed under the leading wiring part of the CG wiring pattern P4. However, the fringe 2 of the CG wiring pattern P3 adjacent to the CG wiring pattern P4 is disposed on the leading wiring part of the CG wiring pattern P4. Is not arranged. That is, there is no CG wiring pattern in which the lead-out wiring part is sandwiched between the upper and lower CG wiring pattern fringes adjacent to it.

  In the case of the CG wiring pattern layout of FIG. 4, it was confirmed that a necessary lithography margin could be obtained. As shown in FIG. 5, it was confirmed that a necessary lithography margin could be obtained in the case of a saw-shaped CG wiring pattern layout in which the longitudinal dimension monotonously increases with respect to one direction.

  In the case of the present embodiment, as shown in FIG. 6, the fringe is arranged in the region R on one end side of the lead portion of the CG wiring pattern P. Therefore, the periodicity (symmetry) is lost between the one end and the other end of the lead portion of the CG wiring pattern P. In this case, the lithography margin decreases at both ends. If this makes it impossible to secure a necessary lithography margin, it is preferable to adopt the CG wiring pattern layout shown in FIG.

  The CG wiring pattern layout of FIG. 7 has been subjected to the following processing (1)-(3).

(1) The distance L between the fringe 2 and the adjacent CG wiring pattern P is increased.

(2) The fringe 2 and the CG wiring pattern are connected by a connecting portion (drawing wiring portion) 4 including a diagonally inclined pattern.

(3) The corners of the fringe 2 are slanted. In FIG. 7, one corner C of the fringe 2 has an oblique shape, but a plurality of corners may have an oblique shape.

  The CG wiring pattern layout of FIG. 7 is subjected to processes not shown other than the processes (1) to (3). Specifically, a process of further adjusting the size of the fringe 2 according to the exposure conditions, a process of changing the thickness of the CG wiring pattern in the vicinity of the connection part (drawing wiring part) 4, and the like.

  All of these processes are not necessarily performed, and can be selected within a range in which a necessary lithography margin can be secured.

  An example of a method for creating the CG wiring pattern layout of FIG. 2 is shown below.

  First, a wiring pattern P1 and a wiring pattern P1 'serving as a reference when arranging 32 CG wiring patterns P1-P7, P1'-P25' in the CG wiring group are defined. The CG wiring pattern P1 and the CG wiring pattern P1 'have the same longitudinal direction, and the CG wiring pattern P1' is arranged below the CG wiring pattern P1 in one direction different from the longitudinal direction. Each of the 32 CG wiring patterns P1-P7, P1'-P25 'includes a fringe for electrically connecting to a wiring pattern in a wiring pattern group different from the CG wiring pattern group. The CG wiring pattern group and the wiring pattern group are arranged in different layers.

  Next, the remaining wiring patterns obtained by removing the CG wiring patterns P1, P1 ′ from the 32 CG wiring patterns P1-P7, P1′-P25 ′ are arranged between the CG wiring patterns P1 and CG wiring patterns P1 ′. Is done. At this time, the six CG wiring patterns P2-P7 (Pi) are arranged at positions farther from the CG wiring pattern P1 as the value of i is larger, and the 24 CG wiring patterns P2′-P25 ′ (Pj ′). ) Is arranged at a position farther from the CG wiring pattern P1 ′ as the value of j is larger and at a position lower than the CG wiring pattern P7 (a position away from the CG wiring pattern P7 by a certain distance).

  Finally, the larger the value of i, the longer the dimension in the longitudinal direction of the CG wiring pattern P2-P7 (Pi), and the larger the value of j, the longer the dimension in the longitudinal direction of the CG wiring patterns P2′-P25 ′. And the dimension in the longitudinal direction of the CG wiring pattern P25 ′ is made larger than the dimension in the longitudinal direction of the CG wiring pattern P7.

  In the present embodiment, the longitudinal dimension of the CG wiring pattern P25 ′ is longer than the longitudinal dimension of the CG wiring pattern P7. Conversely, the longitudinal dimension of the CG wiring pattern P7 is CG wiring pattern P25 ′. The 32 CG wiring patterns P1-P7, P1′-P25 ′ may be arranged so as to be longer than the longitudinal dimension.

  In general, the number of CG wiring patterns arranged from the top (here, 7) and the number of CG wiring patterns arranged from the bottom (here, 25) are compared with a plurality of CG wiring patterns having a larger number. The dimension in the longitudinal direction is larger on the wiring pattern side. In the case where the fringe size of the plurality of CG wiring patterns having the larger number can be made smaller than the fringe size of the plurality of CG wiring patterns having the smaller number, the size relationship in the longitudinal direction is reversed. It is also possible. In particular, when the difference between the number of CG wiring patterns arranged from the top and the number of CG wiring patterns arranged from the bottom is small, the size relationship in the longitudinal direction can be easily reversed.

  Also, here, 32 CG wiring patterns are divided into 7 (the number of CG wiring patterns arranged from the top) and 25 (the number of CG wiring patterns arranged from the bottom), and an asymmetrical mountain layout However, when 32 CG wiring patterns are divided into 1 and 31, the number of CG wiring patterns arranged from the bottom is zero. That is, the reference wiring pattern P1 'is defined, but there is no CG wiring pattern arranged upward from the wiring pattern P1'.

  Next, an example of a method for creating the CG wiring pattern layout of FIG. 5 is shown below.

  First, a wiring pattern P1 serving as a reference when the four CG wiring patterns P1-P4 in the CG wiring pattern group are arranged is defined. Each of the four CG wiring patterns P1-P4 includes a fringe 2 for electrically connecting to a wiring group wiring pattern different from the CG wiring pattern group. The CG wiring pattern group and the wiring pattern group are arranged in different layers.

  Next, three CG wiring patterns Ni (i = 2, 3, 4) are arranged in one direction different from the longitudinal direction of the CG wiring pattern P1. At this time, as the value of i increases, the three CG wiring patterns Ni are arranged at positions farther from the CG wiring pattern N1.

  Finally, the larger the value of i, the longer the dimension in the longitudinal direction of the three CG wiring patterns Ni.

  By the way, the contrast of the light intensity with respect to the gate pattern portion and the fringe can be improved by arranging a dummy pattern in the space portion of the gate pattern portion. FIG. 8 is an experimental result (light intensity distribution) showing this.

  FIG. 8 shows the position dependency of the light intensity distribution of three CG wiring pattern layouts without a dummy pattern (coverage 0%), with a dummy pattern (coverage 50%), and with a dummy pattern (coverage 100%). It is shown.

  The light intensity distribution of the CG wiring pattern layout is obtained by performing OPC on the CG wiring pattern layout, performing optical image calculation using the mask data of the CG wiring pattern layout obtained by performing the OPC, and the result of the optical calculation. Was obtained by calculating the light intensity distribution on the wafer based on the above.

  FIGS. 9A to 9C show three types of CG wiring pattern layouts with no dummy pattern (coverage rate 0%), with a dummy pattern (coverage rate 50%) and with a dummy pattern (coverage rate 100%). The top view of is shown. FIGS. 10A to 10C are perspective views showing the CG wiring pattern layout of FIGS. 9A to 9C in a three-dimensional manner.

  The light intensity distribution of FIG. 8 shows the light on the thin broken line extending in the horizontal direction (X direction) in the region (the region including the vicinity of the fringe) surrounded by the thick broken line in FIGS. 9 (a) -9 (c). The intensity distribution direction is shown.

  From FIG. 8, the contrast of the light intensity with respect to the gate pattern portion and the fringe is improved in the order of no dummy pattern (coverage 0%), dummy pattern (coverage 100%), and dummy pattern (coverage 50%). I understood that. That is, by arranging an L & S pattern (dummy pattern) having a period similar to that of the gate pattern portion in the space portion of the gate pattern portion, the contrast is increased, and in particular, a dummy pattern having a coverage of 50% is disposed. As a result, it was confirmed that the contrast became the highest.

  In order to reduce the EB exposure time at the time of reticle production, a fine dummy pattern (L & S pattern having a period similar to that of the gate pattern portion) is arranged only where necessary, and a large dummy pattern (otherwise) A large dummy pattern) should be placed. The large dummy pattern includes a pattern defined by a dimension larger than the space width (line width) of the L & S pattern.

  11 to 20 show plan views of other CG wiring pattern layouts of the embodiment.

  FIG. 11 shows a CG wiring pattern layout including a dummy pattern (OPC target dummy pattern) DP1 subjected to OPC and a dummy pattern (OPC asymmetric dummy pattern) DP2 not subjected to OPC. In the example of FIG. 11, the dummy pattern that is the target of the OPC asymmetric dummy pattern DP2 is not limited.

  FIG. 12 shows a CG wiring pattern layout including the OPC target dummy pattern DP1 and the OPC asymmetric dummy pattern DP2 '. The dummy pattern that is the target of the OPC asymmetric dummy pattern DP2 'includes a large dummy pattern. OPC processing time can be shortened by not applying OPC to the large dummy pattern. When MDP is performed, the MDP processing time can be shortened by not performing MDP on the large dummy pattern.

  FIG. 13 shows a CG wiring pattern layout including a strip-like dummy pattern DP3.

  FIG. 14 shows another CG wiring pattern layout not including a dummy pattern.

  FIG. 15 shows a CG wiring pattern layout including a pattern (auxiliary pattern) SP for SRAF (Sub Resolution Assist Feature) disposed between the selection gates 10 and 11. The CG wiring pattern layout shown in FIG. 15 is a layout on an exposure mask, but the CG wiring pattern layout of other embodiments may be a layout on a wafer or a layout on an exposure mask.

  FIG. 16 shows a CG wiring pattern layout in which the ends of the selection gates 10 and 11 are shifted in the longitudinal direction of the gate pattern portion of the CG wiring pattern.

  FIG. 17 shows a CG wiring pattern layout in which 15 CG wiring patterns are periodically arranged. In addition, a CG wiring pattern layout in which 16, 64 or 32 (an integer multiple of 16 or 32) CG wiring patterns are periodically arranged may be used. Further, a CG wiring pattern layout in which eight CG wiring patterns are periodically arranged may be used. That is, the number of CG wiring patterns is not particularly limited.

  FIG. 18 shows a CG wiring pattern layout in which the fringes 2 are distributed and arranged on the left and right.

  FIG. 19 shows a CG wiring pattern layout in which gate lead-out portions (fringe 2) are alternately arranged at the left end portion and the right end portion of the CG wiring pattern. In FIG. 19, the gate lead-out portion (fringe 2) is switched left and right for each CG wiring, but the left and right may be switched for every two or more CG wirings.

  FIG. 20 shows a CG wiring pattern layout in which the arrangement position of the gate lead-out part (fringe 2) is switched left and right in units of one block. Two or more blocks may be used as a unit. The number of CG wiring patterns in one block may be other than 32.

  FIG. 21 shows a more detailed saw-shaped CG wiring pattern layout than the saw-shaped CG wiring pattern layout shown in FIG.

  FIG. 22 shows a modification of the CG wiring pattern layout shown in FIG. In FIG. 5, the positions of the ends opposite to the fringes 2 of the plurality of CG wiring patterns are aligned, but are not aligned in FIG. In FIG. 22, the fringe 2 of the CG wiring pattern P that is farther from the CG wiring pattern P (reference CG wiring pattern) closest to the selection gate SG11 is arranged at a position farther in the wiring longitudinal direction. That is, when only the fringe 2 side is viewed, the dimension in the longitudinal direction is longer as the CG wiring pattern P is farther from the reference CG wiring pattern.

  FIG. 23 shows another modification of the CG wiring pattern layout shown in FIG. In FIG. 5, the fringes 2 of the plurality of CG wiring patterns are all arranged on the same side (left side). However, in FIG. 5, the fringes 2 of the fringes 2 of the plurality of CG wiring patterns are alternately arranged on the left and right sides. Further, when looking at a plurality of CG wiring patterns in which the fringe 2 is arranged on the same side, the fringe 2 of the CG wiring pattern P far from the reference CG wiring pattern is located farther in the wiring longitudinal direction as in FIG. Has been placed. In FIG. 5, the fringes 2 are arranged so that the left and right are alternated every other one, but two or more, or every other and every other two may be mixed.

  In the above description, the type of deformation is not particularly mentioned, but either the second illumination or the fourth illumination may be used. That is, the layout of this embodiment is effective regardless of the type of modified illumination.

  24A and 24B show examples of illumination shapes of modified illumination. The illumination shape 21 shown in FIG. 24A includes two illuminations 22 corresponding to the second illumination. The illumination shape 21 shown in FIG. 24A includes four illuminations 23 in addition to the two illuminations 22. These four illuminations 23 are used to assist the second illumination.

  The present embodiment is effective not only in a lithography process using modified illumination but also in a lithography process that improves resolution by adjusting the light deflection state. Specifically, a lithography process using immersion exposure can be given.

  The exposure mask of this embodiment includes a transparent substrate and a pattern that is provided on the transparent substrate and corresponds to the CG wiring pattern layout of this embodiment. The transparent substrate is, for example, a glass substrate. The pattern is formed of a film including a light shielding film such as a Cr film. The film is present on the transparent substrate in a portion corresponding to the CG wiring pattern layout.

  In the present embodiment, the CG wiring pattern layout has been described. However, the present invention is also effective for the layout of other wiring patterns in other NAND flash memories. Furthermore, the present invention is also effective for the layout of wiring patterns in semiconductor devices other than NAND flash memories.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

  In addition, various modifications can be made without departing from the scope of the present invention.

The top view which shows the layout of the control gate (CG) wiring pattern of the conventional NAND type flash memory. FIG. 3 is a plan view showing a layout of a CG wiring pattern of the NAND flash memory according to the embodiment. The top view which shows the layout of an asymmetrical CG wiring pattern. The top view which shows the layout of the symmetrical CG wiring pattern of embodiment. The top view which shows the layout of the other symmetrical CG wiring pattern of embodiment. The figure for demonstrating the arrangement | positioning area | region of the fringe of embodiment. The top view which shows the layout of the CG wiring pattern in which the fall of the margin of the lithography of embodiment was prevented. The figure which shows the light intensity distribution for demonstrating the effect of a dummy pattern. The top view which shows the layout of the CG wiring pattern which does not contain a CG wiring pattern including a dummy pattern, and a dummy pattern. The perspective view which shows the layout of the CG wiring pattern which does not contain a CG wiring pattern including a dummy pattern, and a dummy pattern. The top view which shows the layout of the other CG wiring pattern of embodiment. The top view which shows the layout of the other CG wiring pattern of embodiment. The top view which shows the layout of the other CG wiring pattern of embodiment. The top view which shows the layout of the other CG wiring pattern of embodiment. The top view which shows the layout of the other CG wiring pattern of embodiment. The top view which shows the layout of the other CG wiring pattern of embodiment. The top view which shows the layout of the other CG wiring pattern of embodiment. The top view which shows the layout of the other CG wiring pattern of embodiment. The top view which shows the layout of the other CG wiring pattern of embodiment. The top view which shows the layout of the other CG wiring pattern of embodiment. The top view which shows the layout of the other CG wiring pattern of embodiment. The top view which shows the layout of the other CG wiring pattern of embodiment. The top view which shows the layout of the other CG wiring pattern of embodiment. The top view which shows the illumination shape of deformation | transformation illumination.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Gate pattern, 2 ... Fringe, 3 ... Contact part, 4 ... Lead-out wiring part, 10, 11 ... Selection gate, 13 ... Semiconductor substrate, DP1, DP2, DP2 ', DP3 ... Dummy pattern, P, P1-P7, P1'-P25 '... CG pattern, SP ... auxiliary pattern.

Claims (17)

A semiconductor substrate;
A wiring pattern group provided on the semiconductor substrate and provided with N (N ≧ 2) wiring patterns, wherein one end of each of the N wiring patterns is a wiring pattern group different from the wiring pattern group. The N wiring patterns include a wiring pattern N1 and at least one or more arranged in one direction different from the longitudinal direction of the wiring pattern N1. A wiring pattern Ni (i ≧ 2), and the at least one wiring pattern Ni is arranged at a position farther from the wiring pattern N1 as the value of i is larger, and the at least one wiring pattern Ni. Among the wiring patterns Ni of the wiring patterns Ni, those having the connection region at the end on the same side, the larger the value of i, the farther the connection region is arranged in the longitudinal direction. That, the semiconductor device characterized by comprising comprises a said wiring pattern group. A semiconductor substrate;
A wiring pattern group provided on the semiconductor substrate and including N (N ≧ 3) wiring patterns, wherein each of the N wiring patterns is a wiring pattern in a wiring group different from the wiring pattern group. The N wiring patterns include a wiring pattern N1 and two or more wiring patterns Ni (i) arranged in one direction different from the longitudinal direction of the wiring pattern N1. ≧ 2), the two or more wiring patterns Ni are arranged at a position farther from the wiring pattern N1 as the value of i is larger, and the two or more wiring patterns Ni are at least Including at least one wiring pattern Np (2 ≦ p <N) and at least one wiring pattern Nq (p <q ≦ N), wherein the at least one wiring pattern Np has a value of the p Is large The length of the longitudinal direction is longer, and the at least one wiring pattern Nq includes the wiring pattern group having a shorter dimension in the longitudinal direction as the value of q is larger. A semiconductor device. When the number of the at least one wiring pattern Np is smaller than the number of the at least one wiring pattern Nq, the dimension in the longitudinal direction of the wiring pattern Nq having the smallest value of q is the p Larger than the dimension in the longitudinal direction of the wiring pattern Np having the largest value of
When the number of the at least one wiring pattern Np is larger than the number of the at least one wiring pattern Nq, the dimension in the longitudinal direction of the wiring pattern Nq having the smallest value of q is the p The semiconductor device according to claim 2, wherein a value of the wiring pattern Np is smaller than a dimension in the longitudinal direction of the wiring pattern Np. 4. The semiconductor device according to claim 1, wherein in each of the wiring patterns Nj (j ≧ 1), the width of the connection region is wider than the width of the wiring pattern. 5. The semiconductor device according to claim 1, wherein the wiring pattern group further includes a dummy pattern. 6. The semiconductor device according to claim 5, wherein the dummy pattern includes a dummy pattern that is a target of optical proximity effect correction and a dummy pattern that is not a target of optical proximity effect correction. The semiconductor device according to claim 6, wherein the dummy pattern includes a line & space pattern and a large pattern having a size defined by a dimension larger than a dimension defining the size of the line & space pattern. The N wiring patterns are arranged so that the connection region of the wiring pattern Nj (j ≧ 1) and the connection region of the wiring pattern Nj + 1 do not overlap in the one direction. The semiconductor device according to any one of claims 1 to 7. A step of defining a wiring pattern N1 which is a reference when arranging N (N ≧ 2) wiring patterns in the wiring pattern group, each of the N wiring patterns being different from the wiring pattern group. Including the connection region for electrically connecting to the wiring pattern in the wiring group of
A step of disposing at least one wiring pattern Ni (i ≧ 2) in one direction different from the longitudinal direction of the wiring pattern N1, wherein the larger the value of i, the farther the position from the wiring pattern N1 is And arranging the at least one wiring pattern Ni;
And a step of lengthening the longitudinal dimension of the at least one wiring pattern Ni as the value of i increases. A step of defining a wiring pattern N1 and a wiring pattern N1 ′ that are used as a reference when arranging N (N ≧ 3) wiring patterns in the wiring group, the wiring pattern N1 and the wiring pattern N1 ′ Have the same longitudinal direction, and the wiring pattern N1 ′ is arranged at a certain distance from the wiring pattern N1 in one direction different from the longitudinal direction, and each of the N wiring patterns is the wiring Including the connection region for electrically connecting to a wiring pattern in a wiring group different from the pattern group;
This is a step of arranging the remaining wiring pattern obtained by removing the wiring pattern N1 and the wiring pattern N1 ′ from the N (N ≧ 3) wiring patterns between the wiring pattern N1 and the wiring pattern N1 ′. Then, at least one wiring pattern Np (2 ≦ p <N) is arranged at a position farther from the wiring pattern N1 as the value of p is larger, and after the one or more wiring patterns Np are arranged, When at least one wiring pattern Nq (p <q <N) remains in the remaining wiring pattern, the larger the value of q, the farther from the wiring pattern N1 ′, and placing the at least one wiring pattern Nq at a position away from the wiring pattern Np having the largest value of p by a certain distance;
The larger the value of p, the longer the dimension in the longitudinal direction of the at least one wiring pattern Np, and the value of q when the at least one wiring pattern Nq remains. Is larger, the dimension in the longitudinal direction of the at least one wiring pattern Nq is reduced, and the dimension in the longitudinal direction of the wiring pattern Nq having the smallest q value is the largest in the value of p. And a step of making the wiring pattern Np larger or smaller than the dimension in the longitudinal direction of the large wiring pattern Np. When the number of the at least one wiring pattern Np is small and the number of the at least one wiring pattern Nq is small, the dimension in the longitudinal direction of the wiring pattern Nq having the smallest q value is set to the value of p. Larger than the dimension in the longitudinal direction of the wiring pattern Np having the largest value;
When the number of the at least one wiring pattern Np is large, the dimension in the longitudinal direction of the wiring pattern Nq having the smallest q value is expressed as p. The pattern layout creation method according to claim 10, wherein the pattern layout creation method is smaller than the dimension in the longitudinal direction of the wiring pattern Np having the largest value. 12. The pattern layout creation method according to claim 9, wherein in each of the wiring patterns Nj (j ≧ 1), the width of the connection region is wider than the width of the wiring pattern. 13. The pattern layout creation method according to claim 9, wherein the wiring pattern group further includes a dummy pattern. The pattern layout creation method according to claim 13, wherein the dummy pattern includes a dummy pattern that is a target of optical proximity effect correction and a dummy pattern that is not a target of optical proximity effect correction. The dummy pattern that is subject to optical proximity correction includes a line & space pattern, and the dummy pattern that is not subject to optical proximity correction is defined by a dimension that is larger than the dimension that defines the size of the line & space pattern. The pattern layout creation method according to claim 14, comprising a large pattern having a size. The N wiring patterns are arranged so that the connection region of the wiring pattern Nk (k ≧ 1) and the connection region of the wiring pattern Nk + 1 do not overlap in the one direction. The pattern layout creation method according to claim 9. A transparent substrate for exposure light;
An exposure mask comprising: a pattern corresponding to a plurality of wiring patterns of the wiring pattern group according to any one of claims 1 to 8 provided on the transparent substrate.

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