JP2006171827A - Processor and processing program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable a vector processor to process, at high speed, instructions having a saturation function, while keeping circuit scale from increasing. <P>SOLUTION: When either an add-subtract shift unit A25 or B26 performs an addition process, a saturation process part 25a or 26a refers to an S-bit in a status register 22. When the S-bit is "1" a decision is made as to whether the result of the addition by the add-subtract shift unit A25 or B26 overflows or underflows. When the result of the addition by the add-subtract shift unit A25 or B26 overflows, "0x7FFFFFFF" is outputted as the result of the addition. When the result of the addition by the add-subtract shift unit A25 or B26 underflows, "0x80000000" is outputted as the result of the addition. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an arithmetic processing unit and an arithmetic processing program, and in particular, is suitably applied to a vector pipeline processor used in an AMR-NB (Adaptive Multi-Rate Narrow Band) codec (hereinafter referred to as an AMR codec). It is.

  The AMR codec is one of the speech codecs proposed by 3GPP (3rd Generation Partnership Project), and is characterized by the ability to efficiently compress and encode human speech, with saturation processing and sum of products with 16-bit accuracy. Arithmetic etc. are frequently performed. In particular, as a function having a large number of calls in an AMR decoder, there is a product-sum operation function called L_MAC (). In this L_MAC () function, a product-sum operation is performed by calling the L_mult () function and the L_add () function, and saturation processing is performed depending on whether there is an overflow.

FIG. 17 is a diagram illustrating an example of the source code of the L_MAC () function, and FIG. 18 is a diagram illustrating a compilation example of the source code of FIG.
In FIG. 17, when the L_MAC () function is executed, the L_multi () function is called and normal multiplication is performed. When the multiplication result does not overflow when shifted by 1 bit to the left, the multiplication result is shifted by 1 bit to the left. When overflow occurs, an overflow flag is set and a saturation value is substituted as the multiplication result.

Next, the L_add () function is called and normal addition is performed. Then, it is determined whether or not the addition result has overflowed, and when it has overflowed, an overflow flag is set and a saturation value is substituted as the addition result.
As described above, since complicated processing is performed in the L_MAC () function in FIG. 17, when the source code in FIG. 17 is compiled, as shown in FIG.

Further, in Patent Document 1, in a MAC (Multiple and Accurate) instruction, a 16-bit operand having the contents of general-purpose registers Rm and Rn as an address is multiplied with a sign, and 32 bits of the multiplication result and the contents of the MAC register are multiplied. A method is disclosed in which addition is performed and the addition result is stored in the MAC register, and when the S bit is 1, addition to the MAC register is a saturation operation. In this saturation operation, when an overflow occurs, the LSB of the MACH register is set to 1, and when the addition result overflows in the negative direction, H "80000000 (minimum value) is stored in the MAC register, and the addition result is When overflowing in the positive direction, H ″ 7FFFFFFF (maximum value) is stored in the MAC register. When the S bit is 0, 42 bits of the addition result are stored in the concatenated MACH / L register.
JP-A-6-150023

However, since the saturation function is implemented in the L_MAC () function, it is necessary to determine whether or not there is an overflow every time one calculation is performed, and to perform branch processing according to the determination result. For this reason, the number of cycles fluctuates for each operation for one instruction, and the L_MAC () function cannot be converted into a vector instruction, which hinders the increase in the operation speed.
In addition, in the method disclosed in Patent Document 1, a saturation operation in the MAC instruction is executed while referring to the S bit. However, in order to be able to process the MAC instruction at high speed, dedicated hardware is added to the MAC instruction. Then, there was a problem that the circuit scale was increased.

  Accordingly, an object of the present invention is to provide an arithmetic processing device and an arithmetic processing program capable of processing an instruction having a saturation function at high speed while suppressing an increase in circuit scale.

In order to solve the above-described problem, according to an arithmetic processing device according to one aspect of the present invention, a vector adder that performs vector addition processing and the vector adder are mounted on the vector adder and obtained by the vector adder. And a saturation processing unit that performs saturation processing based on the addition result.
As a result, the saturation processing associated with the addition operation can be performed on the hardware, and the saturation processing can be executed without describing the determination of the presence or absence of overflow and the branch processing according to the determination result in the program. It becomes possible. For this reason, even when the saturation function is implemented in the addition instruction, it is possible to execute the operation for one instruction in one cycle, and the vectorization of the addition instruction in which the saturation function is implemented can be performed. It is possible to speed up the addition processing in which the function is implemented.

The arithmetic processing device according to an aspect of the present invention further includes a status register that stores a saturation designation flag for enabling the saturation processing, and the saturation processing unit includes a reference result of the saturation designation flag. Based on the above, saturation processing is performed.
This makes it possible to specify from the program whether or not to execute saturation processing. This makes it possible to prevent the saturation process from being uniformly performed on the addition result even when the saturation process associated with the addition operation is implemented by hardware, and by preparing one addition instruction. Thus, it is possible to realize an addition process in which the saturation function is implemented and an addition process in which the saturation function is not implemented.

Further, according to the arithmetic processing device according to one aspect of the present invention, a vector shift arithmetic unit that performs vector shift arithmetic processing, and a shift arithmetic result that is mounted on the vector shift arithmetic unit and obtained by the vector shift arithmetic unit And a saturation processing unit that performs saturation processing based on the above.
As a result, the saturation processing associated with the shift operation can be performed on the hardware, and the saturation processing can be executed without describing the determination of the presence of overflow and the branch processing according to the determination result in the program. It becomes possible. For this reason, even when the saturation function is implemented in the shift operation instruction, it is possible to execute the operation for one instruction in one cycle, and to enable vectorization of the shift operation instruction in which the saturation function is implemented. Therefore, it is possible to increase the speed of the shift operation processing in which the saturation function is implemented.

  Moreover, according to the arithmetic processing device which concerns on 1 aspect of this invention, the said saturation process part is the shift obtained by the said vector shift computing unit, when the shift operation performed by the said vector shift computing unit is an arithmetic shift When saturation processing is unconditionally executed in accordance with the operation result and the shift operation performed by the vector shift operator is a logical shift, whether or not the shift operation result obtained by the vector shift operator has overflowed. This is characterized in that saturation processing is not executed.

  As a result, it is possible to realize the left shift operation processing in which the saturation function is implemented by describing the arithmetic shift instruction on the program, and it is possible to realize the saturation function by describing the logical shift instruction on the program. It is possible to realize left shift calculation processing that is not implemented. This makes it possible to prevent the saturation processing from being uniformly performed on the shift operation result even when the saturation processing associated with the shift operation is implemented in hardware, and the same operation result for the left shift. By properly using the two types of redundant left and right shift operation instructions that can be obtained, it is possible to realize shift operation processing in which the saturation function is implemented and shift operation processing in which the saturation function is not implemented.

  In addition, according to the arithmetic processing device according to an aspect of the present invention, a vector multiplier that performs vector multiplication processing, a vector adder that performs vector addition processing, and the vector adder are mounted on the vector adder. The first saturation processing unit that performs saturation processing based on the obtained addition result, the vector shift arithmetic unit that performs vector shift arithmetic processing, and the vector shift arithmetic unit are obtained by the vector shift arithmetic unit. And a second saturation processing unit that performs saturation processing based on the shift result.

  As a result, the L_MAC () function can be executed by executing three instructions including a multiplication instruction, a shift operation instruction, and an addition instruction. It is possible to execute the L_MAC () function without describing it in the program. Therefore, the L_MAC () function can be converted into a vector instruction without adding dedicated hardware to the L_MAC () function, and the L_MAC () function is executed at high speed while suppressing an increase in circuit scale. It becomes possible.

Further, according to the arithmetic processing device according to one aspect of the present invention, the saturation processing unit sets an overflow flag in the status register based on the presence or absence of the saturation processing.
As a result, by referring to the value of the overflow flag set in the status register, it is possible to detect the presence or absence of saturation after the calculation is completed, and to enable branching of processing depending on the presence or absence of saturation.

In addition, according to the arithmetic processing program according to one aspect of the present invention, a vector multiplication instruction in which the saturation function is not implemented, a vector addition instruction in which the saturation function is implemented, and a vector shift instruction in which the saturation function is implemented The computer is executed.
This makes it possible to execute the L_MAC () function without describing in the program the determination of whether or not there is an overflow and the branch process according to the determination result. Therefore, the L_MAC () function can be converted into a vector instruction without adding dedicated hardware to the L_MAC () function, and the L_MAC () function is executed at high speed while suppressing an increase in circuit scale. It becomes possible.

The arithmetic processing program according to one aspect of the present invention causes a computer to execute an instruction that specifies on / off of the saturation function of the vector addition instruction.
This makes it possible to specify from the program whether or not to execute saturation processing. This makes it possible to prevent the saturation process from being uniformly performed on the addition result even when the saturation process associated with the addition operation is implemented by hardware, and by preparing one addition instruction. Thus, it is possible to realize an addition process in which the saturation function is implemented and an addition process in which the saturation function is not implemented.

According to the arithmetic processing program of one aspect of the present invention, the computer is caused to execute a detection function for detecting the presence or absence of overflow of the addition result by the vector addition instruction or the shift operation result by the vector shift instruction. To do.
Thus, by describing the detection function in the program, it is possible to detect the presence or absence of saturation after the calculation is completed, and to enable branching of processing depending on the presence or absence of saturation.

Hereinafter, an arithmetic processing apparatus according to an embodiment of the present invention will be described with reference to the drawings. In the following embodiment, a case where vector pipeline processing is performed by operating each arithmetic unit of the vector processor 100 of FIG. 2 in the computer system of FIG. 1 will be described as an example.
FIG. 1 is a block diagram showing a schematic configuration of a computer system according to an embodiment of the present invention.

  In FIG. 1, a computer system includes a vector processor 100 having a vector calculator, a main memory 110 for storing a control program of the vector processor 100 in a predetermined area in advance, an input unit 120 as a human interface capable of inputting data, a display An output unit 130 that can output data such as a communication unit 140 and a communication unit 140 that communicates with the outside via a network or the like are provided.

  Here, in the main memory 110, a program / text area 111 for storing a program, an initialized data area 112 for storing data such as constants in advance, and an uninitialized area reserved in advance for storing data such as constants Data area 113, heap area 114 and stack area 115 which are dynamically secured during program execution, and other logically partitioned storage areas.

  The control program is composed of a low-level language (for example, machine language) that can be directly executed by the vector processor 100, and an assembly source code 200 described in a high-level language (for example, C language) is converted into an assembler 210. The program is compiled into a low-level language by an instruction code generation system including the linker 220 and generated as an execution program 230. The generated control program is stored in an auxiliary storage device such as a hard disk. When the vector processor 100 executes the program, it is placed in the program / text area 111 in the storage area of the main memory 110 by the program loader 240. , Put into a workable state. The assembler 210, linker 220, and program loader 240 can generally be configured by software.

FIG. 2 is a block diagram showing a schematic configuration of the vector processor 100 of FIG.
In FIG. 2, the vector processor 100 includes an instruction decoder 21 that decodes the contents of instructions read from the main memory 110, a status register 22 that stores information about the status of the vector processor 100, and a scalar register register that is used for scalar operations. A register file 23 in which vector registers used for vector operations are arranged, a multiplication unit 24 that performs multiplication, an addition / subtraction / shift unit A25 that performs addition / subtraction and shift operations, an addition / subtraction / shift unit B26 that performs addition / subtraction and shift operations, shift, and AND MOVE unit A27 that performs logical operations such as shift and OR, MOVE unit B28 that performs logical operations such as shift, AND, and OR, ALU 29 that performs arithmetic processing, and an address that generates a load address Forming unit X30, the address generation unit Y31 to generate an address for the load, the address generation unit Z32 to generate an address for the store is provided.

  Here, the instruction decoder 21 is provided with a branch control unit 21a for performing branch control. The status register 22 is assigned an S bit for storing a saturation designation flag for enabling saturation processing during addition / subtraction processing, and a VV bit for storing an overflow flag during addition / subtraction processing and shift operation. ing. Further, saturation processing units 25a to 28a are mounted on the addition / subtraction / shift unit A25, addition / subtraction / shift unit B26, MOVE unit A27, and MOVE unit B28, respectively.

  Here, the saturation processing unit 25a refers to the S bit of the status register 22. When the S bit is “1”, the saturation processing unit 25a executes saturation processing according to the addition / subtraction result obtained by the addition / subtraction / shift unit A25 and When the process is executed, “1” is set to the VV bit of the status register 22. The saturation processing unit 26a refers to the S bit of the status register 22. When the S bit is "1", the saturation processing unit 26a executes the saturation processing according to the addition / subtraction result obtained by the addition / subtraction / shift unit B26, and also performs the saturation processing. Is executed, the VV bit of the status register 22 is set to “1”.

  Further, when the shift operation performed in the MOVE unit A27 is an arithmetic shift, the saturation processing unit 27a unconditionally executes the saturation processing according to the shift operation result obtained in the MOVE unit A27, and When the VV bit is set to “1” and the shift operation performed in the MOVE unit A27 is a logical shift, the saturation process is not executed regardless of whether the shift operation result obtained in the MOVE unit A27 overflows. To do. Further, when the shift operation performed in the MOVE unit B28 is an arithmetic shift, the saturation processing unit 28a unconditionally executes the saturation processing according to the shift operation result obtained in the MOVE unit B28, and When the VV bit is set to “1” and the shift operation performed in the MOVE unit B28 is a logical shift, the saturation processing is not executed regardless of whether or not the shift operation result obtained in the MOVE unit B28 overflows. To do.

  The instruction decoder 21 is connected to the program bus PB and the program address bus PAB, and via the buses B1 to B3, the register file 23, the multiplication unit 24, the addition / subtraction / shift unit A25, the addition / subtraction / shift unit B26, and MOVE. The unit A27, the MOVE unit B28, the ALU 29, the address generation unit X30, the address generation unit Y31, and the address generation unit Z32 are connected. The register file 23 is connected to the X-bus XB, Y-bus XY, ZX-bus ZXB, and ZY-bus ZYB, and via the bus B4, the multiplication unit 24, the addition / subtraction / shift unit A25, and the addition / subtraction / shift. The unit B26, the MOVE unit A27, the MOVE unit B28, the ALU 29, the address generation unit X30, the address generation unit Y31, and the address generation unit Z32 are connected. The address generation unit X30 is connected to the X-address bus XAB, the address generation unit Y31 is connected to the Y-address bus YAB, and the address generation unit Z32 is connected to the ZX-address bus ZXAB and the ZY-address bus ZYAB. Yes.

FIG. 3 is a block diagram showing a schematic configuration of the register file 23 of FIG.
In FIG. 3, the register file 23 includes a scalar register and a vector register. Here, for example, only 16 storage areas SR0 to SR15 for storing 32-bit data can be provided in the scalar register.
For example, assuming that the number of elements of a vector is 8, one vector register can be configured by eight storage areas VR0 [0] to VR0 [7] each storing 32-bit data. it can. Then, for example, 64 storage areas VR0 [0] to VR0 [7], VR1 [0] to VR1 [7], VR2 [0] to VR2 [7], VR3 [ 0] to VR3 [7], VR4 [0] to VR4 [7], VR5 [0] to VR5 [7], VR6 [0] to VR6 [7], VR7 [0] to VR7 [7] are provided. Thus, eight vector registers can be provided.

FIG. 4 is a diagram illustrating the data structure of a vector instruction.
In FIG. 4, the vector instruction is provided with an opcode opecode that defines the type of instruction such as multiplication and addition, and a repeat amount rptamt that defines the number of executions of the vector operation. In the vector instruction, the destination register dst to be written and the source registers src1 and src2 to be read can be designated. Also, in the data structure of FIG. 4, when the repeat amount rptam is set to 0, scalar instructions and vector instructions can be stored using the same data structure.

FIG. 5 is a diagram showing vector addition processing of the vector processor 100 of FIG.
In FIG. 5, in the vector instruction, for example, addition is designated by the operation code opecode, 8 is designated by the repeat amount rptamt, the vector register VR0 of FIG. 3 is designated as the destination register dst, and the source registers src1, src2 are shown. 3 vector registers VR1 and VR2 are respectively designated. In this case, the addition / subtraction / shift unit A25 or the addition / subtraction / shift unit B26 of FIG. 2 is selected as the adder A1, and the elements a0 to a7 stored in the vector register VR1 and the elements x0 to x7 stored in the vector register VR2 are selected. Are sequentially sent to the adder A1. Then, after addition is performed for each element by the adder A1, the addition result is stored in the vector register VR0.

FIG. 6 is a block diagram showing a schematic configuration of the saturation processing units 25a and 26a of FIG.
In FIG. 6, the saturation processing units 25 a and 26 a can be connected to the S bit and the VV bit of the status register 22. Further, it is assumed that “0x7FFFFFFF” is set as the saturation value when overflowing, and “0x80000000” is set as the saturation value when underflowing. When the addition processing is performed in the addition / subtraction / shift unit A25 or the addition / subtraction / shift unit B26, the saturation processing units 25a and 26a refer to the S bit of the status register 22, and when the S bit is “1”, the addition / subtraction is performed. It is determined whether or not the addition result obtained by / shift unit A25 or addition / subtraction / shift unit B26 overflows or underflows.

  When the addition result obtained by the addition / subtraction / shift unit A25 or the addition / subtraction / shift unit B26 does not overflow or underflow, the addition result obtained by the addition / subtraction / shift unit A25 or the addition / subtraction / shift unit B26 is used as it is. Output. On the other hand, when the addition result obtained by the addition / subtraction / shift unit A25 or the addition / subtraction / shift unit B26 overflows, “0x7FFFFFFF” is output as the addition result, and “1” is set to the VV bit of the status register 22 To do. If the addition result obtained by the addition / subtraction / shift unit A25 or the addition / subtraction / shift unit B26 underflows, “0x80000000” is output as the addition result, and “1” is output to the VV bit of the status register 22. Set.

On the other hand, as a result of referring to the S bit of the status register 22 as a result of referring to the S bit of the status register 22, the saturation processing units 25a and 26a indicate the addition results obtained by the addition / subtraction / shift unit A25 or the addition / subtraction / shift unit B26, respectively. Output as is.
As a result, the saturation processing associated with the addition operation of the addition / subtraction / shift unit A25 or the addition / subtraction / shift unit B26 can be performed on the hardware, and it is determined whether there is an overflow or underflow, and branch processing according to the determination result. It is possible to execute saturation processing without describing the above in the program. For this reason, even when the saturation function is implemented in the addition instruction, it is possible to execute the operation for one instruction in one cycle, and the vectorization of the addition instruction in which the saturation function is implemented can be performed. It is possible to speed up the addition processing in which the function is implemented.

  Further, by assigning the S bit to the status register 22, it is possible to specify from the program whether or not to execute saturation processing. This makes it possible to prevent the saturation process from being uniformly performed on the addition result even when the saturation process associated with the addition operation is implemented by hardware, and by preparing one addition instruction. Thus, it is possible to realize an addition process in which the saturation function is implemented and an addition process in which the saturation function is not implemented.

Further, by assigning the VV bit to the status register 22, it is possible to detect the presence or absence of saturation after the operation is completed by referring to the value of the VV bit set in the status register 22, and debugging and the like. Can be useful.
FIG. 7 is a block diagram showing a schematic configuration of the saturation processing units 27a and 28a of FIG.
In FIG. 7, the saturation processing units 27 a and 28 a can be connected to the VV bit of the status register 22. Further, it is assumed that “0x7FFFFFFF” is set as the saturation value when overflowing, and “0x80000000” is set as the saturation value when underflowing. The saturation processing units 27a and 28a, when the shift operation performed in the MOVE unit A27 and the MOVE unit B28 is an arithmetic shift, causes the left shift operation result obtained in the MOVE unit A27 or the MOVE unit B28 to overflow or underflow. Judge whether or not

  If the left shift calculation result obtained by the MOVE unit A27 or the MOVE unit B28 does not overflow or underflow, the left shift calculation result obtained by the MOVE unit A27 or the MOVE unit B28 is output as it is. On the other hand, if the left shift calculation result obtained by MOVE unit A27 or MOVE unit B28 overflows, “0x7FFFFFFF” is output as the left shift calculation result, and “1” is set to the VV bit of status register 22 To do. If the left shift operation result obtained by the MOVE unit A27 or the MOVE unit B28 is underflowing, “0x80000000” is output as the left shift operation result, and “1” is output to the VV bit of the status register 22. Set.

On the other hand, when the shift operations performed in MOVE unit A27 and MOVE unit B28 are logical shifts, saturation processing units 27a and 28a output the shift operation results respectively obtained in MOVE unit A27 and MOVE unit B28 as they are.
As a result, the saturation processing associated with the shift operation of the MOVE unit A27 and the MOVE unit B28 can be performed on the hardware, and the determination of the presence or absence of overflow and the branch processing according to the determination result are not described in the program. The saturation process can be executed. For this reason, even when the saturation function is implemented in the shift operation instruction, it is possible to execute the operation for one instruction in one cycle, and to enable vectorization of the shift operation instruction in which the saturation function is implemented. Therefore, it is possible to increase the speed of the shift operation processing in which the saturation function is implemented.

  In addition, by describing the arithmetic shift instruction on the program, it is possible to realize the shift operation processing in which the saturation function is implemented, and the saturation function is implemented by describing the logical shift instruction on the program. It is possible to realize shift operation processing that is not performed. For this reason, even when the hardware of the saturation processing associated with the shift operation is performed, it is possible to prevent the saturation processing from being uniformly performed on the shift operation result, and two types that can obtain the same operation result. By using different redundant shift operation instructions, it is possible to realize shift operation processing in which the saturation function is implemented and shift operation processing in which the saturation function is not implemented.

Further, by assigning the VV bit to the status register 22, it is possible to detect the presence or absence of saturation after the operation is completed by referring to the value of the VV bit set in the status register 22, and debugging and the like. Can be useful.
FIG. 8 is a block diagram showing pipeline processing of the vector processor 100 of FIG.

  When the instruction fetch IF of a vector instruction is performed in cycle C1 in FIG. 8, the vector instruction is sent to the instruction decoder 21 in FIG. When the vector instruction on which the instruction fetch IF has been performed is sent to the instruction decoder 21 in FIG. 2, the decode RD is performed in the instruction decoder 21 in cycle C2, and the vector instruction is decoded. Then, by decoding the vector instruction by the instruction decoder 21, the operation code opecode and repeat amount rptamt are extracted, and in the vector instruction, it is possible to determine what kind of vector operation is performed how many times. .

  Here, assuming that addition is specified by the opcode opecode of the vector instruction and 4 is set in the repeat amount rptamt, the execution EXE corresponding to the first addition of the vector instruction is added / subtracted / shifted in cycle C3. This is performed by A25 or addition / subtraction / shift unit B26. The saturation processing units 25a and 26a refer to the S bit of the status register 22 when the execution EXE is performed in the addition / subtraction / shift unit A25 or the addition / subtraction / shift unit B26, and when the S bit is “1”, the addition / subtraction is performed. It is determined whether or not the addition result obtained by / shift unit A25 or addition / subtraction / shift unit B26 overflows or underflows.

If the addition result obtained by the addition / subtraction / shift unit A25 or the addition / subtraction / shift unit B26 overflows or underflows, a saturation value is output as the addition result, and “1” is output to the VV bit of the status register 22. Set.
Next, in cycle C4, storage MEM of the first addition result of the vector instruction is performed in the vector register, and execution EXE corresponding to the second addition of the vector instruction is performed. The saturation processing units 25a and 26a refer to the S bit of the status register 22 when the execution EXE is performed in the addition / subtraction / shift unit A25 or the addition / subtraction / shift unit B26, and when the S bit is “1”, the addition / subtraction is performed. It is determined whether or not the addition result obtained by / shift unit A25 or addition / subtraction / shift unit B26 overflows or underflows.

If the addition result obtained by the addition / subtraction / shift unit A25 or the addition / subtraction / shift unit B26 overflows or underflows, a saturation value is output as the addition result, and “1” is output to the VV bit of the status register 22. Set.
Next, in cycle C5, storage MEM of the second addition result of the vector instruction is performed in the vector register, and execution EXE corresponding to the third addition of the vector instruction is performed. The saturation processing units 25a and 26a refer to the S bit of the status register 22 when the execution EXE is performed in the addition / subtraction / shift unit A25 or the addition / subtraction / shift unit B26, and when the S bit is “1”, the addition / subtraction is performed. It is determined whether or not the addition result obtained by / shift unit A25 or addition / subtraction / shift unit B26 overflows or underflows.

If the addition result obtained by the addition / subtraction / shift unit A25 or the addition / subtraction / shift unit B26 overflows or underflows, a saturation value is output as the addition result, and “1” is output to the VV bit of the status register 22. Set.
Next, in cycle C6, the storage MEM of the third addition result of the vector instruction is performed in the vector register, and the execution EXE corresponding to the fourth addition of the vector instruction is performed. The saturation processing units 25a and 26a refer to the S bit of the status register 22 when the execution EXE is performed in the addition / subtraction / shift unit A25 or the addition / subtraction / shift unit B26, and when the S bit is “1”, the addition / subtraction is performed. It is determined whether or not the addition result obtained by / shift unit A25 or addition / subtraction / shift unit B26 overflows or underflows.

If the addition result obtained by the addition / subtraction / shift unit A25 or the addition / subtraction / shift unit B26 overflows or underflows, a saturation value is output as the addition result, and “1” is output to the VV bit of the status register 22. Set.
Next, in cycle C7, the storage MEM of the fourth addition result of the vector instruction is performed in the vector register, and the processing of the vector instruction for which the instruction fetch IF has been performed this time is completed.

FIG. 9 is a diagram illustrating an example of hand assembly of the L_MAC () function according to an embodiment of the present invention.
When the addition / subtraction / shift unit A25, the addition / subtraction / shift unit B26, the MOVE unit A27, and the MOVE unit B28 are not equipped with the saturation processing units 25a to 28a, the presence / absence of overflow is determined every time one calculation is performed. It is necessary to perform branch processing according to the determination result. Therefore, it is necessary to insert an instruction such as a conditional branch into the source code of the L_MAC function as shown in FIG. 17, and the source code compilation example of FIG. 17 has 36 lines as shown in FIG. It becomes a huge function that extends to.

  On the other hand, by adding saturation processing units 25a to 28a to the addition / subtraction / shift unit A25, the addition / subtraction / shift unit B26, the MOVE unit A27, and the MOVE unit B28, as shown in FIG. The L_MAC () function can be realized by three instructions: an instruction, a SAW instruction for performing a shift operation with a saturation function, and an ADDW instruction for performing an addition with a saturation function.

FIG. 10 is a diagram illustrating a usage example of the L_MAC () function converted into a vector instruction according to an embodiment of the present invention, and FIG. 11 is a diagram illustrating a hand assembly example of the source code of FIG.
When the addition / subtraction / shift unit A25, addition / subtraction / shift unit B26, MOVE unit A27, and MOVE unit B28 are not equipped with the saturation processing units 25a to 28a, vector instructions cannot be used. For example, the L_MAC () function is executed 40 times. In order to execute only this, it is necessary to repeat the huge function of 36 lines shown in FIG. 18 40 times.

  On the other hand, by adding saturation processing units 25a to 28a to the addition / subtraction / shift unit A25, addition / subtraction / shift unit B26, MOVE unit A27, and MOVE unit B28, as shown in FIG. And the shift operation with a saturation function can be executed in one cycle. Therefore, as shown in FIG. 10, the L_MAC () function can be converted into a vector instruction. For example, when the L_MAC () function is executed 40 times, as shown in FIG. It is sufficient to issue vector instructions five times. As a result, in the example of FIG. 10, the speed was improved by about 20 times compared to the case where the L_MAC () function was executed without using a vector instruction.

As a result, while maintaining consistency with the instruction set of an existing vector processor, the amount of instruction change can be reduced as much as possible to increase the speed of the L_MAC () function, which is realized on the vector processor 100 of the AMR codec. It becomes possible.
In the example of FIG. 11, the commented-out NOP is written four times at a time. However, other instructions can be written here if the unit does not require interlock. For example, the product-sum value may be constantly checked during the product-sum operation, and if the value is saturated, the processing may be immediately shifted to another process.

FIG. 12 is a diagram showing an example of a method for specifying the saturation function of the status register according to an embodiment of the present invention.
When the saturation function is turned on / off, for example, an instruction as shown in FIG. 12 can be inserted into the source code. Thereby, on / off of the saturation function can be designated in the source code, and the programmer can designate on / off of the saturation function. In the example of FIG. 12, an inline assembler is used, but it may be described directly in an assembler file.

FIG. 13 is a diagram illustrating an example of a VV bit detection function according to an embodiment of the present invention, and FIG. 14 is a diagram illustrating an example of an overflow detection method according to an embodiment of the present invention.
In FIG. 13, in order to confirm the presence or absence of overflow, source code defining an instruction Test_Overflow () is written in a header file. Then, as shown in FIG. 14, the inline assembler shown in FIG. In this method, when the global variable “Overflow” is already 1 or the VV bit is 1, “Overflow” can be set to 1, so that overflow can be detected without conflicting with the variable Overflow of the original source code.

FIG. 15 is a diagram showing a list of addition / subtraction instructions with a saturation function that can be executed by the addition / subtraction / shift unit A25 and the addition / subtraction / shift unit B26 of FIG.
In FIG. 15, in the ADDW instruction, the words of the registers src1 and src2 are added. In the ADDW instruction, the addition result can be arithmetically shifted to the right by the number of bits specified by shamt. In the ADD2H instruction, addition is performed for each of the upper and lower halfwords of the registers src1 and src2. In the ADD2H instruction, the addition result can be arithmetically shifted to the right by the number of bits specified by the shamt.

  In the SUBW instruction, the word of the register src2 is subtracted from the register src1. In the SUBW instruction, the addition result can be arithmetically shifted to the right by the number of bits specified by shamt. In the SUB2H instruction, subtraction is performed from the register src1 for each of the upper and lower halfwords of the register src2. In the SUB2H instruction, the subtraction result can be arithmetically shifted to the right by the number of bits specified by shamt.

  In the ADSB2H instruction, addition / subtraction is performed for each of the upper and lower halfwords of the register src1 and the register src2. Here, addition is performed on the lower halfword and subtraction is performed on the upper halfword. In the ADSB2H instruction, the arithmetic right shift of the addition / subtraction result can be performed by the number of bits specified by shamt. In the SBAD2H instruction, addition / subtraction is performed for each of the upper and lower halfwords of the registers src1 and src2. Here, subtraction is performed on the lower halfword and addition is performed on the upper halfword. In the SBAD2H instruction, the arithmetic right shift of the addition / subtraction result can be performed by the number of bits specified by the shamt.

In the ADDWI instruction, the word of the register src1 and the 10-bit extension code immediate is added. In the ADD2HI instruction, the 10-bit extension code “immediate” is added to the upper and lower halfwords of the register src1.
In the ADD2W instruction, a dual unit instruction of the ADDW instruction is issued. In the ADD4H instruction, a dual unit instruction of the ADD2H instruction is issued. In the SUB2W instruction, a dual unit instruction of the SUBW instruction is issued. In the SUB4H instruction, a dual unit instruction of the SUB2H instruction is issued. In the ADSB4H instruction, a dual unit instruction of the ADSB2H instruction is issued. In the SBAD4H instruction, a dual unit instruction of the SBAD2H instruction is issued. In the ADD2WI instruction, a dual unit instruction of the ADDWI instruction is issued. In the ADD4HI instruction, a dual unit instruction of the ADD2HI instruction is issued.

  Here, in the instruction 1), when the S bit of the status register 22 is “1”, the operation result before the shift obtained by the addition / subtraction / shift unit A25 or the addition / subtraction / shift unit B26 is a signed 32-bit value. To be interpreted. If the pre-shift operation result obtained by the addition / subtraction / shift unit A25 or the addition / subtraction / shift unit B26 overflows, it is saturated to “0x7FFFFFFF”, and the addition / subtraction / shift unit A25 or addition / subtraction / shift unit B26 When the operation result before shifting obtained in this way is underflowing, it is saturated to “0x80000000”. When the saturation processing is performed, “1” is set to the VV bit of the status register 22. Note that the 1) ′ instruction does not shift.

  Further, in the instruction 2), when the S bit of the status register 22 is “1”, the calculation result before the shift obtained by the addition / subtraction / shift unit A25 or the addition / subtraction / shift unit B26 is signed 16 Interpreted as bit value. When the pre-shift operation result obtained by the addition / subtraction / shift unit A25 or the addition / subtraction / shift unit B26 overflows, it is saturated to “0x7FFF”, and the addition / subtraction / shift unit A25 or addition / subtraction / shift unit B26 When the operation result before shifting obtained underflows underflows, it is saturated to “0x8000”. When the saturation processing is performed, “1” is set to the VV bit of the status register 22. Note that the 2) ′ instruction does not shift.

FIG. 16 is a diagram showing a list of shift instructions with a saturation function that can be executed by the MOVE unit A27 and the MOVE unit B28 of FIG.
In FIG. 16, in the SAW instruction, the word of the register src1 is arithmetically shifted by the number of bits specified by shamt. In the SA2H instruction, an arithmetic shift is performed by the number of bits specified by shamt for each of the upper and lower halfwords of the register src1. In the SAVW instruction, the word of the register src1 is arithmetically shifted by the number of bits specified by the register src2. In the SA2W instruction, the two words of the two registers are arithmetically shifted by the number of bits specified by the shamt. In the SA4H instruction, the upper and lower halfwords of the two registers are arithmetically shifted by the number of bits specified by shamt. In the SAV2W instruction, the word of the register src1 is arithmetically shifted by the number of bits designated by the register src2 in two parallel.

  Here, in the instruction 1), in the case of left shift, when the 32-bit value of the operation result obtained by the MOVE unit A27 or the MOVE unit B28 overflows, it is saturated to “0x7FFFFFFF”, and the MOVE unit A27 or When the 32-bit value of the calculation result obtained by the MOVE unit B28 is underflowing, it is saturated to “0x80000000”. When the saturation processing is performed, “1” is set to the VV bit of the status register 22.

  In the case of the instruction 2), in the case of left shift, if the upper or lower 16-bit value of the operation result obtained by the MOVE unit A27 or the MOVE unit B28 overflows, it is saturated to “0x7FFF”, and the MOVE When the upper or lower 16-bit value obtained by the unit A27 or the MOVE unit B28 is underflowing, it is saturated to “0x8000”. When the saturation processing is performed, “1” is set to the VV bit of the status register 22.

1 is a block diagram showing a schematic configuration of a computer system according to an embodiment of the present invention. FIG. 2 is a block diagram showing a schematic configuration of the vector processor 100 of FIG. 1. FIG. 3 is a block diagram showing a schematic configuration of a register file 23 in FIG. 2. It is a figure which shows the data structure of the vector command which concerns on one Embodiment of this invention. The figure which shows the vector addition process of the vector processor 100 of FIG. The block diagram which shows schematic structure of the saturation process parts 25a and 26a of FIG. The block diagram which shows schematic structure of the saturation process parts 27a and 28a of FIG. FIG. 3 is a block diagram showing pipeline processing of the vector processor 100 of FIG. 2. The figure which shows the hand assembly example of the L_MAC () function which concerns on one Embodiment of this invention. The figure which shows the usage example of L_MAC () function made into vector instruction. The figure which shows the hand assembly example of L_MAC () function made into vector instruction. The figure which shows an example of the designation | designated method of the saturation function of a status register. The figure which shows an example of the detection function of the VV bit which concerns on one Embodiment of this invention. The figure which shows an example of the detection method of the overflow which concerns on one Embodiment of this invention. The figure which shows the list of the addition / subtraction instruction with a saturation function which concerns on one Embodiment of this invention. The figure which shows the list of the shift instruction with a saturation function which concerns on one Embodiment of this invention. The figure which shows an example of the source code of a L_MAC () function. The figure which shows the compilation example of a L_MAC () function.

Explanation of symbols

100 vector processor, 21 instruction decoder, 21a branch control unit, 22 status register, 23 register file, 24 multiplication unit, 25 addition / subtraction / shift unit A, 26 addition / subtraction / shift unit B, 27 MOVE unit A, 28 MOVE unit B, 25a ˜28a Saturation processing unit, 29 ALU, 30, address generation unit X, 31, address generation unit Y, 32, address generation unit Z, B1-B4 bus, 110 main memory, 111 program text area, 112 initialized data area , 113 Uninitialized data area, 114 heap area, 115 stack area, 120 input section, 130 output section, 140 communication section, 200 assembly source code, 210 assembler, 220 linker, 230 Line program, 240 program loader, A1 adder, VR0-VR2 vector register

Claims (9)

A vector adder for performing vector addition processing;
An arithmetic processing apparatus, comprising: a saturation processing unit that is mounted on the vector adder and performs a saturation process based on an addition result obtained by the vector adder. A status register for storing a saturation designation flag for enabling the saturation processing;
The arithmetic processing apparatus according to claim 1, wherein the saturation processing unit performs saturation processing based on a reference result of the saturation designation flag. A vector shift computing unit for performing vector shift computing processing;
An arithmetic processing apparatus, comprising: a saturation processing unit mounted on the vector shift computing unit and performing a saturation processing based on a shift computation result obtained by the vector shift computing unit.   When the shift operation performed by the vector shift computing unit is an arithmetic shift, the saturation processing unit unconditionally executes saturation processing according to the shift operation result obtained by the vector shift computing unit, and The saturation processing is not executed regardless of whether or not the shift operation result obtained by the vector shift operation unit overflows when the shift operation performed by the shift operation unit is a logical shift. 3. The arithmetic processing apparatus according to 3. A vector multiplier for performing vector multiplication processing;
A vector adder for performing vector addition processing;
A first saturation processing unit mounted on the vector adder and performing saturation processing based on the addition result obtained by the vector adder;
A vector shift computing unit for performing vector shift computing processing;
An arithmetic processing apparatus, comprising: a second saturation processing unit that is mounted on the vector shift computing unit and performs saturation processing based on a shift result obtained by the vector shift computing unit.   The arithmetic processing apparatus according to claim 1, wherein the saturation processing unit sets an overflow flag in the status register based on presence or absence of the saturation processing. A vector multiply instruction that does not implement the saturation function;
A vector addition instruction with a saturation function implemented;
An arithmetic processing program for causing a computer to execute a vector shift instruction in which a saturation function is implemented.   8. The arithmetic processing program according to claim 7, causing a computer to execute an instruction designating on / off of a saturation function of the vector addition instruction.   The arithmetic processing program according to claim 7 or 8, wherein a computer executes a detection function for detecting whether or not an overflow of a result of addition by the vector addition instruction or a result of shift operation by the vector shift instruction is overflowed.

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