JP2006166415A - High-gain rectifier circuit and rfid tag using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-gain rectifier circuit capable of reducing power consumption and elemental variations due to the driving of the rectifier circuit, and to provide a RFID (Radio Frequency Identification) tag that uses the high-gain rectifier circuit. <P>SOLUTION: The high gain rectifier circuit is composed of a rectifier circuit 200 and a bias-setting circuit 100. The rectifier circuit 200 comprises is provided with: an MOS transistor M1, in which a capacitor C12 is connected between a gate terminal and a source terminal, as a rectifying element; and a switching unit, which supplies a predetermined bias voltage V<SB>T</SB>to the capacitor C12 in response to a control signal V<SB>1</SB>. The bias-setting circuit 100 is provided with an MOS transistor M30 configured to imitate the MOS transistor M1; a capacitor C32 configured to simulate the capacitor C12; and a dummy switching unit, which supplieds the bias voltage V<SB>T</SB>to the capacitor C32, in response to the control signal V<SB>1</SB>, and generates the control signal V<SB>1</SB>based on a potential V<SB>0</SB>of the capacitor C32. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a high gain rectifier circuit including, as a rectifier, a MOS transistor having a capacitor connected between a gate terminal and a source terminal, and an RFID (Radio Frequency Identification) tag using the high gain rectifier circuit.

  The rectifier circuit converts an AC signal into a DC signal by using the rectification characteristics of the diode. When the rectifier circuit is realized by a semiconductor integrated circuit, a so-called diode-connected MOS transistor in which a source terminal and a gate terminal are connected to each other is usually used as a rectifier diode. For example, in a rectifier diode using an NMOS transistor that is isolated from the substrate by a triple well, the drain terminal and the source terminal are each connected to the N region, and the source terminal is connected to the P well below the transistor. Also connected to the gate terminal. Thereby, a diode element in which a PN connection is formed between the source terminal and the drain terminal is realized.

  In recent years, RFID tags have attracted attention because of their wide application fields. In this RFID tag, a rectifier circuit is essential. The RFID tag generates a DC power source for driving an integrated circuit in the RFID tag and demodulates a data signal from an AC current induced in the antenna. A rectifier circuit is required for these processes.

  For example, configurations disclosed in Patent Document 1 and Non-Patent Document 1 are known as rectifier circuits used in RFID tags. However, these configurations also use the diode-connected MOS transistor described above. However, when the threshold value of the MOS transistor is smaller than the threshold value of the PN junction, the rectification characteristic is determined by the characteristic of the MOS transistor and shows a characteristic equivalent to the rectification characteristic of a diode having the threshold value of the MOS transistor as the threshold value of the PN junction.

  In order to develop rectification characteristics in the diode, it is necessary to apply a voltage higher than the threshold of the PN junction or a voltage higher than the threshold of the MOS transistor between the PN connection terminals of the diode-connected MOS transistor. This voltage application can be realized, for example, by connecting a capacitor between the gate and the source of a MOS transistor and holding the voltage not less than 0 and not more than the threshold value (hereinafter referred to as a bias voltage). Thus, even when an AC signal having an effective value less than the bias voltage is input to the rectifier circuit, the signal can be rectified. This means that the RFID tag can receive a weak signal transmitted from the reader / writer and can increase the communicable distance between the reader / writer. The expansion of the communication distance facilitates simultaneous recognition of a plurality of RFID tags by one reader / writer, and widens the application range of the RFID tags.

JP 2002-152080 A M. Usami et al., "Powder LSI: An ultra small RF identification chip for individual recognition applications", ISSCC Dig. Tech. Papers, Feb 2003, pp.398-399

  However, since the electric charge stored in the capacitor is discharged by the leakage current of the MOS transistor to which the capacitor is connected, the voltage between the capacitors decreases with time. This means that the size of the AC signal that can be rectified increases. In other words, the conversion gain of the rectifier circuit is reduced. Therefore, it is necessary to periodically transmit a control signal for charging the capacitor to the rectifier circuit. However, if the control signal is periodically generated by a counter or the like, the capacitor charging operation is repeated more than necessary. In particular, in a device such as an RFID tag in which a reduction in power consumption is an important design factor, it is desirable to avoid such wasteful power consumption.

  Further, the above bias voltage is preferably about the threshold voltage of the MOS transistor to be biased. This is because the current flowing through the MOS transistor flows backward above the threshold voltage, thereby reducing the gain of the rectifier circuit. However, since the threshold voltage of the MOS transistor varies depending on the manufacturing variation of the MOS transistor, if the bias voltage is simply fixed to a predetermined value, the gain of the rectifier circuit becomes small due to the manufacturing variation.

  The present invention has been made in view of the above, and provides a high-gain rectifier circuit capable of reducing the influence of power consumption and element variations accompanying driving of the rectifier circuit, and an RFID tag using the same. Objective.

  In order to solve the above-described problems and achieve the object, a high gain rectifier circuit according to the present invention uses, as a rectifying element, a first MOS transistor in which a first capacitor is connected between a gate terminal and a source terminal. A rectifier circuit including a switching unit that supplies a predetermined bias voltage to the first capacitor based on a control signal, a second MOS transistor that simulates the first MOS transistor, and the first capacitor And a dummy switching unit that supplies the bias voltage to the second capacitor based on the control signal, and generates the control signal based on the potential of the second capacitor. And a bias setting circuit.

  The RFID tag according to the present invention includes the above-described high gain rectifier circuit.

  In the high gain rectifier circuit and the RFID tag according to the present invention, useless charging operation for biasing the MOS transistor constituting the rectifier unit is reduced, and a reduction in power consumption can be realized. Further, rectification always having a gain of a certain value or more can be realized without being affected by manufacturing variations between high gain rectifier circuits.

  Embodiments of a high gain rectifier circuit and an RFID tag using the same according to the present invention will be described below in detail with reference to the drawings.

(Embodiment 1)
A high gain rectifier circuit according to a first embodiment of the present invention includes a MOS transistor (hereinafter referred to as a simulated MOS transistor) that simulates a MOS transistor (hereinafter referred to as a rectified MOS transistor) that functions as a rectifier element, and simulates the same. The capacitor connected to the rectifying MOS transistor is charged at an optimal timing by monitoring the potential of the capacitor connected between the gate terminal and the source terminal of the MOS transistor.

  FIG. 1 is a circuit diagram illustrating a high gain rectifier circuit according to a first embodiment. As shown in FIG. 1, the high gain rectifier circuit according to the first embodiment includes a rectifier circuit 200 and a bias setting circuit 100.

  The rectifier circuit 200 includes a rectifier that rectifies an input AC signal, and a switching unit that applies a predetermined potential to a capacitor constituting the rectifier.

  The rectifying unit includes NMOS transistors M1 and M2 connected in series. In the NMOS transistor M1, the back gate terminal and the source terminal are connected, and the drain terminal is connected to the plus terminal T1. A capacitor C12 is connected between the gate terminal and the source terminal. With this connection configuration, the NMOS transistor M1 functions as a high-gain rectifying element because it is biased by the voltage across the capacitor C12.

  Similarly, in the NMOS transistor M2, the back gate terminal and the source terminal are connected, and the source terminal is connected to the minus terminal T2. A capacitor C22 is connected between the gate terminal and the source terminal. The NMOS transistor M2 also functions as a high-gain rectifying element, like the NMOS transistor M1, and is biased by the voltage across the capacitor C22.

  The source terminal of the NMOS transistor M1 and the drain terminal of the NMOS transistor M2 are connected to each other, and one end of the capacitor C1 is connected to the connection point. The other end of the capacitor C1 is connected to a signal input terminal TA to which an AC signal is input. This capacitor C1 functions as a coupling capacitance. In particular, when the high gain rectifier circuit according to this embodiment is used in an RFID tag, the capacitor C1 is connected to an antenna (for example, a loop antenna) and functions as a series resonant capacitor.

  A capacitor C2 is connected between the drain terminal of the NMOS transistor M1 and the source terminal of the NMOS transistor M2. The signal half-wave rectified by the NMOS transistors M1 and M2 is smoothed by the capacitor C2. By this smoothing, a DC voltage can be taken out from both ends of the capacitor C2, that is, between the plus terminal T1 and the minus terminal T2.

  The NMOS transistors M1 and M2 are formed in a triple well structure and are isolated from the substrate. Each source terminal is connected to a P-type well below the NMOS transistor, and each drain terminal is connected to the N region, and operates as a rectifying element unit that simulates a PN connection by a MOS transistor.

On the other hand, the switching unit, a control signal based on V _1, gives a voltage supplied from the bias voltage source 210 to capacitors C12 and C22 above. The voltage applied to the capacitors C12 and C22 is a voltage (hereinafter referred to as a bias voltage V _T ) that is lower than a threshold voltage necessary for the NMOS transistors M1 and M2 to exhibit rectifying characteristics. It is a range. This bias voltage V _T is particularly preferably a value in the vicinity of the threshold voltage (for example, 0.6 V). As a result, the NMOS transistors M1 and M2 can rectify even when an AC signal having an effective value equal to or lower than the above-described threshold voltage is input to the signal input terminal TA. For example, when the bias voltage V _T is 0.6 V, an AC signal having an effective value of about 100 mV can be rectified.

  Specifically, as shown in FIG. 1, the switching unit includes a plurality of NMOS transistors M11 to M14, M21 to M24 functioning as transfer gates, inverters INV1 and INV2, and a bias voltage source 210. The The NMOS transistors M11 and M12 are connected in series and are arranged on a first plus line connected to the positive terminal of the bias voltage source 210. The first plus line is connected from the positive terminal of the bias voltage source 210 to one end of the capacitor C12 and the gate terminal of the NMOS transistor M1 via the NMOS transistors M12 and M11. NMOS transistors M13 and M14 are also connected in series and arranged on a first negative line connected to the negative terminal of the bias voltage source 210. The first negative line is connected from the negative terminal of the bias voltage source 210 to the other end of the capacitor C12 and the source terminal of the NMOS transistor M1 through the NMOS transistors M14 and M13. A capacitor C11 is connected between a connection point between the source terminal of the NMOS transistor M11 and the drain terminal of the NMOS transistor M12 and a connection point between the source terminal of the NMOS transistor M13 and the drain terminal of the NMOS transistor M14. In other words, the capacitor C11 is connected between the first plus line and the first minus line.

  The NMOS transistors M21 and M22 are connected in series and are arranged on a second plus line connected to the positive electrode of the bias voltage source 210. The second plus line is connected from the positive terminal of the bias voltage source 210 to one end of the capacitor C22 through the NMOS transistors M22 and M21 and to the gate terminal of the NMOS transistor M2. NMOS transistors M23 and M24 are also connected in series and are arranged on a second negative line connected to the negative electrode of bias voltage source 210. The second minus line is connected to the other end of the capacitor C22 and the source terminal of the NMOS transistor M2 via the NMOS transistors M24 and M23. A capacitor C21 is connected between a connection point between the source terminal of the NMOS transistor M21 and the drain terminal of the NMOS transistor M22 and a connection point between the source terminal of the NMOS transistor M23 and the drain terminal of the NMOS transistor M24. In other words, the capacitor C21 is connected between the second plus line and the second minus line.

  The gate terminals of the NMOS transistors M11, M13, M21, and M23 are connected to the output terminal of the inverter INV1. The gate terminals of the NMOS transistors M12, M14, M22, and M24 are connected to the input terminal of the inverter INV1. The input terminal of the inverter INV1 is connected to the output terminal of the inverter INV2.

The operation of the switching unit configured as described above is as follows. During the period in which the control signal V ₁ input to the inverter INV 2 indicates the logic level “L”, the NMOS transistors M 12, M 14, M 22, and M 24 are turned on, and the capacitors C 11 and C 21 are biased by the bias voltage source 210. It is charged to be equal to V _T. Meanwhile, since the output of the inverter INV1 indicates the logic level “L”, the NMOS transistors M11, M13, M21, and M23 are OFF, and the capacitors C12 and C22 are not charged. On the other hand, during the period in which the control signal V ₁ is at the logic level “H”, the NMOS transistors M12, M14, M22, and M24 are turned off, and the NMOS transistors M11, M13, M21, and M23 are turned on, so The charged electric charge is supplied to the capacitor C12, and the electric charge charged in the capacitor C21 is supplied to the capacitor C22. As a result, the bias voltage V _T is applied between the gate and source of the NMOS transistor M1 and between the gate and source of the NMOS transistor M2.

A control signal V ₁ input to the inverter INV 2 of the rectifier circuit 200 is generated by the bias setting circuit 100. The bias setting circuit 100 includes a dummy rectification unit, a dummy switching unit, and a control signal generation unit. The dummy rectifier unit includes a circuit obtained by duplicating a part of the rectifier unit of the rectifier circuit 200, and includes an NMOS transistor M30 having the same characteristics as the NMOS transistor M1 or M2, and a capacitor C32 corresponding to the capacitor C12 or C22. In the NMOS transistor M30, the back gate terminal and the source terminal are connected, and the source terminal and the drain terminal are both grounded. Further, the capacitor C32 is connected between the gate terminal and the source terminal of the NMOS transistor M30. That is, the dummy rectifying unit simulates one of the rectifying elements that constitute the rectifying unit of the rectifying circuit 200.

The dummy switching unit has a configuration corresponding to a circuit for supplying the bias voltage V _T to either one of the capacitors C12 and C22 of the rectifying unit among the circuits configuring the switching unit of the rectifying circuit 200. In FIG. 1, a circuit including NMOS transistors M31 to M34, a capacitor C31, an inverter INV11, and a bias voltage source 110 corresponds to a dummy switching unit.

Specifically, the NMOS transistors M31 and M32 are connected in series and arranged on the plus line connected to the positive terminal of the bias voltage source 110. This plus line is connected to one end of the capacitor C32 and the gate terminal of the NMOS transistor M30 via the NMOS transistors M32 and M31. NMOS transistors M33 and M34 are also connected in series and arranged on the negative line connected to the negative terminal of the bias voltage source 110. The minus line is connected to the other end of the capacitor C32 and the source terminal of the NMOS transistor M30 via the NMOS transistors M34 and M33. A capacitor C31 is connected between a connection point between the source terminal of the NMOS transistor M31 and the drain terminal of the NMOS transistor M32 and a connection point between the source terminal of the NMOS transistor M33 and the drain terminal of the NMOS transistor M34. The gate terminals of the NMOS transistors M31 and M33 are connected to the input terminal of the inverter INV11. The gate terminals of the NMOS transistors M32 and M34 are connected to the output terminal of the inverter INV11. In terms of the rectifier circuit 200, for example, a circuit for supplying a bias voltage V _T to the capacitor C12, that is, NMOS transistors M11 to M14, a capacitor C11, inverters INV1 and INV2, and a bias voltage source 210. This corresponds to the circuit configuration. In particular, the bias voltage source 110 supplies the same bias voltage V _T as the bias voltage source 210.

The control signal generation unit monitors the potential of the capacitor C32 of the dummy rectification unit, and generates the control signal V ₁ based on the monitoring result. In FIG. 1, a circuit including an inverter INV12, a reference voltage source 120, and an error amplifier 130 corresponds to a control signal generation unit. The error amplifier 130 has a positive phase input terminal connected to the gate terminal of the NMOS transistor M30 of the dummy rectification unit, and a negative phase input terminal connected to the positive terminal of the reference voltage source 120. To be precise, the positive phase input terminal of the error amplifier 130 is connected to one end (plus line side) of the capacitor C32. Here, it represents one end of the potential of the capacitor C32 and V _0. The reference voltage source 120 generates a reference voltage V _T −V _X. The voltage V _X will be described later. With the above connection configuration, the error amplifier 130 outputs the error voltage V _E corresponding to the difference obtained by subtracting the reference voltage V _T −V _X from the potential V ₀ at one end of the capacitor C32.

  FIG. 2 is a circuit diagram illustrating an example of the error amplifier 130. The error amplifier shown in FIG. 2 includes PMOS transistors M121 and M122 that function as load transistors, NMOS transistors M123 and M124 that form a differential pair, and a constant current source 121. In particular, the PMOS transistors M121 and M122 include The respective gate terminals and drain terminals are connected so as to provide positive feedback. In FIG. 2, the gate terminal of the NMOS transistor M124 corresponds to the positive phase input terminal IN1 of the error amplifier 130, and the gate terminal of the NMOS transistor M123 corresponds to the negative phase input terminal IN2 of the error amplifier 130. The output terminal OUT connected to the drain of the NMOS transistor M124 corresponds to the output terminal of the error amplifier 130. The error amplifier 130 may be a differential amplifier other than the type shown in FIG. 2. For example, a load transistor may be configured by a current mirror pair that does not apply positive feedback.

The output terminal of the error amplifier 130 is connected to the input terminal of the inverter INV12. Thus, when the error voltage V _E output from the error amplifier 130 becomes equal to or higher than a predetermined level, a signal of logic level “L” is output from the inverter INV12, and when the error voltage V _E becomes lower than the predetermined level. In addition, a signal of logic level “H” is output from the inverter INV12. The signal output from the inverter INV12 is a control signal V ₁ described above. In other words, the control signal generator rectifies the potential of the capacitor C32 of the dummy rectifier as a control signal V ₁ having a logic level “L” if the potential is equal to or higher than the potential V _X dropped from the bias voltage V _T. Output to the circuit 200. An output terminal of the inverter INV12 is connected to the input terminal of the inverter INV11, a control signal V ₁ was inputted to the dummy switching unit. Thereby, the dummy rectification unit and the dummy switching unit simulate the operation of the rectification unit and the switching unit of the rectifier circuit 200.

As described above, in the rectifier circuit 200 and the bias setting circuit 100, it is necessary to generate a constant voltage called the bias voltage V _T in the bias voltage source 210 and the bias voltage source 110, respectively. However, there is a possibility that the bias voltage V _T does not show a desired value due to manufacturing variations of electronic elements constituting the bias voltage source. This is also true for the reference voltage source 120.

3A to 3D are circuit diagrams illustrating examples of the bias voltage source or the reference voltage source used in the high gain rectifier circuit according to the present embodiment. The voltage source shown in FIG. 3A includes an NMOS transistor M101 having a gate terminal and a drain terminal connected, and a constant current source 111 that generates a weak current I _BB from the power supply voltage V _DD . Output terminal T100 is connected to the drain terminal of the NMOS transistor M101, a gate of the NMOS transistor M101 produced by the current I _BB - it outputs a source voltage. Since the gate-source voltage substantially matches the threshold voltage of the NMOS transistor M101, this voltage source can be used as the bias voltage sources 210 and 110 that generate the bias voltage V _T. This is based on the theory that the characteristic of a MOS transistor is generally expressed as I _D = β (V _GS −V _th ) ^2, and when I _D is reduced, the gate-source voltage V _GS becomes almost the threshold voltage V _th. Based on.

In particular, the NMOS transistor M101 is taken from the semiconductor wafer on which the NMOS transistors M1 and M2 of the rectifier circuit 200 and the NMOS transistor M30 of the bias setting circuit 100 are formed, and therefore has substantially the same characteristics as the NMOS transistors M1, M2, and M30. Indicates. That is, the generated bias voltage V _T substantially matches the threshold voltage of the NMOS transistors M1 and M2 constituting the rectifying unit of the rectifying circuit 200 at least in the same high gain rectifying circuit. In other words, it is not necessary to set the bias voltage V _T as an absolute value, and the operation of the high gain rectifier circuit is not affected by manufacturing variations between the high gain rectifier circuits. Since β is a function of dimensions, if the value is increased, the gate-source voltage V _GS can be made substantially equal to the reference voltage V _T -V _X , and the voltage shown in FIG. The source can also be used as the reference voltage source 120. The voltage V _X is, for example, 50 mV or less.

The voltage source shown in FIG. 3-2 includes a constant current source 111 in which two NMOS transistors M111 and M112 having a gate terminal and a drain terminal connected to each other generate a weak current I _BB as in FIG. 3-1. It is prepared for. The NMOS transistors M111 and M112 are connected in cascade. Output terminal T100 is connected to the drain terminal of the NMOS transistor M112, a gate of the NMOS transistor M112 produced by the current I _BB - source voltage and the gate of the NMOS transistor M111 - outputting the sum of the source voltage. In particular, the threshold voltages of the NMOS transistors M111 and M112 are smaller than the threshold voltages of the NMOS transistors M1 and M2 of the rectifier circuit 200 and the NMOS transistor M30 of the bias setting circuit 100, and the sum of the gate-source voltages described above is biased. The value is equal to the voltage V _T or the reference voltage V _T −V _X. As described above, even if the voltage source uses a plurality of MOS transistors whose threshold voltage V _th is smaller than that of the NMOS transistors M1, M2, and M30, the bias voltage sources 210 and 110 or the reference voltage source 120 that are not affected by manufacturing variations. Can be used. However, in this case, since the threshold voltages are not the same, the manufacturing variation becomes larger than when the same threshold voltage is used.

The voltage source shown in FIG. 3C is the same as the voltage source shown in FIG. 3B. The first output terminal T102 is taken out from the drain terminal of the NMOS transistor M112, and the second output terminal T101 is taken out from the drain terminal of the NMOS transistor M111. This is an example. In this example, the bias voltage V _T is output from the first output terminal T102 and the reference voltage V _T −V _X is output from the second output terminal T101 by adjusting the respective β and threshold voltages of the NMOS transistors M111 and M112. Can be output.

The voltage source shown in FIG. 3-4 allows the current of the current source 111 to flow through the NMOS transistor M113 and the resistor R1 + R2. This is another circuit example in which the first output terminal T102 is set to the bias voltage V _T and the second output terminal T101 is set to the reference voltage V _T −V _X. Since the current flowing through the NMOS transistor M113 is small, a voltage between the gate and the source of the NMOS transistor M113, that is, a voltage V _T is applied to the resistor R1 + R2. A voltage R2 / (R2 + R1) times this voltage is generated at T101. By adjusting the resistors R1 and R2, a voltage of V _T −V _X can be generated.

Hereinafter, the operation of the bias setting circuit 100 will be described. FIG. 4 shows the potential V ₀ at one end of the capacitor C32, the error voltage V _E output from the error amplifier 130, the control signal V ₁ output from the inverter INV12, and the signal V ₂ output from the inverter INV11. It is a figure which shows each timing chart.

During a period in which the potential V ₀ is greater than the reference voltage V _T −V _X (until time t ₀ ), the error amplifier 130 outputs a positive error voltage V _E saturated to a predetermined value (first phase). This positive error voltage V _E is an input signal having a logic level “H” for the inverter INV12. Thus, in that period, the inverter INV12 outputs a control signal V ₁ of the logic level "L", the inverter INV11 outputs a signal V ₂ of the logic level "H". As a result, the NMOS transistors M32 and M34 are turned on, the bias voltage V _T of the bias voltage source 110 is applied to the capacitor C31, and the potential of the capacitor C31 becomes the bias voltage V _T.

Since the capacitor C32 is discharged by the leakage current of the NMOS transistor M30, the potential V ₀ gradually decreases and finally becomes smaller than the reference voltage V _T −V _X (second phase). That is, the error voltage V _E output from the error amplifier 130 gradually decreases from a positively saturated value, and finally becomes an input signal of logic level “L” for the inverter INV12 (time t ₁ : third phase ). Thus, the inverter INV12 outputs a control signal V ₁ of the logic level "H", the inverter INV11 outputs a signal V ₂ of the logic level "L". As a result, the NMOS transistors M31 and M33 are turned ON, and the potential V _{T of the} capacitor C31 is applied to the capacitor C32. That is, the potential V _{0 of the} capacitor C32 substantially coincides with the potential V _T higher than the reference voltage V _T −V _X , and the first phase state described above is obtained. Thereafter, the first to third phases are repeated.

In repeating phases described above, when attention is paid to the transition of the control signal V _1, the control signal V ₁ was, has become a regular occurrence pulse. The rectifier circuit 200 operates in synchronization with the control signal V ₁ , and the dummy rectifier unit and the dummy switching unit of the bias setting circuit 100 simulate the rectifier unit and the switching unit of the rectifier circuit 200. Therefore, the bias setting circuit 100 can charge the capacitors C12 and C22 of the rectifier unit of the rectifier unit 200 at an optimum timing without waste, and the NMOS transistors M1 and M2 constituting the rectifier unit are always at a voltage higher than a certain value. Can be biased. In other words, the gain of the rectifier circuit 200 can always be maintained above a certain value.

  In the above example, an NMOS transistor is used as the MOS transistor, but a PMOS transistor may be used.

As described above, according to the high gain rectifier circuit according to the first embodiment, the capacitors C12 and C22 that bias the NMOS transistors M1 and M2 of the rectifier circuit 200 are indirectly monitored by the bias setting circuit 100, and Based on the monitoring result, the control signal V ₁ for instructing the charging timing of the capacitors C12 and C22 is generated, so that useless charging operation is reduced and power consumption can be reduced. The bias voltage V _T applied to the capacitors C12 and C22 and the reference voltage V _T −V _X used in the bias setting circuit 100 are the threshold values of another NMOS transistor designed in consideration of the characteristics of the NMOS transistors M1 and M2. Since it is generated based on the voltage, it is possible to realize rectification that always has a gain of a certain value or more without being affected by manufacturing variations of the high gain rectifier circuit.

(Embodiment 2)
The high gain rectifier circuit according to the second embodiment is characterized in that an initial setting function is added to the high gain rectifier circuit according to the first embodiment.

In the bias setting circuit 100 shown in FIG. 1, in the initial state of the high gain rectifier circuit, the potential of the capacitor C32 may be sufficiently smaller than the reference voltage V _T −V _x . In this case, even if the charge of the capacitor C31 is transferred to the capacitor C32, the potential V _{O of the} capacitor C32 may still be smaller than the reference voltage V _T −V _x . That is, the operation based on the repetition phase shown in FIG. 4 does not shift to the third phase described above, and the pulse of the control signal V ₁ is not generated. In order to prevent this state, in the second embodiment, a bias voltage bypass unit that forcibly applies the bias voltage V _T to the capacitor C32 is provided in the bias setting circuit.

  FIG. 5 is a circuit diagram illustrating a bias setting circuit of the high gain rectifier circuit according to the second embodiment. In FIG. 5, parts common to the bias setting circuit 100 shown in FIG.

In the bias setting circuit 300 shown in FIG. 5, the bias voltage bypass unit described above includes NMOS transistors M41 and M42. The NMOS transistor M41 has a source terminal connected to the positive terminal of the bias voltage source 110 and a drain terminal connected to one end (plus line side) of the capacitor C32. The NMOS transistor M42 has a source terminal connected to the negative terminal of the bias voltage source 110 and a drain terminal connected to the other end (minus line side) of the capacitor C32. The gate terminal of the NMOS transistor M41 and the gate terminal of the NMOS transistor M42 are both connected to the initialization terminal T300. The initialization signal _VCNT is input to the initialization terminal T300.

Hereinafter, the operation of the bias setting circuit 300 will be described. FIG. 6 shows a potential V ₀ at one end of the capacitor C32, an error voltage V _E output from the error amplifier 130, a control signal V ₁ output from the inverter INV12, a signal V ₂ output from the inverter INV11, It is a figure which shows each timing chart of the initialization signal _VCNT .

As shown in FIG. 6, when a pulse indicating the initialization signal V _CNT is inputted, that is, in a period (time t ₀ -t ₁ ) in which the initialization signal V _CNT shows the logic level “H”, the NMOS transistor M 41 And M42 are turned ON, and the bias voltage V _T supplied from the bias voltage source 110 is applied to the capacitor C32 without passing through the dummy switching unit. That is, the potential V _{0 of the} capacitor C32 matches the bias voltage V _T. From this state, after the fall of the pulse indicating the initialization signal _VCNT , that is, when the initialization signal _VCNT indicates the logic level “L”, the process proceeds to the first phase described above. During the period (time t ₀ -t ₁ ) in which the potential V _{0 of the} capacitor C32 coincides with the bias voltage V _T , the signal V ₂ output from the inverter INV11 indicates the logic level “H”. The transistors M32 and M34 are turned on, and the bias voltage V _T is also applied to the capacitor C31. This means that the operations of the second and third phases after the first phase are executed.

  The bias voltage bypass unit described above may be provided not only in the bias setting circuit but also in the rectifier circuit. FIG. 7 is a circuit diagram of a rectifier circuit of the high gain rectifier circuit according to the second embodiment. In FIG. 7, the same reference numerals are given to portions common to the rectifier circuit 200 shown in FIG. 1, and the description thereof is omitted.

In the rectifier circuit 400 shown in FIG. 7, the bias voltage bypass unit described above includes NMOS transistors M51 to M54. The NMOS transistor M51 has a source terminal connected to the positive terminal of the bias voltage source 210, and a drain terminal connected to one end (first positive line side) of the capacitor C12. The NMOS transistor M52 has a source terminal connected to the negative terminal of the bias voltage source 210, and a drain terminal connected to the other end (first negative line side) of the capacitor C12. The NMOS transistor M53 has a source terminal connected to the positive terminal of the bias voltage source 210 and a drain terminal connected to one end (second positive line side) of the capacitor C22. The NMOS transistor M54 has a source terminal connected to the negative terminal of the bias voltage source 210 and a drain terminal connected to the other end (second negative line side) of the capacitor C22. The gate terminals of the NMOS transistors M51 to M54 are connected to the initialization terminal T400. The initialization signal _VCNT is input to the initialization terminal T400.

Due to the bias voltage bypass unit of the rectifier circuit 400, the rectifier circuit 400 exhibits the same initial operation as the timing chart shown in FIG. That is, when the initialization signal _VCNT is input, the bias voltage V _T supplied from the bias voltage source 210 is applied to the capacitors C12 and C22 of the rectifying unit and the capacitors C11 and C21 of the switching unit.

The initialization signal V _CNT can be generated by detecting the power source when the high gain rectifier circuit is started up. FIG. 8 is a circuit diagram showing a power supply detection circuit that generates the initialization signal _VCNT . A power supply detection circuit 500 shown in FIG. 8 includes a capacitor C501, a first CMOS inverter constituted by a PMOS transistor M501 and an NMOS transistor M502, a second CMOS inverter constituted by a PMOS transistor M503 and an NMOS transistor M504, And a pull-down resistor R1. One end of the capacitor C501 and the source terminals of the PMOS transistor M501 and the PMOS transistor M503 are connected to the power supply _VDD . The drain terminals of the NMOS transistors M502 and M504 are grounded. The other end of the capacitor C501 is connected to the input terminal of the first CMOS inverter, that is, the gate terminals of the PMOS transistor M501 and the NMOS transistor M502. The output terminals of the first CMOS inverter, that is, the drain terminals of the PMOS transistor M501 and the NMOS transistor M502 are connected to the input terminals of the second CMOS inverter, that is, the gate terminals of the PMOS transistor M503 and the NMOS transistor M504. The output terminals of the second CMOS inverter, that is, the drain terminals of the PMOS transistor M503 and the NMOS transistor M504 are connected to the output terminal from which the initialization signal _VCNT is output. The pull-down resistor R1 is connected between the gate terminal of the NMOS transistor M502 and the ground line.

Hereinafter, an operation of the power supply detection circuit 500 will be described. FIG. 9 is a diagram showing timing charts of the power supply voltage V _DD , the potential V _INT of the other end of the capacitor C501 (the potential of the node N1 in FIG. 8), and the generated initialization signal _VCNT . When the power supply voltage V _DD is generated by starting the high gain rectifier circuit or the like, the capacitor C501 is charged with the rise of the power supply voltage V _DD (until time t ₁ ). During the rise, the potential V _INT of the input terminal of the first CMOS inverter also rises. When the threshold voltage V _th of the NMOS transistor M502 is reached (time t ₀ ), the logic level “H” is set by the first CMOS inverter. "Is recognized as a signal. As a result, the first CMOS inverter outputs a signal having a logic level “L”, and the second CMOS inverter outputs an initialization signal V _CNT having a logic level “H”. After the charging of the capacitor C501 is completed (after time t ₁ ), the potential V _INT gradually decreases to the ground potential via the pull-down resistor R1, and finally becomes smaller than the threshold voltage V _th of the NMOS transistor M502 ( Time t ₂ ). Accordingly, the first CMOS inverter outputs a logic level “H” signal, and the second CMOS inverter outputs a logic level “L” initialization signal _VCNT . With the above operation, the power supply detection circuit 500 can generate the pulsed initialization signal _VCNT when the high gain rectifier circuit is activated.

As described above, according to the high gain rectifier circuit according to the second embodiment, the capacitor C32 of the bias setting circuit 300 to be monitored and the capacitor C31 that applies the bias voltage V _T to the capacitor C32 in the repetitive operation. On the other hand, the bias voltage V _T can be given as an initial value.

(Embodiment 3)
The high-gain rectifier circuit according to the third embodiment is a circuit that includes a plurality of rectifier circuits described in the first or second embodiment and that employs a configuration in which they are cascade-connected. Addressing new concerns arising from First, I will explain the new concerns. Here, the rectifier circuit 200 described in the first embodiment is taken as an example of a rectifier circuit connected in cascade (hereinafter referred to as a cascade rectifier circuit).

  FIG. 10 is a circuit diagram illustrating an example of a cascade rectifier circuit. A cascade rectifier circuit 600 shown in FIG. 10 includes n rectifier circuit blocks 200-1 to 200-n connected in cascade, a bias voltage source 610, inverters INV1 and INV2, a backflow prevention circuit 630, and a battery 660. . Each of the rectifier circuit blocks 200-1 to 200-n includes the above-described rectifier unit and eight NMOS transistors functioning as transfer gates among the components of the rectifier circuit 200 illustrated in FIG. Between adjacent rectifier circuit blocks, the positive terminal of the rectifier of one rectifier circuit block and the negative terminal of the rectifier of the other rectifier circuit block are connected, and two signal lines connected to the gate terminal of the transfer gate group Are shared. The bias power source 610 corresponds to the bias power source 210 illustrated in FIG. 1 and is shared by the rectifier circuit blocks 200-1 to 200-n.

  FIG. 10 specifically shows only the circuit configuration of the lowermost rectifying block 200-1 among the rectifying circuit blocks 200-1 to 200-n. NMOS transistors M1-1, M2-1, M11-1 to M14-1, M21-1 to M24-1, and capacitors C1-1, C2-1, C11-1, C12-1, C21-1, C22- 1 corresponds to the NMOS transistors M1, M2, M11 to M14, M21 to M24 and capacitors C1, C2, C11, C12, C21, and C22 of FIG. Inverters INV1 and INV2 shown in FIG. 10 are also shared by rectifier circuit blocks 200-1 to 200-n and function in the same manner as inverters INV1 and INV2 in FIG.

The battery 660 is a power source that generates a power supply voltage V _DD , and a secondary battery is assumed here. The battery 660 is connected to the plus terminal of the rectification unit of the uppermost rectifier circuit block 200-n via the backflow prevention circuit 630. That is, the voltage rectified by the rectifier circuit blocks 200-1 to 200-n is stored in the battery 660. Note that the backflow prevention circuit 630 is, for example, a diode having a cathode connected to the terminal connected to the battery 660.

  As shown in FIG. 10, the NMOS transistors constituting the rectifiers of the rectifier circuit blocks 200-1 to 200-n are connected in series on the line from the battery 660 to the ground line, and therefore leaks generated in each. The magnitudes of the currents are equal to each other. In other words, there is no difference in the magnitude of the leakage current generated in the rectifier between the rectifier circuit blocks 200-1 to 200-n. Therefore, the bias setting circuit 100 shown in FIG. 1 can also accurately simulate the leakage current of the rectifier generated in the cascade rectifier circuit 600.

Next, in the cascade rectifier circuit 600, attention is paid to the lowermost rectifier circuit block 200-1. Now, assuming that the voltages across the capacitors C12-1 and C22-1 match the bias voltage V _T (defined in the first embodiment) supplied from the bias voltage source 610, the NMOS transistors M11-1, M13-1, M21-1, and M23-1 are OFF. In this state, when a minute AC signal is input to the signal input terminal TA, that is, the connection point between the NMOS transistors M1-1 and M2-1 of the rectifying unit, the connection point is substantially the same as the source terminal of the NMOS transistor M2-1. It shows the same potential, that is, almost the ground potential. Therefore, the potential of the gate terminal of the NMOS transistor M1-1 shows the same value as the voltage V _T across the capacitor C12-1.

The gate terminal of the NMOS transistor M1-1 is because it is connected to the drain terminal of the NMOS transistor M11-1 is one of the transfer gates, also shows the potential V _T drain terminal of the NMOS transistor M11-1. On the other hand, the source terminal of the NMOS transistor M11-1 has the same potential as the positive terminal of the bias voltage source 610, that is, the bias, via the NMOS transistor 12-1 that is turned on by complementary operation with the NMOS transistor M11-1. It corresponds to the voltage V _T. Therefore, no potential difference is generated between the source and drain of the NMOS transistor M11-1, and the leakage current of the NMOS transistor M11-1 is negligible.

  In the same state, the source-drain voltages of the NMOS transistors M13-1, M21-1, and M23-1 are almost zero, and the leakage currents of these NMOS transistors can be ignored. This state is substantially the same for the rectifying block 200-n.

  Next, the state of the uppermost rectifier circuit block will be considered when the input signal is large and the bias voltage source 610 is charged. FIG. 11 shows the same cascade rectifier circuit 600 as FIG. 10, but only the circuit configuration of the uppermost rectifier block 200-n among the rectifier circuit blocks 200-1 to 200-n is specifically shown. In FIG. 11, NMOS transistors M1-n, M2-n, M11-n to M14-n, M21-n to M24-n, capacitors C1-n, C2-n, C11-n, C12-n, C21- n and C22-n correspond to the NMOS transistors M1, M2, M11 to M14 and M21 to M24 and capacitors C1, C2, C11, C12, C21 and C22, respectively, in FIG.

Now, assuming that the voltages at both ends of the capacitors C12-n and C22-n coincide with the bias voltage V _T supplied from the bias voltage source 610, the NMOS transistors M11-n, M13-n, M21-n, M23-n is OFF. In this state, when a large signal that can sufficiently charge the bias voltage source 610 is input to the signal input terminal TA, that is, the connection point between the NMOS transistors M1-n and M2-n of the rectifier, the connection point is the rectifier circuit block. It is substantially equal to the sum of the voltages at both ends of each of the smoothing capacitors C2-1 to C2- (n-1) of 200-1 to 200- (n-1). Since the voltage between the input and output terminals of the backflow prevention circuit 630 is very small, if neglected, the potential at this connection point substantially matches the power supply voltage V _DD to be charged in the battery 660. Therefore, the potential of the gate terminal of the NMOS transistor M1-n has the same value as the voltage V _T + V _{DD obtained} by adding the power supply voltage V _DD to the voltage V _T across the capacitor C12-n.

Since the gate terminal of the NMOS transistor M1-n is connected to the drain terminal of the NMOS transistor M11-n, which is one of the transfer gates, the drain terminal of the NMOS transistor M11-n also exhibits the potential V _T + V _DD . On the other hand, the source terminal of the NMOS transistor M11-n has the same potential as the positive terminal of the bias voltage source 610, that is, the bias, via the NMOS transistor 12-n that is turned on by complementary operation with the NMOS transistor M11-n. It corresponds to the voltage V _T. Therefore, a potential difference V _DD is generated between the source and drain of the NMOS transistor M11-n. This potential difference V _DD becomes a factor for transferring the charge of the capacitor C12-n to the capacitor C11-n. In the same state, the source-drain voltage of the NMOS transistor M13-n is also approximately V _DD , and a leak current flows. Therefore, the capacitor C12-n connected to the NMOS transistor M1-n of the rectifying unit is also discharged by the leakage current of the NMOS transistor M11-n that is the transfer gate. For the same reason, the capacitor C22-n connected to the NMOS transistor M2-n in the rectifying unit is also discharged by the leakage current of the NMOS transistor M21-n as the transfer gate.

  However, the bias setting circuit 100 shown in FIG. 1 does not simulate the generation of leakage current of these transfer gates. That is, the bias setting circuit 100 cannot accurately monitor the potential state of the capacitor in the rectifying unit of the cascade rectifier circuit 600 shown in FIG. The high gain rectifier circuit according to the third embodiment is characterized by including a bias setting circuit that solves this problem.

  FIG. 12 is a circuit diagram of a bias setting circuit constituting the high gain rectifier circuit according to the third embodiment. In FIG. 12, parts common to the bias circuit 100 in FIG. 1 are denoted by the same reference numerals and description thereof is omitted.

A bias setting circuit 700 shown in FIG. 12 is different from the bias setting circuit 100 of FIG. 1 in that it includes two NMOS transistors M61 and M62 and a current source 710 connected in series. Further, the reference voltage source 720 connected to the negative phase input terminal IN2 of the error amplifier 130 generates the reference voltage V _DD −V _T −V _X , and the drain terminal and the source terminal of the NMOS transistor M30 of the dummy rectifier unit are Another difference is that it is not grounded.

The NMOS transistors M61 and M62 function as a load element in which the gate terminal and the drain terminal are connected to each other. In FIG. 12, the source terminal of the NMOS transistor M61 and the drain terminal of the NMOS transistor M62 are connected to each other. The drain terminal of the NMOS transistor M61 is connected to the power supply line (power supply voltage V _DD ), and the source terminal of the NMOS transistor M62 is connected to the drain terminal and the source terminal of the NMOS transistor M30. The current source 710 is also connected to the drain terminal and the source terminal of the NMOS transistor M30. With this configuration, the NMOS transistors M61 and M62 give a voltage drop between the power supply line and the NMOS transistor M30, which is almost the same as the sum of the threshold voltages of the NMOS transistors M61 and M62, by the minute current supplied from the current source 710. . In particular, the NMOS transistors M61 and M62 are transistors whose threshold voltages are equal to the bias voltage V _T generated by the bias voltage sources 110 and 210. Therefore, the potential V _DD -2V _T is applied to the drain terminal and the source terminal of the NMOS transistor M30. Note that the current source 710 may be a commonly used bias circuit, but may be configured by a transistor having a gate-source voltage set to 0 V and may use the leakage current.

In a state in which the voltage across the capacitor C32 coincides with the bias voltage V _T , the drain terminal of the NMOS transistor M31 serving as the transfer gate is bias voltage V _T from the potential V _DD -2V _T of the drain terminal and source terminal of the NMOS transistor M30. Shows a higher potential V _DD -V _T. On the other hand, the source terminal of the NMOS transistor M31 coincides with the same potential as the positive terminal of the bias voltage source 110, that is, the bias voltage V _T , through the NMOS transistor 32 which is turned on by complementary operation with the NMOS transistor M31. . Therefore, a potential difference V _DD -2V _T is generated between the source and drain of the NMOS transistor M31. This potential difference V _DD -2V _T causes discharge of the capacitor C32. That is, a current leakage state similar to that of the uppermost rectifier circuit block 200-n illustrated in FIG. 11 can be realized.

However, the source-drain voltage V _DD -2V _T of the NMOS transistor M31 is smaller than the source-drain voltage V _DD of the NMOS transistor M11-n of the rectifier circuit block 200-n by 2V _T. Therefore, precisely, the bias setting circuit 700 does not simulate the current leakage state of the cascade rectifier circuit 600. However, this 2V _T difference can be ignored by adjusting the size of the NMOS transistor M31. In general, the leakage current of an NMOS transistor whose gate terminal is grounded depends on the drain-source voltage (V _DS ). The dependence depends on the process conditions of the transistor. When the V _DS dependency of the NMOS transistor M31 is small, the leakage current generated by the V _DS is also small. On the other hand, when the V _DS dependency of the NMOS transistor M31 is large, for example, the leakage current changes several times depending on the error voltage 2V _T. Therefore, the dimensions of the NMOS transistors M31 and M33 are set larger, for example, between 1 and 10 than the transfer gates of the cascade rectifier circuit 600. Thereby, in the bias setting circuit 700, the current leak state of the cascade rectifier circuit 600 can be simulated.

The operation of the bias setting circuit 700 is the same as the timing chart shown in FIG. 4 except that, in the reference voltage source 720, the reference voltage compared with the potential V ₀ of the capacitor C32 is V _DD −V _T −V _X. Since there is, explanation is omitted here.

In the cascade rectifier circuit 600, a leakage current may be generated in the transfer gate even in the rectifier circuit blocks 200-2 to 200- (n-1) other than the uppermost rectifier circuit block 200-n. The leak current is also generated in the uppermost rectifier circuit block 200-n. Therefore, as described above, the bias setting circuit 700 is most effective in simulating generation of the drain-source voltage V _DD of the transfer gate of the uppermost rectifier circuit block 200-n.

  As described above, according to the high gain rectifier circuit according to the third embodiment, the bias setting circuit 700 simulates the leakage current of the transfer gate generated in the uppermost rectifier circuit block 200-n of the cascade rectifier circuit 600. Therefore, the same effect as that of the first embodiment can be obtained for the cascade rectifier circuit 600.

(Embodiment 4)
The high gain rectifier circuit according to the fourth embodiment is characterized by including a bias setting circuit that solves the problem described in the third embodiment by another method. FIG. 13 is a circuit diagram showing a bias setting circuit constituting the high gain rectifier circuit according to the fourth embodiment. In FIG. 13, parts common to the bias circuit 100 of FIG.

13 includes three PMOS transistors M71, PMOS transistors M73, and NMOS transistors M72, a current source 810, a delay circuit 830, an EXOR circuit 840, and an AND circuit 850 connected in series. This is different from the bias circuit 100 of FIG. Further, the reference voltage source 820 connected to the negative phase input terminal IN2 of the error amplifier 130 generates the reference voltage V _DD -V _X , and the drain terminal and the source terminal of the NMOS transistor M30 of the dummy rectifier are grounded. There is no difference.

The PMOS transistor M71 and the NMOS transistor M72 function as a CMOS inverter. In FIG. 13, the source terminal of the PMOS transistor M71 is connected to the power supply line (power supply voltage V _DD ), and the source terminal of the NMOS transistor M72 is connected to the ground line. ing. The NMOS transistor M73 has both a gate terminal and a drain terminal connected to the drain terminal of the PMOS transistor M71, and a source terminal connected to the drain terminal of the NMOS transistor M72. The connection point of the NMOS transistor M72 and the NMOS transistor M73 is connected to the drain terminal and the source terminal of the NMOS transistor M30 of the dummy rectification unit, and also functions as an output point of the above-described CMOS inverter. The gate terminal of the PMOS transistor M71 and the gate terminal of the NMOS transistor M72 are connected to each other and function as an input point of the above-described CMOS inverter.

The input point of this CMOS inverter is connected to the output terminal (signal V _c ) of the AND circuit 850. The AND circuit 850 outputs the output of the inverter INV12 (ie, the control signal V ₁ ) and the output of the EXOR circuit 840 (signal V _b ). input. The EXOR circuit 840 receives the output of the inverter INV12 and the output of the delay circuit 830 (signal V _a ). The delay circuit 830 outputs a signal V _a in which the output of the inverter INV12 is delayed by the time tau.

Hereinafter, the operation of the bias setting circuit 800 will be described. FIG. 14 shows a control signal V ₁ output from the inverter INV 12, a signal V _a output from the delay circuit 830, a signal V _b output from the EXOR circuit 840, and a signal V _c output from the AND circuit 850. FIG. 6 is a timing chart showing the potential V ₀ at one end of the capacitor C32 and the potential V _{3 at} the other end of the capacitor C32.

Here, as an initial state, immediately after the control signal V ₁ transitions from the logic level “L” to “H” is considered. In this state, the delay circuit 830 starts the time measurement of the time tau, the output signal V _a to the elapsed time tau shows a logic level "L". Therefore, until the time τ elapses after the control signal V ₁ transitions from the logic level “L” to “H”, both the signal V _b and the signal V _c are at the logic level as shown in FIG. “H” is shown. Accordingly, a logic level “H” signal is input to each gate of the PMOS transistor M71 and the NMOS transistor M72, and a signal having a logic level “L” obtained by inverting the signal is output from the connection point between the NMOS transistor M72 and the PMOS transistor M73. The Since this logic level “L” signal is approximately 0 V (ground potential GND), the potential V _{3 at} the other end of the capacitor C32 also indicates GND. During this time, the potential V ₀ at one end of the capacitor C32 coincides with a value higher than the potential V ₃ by the bias voltage V _T , that is, the potential V _T.

The time τ is a time required for completing the transfer of charges from at least the capacitor C31 to the capacitor C32 via the NMOS transistors M31 and M33. When the time τ elapses, the output signal Va of the delay circuit 830 shows _a logic level “H”. The signal V _b remains at the logic level “H”, but the signal V _c indicates the logic level “L”. Accordingly, a logic level “L” signal is input to each gate of the PMOS transistor M71 and the NMOS transistor M72, and a logic level “H” signal obtained by inverting the signal is output from a connection point between the NMOS transistor M72 and the NMOS transistor M73. The This logic level “H” signal has a potential V _DD −V _T which is lowered from the power supply voltage V _{DD by} the threshold voltage V _T of the NMOS transistor M73. That is, the potential V _{3 at} the other end of the capacitor C32 also shows V _DD -V _T. During this time, the potential V ₀ at one end of the capacitor C32 coincides with a value higher than the potential V ₃ by the bias voltage V _T , that is, the potential V _DD . The error amplifier 130 outputs a difference V _X between the potential V _DD and the reference voltage V _DD −V _X. This difference V _X is recognized as the logic level “H” by the inverter INV12 as in the timing chart shown in FIG. 4, and as a result, the logic level of the control signal V ₁ is changed from “H” to “L”. . The logic level “L” control signal V ₁ turns off the NMOS transistors M31 and M33 and turns on the NMOS transistors M32 and M34 via the inverter INV11. In this state, since the potential V ₀ matches the power supply voltage V _DD , the drain-source voltage of the NMOS transistor M31 becomes V _DD -V _T , and current leakage by the NMOS transistor M31 is realized. Due to this current leakage, the potential V _{0 of the} capacitor C32 gradually decreases and finally becomes lower than the reference voltage V _DD -V _X. That is, the error voltage V _E output from the error amplifier 130 becomes an input signal having a logic level “L” for the inverter INV12. As a result, the control signal V ₁ again exhibits the logic level “H” as in the initial state. Thereafter, the above-described phase is repeated.

That is, as in the first embodiment, the state of the capacitor of the rectifier unit of the rectifier circuit can be monitored. In particular, in the fourth embodiment, the current leakage state by the NMOS transistor M31 is realized by the drain-source voltage V _DD -V _X. This voltage is closer to V _DD by the voltage V _X than the drain-source voltage V _DD -2V _X shown in the third embodiment. In other words, this is a value closer to the drain-source voltage V _DD that causes current leakage in the uppermost rectifier circuit block of the cascade rectifier circuit, which is more than the bias setting circuit 700 shown in the third embodiment. In addition, the current leakage state of the cascade rectifier circuit 600 can be simulated with high accuracy.

(Embodiment 5)
The high gain rectifier circuit according to the fifth embodiment is characterized by including a bias setting circuit that solves the problem described in the third embodiment by another method. FIG. 15 is a circuit diagram showing a bias setting circuit constituting the high gain rectifier circuit according to the fifth embodiment. In FIG. 15, parts common to those of the bias circuit 100 of FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

A bias setting circuit 900 shown in FIG. 15 is different from the bias setting circuit 100 of FIG. 1 in that an NMOS transistor M81 is provided. Another difference is that one end (potential V ₀ ) of the capacitor C32 is connected to the negative phase input terminal IN2 of the error amplifier 130, and the positive terminal of the bias voltage source 110 is connected to the positive phase input terminal IN1. Further, with this, the reference voltage source 120 is also eliminated.

The NMOS transistor M81 has a drain terminal connected to the power supply line (power supply voltage V _DD ), a source terminal connected to one end (potential V ₀ ) of the capacitor C32, and a gate terminal connected to the drain terminal and the source terminal of the NMOS transistor M30. Connected to the terminal.

In this circuit, the NMOS transistor M81 is always OFF because the ground potential is input to the gate terminal, and the drain-source voltage is V _DD −V _T obtained by subtracting the threshold voltage V _T from the power supply voltage V _DD. expressed. This means that the leakage current of the NMOS transistor M81 due to the drain-source voltage V _DD -V _T is given to one end (potential V ₀ ) of the capacitor C32 during the period when the NMOS transistors M31 and M33 are OFF. In other words, the drain-source voltage V _DD -V _T of the NMOS transistor M31 described in the fourth embodiment is generated by the NMOS transistor M81. However, this leakage current does not induce discharge of the capacitor C32, but conversely flows into the capacitor C32 and raises the potential V ₀ at one end of the capacitor C32. Therefore, the error amplifier 130 detects the increase in the potential V ₀ by inputting the voltage V _T of the bias voltage source 110 to the positive phase input terminal IN1. Specifically, for example, when the potential V ₀ that initially indicated the bias voltage V _T rises by more than the voltage V _X due to the drain-source voltage V _DD -V _{T of} the NMOS transistor M81, that is, V _T + V _X. When the value becomes larger than that, the logic level of the error voltage V _E is inverted. Except for this point, the operation of the bias setting circuit 900 is the same as the timing chart shown in FIG. The voltage V _X is obtained by adjusting the dimensions of the NMOS transistors M123 and M124 in FIG.

  As described above, according to the high gain rectifier circuit according to the fifth embodiment, the bias setting circuit 900 simulates the current leakage of the transfer gate that occurs in the uppermost rectifier circuit block 200-n of the cascade rectifier circuit 600. Therefore, the same effect as in the first embodiment can be enjoyed.

(Embodiment 6)
The high gain rectifier circuit according to the sixth embodiment is a modification of the high gain rectifier circuit according to the fifth embodiment. FIG. 16 is a circuit diagram showing a bias setting circuit constituting the high gain rectifier circuit according to the sixth embodiment. In FIG. 16, parts common to the bias setting circuit 100 of FIG.

A bias setting circuit 1000 shown in FIG. 16 is different from the bias setting circuit 100 of FIG. 1 in that a second dummy rectification unit and a second dummy switching unit are added. Hereinafter, the dummy rectification unit and the dummy switching unit in FIG. 1 are referred to as a first dummy rectification unit and a second dummy switching unit, respectively. The bias setting circuit 1000 includes an NMOS transistor M30 ′ and a capacitor C32 ′ respectively corresponding to the NMOS transistor M30 and the capacitor C32 of the first dummy rectifier as the second dummy rectifier. Further, as the second dummy switching unit, the NMOS transistors M31 ′, M32 ′ corresponding to the NMOS transistors M31, M32, M33, M34, the capacitors C31, C32, and the bias voltage source 110 of the first dummy switching unit, respectively. , M33 ′, M34 ′, capacitors C31 ′, C32 ′, and a bias voltage source 110. Furthermore, the bias setting circuit 1000 includes an NMOS transistor M91, and is also different in that one end (potential V ₀ ′) of the capacitor C32 ′ is connected to the negative phase input terminal IN2 of the error amplifier 130. As a result, the reference voltage source 120 is eliminated.

The NMOS transistor M91 has a drain terminal connected to the power supply line (power supply voltage V _DD ), a source terminal connected to one end (potential V ₀ ′) of the capacitor C32 ′, and a gate terminal connected to the drain terminal and source of the NMOS transistor M30 ′. The terminal is connected to the gate terminal.

In other words, the bias setting circuit 1000 replaces the positive phase input terminal IN1 of the error amplifier 130 of FIG. 15 with the positive terminal of the bias power supply 110, and the positive phase input terminal IN1 is the first dummy rectifier. The circuit configuration is connected to one end (potential V ₀ ) of the capacitor C32.

That is, the operation of the bias setting circuit 1000 is almost the same as that of the bias setting circuit 900 described in the fifth embodiment. However, in the bias setting circuit 1000, since the reference voltage input to the positive phase input terminal IN1 of the error amplifier 120 is not the bias voltage V _T itself but the current potential of the capacitor C32 of the rectifier unit, to the capacitor C32 ′. There is an advantage that the voltage error due to the inflow of the leakage current can be detected more accurately.

(Embodiment 7)
The high gain rectifier circuit according to the first to sixth embodiments can be used as a rectifier circuit of an RFID tag. In the seventh embodiment, an example of an RFID tag configured using the high gain rectifier circuit according to the second embodiment will be described. FIG. 17 is a block diagram of an RFID tag according to the seventh embodiment. An RFID tag 1010 shown in FIG. 17 includes an antenna 9, a bias setting circuit 10 as shown in FIG. 5, a rectifier circuit 20 as shown in FIG. 7, a backflow prevention circuit 30, an RF detection circuit 40, A control circuit 50 and a battery 60 that is a secondary battery are provided. In particular, the bias setting circuit 10 and the rectifier circuit 20 constitute a high gain rectifier circuit according to the second embodiment. Further, the RFID 1010 tag is an RFID tag that is driven by the power supply voltage V _DD supplied from the battery 60, and it is not an essential requirement to generate the power supply voltage from the rectifier circuit 20 for its operation. That is, the bias setting circuit 10, the rectifier circuit 20, the backflow prevention circuit 30, the RF detection circuit 40, and the control circuit 50 are respectively connected to a power supply line and a ground line extended from the battery 60. In this example, the initialization signal _VCNT is not generated by the power supply detection circuit shown in FIG. 8, but is generated by the control circuit 50.

The antenna 9 induces an alternating current in the antenna line in accordance with an electric field applied by a reader / writer (not shown). This alternating current is input to the signal input terminal of the rectifier circuit 20. The rectifier circuit 20 is driven by a power supply voltage supplied from the battery 60. Therefore, the bias voltage source or the reference voltage source as shown in FIGS. 3-1 to 3-4 generates the bias voltage V _T or the reference voltage V _T −V _X from the power supply voltage V _DD supplied from the battery 60. To do. That is, in the rectifier circuit 20, regardless of whether or not an alternating current is input from the antenna 9, the bias voltage V _T is applied between the gate terminal and the source terminal of the MOS transistor constituting the rectifier unit of the rectifier circuit 20. Applied. Therefore, as shown in the first and second embodiments, the rectifier circuit 20 can rectify a weak alternating current having an effective value less than about 0.7 V induced in the antenna 9. That is, the weak data signal received by the antenna 9 can be demodulated. In particular, in this rectification operation, the control signal V ₁ is input to the rectifier circuit 20 from the bias setting circuit 10 at an optimal timing as described in the second embodiment, and the rectifier circuit 20 receives the control signal V _1. Therefore, the bias voltage of the MOS transistor constituting the rectifying unit is maintained at a predetermined value or higher.

  The demodulated data signal is input to the RF detection circuit 40. The RF detection circuit 40 drives the control circuit 50 by detecting this data signal and outputs the detected data signal to the control circuit 50. The DC voltage obtained by the rectifier circuit 20 is also supplied to the battery 60 through the backflow prevention circuit 30 as charging power.

  Based on the data signal received from the rectifier circuit 20, the control circuit 50 extracts data (typically tag identification information) stored in a memory (not shown) and writes data to the memory. The control circuit 50 includes a load modulation unit connected to the antenna 9, and data extracted from the memory or the like is transmitted to the reader / writer by modulation of the current of the antenna 9 by the load modulation unit. Specifically, the load modulation unit changes the load of the antenna 9, and this change slightly changes the current flowing through the reader / writer antenna. This minute change is detected by the reader / writer and recognized as a data signal.

In addition, the control circuit 50 generates an initialization signal _VCNT that is input to the bias setting circuit 10 and the rectifier circuit 20. FIG. 18 is a timing chart for explaining the generation timing of the initialization signal _VCNT . As shown in FIG. 18, the control circuit 50 outputs a pulse that is the initialization signal V _CNT immediately before the control circuit 50 is stopped from its own operating state (time t ₁ ). When shifting, the bias setting circuit 10 and the rectifier circuit 20 can be initialized. However, when the battery 60 is connected to the RFID tag for the first time after the RFID tag is manufactured, the control circuit 50 is not operating, and therefore the initialization signal _VCNT is not generated at the timing according to FIG. However, when testing at the time of manufacturing the RFID tag, it is possible to operate the control circuit 50 by applying a strong RF signal to the RFID tag, thereby generating the initialization signal _VCNT. . In other words, before the manufacturing test, the configuration including the bias setting circuit 10 and the rectifier circuit 20 does not operate as a high gain rectifier circuit but operates as a conventional low gain rectifier circuit and gives a strong RF signal. Thus, it can be operated as a high gain rectifier circuit.

In the RFID tag described above, the control circuit 50 generates the initialization signal _VCNT . However, the initialization signal _VCNT may be generated by the power supply detection circuit shown in FIG. FIG. 19 is a block diagram of an RFID tag including a power supply detection circuit. Note that, in FIG. 19, the same reference numerals are given to portions common to the RFID tag illustrated in FIG. 17, and description thereof is omitted. The RFID 1020 tag shown in FIG. 19 includes a power supply detection circuit 70 as shown in FIG. 8, and this power supply detection circuit 70 generates the initialization signal _VCNT instead of the control circuit 50. Thereby, even when the battery 60 is connected to the RFID tag for the first time after the RFID tag is manufactured, the power supply detection circuit 70 can detect it and generate the initialization signal _VCNT .

  Further, since the RFID tag according to this embodiment includes a battery, it is easy to mount various input / output devices such as a temperature sensor, a speaker, a microphone, and a light emitting element on the RFID tag. In that case, the application of the RFID tag can be further expanded. For example, when a sensor is mounted on an RFID tag, the configuration is as shown in FIG. Note that, in FIG. 20, the same reference numerals are given to portions common to the RFID tag illustrated in FIG. 17, and description thereof is omitted. In the RFID tag 1030 shown in FIG. 20, the sensor 80 is connected to a power supply line and a ground line supplied from the battery 60. Transmission / reception of signals to / from the sensor 80 is performed with the control circuit 50, for example. Here, an example of an RFID tag equipped with a temperature sensor will be described as an example of the sensor. When there is no transmission from a reader / writer (not shown), the temperature sensor is in a sleep state and does not consume current. When there is a transmission signal from the reader / writer and there is a signal transmission command to the RFID tag with sensor 1030, the temperature sensor is activated, detects the temperature, and sends data to the control circuit 50. The signal data in which the signal data and the unique data of the RFID tag are combined is returned from the RFID tag to the reader / writer. As another method for implementing the temperature sensor, the control circuit 50 instructs the temperature sensor to output temperature data every certain time, and the data from the temperature sensor is stored in the memory block. When there is a command from the reader / writer, the accumulated temperature data is sent together with the recording time data. Further, as a temperature sensor activation means, there is a method in which the temperature sensor is activated when a stimulus such as vibration, sound, or light is present, and data is stored in a memory.

  As described above, according to the RFID tag according to the seventh embodiment, since the high gain rectifier circuit according to the second embodiment is mounted, the MOS transistor constituting the rectifier of the rectifier circuit 10 is biased. For this reason, useless charging operation is reduced, and power consumption can be reduced. Further, it is possible to realize rectification always having a gain of a certain value or more without being affected by manufacturing variations of the high gain rectifier circuit.

  Although the present invention has been described in detail above, the present invention is not limited to the specific embodiments described above, and further effects and modifications can be easily derived by those skilled in the art. That is, the embodiment according to the present invention can be variously modified without departing from the gist of the invention according to the appended claims and equivalents thereof.

  As described above, the high gain rectifier circuit according to the present invention is useful for rectifying minute signals, and is particularly suitable as a rectifier circuit mounted on an RFID tag.

1 is a circuit diagram of a high gain rectifier circuit according to a first embodiment; It is a circuit diagram which shows an example of an error amplifier. It is a circuit diagram which shows the example of a bias voltage source or a reference voltage source. It is a circuit diagram which shows the other example of a bias voltage source or a reference voltage source. FIG. 6 is a circuit diagram showing another example of a bias voltage source or a reference voltage source used in the high-interest rectifier circuit according to the first embodiment. It is a circuit diagram which shows the other example of a bias voltage source or a reference voltage source. 4 is a timing chart for explaining the operation of the bias setting circuit of the high gain rectifier circuit according to the first embodiment; FIG. 4 is a circuit diagram showing a bias setting circuit of a high gain rectifier circuit according to a second embodiment; FIG. FIG. 9 is a timing chart for explaining the operation of the bias setting circuit of the high gain rectifier circuit according to the second embodiment; 6 is a circuit diagram of a rectifier circuit of a high gain rectifier circuit according to a second embodiment; FIG. It is a circuit diagram of the power supply detection circuit which produces | generates an initialization signal. FIG. 6 is a timing chart for explaining the operation of the power supply detection circuit of the high gain rectifier circuit according to the second embodiment; FIG. 6 is a circuit diagram illustrating an example of a cascade rectifier circuit of a high gain rectifier circuit according to a third embodiment; It is a circuit diagram which shows the detail of the uppermost rectifier circuit block of the cascade rectifier circuit of FIG. FIG. 6 is a circuit diagram showing a bias setting circuit constituting a high gain rectifier circuit according to a third embodiment; FIG. 6 is a circuit diagram showing a bias setting circuit constituting a high gain rectifier circuit according to a fourth embodiment; FIG. 10 is a timing chart for explaining the operation of the bias setting circuit of the high gain rectifier circuit according to the fourth embodiment; FIG. 10 is a circuit diagram showing a bias setting circuit constituting a high gain rectifier circuit according to a fifth embodiment; FIG. 10 is a circuit diagram showing a bias setting circuit constituting a high gain rectifier circuit according to a sixth embodiment; FIG. 9 is a block diagram of an RFID tag according to a seventh embodiment. It is a timing chart explaining the production | generation timing of an initialization signal. FIG. 10 is a block diagram of another example of an RFID tag according to the seventh embodiment. It is a block diagram which shows the structure which mounted the sensor in the RFID tag of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 9 Antenna 10,100,300,700,800,900,1000 Bias setting circuit 20,200,400 Rectifier circuit 30,630 Backflow prevention circuit 40 RF detection circuit 50 Control circuit 60,660 Battery 70,500 Power supply detection circuit 80 Sensor (Eg temperature sensor)
110, 210, 610 Bias voltage source 111, 121 Constant current source 120, 720, 820 Reference voltage source 130 Error amplifier 600 Cascaded rectifier circuit 710, 810 Current source R1, R2 Resistance M1, M2, M11-M14, M21-M24, M30 to M34, M41, M42, M51 to M54, M61, M62, M71, M72, M73, M81, M91, M101, M111 to M113, M121 to M124, M501 to M504 MOS transistors C1, C2, C11, C12, C21 , C22, C31, C32, C501 Capacitor INV1, INV2, INV11, INV12 Inverter

Claims (18)

A switching unit that includes a first MOS transistor having a first capacitor connected between a gate terminal and a source terminal as a rectifying element, and that supplies a predetermined bias voltage to the first capacitor based on a control signal. A rectifier circuit comprising:
A second MOS transistor simulating the first MOS transistor; a second capacitor simulating the first capacitor; and dummy switching for supplying the bias voltage to the second capacitor based on the control signal. A bias setting circuit that generates the control signal based on the potential of the second capacitor,
A high gain rectifier circuit comprising:   2. The high voltage transistor according to claim 1, further comprising a third MOS transistor, and further comprising a bias voltage source that generates the bias voltage from a voltage between a gate terminal and a source terminal of the third MOS transistor. Gain rectifier circuit. A reference voltage source for generating a reference voltage smaller than the predetermined voltage;
3. The high gain rectifier circuit according to claim 1, wherein the bias setting circuit generates the control signal based on a comparison between the reference voltage and the potential of the second capacitor. 4.   4. The high voltage according to claim 3, wherein the reference voltage source includes a fourth MOS transistor, and generates the reference voltage from a voltage between a gate terminal and a source terminal of the fourth MOS transistor. Gain rectifier circuit.   The bias setting circuit supplies the bias voltage to the second capacitor based on an initialization signal for initializing a voltage across the second capacitor simulating the first capacitor. The high gain rectifier circuit according to any one of 1 to 4.   6. The high gain rectifier according to claim 5, wherein the rectifier circuit supplies the bias voltage to the first capacitor based on the initialization signal for initializing a voltage across the first capacitor. circuit.   7. The high gain rectifier circuit according to claim 5, further comprising a power supply voltage detection circuit that generates the initialization signal based on detection of a power supply voltage.   8. The high gain rectifier circuit according to claim 1, wherein a source terminal of the second MOS transistor is grounded.   8. The high gain rectifier circuit according to claim 1, wherein a source terminal of the second MOS transistor has a predetermined potential between a power supply potential and a ground potential. A logic circuit that generates a logic signal based on the control signal and a signal obtained by delaying the control signal by a predetermined time;
An inverter circuit that outputs a predetermined potential or a ground potential between a power supply potential and a ground potential to a source terminal of the second MOS transistor according to the logic signal;
The high gain rectifier circuit according to claim 1, further comprising:   11. The high gain rectifier circuit according to claim 10, wherein the predetermined time is at least a time required for the supply of the bias voltage to the second capacitor by the dummy switching unit to be completed. The bias setting circuit further includes a current supply circuit that supplies a predetermined current to one end of the second capacitor,
8. The high gain rectifier circuit according to claim 1, wherein the control signal is generated based on a potential of the second capacitor increased by the supply of the predetermined current. 9. The switching unit includes a MOS transistor that supplies the bypass voltage to the first capacitor based on the control signal;
The high gain rectifier circuit according to claim 1, wherein the predetermined current has a value corresponding to a leakage current of the MOS transistor of the switching unit. The bias setting circuit includes:
A third MOS transistor that simulates the first MOS transistor; a third capacitor that simulates the first capacitor; and a second that supplies the bias voltage to the third capacitor based on the control signal. And a dummy switching part of
14. The high gain rectifier circuit according to claim 12, wherein the control signal is generated based on potentials of the second capacitor and the third capacitor. The switching unit includes a fifth MOS transistor that supplies the bypass voltage to the first capacitor based on the control signal;
15. The dummy switching unit includes a sixth MOS transistor that simulates the fifth MOS transistor and has a size larger than that of the fifth MOS transistor. The high gain rectifier circuit described in 1. An antenna,
The high gain rectifier circuit according to any one of claims 1 to 15, which rectifies a current induced in the antenna;
A battery charged by a direct current obtained from the high gain rectifier circuit;
A control circuit that transmits at least tag identification information via the antenna based on a direct current obtained from the high gain rectifier circuit;
An RFID tag comprising: An antenna,
The high gain rectifier circuit according to claim 5 or 6, which rectifies a current induced in the antenna;
A battery charged by a direct current obtained from the high gain rectifier circuit;
Based on the direct current obtained from the high gain rectifier circuit, at least tag identification information is transmitted via the antenna, and the initialization signal is output when the control circuit transitions from an operating state to a stopped state. A control circuit;
An RFID tag comprising: A sensor,
The RFID tag according to claim 16 or 17, wherein the control circuit transmits a signal detected by the sensor via the antenna.

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