JP2006155223A - Data processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processor capable of responding to a required complicate application while preventing increase in circuit scale or increase in power consumption as well as deterioration of processing performance. <P>SOLUTION: This data processor comprises a plurality of exclusive arithmetic parts 4, 5 and 6 performing predetermined arithmetic processing, a signal line 10 connected to the plurality of exclusive arithmetic parts 4, 5 and 6, and a common arithmetic part 9 performing specified processing, which is connected to the plurality of exclusive arithmetic parts through the signal line 10. The common arithmetic part 9 is used commonly in at least two or more of the plurality of exclusive arithmetic parts 4, 5 and 6. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data processing apparatus equipped with a dedicated arithmetic unit that executes predetermined data processing.

  A conventional data processing apparatus that performs image processing and data compression has a configuration in which a dedicated arithmetic unit that performs specific arithmetic processing is connected to a main processor for control. The dedicated arithmetic unit may be a dedicated circuit that performs specific arithmetic processing, or may be a part or all of a dedicated LSI or ASIC (specific application IC).

  FIG. 14 is a block diagram of a conventional data processing apparatus.

  The data processing device 100 includes a main processor 101 and a plurality of dedicated arithmetic units 102 and performs arbitrary data processing. In FIG. 14, three dedicated arithmetic units 102 are provided. Further, the main processor 101 is not an essential component and may be anything that controls a plurality of dedicated arithmetic units 102 (synchronous control, command control, etc.).

  In addition, the dedicated arithmetic unit 102 may execute different arithmetic processes, or may execute similar or identical arithmetic processes. Since a plurality of dedicated calculation units 102 execute processing with a large amount of calculation, power consumption can be reduced and real-time processing can be performed.

  Note that the data processing apparatus 100 is often realized entirely or partially by an LSI.

  The configuration of a conventional data processing apparatus as shown in FIG. 14 is introduced in the technical trend topics / system LSI layout / image processing LSI / data compression LSI on the JPO data room homepage.

  Examples of data processing devices include code compression / decoding processing devices and processing LSIs such as MPEG2, MPEG4, and JPEG.

  Further, in order to reduce power consumption in such a data processing apparatus, operation frequency control is effective (see, for example, Patent Document 1 and Patent Document 2).

  In recent years, there has also been a demand for realization of encoding / decoding processing corresponding to a plurality of image processing formats, realization of audio processing in addition to image processing, and the like. That is, the amount of applications processed by one data processing device or an LSI that realizes the data processing device tends to increase.

  However, the conventional data processing apparatus has the following problems.

  In order to ensure low power consumption and real-time performance against the increase and complexity of the amount of applications processed by one data processing device or LSI that realizes this, the number and circuit scale of dedicated operation units 102 to be mounted are limited. There was an increasing problem. Due to the increase in circuit scale, an increase in the chip area of the LSI has been a problem when it is realized by an LSI. Or it was a problem in terms of cost. Even when the system is realized by a system or another circuit, there are problems such as an increase in mounting area due to an increase in circuit scale.

Further, when implemented by a program, there is a problem of an increase in power consumption as the program scale increases.
JP 2003-248524 A JP-A-7-334267 JP 2000-298652 A

  SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing apparatus that can reduce the circuit scale and power consumption while preventing deterioration in processing performance, and can cope with a required complex application.

  A data processing apparatus according to a first aspect of the present invention includes a plurality of dedicated calculation units that perform predetermined calculations, a signal line that is connected to the plurality of dedicated calculation units, and a plurality of dedicated calculation units that are connected via the signal lines. The data processing device includes a common arithmetic unit that performs the arithmetic processing of the above, and the common arithmetic unit is configured to be commonly used in at least two or more of the plurality of dedicated arithmetic units.

  The data processing device is configured such that the calculation unit provided redundantly in the plurality of dedicated calculation units is deleted from the dedicated calculation unit as a common calculation unit and provided separately, and then shared by the plurality of dedicated calculation units The circuit scale can be appropriately reduced.

  In the data processing device according to the second aspect of the present invention, the common operation unit includes at least one common product-sum operation unit that performs a product-sum operation commonly used by at least two or more of the plurality of dedicated operation units.

  A product-sum operation unit that has a large circuit scale and power consumption that are duplicated in a plurality of dedicated operation units is deleted from the dedicated operation unit as a common product-sum operation unit, and is provided separately and shared. Reduction of circuit scale and power consumption is further promoted.

  In the data processing device according to the third aspect of the present invention, the common arithmetic unit further includes at least one individual arithmetic unit that performs arithmetic operations that are not commonly used by the plurality of dedicated arithmetic units.

  In addition to computing units that are used in common by multiple dedicated computing units, computing units that are used individually are also provided in the common computing unit, so that the processing capacity of the dedicated computing unit can be reduced and the processing load of the dedicated computing unit can be reduced. In addition to reducing the circuit scale, the processing capability can be improved.

  In the data processing apparatus according to the fourth aspect of the invention, each of the plurality of dedicated calculation units uses a calculation result obtained by combining the common product-sum calculation unit and the individual calculation unit.

  It is possible to appropriately reduce the circuit scale while increasing the processing capability of the common arithmetic unit and consequently improving the processing capability of the entire data processing apparatus.

  In a data processing device according to a fifth aspect of the present invention, the common calculation unit includes a plurality of individual calculation units, and further includes a selection unit that selects a predetermined individual calculation unit corresponding to the request of the dedicated calculation unit from the plurality of individual calculation units.

  When the individual calculation unit performs the calculation appropriately corresponding to the request of the dedicated calculation unit, the performance of the entire data processing apparatus can be improved.

  In the data processing device according to the sixth aspect of the invention, there are a plurality of common arithmetic units and less than the number of the dedicated arithmetic units.

  By maximizing the number of overlapping calculation units in the dedicated calculation unit, even a data processing apparatus having various dedicated calculation units corresponding to complex applications can reduce the circuit scale.

  In the data processing device of the seventh invention, the plurality of dedicated arithmetic units are at least one of a filter processing unit, an orthogonal transformation processing unit, a motion detection unit, and a motion compensation unit.

  Since these dedicated arithmetic units have overlapping product-sum arithmetic units such as multipliers and adders, it is easy to share common arithmetic units, and it is a data processing device that supports multiple complex applications. Even in this case, the circuit scale can be reduced.

  In the data processing device according to the eighth aspect of the present invention, the common calculation unit further includes a clock control unit that outputs a clock different from that of the dedicated calculation unit.

  Since the common arithmetic unit operates with separate and independent clocks, when multiple dedicated arithmetic units are operated in parallel, the common arithmetic unit used in common can be operated in parallel in a pseudo manner. This prevents the processing capacity from being reduced.

  In the data processing device according to the ninth aspect of the invention, the clock control unit outputs no clock signal when the common operation unit is not operating.

  The power consumption reduction realized by sharing the commonly used arithmetic unit can be further reduced.

  In the data processing device according to the tenth aspect of the present invention, when the number of the plurality of dedicated arithmetic units is N, the clock frequency of the dedicated arithmetic units is F, and the clock frequency of the common arithmetic unit is f, the clock frequency f is f = N. * Determined by F.

  Depending on the number of dedicated calculation units, the processing of the common calculation unit can be made the same as the parallel processing in a pseudo manner, and all of the dedicated calculation units can be executed simultaneously.

  In a data processing device according to an eleventh aspect, the common arithmetic unit includes a processor unit that executes program processing.

  By sharing the operations that are duplicated in multiple dedicated calculation units as a processor unit that performs separate program processing, the circuit scale is reduced, and post-processing such as changes in calculation coefficients and processing procedures in the common calculation unit Can respond to changes, and flexibility is improved.

  In a data processing device according to a twelfth aspect, the processor unit includes a common product-sum operation program for executing a product-sum operation commonly used by at least two or more of the plurality of dedicated arithmetic units.

  Since a product-sum operation unit having a large circuit scale composed of a multiplier and an adder can be processed by a common program, the flexibility is high and the circuit scale can be reduced.

  According to the present invention, the circuit scale, the chip area, and the mounting area can be reduced by sharing the common arithmetic processing that a plurality of dedicated arithmetic units overlap with each other as a common arithmetic unit.

  In addition, since the shared common operation unit has an independent clock control unit, it is possible to prevent a reduction in processing speed and reduce power consumption.

  In addition, by installing a common arithmetic unit in a sub-processor, etc., and implementing it with software, a data processing device with a configuration that can flexibly cope with not only reduction in circuit scale but also subsequent specification changes and coefficient changes, etc. be able to.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
First, the data processing apparatus according to the first embodiment of the present invention will be described with reference to FIGS. 1A, 1B, and 2 including changes from the prior art.

  FIG. 1A is a block diagram of a conventional data processing apparatus, FIG. 1B is a block diagram of a data processing apparatus according to Embodiment 1 of the present invention, and FIG. 1 is shown for comparison with FIG. 1B showing the data processing apparatus in the first embodiment. FIG. 2 is a block diagram of the data processing apparatus according to Embodiment 1 of the present invention.

  In the conventional data processing apparatus 1 shown in FIG. 1A, a plurality of dedicated calculation units 4, 5, 6 that perform predetermined calculations are connected via a signal line 8. The plurality of dedicated calculation units 4, 5, 6 include a calculation unit 7 that performs a common calculation.

  The data processing device 2 shown in FIG. 1B includes a plurality of dedicated calculation units 4, 5, and 6 that perform predetermined calculations, and signal lines connected to the plurality of dedicated calculation units 4, 5, and 6. 10 and a plurality of dedicated arithmetic units 4, 5, and 6 through a signal line 10, and a common arithmetic unit 9 that performs common arithmetic processing. The common calculation unit 9 is used in common by at least two or more of the plurality of dedicated calculation units 4, 5, 6. Here, the signal lines 8 and 10 may be single-bit signal lines or multi-bit signal lines.

  In this way, as shown in FIG. 1A, the calculation unit 7 that executes a common calculation that has been duplicated in the plurality of dedicated calculation units 4, 5, 6 includes the dedicated calculation units 4, 5, The circuit scale can be efficiently reduced by being connected as a common arithmetic unit 9 that is bundled from 6 and shared separately.

  1A and 1B, the main processor 3 is connected via the signal line 8, but the main processor 3 is connected as necessary. Further, not only the main processor 3 but also a control circuit or the like may be appropriately connected. Further, three dedicated operation units 4, 5, and 6 are shown in FIG. 1A and FIG. 1B, respectively, but may be four or more.

  Next, FIG. 2 shows a data processing apparatus 2 that includes three or more dedicated arithmetic units 4, 5, 6, and 12, and a plurality of common arithmetic units 9 are connected via a signal line 10. . A plurality of common calculation units are connected, but the number of common calculation units is less than the number of dedicated calculation units. This is because the same number does not reduce the circuit scale. As described above, the common arithmetic unit 9 may be singular or plural.

  In FIG. 2, the common calculation unit 9 further includes a common product-sum calculation unit 15 and an individual calculation unit 16. The common product-sum operation unit 15 is an operation block that executes a product-sum operation common to at least two or more of the plurality of dedicated operation units, and performs, for example, common addition and multiplication. Among the operations that are duplicated in multiple dedicated operation units, the product-sum operation combined with addition and multiplication is very large in circuit scale, processing scale, and power consumption, and has the advantage of being shared as a separate block. is there.

  The individual calculation unit 16 is a block that executes a calculation that is not commonly used by a plurality of dedicated calculation units, and is provided in the common calculation unit 9 as necessary. In this case, the common operation unit 9 can execute individual operations such as individual data addition and bit replacement in addition to operations commonly used by at least two of the dedicated operation units (for example, common product-sum operation). . Even in the case where the individual arithmetic unit 16 is further included, circuit elements (for example, flip-flops, shift registers, adders, multipliers, etc.) required for the individual arithmetic unit 16 are connected to the circuit elements of the common product-sum arithmetic unit 15. Since they can be shared, as shown in FIG. 1A, the circuit scale can be reduced as compared with the case where only the dedicated arithmetic units 4, 5, and 6 are provided.

  Next, details of the reduction in circuit scale and the like by the data processing device 2 shown in FIG. 1B and FIG. 2 will be described.

  The dedicated arithmetic units 4, 5, and 6 include an arithmetic unit 7 that executes common arithmetic processing. The calculation unit 7 executes common calculation processing. For example, when the dedicated calculation unit 4 executes MPEG2, the dedicated calculation unit 5 executes MPEG4, and the dedicated calculation unit 6 executes JPEG, discrete cosine transform (hereinafter referred to as “DCT”) is a common calculation. The product-sum operation included in the DCT is a common operation. The calculation unit 7 is a block that performs a calculation common to the plurality of dedicated calculation units 4 to 6. In the data processing apparatus 1 according to the prior art, the common arithmetic unit 7 is included in duplicate over the plurality of dedicated arithmetic units 4, 5, 6. For this reason, uselessness has occurred and the circuit scale has been increased.

  On the other hand, in the data processing device 2, the calculation unit 7 is extracted from each of the dedicated calculation units 4, 5, 6 and connected as a common calculation unit 9 via the bus 10. As a result, the calculation unit 7 that is included in the dedicated calculation units 4, 5, 6 is deleted, and the circuit scale of each of the dedicated calculation units 4, 5, 6 is reduced.

  As described above, the operation unit 7 provided in an overlapping manner is deleted from the dedicated operation units 4, 5, and 6 and connected as a common operation unit 9 to be shared, so that the circuit scale can be greatly reduced. It becomes.

  In particular, the common operation unit 9 includes the common product-sum operation unit 15 that includes the product-sum operation overlapped by a plurality of dedicated operation units, thereby further reducing the circuit scale. This is because the product-sum operation includes many circuit elements such as adders, multipliers, and registers that are likely to have a large circuit scale.

  Here, since the common arithmetic unit 9 is connected via the bus 10, the dedicated arithmetic units 4 to 6 can exchange data with each other. That is, the common calculation unit 9 can be used in common for the plurality of dedicated calculation units 4, 5, 6.

  As described above, the common operation unit 9 often includes the common product-sum operation unit 15 common to the dedicated operation units 4, 5, and 6, but is not limited to the product-sum operation. For example, a common control unit such as a specific control operation, error correction, error code, or error detection may be provided.

  Moreover, although it is preferable that it is a calculating part which is common to all the exclusive calculating parts, the calculating part which is common to two or more of several exclusive calculating parts may be used. Similarly, the circuit scale can be reduced.

  Furthermore, the common calculation unit may include both the common product-sum calculation unit 15 and the individual calculation unit 16. This is because a calculation unit having high affinity with the common product-sum calculation unit 15 is included in the common calculation unit 9 as the individual calculation unit 16, thereby preventing deterioration in processing performance. Furthermore, the circuit scale can also be reduced by sharing the circuit element with the common product-sum operation unit 15 by the individual operation unit 16.

  Next, another variation of the common arithmetic unit 9 will be described with reference to FIGS. 3 (a) and 3 (b). 3 (a) and 3 (b) are internal block diagrams of the common arithmetic unit in the first embodiment of the present invention.

  FIG. 3A shows a common calculation unit 9 including a common product-sum calculation unit 15, an individual calculation unit 16, and a selection unit 17.

  The selection unit 17 selects the individual calculation unit 16 corresponding to the dedicated calculation units 4, 5, and 6 that are operating. As a result, necessary ones of the plurality of individual calculation units 16 are selected, and processing operations in the dedicated calculation units 4, 5, 6 are realized. Here, the selection unit 17 selects the individual calculation unit 16 corresponding to the control signal from the dedicated calculation units 4 to 6 as a reference. Further, at this time, the common product-sum operation unit 15 also operates as necessary, and the combined result with the selected individual operation unit 16 is output to the dedicated operation units 4, 5, 6.

  Through the above operations, the calculation results required by the dedicated calculation units 4, 5, 6 are obtained by the common calculation unit 9.

  Further, as illustrated in FIG. 3B, a common product-sum operation control unit 18 may be provided instead of the individual operation unit 16.

  The common product-sum operation control unit 18 is used when the processing operations in the product-sum operation unit common to the dedicated operation units 4, 5, and 6 are not completely the same. For example, the product-sum operation required by the dedicated operation unit 4 may be up to 3 multiplications, whereas the product-sum operation required by the dedicated operation unit 5 requires 5 multiplications. In other words, the same multiplier element is shared, but the processing result requirements are different.

  In such a case, the common product-sum operation control unit 18 controls the product-sum operation in the common product-sum operation unit 15 according to the request of the corresponding dedicated operation unit. In the above example, in the case of the dedicated operation unit 4, the common product-sum operation control unit 18 controls the multiplication in the common product-sum operation unit 5 to end in three times and outputs the result from the selection unit 17. To do. In the case of the dedicated operation unit 5, the common product-sum operation control unit 18 performs control so that the multiplication in the common product-sum operation unit 15 is completed in five times.

  As described above, the common product-sum calculation control unit 18 performs control corresponding to different calculation requests of the dedicated calculation unit.

  Next, with reference to FIGS. 4A and 4B, specific examples in which the dedicated calculation unit performs specific processing will be described including changes from the past. FIG. 4A is a block diagram of a conventional data processing apparatus, and FIG. 4B is a block diagram of the data processing apparatus in Embodiment 1 of the present invention. Here, in order to effectively explain the features and merits of the data processing apparatus 2 of the present invention, the conventional data processing apparatus 1 is also displayed side by side.

  FIG. 4 shows a case where the two dedicated arithmetic units are the filter processing unit 20 and the orthogonal transform unit 21, respectively.

  Other than this, a motion detection unit, a motion compensation unit, or the like used for image compression or the like may be used. The filter processing unit 20 and the orthogonal transform unit 21 are complicated in processing and have a very large circuit scale. On the other hand, product-sum operations such as multiplication and addition, and common operations such as bit shift and bit replacement. Is often included. For this reason, there are redundant useless arithmetic circuits, and it is easy to increase the circuit scale.

  For example, as shown in FIG. 4A, the filter processing unit 20 and the orthogonal transform unit 21 include a common product-sum operation unit 22. The product-sum operation unit 22 performs a product-sum operation necessary for data processing in the filter processing unit, or performs a product-sum operation necessary for data processing in the orthogonal transform unit.

  Furthermore, the product-sum operation unit 22 basically executes the same operation processing even if there is a difference in the coefficients related to the product-sum. As a result, when the filter processing unit 20 and the orthogonal transformation unit 21 are realized by a circuit or an LSI, an increase in circuit scale and an increase in chip area are caused.

  For this reason, as in the data processing device 2, the product-sum operation unit 22 is preferably provided in the common operation unit 9. By sharing in this way, the circuit scale is reduced.

  The common operation unit 9 includes a common product-sum operation unit 24 and a control unit 23 corresponding to the product-sum operation unit 22 that have been duplicated. The control unit 23 controls the common product-sum operation unit 24 so as to correspond to the filter processing unit 20 and the orthogonal transform unit 21. As a result, the common product-sum operation unit 24 can realize the optimum product-sum operation for the filter processing unit 20 and the orthogonal transform unit 21.

  For example, the control unit 23 changes the coefficient used for the product-sum operation, or recombines the product-sum order.

  As described above, the common arithmetic unit 9 is an arithmetic unit that is included redundantly in the filter processing unit 20, the orthogonal transform unit 21, or the dedicated arithmetic unit that executes the motion detection unit, image processing, audio processing, and the like. By connecting via the signal line 10, it is possible to reduce the number of overlapping circuits, and to realize a reduction in circuit scale, a reduction in mounting area, and a reduction in cost.

  The common arithmetic unit 9 may be realized by a hardware circuit, may be realized as a part of an LSI, may be realized individually by a single LSI, or may be realized as software. It is.

  When implemented with hardware such as a circuit or LSI, the circuit scale can be reduced, and when implemented with software, power consumption or memory can be reduced.

  Further, a plurality of filter processing units 20 may be provided, and a plurality of common calculation units 9 may be provided.

  Next, the operations of the filter processing unit 20 and the orthogonal transform unit 21 shown in FIG. 4 and the operations of the common calculation unit 9 corresponding thereto will be described with reference to FIGS. It is understood that the common operation unit 9 including the common product-sum operation unit 24 operates appropriately to perform processing in order to reduce the circuit scale.

  5 and 6 are operation flowcharts of the data processing apparatus according to Embodiment 1 of the present invention.

  First, the operations of the filter processing unit 20 and the common product-sum operation unit 24 will be described with reference to FIG.

  First, in step 1, the filter processing unit 20 and the orthogonal transform unit 21 enter into the process after activation. Next, in step 2, the data processing device 2 enters the product-sum operation stage. Here, when entering the product-sum operation stage (step 2), the filter processing unit 20 outputs a use request to the common product-sum operation unit 24 in step 3. When the use request in Step 3 is output, the product-sum operation state continues in Step 4. This product-sum operation state continues until the common product-sum operation unit 24 outputs an end notification in step 5.

  In the product-sum operation state of step 4, the filter processing unit 20 causes the common product-sum operation unit 24 to output necessary data and execute the product-sum operation. Specifically, product-sum processing such as multiplying data by a predetermined coefficient and adding the multiplication results is executed.

  When the product-sum operation is completed, in step 5, the common product-sum operation unit 24 outputs an end notification to the filter processing unit 20. In step 6, the filter processing unit 20 that has received the end notification moves to the next processing. Thereby, the predetermined processing operation of the filter processing unit 20 ends.

  Next, the operation of the common product-sum operation unit 24 will be described with reference to FIG.

  The control unit 23 included in the common calculation unit 9 controls the usage request to the common product-sum calculation processing unit 24 from the filter processing unit 20 and the orthogonal transform unit 21.

  Control is divided into a queuing process in step 11 and a process of the common product-sum operation unit 24 in step 12.

  The queuing process in step 11 will be described.

  First, in step 13, the filter processing unit 20 or the orthogonal transform unit 21 outputs a use request. Next, in step 14, the use request from the filter processing unit 20 or the orthogonal transform unit 21 is queued in the request queue. The use request signal is stocked by this queuing.

  Next, the processing of the common product-sum operation unit 24 in step 12 will be described.

  First, in step 15, the control unit 23 takes out a use request queued in the request queue. Next, in step 16, the control unit 23 confirms that a use request exists in the request queue. If there is a use request, in step 17, the control unit 23 sets the common product-sum operation unit to the use state.

  Next, in step 18, the control unit 23 confirms that the common product-sum operation has been completed. Upon confirming the end of the common product-sum operation in step 18, the control unit 23 outputs an end notification to the filter processing unit 20 or the orthogonal transform unit 21 in step 19.

  Here, the queuing process in step 11 and the common product-sum operation unit process in step 12 are performed in parallel.

  As described above, the arithmetic unit 7 provided redundantly is connected and shared as the common arithmetic unit 9 to the outside, so that the circuit scale is reduced and the above-described flow is also described in terms of operation. The performance is not degraded.

  In addition, FIG. 1 and the like have been described with respect to realization with hardware such as a circuit and LSI, but the same is true even when part or all is software. In particular, when the common arithmetic unit 9 is realized by software, the compression of the program and the accompanying reduction in memory and power consumption are realized.

  A case where software processing is performed using a processor unit will be described with reference to FIG. FIG. 7 is a block diagram of the data processing apparatus according to Embodiment 1 of the present invention.

  FIG. 7 shows a configuration in which common operations are realized by software.

  In the conventional data processing apparatus, the plurality of dedicated calculation units 30 include product-sum calculation 31 and individual calculations 32 and 33 that overlap the plurality of dedicated calculation units 30.

  The data processing apparatus 2 of the present invention shown in FIG. 7 stores these overlapping product-sum operations 31 and individual operations 32 and 33 in the processor unit 34 as a software program. Further, the processor unit 34 is connected to a plurality of dedicated arithmetic units 30 via the signal line 10.

  By providing the product-sum operation 31 and the individual operations 32 and 33 that have been duplicated in each dedicated operation unit 30 in the processor unit 34 as a software program instead of a circuit, the circuit scale can be reduced. Furthermore, there is an advantage that it is possible to flexibly cope with a subsequent change such as a change of a coefficient or a change of a processing procedure as compared with a case where the circuit is shared.

  Further, when the program shared by the processor unit 34 is a program originally duplicated in each dedicated arithmetic unit 30, there is an advantage that the power consumption can be reduced in addition to the reduction of the program scale.

  As described above, as in the case of hardware, reduction of the program scale, reduction of power consumption, cost reduction, and the like are realized.

  The operation is the same as that described with reference to FIGS.

  The circuit or program shared as the common arithmetic unit 9 is not limited to a product-sum operation, but may be a multiplier or an adder, or an arithmetic unit that performs a certain amount of processing.

  With the above configuration, there is no demerit in arithmetic processing, and the circuit scale and program scale can be efficiently reduced to reduce LSI chip area, circuit area, and power consumption. The

(Embodiment 2)
In the second embodiment, a case where clock control is independently included in the common arithmetic unit 9 will be described.

  First, the configuration of the data processing apparatus according to the second embodiment of the present invention will be described with reference to FIG. FIG. 8 is a block diagram of the data processing apparatus according to Embodiment 2 of the present invention.

  In the data processing device 2 illustrated in FIG. 8, the common calculation unit 9 further includes a clock control unit 40 that outputs a clock different from the clock used in the filter processing unit 20 and the orthogonal transform unit 21 which are dedicated calculation units. ing.

  The clock control unit 40 outputs a clock signal independent of the dedicated calculation unit to the common calculation unit 9. The control unit 23 and the common product-sum operation unit 24 use the clock signal output from the clock control unit 40.

  Here, the filter processing unit 20 and the orthogonal transform unit 21 may be desired to operate in parallel. In such a case, if the clock frequency in the filter processing unit 20 and the orthogonal transform unit 21 and the clock frequency in the common arithmetic unit 9 are the same, parallel operation cannot be performed. This is because the common arithmetic unit 9 is shared by the filter processing unit 20 and the orthogonal transform unit 21. That is, because the circuit is shared to reduce the circuit scale, the dedicated arithmetic units such as the filter processing unit 20 do not have a common arithmetic unit inside each, so that each dedicated arithmetic unit has a common arithmetic operation. Cannot be operated simultaneously and cannot be operated in parallel.

  On the other hand, most of the filter processing unit 20 and the orthogonal transform unit 21 need to synchronize with the control mechanism that controls the entire system including the main processor 3, so that the processing speed can be improved. There are limits.

  Here, since the clock control unit 40 is provided separately and independently from other parts such as a dedicated calculation unit, the processing speed of the common calculation unit 9 can be individually controlled, and a decrease in the overall processing speed is prevented. However, the circuit scale can be reduced.

  For example, it is assumed that the clock frequency output from the clock control unit 40 is double the clock frequency in the dedicated arithmetic unit. In this case, the common arithmetic unit 9 operates at a double speed as the filter processing unit 20 or the like. Even when there are two dedicated computing units that are processed in parallel, the common computing unit 9 that is used in common operates at twice the speed of the dedicated computing unit, so the two dedicated computing units apparently operate in parallel. Is the same as

  Even if the product-sum operations required by the filter processing unit 20 and the orthogonal transform unit 21 shown in FIG. 8 are sequentially processed, the entire processing ends with the same number of clocks as in the past. That is, it is possible to cover the difficulty of parallel processing that occurs due to sharing of the arithmetic unit. As a result, processing can be performed at a speed that is not different from the apparent parallel processing, and performance degradation can be prevented.

  Note that the clock frequency output from the clock control unit 40 is preferably not only double speed, but also triple speed or quadruple speed (according to the requirements of the dedicated calculation section), other types, or selectable.

For example, when the number of dedicated arithmetic units is N, the clock frequency of the dedicated arithmetic units is F, and the clock frequency of the common arithmetic units is f, the clock frequency f is f = N * F
Can be processed with the same number of clocks as when all N dedicated arithmetic units are processed in parallel.

  In addition, the clock controller 40 outputs a clock signal only when the common arithmetic unit 9 is operating, and the clock signal is not output when the common arithmetic unit 9 is not operating, so that power consumption can be effectively reduced. . Clock output and non-output are realized by using, for example, a gated clock.

  In particular, the product-sum operation included in the common arithmetic unit 9 includes many sequential circuits using a clock such as a shift register. Therefore, stopping the clock output when not operating is highly effective in reducing power consumption. This is because the power consumption increases in proportion to the clock frequency.

  Next, the operation of the common arithmetic unit 9 will be described with reference to FIG.

  FIG. 9 is an operation flowchart of the common arithmetic unit in the second embodiment of the present invention. The control unit 23 included in the common calculation unit 9 will be described as an operation reference. In addition, here, the data processing apparatus 2 including the filter processing unit 20 and the orthogonal transform unit 21 as illustrated in FIG. 8 will be described.

  Further, it is assumed that the operating frequencies of the clocks supplied to the main processor 3, the filter processing unit 20, and the orthogonal transform unit 21 are the same, and are used as reference clocks in the following description.

  The control unit 23 performs queuing processing of a request signal for use of the common arithmetic unit from the filter processing unit 20 or the like in step 21 and operation processing of the common product-sum arithmetic unit 24 in step 22.

  First, the use request queuing process in step 21 will be described.

  First, in step 13, the control unit 23 confirms the use request output from the filter processing unit 20 or the orthogonal transform unit 21. Next, in step 14, the control unit 23 queues the confirmed use request in the request queue.

  Next, in step 23, the control unit 23 starts time counting simultaneously with queuing. The time count is counted for each use request of the filter processing unit 20 and the orthogonal transform unit 21. As a result, use request signals output from different dedicated arithmetic units are appropriately queued.

  Next, the operation process of the common product-sum operation unit 24 in step 22 will be described.

  First, in step 15, the control unit 23 extracts a request signal from the request queue. Next, in step 16, the control unit 23 confirms the presence or absence of a request signal. If there is a request signal in the request queue at step 24, the control unit 23 checks the time count value associated with the request signal and compares the time count value with the threshold th.

  In step 25, when the time count value is equal to or greater than the threshold th, the clock control unit 40 outputs a clock that is double the reference clock. On the other hand, if the time count value is less than the threshold th in step 26, the clock control unit 40 outputs a clock having the same speed as the reference clock. That is, the time count value represents the number of dedicated operation units operating simultaneously, and accordingly, the operation speed of the common operation unit 9 is increased or decreased.

  Next, in step 17, the common product-sum operation unit 24 enters an operating state, and product-sum operation is executed. Further, in step 18, the control unit 23 confirms the end of the product-sum operation. Next, in step 19, the control unit 23 outputs a product-sum operation end notification to the filter processing unit 20, which is a dedicated calculation unit, or the orthogonal transform unit 21 and the clock control unit 40.

  Furthermore, in step 27, the clock control unit 40 that has received the end notification stops the supply of the clock signal. As a result, unnecessary power consumption of the common arithmetic unit 9 is reduced during a period where no operation is required.

  Note that the queuing process for the use request in step 21 and the operation process (22) of the common product-sum operation unit 24 in step 22 are executed in parallel.

  Through the processing as described above, it is possible to prevent a reduction in processing speed due to sharing of circuits and programs that are common operations. Further, the power consumption can be reduced by stopping the clock signal when the operation in the common arithmetic unit 9 is unnecessary.

(Embodiment 3)
In the third embodiment, a case will be described in which the dedicated operation unit becomes more complicated as the application becomes more complicated.

  First, the configuration of the data processing apparatus according to the third embodiment of the present invention will be described using FIG. 10A and FIG. FIG. 10A is a block diagram of a conventional data processing apparatus, and FIG. 10B is a block diagram of the data processing apparatus in Embodiment 3 of the present invention. Here, a conventional data processing apparatus 50 is shown as a comparison for explaining the merits of the data processing apparatus of the present invention.

  The conventional data processing apparatus 50 includes motion detectors 52, 53, and 54 (shown as “ME” in FIG. 10), an absolute error sum (shown as “SAD” in FIG. 10), an arithmetic unit 55, and a filter processor 20. , An orthogonal transform unit 21 and a product-sum operation unit 22. Here, the absolute error sum calculator 55 is redundantly included in the motion detectors 52, 53, and 54, and the product-sum calculator 22 is redundantly included in the filter processor 20 and the orthogonal transform unit 21. That is, the blocks for performing common operations are provided in duplicate, and the circuit scale is increased.

  On the other hand, the data processing device 51 in the third embodiment includes motion detection units 52, 53, 54, a filter processing unit 20, an orthogonal transformation unit 21, and a sub processor 60 connected to these via the signal line 10. Yes.

  Further, the sub-processor 60 includes an engine interface 56 (represented as “engine I / F” in FIG. 10), a processor unit 57 (denoted as “PU” in FIG. 10), and an absolute error total calculation program (in FIG. A product-sum operation program 59).

  The data processing devices 50 and 51 are used when, for example, all of MPEG2, MPEG4 and JPEG are realized by a single processing device or LSI.

  The motion detectors 52, 53, and 54 detect the motion vector in image compression such as MPEG2. The absolute error sum calculator 55 calculates an absolute error in motion vector detection. The product-sum operation unit 22 performs product-sum operations such as addition and multiplication necessary for filter processing and the like.

  In FIGS. 10A and 10B, three motion detection units 52, 53, and 54, one filter processing unit 20, and one orthogonal transform unit 21 are shown. It is not limited, and other blocks may be included.

  In the conventional data processing apparatus 50, three absolute error sum calculators 55 are provided in duplicate. Furthermore, two product-sum operation units 22 are also provided. The absolute error total calculator 55 and the product-sum calculator 22 perform the same calculation process, and the circuit scale is unnecessarily increased due to the overlap.

  For this reason, the data processing device 51 of the present invention realizes a reduction in circuit scale by extracting and summing the absolute error sum calculator 55 and the product-sum calculator 22.

  At this time, the absolute error total calculator 55 and the product-sum calculator 22 are each realized by a program and mounted on the sub processor 60. These programs can be shared by connecting the sub processor 60 to a dedicated arithmetic unit such as the motion detectors 52, 53, and 54 via the bus 10. Furthermore, since the shared arithmetic processing is implemented by software, there is an advantage that it is possible to cope with flexible changes such as subsequent changes and various coefficients. The software is more flexible than when the shared arithmetic processing is implemented by a dedicated electronic circuit. Of course, it may be implemented by a circuit.

  The sub-processor 60 includes an engine interface 56 and a processor unit 57 that perform processing switching and bus 10 control. The processor unit 57 includes an absolute error sum calculation program 58 and a product-sum calculation program 59.

  With such a configuration, the absolute error total computing unit 55 and the product-sum computing unit 22 that are provided in an overlapping manner are collected, and the circuit scale can be reduced. Furthermore, mounting on the sub-processor 60 increases flexibility.

  Next, operation processing in the sub processor 60 will be described with reference to FIGS. FIG. 11 is an operation flowchart of the sub-processor 60 according to the third embodiment of the present invention, and FIG. 12 is a flowchart of interrupt processing according to the third embodiment of the present invention.

  The engine interface 56 executes a use request queuing process in step 11 and a processor unit activation process in step 31.

  First, the use request queuing process in step 11 will be described.

  First, at step 13, the engine interface 56 detects the presence / absence of a use request signal output by the motion detector or the like. Next, in step 14, the detected use request signal is queued (that is, stocked) in the request queue.

  Next, the processor unit activation process in step 31 will be described.

  First, in step 15, the engine interface 56 extracts a request signal from the request queue. Next, at step 16, the presence or absence of a request signal is confirmed. If there is a request signal, in step 32, the engine interface outputs an interrupt signal to the processor unit 57 to put the processor unit into an operating state.

  Next, in step 17, the program included in the processor unit 57 is put into an operating state. By entering the operating state, a program such as a product-sum operation is executed. The result of the program is output to a motion detection unit or the like.

  Next, at step 18, the end of the program operation is confirmed. If the end of the program operation is confirmed, the processor unit 57 outputs an end notification signal to the engine interface 56 in step 19. Thereby, the program operation in the processor unit 58 is completed. Furthermore, returning to the initial state, the next operation process is started as necessary.

  Next, interrupt processing will be described with reference to FIG.

  First, in step 41, while the operation of the processor unit 57 is completed, the processor unit 57 is waiting in an interrupt waiting state.

  Next, in step 42, when an interrupt request is generated from the engine interface 56, the processor unit 57 shifts to an interrupt handler.

  Next, in step 43, the interrupt handler first specifies the request source. Further, in accordance with this specification, the absolute error sum calculation program is executed in step 44. Alternatively, in step 45, the product-sum operation program is executed.

  Next, in step 46, after the computation is completed, these programs set a performance end flag and end the interrupt handler state. As a result, the processor unit 57 enters the interrupt waiting state again.

  As described above, various calculation processes can be realized by one sub-processor 60 by performing the required calculation with the request source by the interrupt handler using the engine interface 56.

  Furthermore, by collecting the overlapping arithmetic units as programs in the sub-processor 60, the circuit scale, LSI chip area, and mounting area can be reduced.

  Moreover, there is an advantage that flexibility is increased by being implemented by a program.

  If there is a necessary process other than the queuing process and the processor unit activation process, the engine interface 56 only needs to further perform switching.

  Further, as shown in FIG. 13, the clock control unit 40 performs clock control independently in the sub-processor 60, so that the processing speed can be prevented from being lowered and the power consumption can be reduced. FIG. 13 is a block diagram of a data processing apparatus according to Embodiment 3 of the present invention.

  As described in the first embodiment, since the sub processor 60 has a clock independently, the overall processing speed can be prevented from being lowered.

  The data processing apparatus according to the present invention can be suitably used, for example, in a technical field where it is necessary to reduce the circuit scale and cope with various applications.

(A) Block diagram of conventional data processing device (b) Block diagram of data processing device in Embodiment 1 of the present invention 1 is a block diagram of a data processing apparatus according to Embodiment 1 of the present invention. (A) Internal block diagram of common arithmetic unit in Embodiment 1 of the present invention (b) Internal block diagram of common arithmetic unit in Embodiment 1 of the present invention (A) Block diagram of conventional data processing device (b) Block diagram of data processing device in Embodiment 1 of the present invention Operation flow chart of data processing apparatus in Embodiment 1 of the present invention Operation flow chart of data processing apparatus in Embodiment 1 of the present invention 1 is a block diagram of a data processing apparatus according to Embodiment 1 of the present invention. The block diagram of the data processor in Embodiment 2 of this invention Operation flow chart of common arithmetic unit in embodiment 2 of the present invention (A) Block diagram of a conventional data processing device (b) Block diagram of a data processing device according to Embodiment 3 of the present invention Operation flowchart of sub-processor 60 in Embodiment 3 of the present invention Flow chart of interrupt processing in Embodiment 3 of the present invention The block diagram of the data processor in Embodiment 3 of this invention Block diagram of a conventional data processing device

Explanation of symbols

1, 2, 50, 51 Data processor 3 Main processor 4, 5, 6, 12 Dedicated operation unit 7 Operation unit 8 Signal line 9, 13 Common operation unit 10 Signal line 15 Common product-sum operation unit 16 Individual operation unit 17 Selection Unit 18 Common product-sum operation control unit 20 Filter processing unit 21 Orthogonal transformation unit 22 Product-sum operation unit 23 Control unit 24 Common product-sum operation unit 30 Dedicated operation unit 31 Common product-sum operation program 32, 33 Individual operation program 34 Processor unit 40 Clock control units 52, 53, 54 Motion detection unit 55 Absolute error total calculator 56 Engine interface 57 Processor unit 58 Absolute error total calculation program 59 Product-sum calculation program 100 Data processor 101 Main processor 102 Calculation processing unit

Claims (12)

A plurality of dedicated calculation units for performing predetermined calculations;
A signal line connected to the plurality of dedicated arithmetic units;
A data processing apparatus including a common arithmetic unit that is connected to the plurality of dedicated arithmetic units via the signal line and performs common arithmetic processing,
The common arithmetic unit is a data processing device that is used in common in at least two of the plurality of dedicated arithmetic units. The data processing apparatus according to claim 1, wherein the common operation unit includes at least one common product-sum operation unit that performs a product-sum operation commonly used by at least two or more of the plurality of dedicated operation units. The data processing apparatus according to claim 2, wherein the common calculation unit further includes at least one individual calculation unit that performs a calculation that is not commonly used by the plurality of dedicated calculation units. 4. The data processing device according to claim 1, wherein each of the plurality of dedicated calculation units uses a calculation result obtained by combining the common product-sum calculation unit and the individual calculation unit. 5. 5. The system according to claim 3, wherein the common calculation unit includes a plurality of the individual calculation units, and further includes a selection unit that selects a predetermined individual calculation unit corresponding to the request of the dedicated calculation unit from the plurality of individual calculation units. The data processing apparatus described. The data processing apparatus according to claim 1, wherein there are a plurality of the common arithmetic units and the number is less than the number of the plurality of dedicated arithmetic units. The data processing apparatus according to claim 1, wherein the plurality of dedicated arithmetic units are at least one of a filter processing unit, an orthogonal transformation processing unit, a motion detection unit, and a motion compensation unit. The data processing apparatus according to claim 1, wherein the common calculation unit further includes a clock control unit that outputs a clock independent of the dedicated calculation unit. The data processing apparatus according to claim 8, wherein the clock control unit outputs no clock signal when the common arithmetic unit is not operating. When the number of the dedicated arithmetic units is N, the clock frequency of the dedicated arithmetic units is F, and the clock frequency of the common arithmetic unit is f, the clock frequency f is f = N * F
The data processing device according to claim 8, defined by The data processing apparatus according to claim 1, wherein the common arithmetic unit includes a processor unit that executes program processing. 12. The data processing apparatus according to claim 11, wherein the processor unit includes a common product-sum operation program that executes a product-sum operation that is commonly used by at least two or more of the plurality of dedicated operation units.

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