JP2006146390A - Memory bus conversion device and information processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To mutually connect semiconductor memories differed in working speeds or access methods. <P>SOLUTION: An address conversion part 21 transmits an address signal SIG20 accepted from a bus 7 to a ROM 5, and a signal conversion part 20 converts a control signal SIG21 accepted from the bus 7 to a ROM-read signal SIG27 transmitted to the ROM 5. A storage part 22 temporarily holds data accepted from the ROM 5, and an output control part 23 reads data stored in the storage part 22 and outputs data based on a control protocol of an SDRAM 3. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a memory bus converter for connecting different buses, and more particularly to a memory bus converter for connecting a plurality of semiconductor memories having different operation speeds and access methods in common, and an information processing system using the same.

Conventionally, as this type of memory bus conversion device, a technique for converting the amplitude level of signals that are arranged between two buses to which semiconductor memories having different power supply voltages are connected and exchanged with each other has been disclosed. (See Patent Document 1). In this technique, a bus B is connected to a bus A connected to a CPU (microprocessor) via a memory bus converter. The semiconductor memory A is connected to the bus A, and the semiconductor memory B is connected to the bus B. The semiconductor memory A and the semiconductor memory B have different power supply voltages. Therefore, the memory bus conversion device converts the amplitude levels of the semiconductor memory A and the semiconductor memory B to the same level. Therefore, even if the power supply voltages are different, it is possible to connect the same type of semiconductor memories, for example, DRAMs or SRAMs, but it is impossible to connect semiconductor memories having different operation speeds or access methods. .
Japanese Patent Laid-Open No. 10-289043

  The problem to be solved is that in the above prior art, for example, DRAMs or SRAMs can be connected, but semiconductor memories having different operation speeds and access methods cannot be connected. .

  In the memory bus conversion device according to the present invention, the address information and the control signal based on the control protocol of the first memory are received from one bus and converted into the address information and the control signal based on the control protocol of the second memory internally. The most important feature is that desired data is read from the second memory, and this data is output to the one bus based on the control protocol of the first memory.

  By using the bus to which the first memory is connected as a common bus, a single memory controller can control a plurality of memories having different control protocols.

  An information processing system having a plurality of semiconductor memories with different control protocols could be easily realized with a simple configuration.

First, an outline of an information processing system for controlling SDRAMs and ROMs having different control protocols using a memory controller using the memory bus conversion device according to this embodiment will be described, and then the details of the memory bus conversion device according to this embodiment. Will be described.
FIG. 1 is a block diagram illustrating the configuration of the information processing system according to the first embodiment.
As shown in the figure, the information processing system 100 includes a CPU 1, a memory controller 2, an SDRAM 3, a memory bus conversion device 4, a ROM 5, and an input / output control means 6.

The CPU 1 is a central processing unit that controls the entire information processing apparatus 100, and is connected to the memory controller 2.
The memory controller 2 is a part that controls access from the CPU 1 and the input / output control means 6 to the SDRAM 3 and the ROM 5, and is connected to the SDRAM 3 and the memory bus conversion device 4 by the bus 7.

The SDRAM 3 is a synchronous random access memory and is connected to the bus 7.
The memory bus conversion device 4 accepts a signal based on the control protocol of the SDRAM 3 from the bus 7, converts it into a signal based on the control protocol of the ROM 5, outputs it to the bus 8, and accepts a signal based on the control protocol of the ROM 5 from the bus 8. The control protocol conversion device converts the signal into a signal based on the control protocol of the SDRAM 3 and outputs the signal to the bus 7. This apparatus is connected to the memory controller 2 and the bus 7 and to the ROM 5 and the bus 8 respectively. This apparatus will be described in detail later.
The ROM 5 is an asynchronous read-only memory and is connected to the bus 8.

The input / output control means 6 includes a keyboard and a display device, serves as a man-machine interface between the memory controller 2 and an operator, and is connected to the memory controller 2.
The bus 7 is a signal path that connects the memory controller 2, the SDRAM 3, and the memory bus conversion device 4. The bus 7 transmits a signal based on the control protocol of the SDRAM 3.
The bus 8 is a signal path that connects the memory bus conversion device 4 and the ROM 5. The bus 8 transmits a signal based on the control protocol of the ROM 5.

Next, details of the memory bus converter 4 will be described.
FIG. 2 is a block diagram illustrating a configuration of the memory bus conversion device according to the first embodiment.
As shown in the figure, the memory bus conversion device 4 includes therein a signal conversion unit 20, an address conversion unit 21, a storage unit 22, and an output control unit 23, and a bus 7 to which the SDRAM 3 is connected, and a ROM 5 Is connected to the bus 8 to which is connected.

The signal converter 20 is a part that receives an address signal SIG 20 and a control signal SIG 21 from the bus 7 and sends a ROM read signal SIG 27 to the ROM 5 via the bus 8. Further, an address load signal SIG23 is generated based on the control signal SIG21 and sent to the address conversion unit 21, and further a data latch signal SIG24 is generated based on the control signal SIG21 and sent to the address conversion unit 21 and the storage unit 22. It is also a part to do.
The address conversion unit 21 is a part that receives the address signal SIG20 from the bus 7, receives the address load signal SIG23 and the data latch signal SIG24 from the signal conversion unit 20, and sends the ROM address signal SIG26 to the ROM 5 via the bus 8. .

The storage unit 22 is a rewritable semiconductor memory such as a flip-flop or static RAM, for example. The storage unit 22 receives a ROM data signal SIG28 read from the ROM 5 via the bus 8, and receives a data latch signal SIG24 received from the signal conversion unit 20. The data (value) is temporarily stored in synchronization with the.
The output control unit 23 is a part that reads data (value) temporarily stored in the storage unit 22 and sends the data signal SIG 22 to the bus 7 based on the control protocol of the SDRAM 3.

Next, the control protocol of the SDRAM 3 connected to the bus 7 will be described by limiting only the part necessary for the description of the present invention.
FIG. 3 is an explanatory diagram (part 1) of mode setting.
(A) is a figure explaining the access at the time of mode register setting, (b) is a figure explaining the operation | movement which reads data from SDRAM3 (FIG. 1) in operation.
FIG. 4 is an explanatory diagram (part 2) of mode setting.
(A) is a diagram showing the relationship between the mode register address and the setting contents at the time of the mode register setting command for the SDRAM, and (b) is the relationship between the mode register address and the setting contents at the memory bus converter setting command. FIG.

  After power-on, CPU 1 (FIG. 1) sends a mode register setting command to SDRAM 3 (FIG. 1) via memory controller 2 (FIG. 1). The control signal SIG21 (FIG. 2) at this time is MRS. Here, MRS is a standard command combined at the logic level described in the SDRAM user's manual, and therefore, the description thereof is omitted. At the same time, the set value is sent out. As shown in FIG. 4A, the set value stores the burst length from a0 to a2 of the mode register, the lap type from a3, and the CAS latency from a4 to a6. Here, as shown in FIG. 3B, the burst length is the number of times the SDRAM 3 (FIG. 1) outputs data at consecutive addresses in one read command. The wrap type is irrelevant to the present invention and will not be described. The CAS latency is the number of clock cycles from when the SDRAM 3 (FIG. 2) receives a read command until the data signal SIG22 (FIG. 2) is output.

  Similarly, after the power is turned on, the CPU 1 (FIG. 1) sends a mode register setting command to the memory bus converter 4 (FIG. 1) via the memory controller 2 (FIG. 1). The control signal SIG21 (FIG. 2) at this time is the same as that of the SDRAM 3 (FIG. 1). At the same time, the set value is sent out. As shown in FIG. 4B, the set values are as follows: ROM burst length from a0 to a2 of the mode register, CAS latency from a3 to a6, start access cycle from a7 to a9, burst from a10 to a11 Each access cycle is stored. Here, the burst access cycle and the start access cycle are unique to the memory bus converter 4 (FIG. 1) and are the number of clock cycles when accessing the ROM 5 (FIG. 1). The ROM burst length is the number of continuous accesses to the ROM 5 (FIG. 1), and the CAS latency is the same as that of the SDRAM 3 (FIG. 1).

The operation of the memory bus conversion device according to the first embodiment will be described.
FIG. 5 is a time chart illustrating the operation of the memory bus conversion device according to the first embodiment.
This figure shows the operation of reading data from the ROM 5 (FIG. 1).
In order from the top of the figure, (a) shows the passage of time expressed by a clock cycle common to all items, (b) shows the control signal SIG21, (c) shows the address signal SIG20, and (d) shows the data signal SIG22. (E) shows the address load signal SIG23, (f) shows the data latch signal SIG24, (g) shows the ROM read signal SIG27, (h) shows the ROM address signal SIG26, and (i) shows the ROM data signal SIG28. , Respectively.

  As a premise of the operation description, the CAS latency is set to 11, the ROM burst length is set to 4, the start cycle is set to 3, and the burst cycle is set to 2 for the memory bus conversion device 4 (FIG. 1) when the mode register is set. To do. The description will be given below in the order of clock cycles.

Clock 20
The memory controller 2 (FIG. 1) changes the control signal SIG21 to READ and at the same time changes to the address (A0) from which the address signal SIG20 is read. The signal converter 20 (FIG. 2) recognizes the READ command and turns on the address load signal.

Clock 21
The address conversion unit 21 (FIG. 2) recognizes that the address load signal SIG23 is turned on, and outputs the address A0 to the ROM 5 (FIG. 2) (ROM address signal SIG26). The ROM 5 (FIG. 2) outputs data D0 corresponding to the address A0 after a predetermined time has elapsed (ROM data signal SIG28).

Clock 23
The signal converter 20 (FIG. 2) turns on the data latch signal SIG24 in accordance with the start cycle set at the time of the mode register setting instruction.
Clock 24
The address conversion unit 21 (FIG. 2) recognizes that the data latch signal SIG24 is turned on, increments the ROM address signal SIG26 to A0 + 1, and outputs it to the ROM 5 (FIG. 1). The storage unit (FIG. 1) recognizes that the data latch signal SIG24 is turned on and stores the data D0 (ROM data signal SIG28).

Clock 25
The signal converter 20 (FIG. 1) turns on the data latch signal SIG24 in accordance with the burst cycle set at the time of the mode register setting instruction.
Clock 26
The address conversion unit 21 (FIG. 2) recognizes that the data latch signal SIG24 is turned on and increments the ROM address signal SIG26 to A0 + 2, and the storage unit (FIG. 2) stores the data D1 (ROM data signal SIG28). ).

Clock 27
The signal converter 20 (FIG. 1) turns on the data latch signal SIG24 in accordance with the burst cycle set at the time of the mode register setting instruction.
Clock 28
The address conversion unit 21 (FIG. 2) recognizes that the data latch signal SIG24 is turned on and increments the ROM address signal SIG26 to A0 + 3, and the storage unit (FIG. 2) stores the data D2 (ROM data signal SIG28). ).

Clock 29
The signal converter 20 (FIG. 1) turns on the data latch signal SIG24 in accordance with the burst cycle set at the time of the mode register setting instruction.
Clock 30
The address conversion unit 21 (FIG. 2) recognizes that the data latch signal SIG24 is turned on and increments the ROM address signal SIG26 to A0 + 4, and the storage unit (FIG. 2) stores the data D3 (ROM data signal SIG28). ). Since the data is read from the ROM 5 (FIG. 1) as many times as the ROM burst length set at the time of the mode register setting command, the ROM read signal SIG27 is turned off.

Clock 31
Since the number of clocks that have elapsed since the memory controller 2 (FIG. 1) issued the READ instruction and the CAS latency set at the time of the mode register setting instruction match, the output control unit 23 (FIG. 2) is changed from the storage unit 22 (FIG. 2). The latch data D0 is read and output to the bus 7 (data signal SIG22).

Clock 32
The output control unit 23 (FIG. 2) reads the next latch data D1 from the storage unit 22 (FIG. 2) and outputs it to the bus 7 (data signal SIG22).
Clock 33
The output control unit 23 (FIG. 2) reads the next latch data D2 from the storage unit 22 (FIG. 2) and outputs it to the bus 7 (data signal SIG22).

Clock 34
The output control unit 23 (FIG. 2) reads the next latch data D3 from the storage unit 22 (FIG. 2) and outputs it to the bus 7 (data signal SIG22).
Clock 35
Since the burst length set at the time of the mode register setting instruction matches the amount of data output by the output control unit 23 (FIG. 2), the access is terminated.

  As described above, address information and control signals based on the SDRAM control protocol are received from the bus 7 and converted into address information and control signals based on the ROM control protocol, and desired data is read from the ROM. Furthermore, since this data can be output to the bus 7 based on the control protocol of the SDRAM, the memory 7 having a different control protocol is controlled by a single memory controller using the bus 7 connected to the SDRAM as a common bus. (ROM) can be controlled.

  In the above description, the difference between the signal amplitude level of the first memory and the signal amplitude level of the second memory is not mentioned. However, as shown in FIG. 2, the address converter 21 is between the address signal SIG20 and the ROM address signal SIG26, and the signal converter 20 is between the control signal SIG21 and the ROM read signal SIG27. And the ROM data signal SIG28 are respectively provided with output control sections 23. Accordingly, the signal amplitude level of the first memory and the second memory are set by setting the input / output signal amplitude levels in the address conversion unit 21, the signal conversion unit 20, and the output control unit 23 to a predetermined level. The difference in signal amplitude level can be easily converted.

  In the first embodiment, the bus 7 to which the SDRAM is connected is used as a common bus, and the ROM having a different control protocol can be controlled by one memory controller. However, the first embodiment assumes that the data width of the SDRAM and the data width of the ROM are the same. However, sometimes the data width of the SDRAM and the data width of the ROM may be different. The present embodiment aims to cope with such a case.

First, an outline of an information processing system for controlling SDRAMs and ROMs having different control protocols using a memory controller using the memory bus conversion device according to this embodiment will be described, and then the details of the memory bus conversion device according to this embodiment. Will be described.
FIG. 6 is a block diagram illustrating a configuration of the information processing system according to the second embodiment.
As shown in the figure, the information processing system 200 includes a CPU 1, a memory controller 2, a memory bus conversion device 40, an SDRAM 41, a ROM 5, and an input / output control means 6.

  In the present embodiment, as an example, the SDRAM 41 is 64 bits and the ROM 5 is 32 bits. In order to control the SDRAM 41 and the ROM 5 having different numbers of bits with one memory controller 2, the memory bus conversion device 40 includes a bit width conversion unit. Since other parts are the same as those in the first embodiment, description thereof will be omitted and only the memory bus converter 40 will be described.

FIG. 7 is a block diagram illustrating a configuration of the memory bus conversion device according to the second embodiment.
As shown in the figure, the memory bus conversion device 40 includes therein a signal conversion unit 31, an address conversion unit 21, a storage unit 22, an output control unit 23, and a bit width conversion unit 30, and an SDRAM 41 is connected thereto. Connected to the bus 7 and the bus 8 to which the ROM 5 is connected. Only differences from the first embodiment will be described below. Portions similar to those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and description thereof is omitted.

  The signal converter 31 is a part that receives the address signal SIG 20 and the control signal SIG 21 from the bus 7 and sends a ROM read signal SIG 27 to the ROM 5 via the bus 8. In addition, an address load signal SIG23 is generated based on the control signal SIG21 and is sent to the address conversion unit 21, and further, a data latch signal SIG24 and a bus width conversion designation signal SIG30 are generated based on the control signal SIG21. The signal SIG 24 is also sent to the address conversion unit 21 and the bit width conversion unit 30, and the bus width conversion designation signal SIG 30 is sent to the bit width conversion unit 30. The signal conversion unit 31 includes a bit width storage unit 31-1 for storing the bit width of the ROM 5 therein.

  Here, the bus width conversion designation signal SIG30 compares the control signal SIG21 with the bit width of the ROM 5 stored in the bit width storage means 31-1, and collects the ROM data signal SIG28 for the bit width conversion unit 30 several times. It is a signal that specifies whether to memorize. As an example, when the bit width of the SDRAM 41 is 64 bits and the bit width of the ROM 5 is 32 bits, it is a signal that specifies that the ROM data signals SIG28 are combined twice to match the bit width 64 bits of the SDRAM 41.

  The bit width conversion unit 30 receives the data latch signal SIG24 and the bus width conversion designation signal SIG30 from the signal conversion unit 31, and the ROM data signal SIG28 from the bus 8, and outputs the bus width conversion data signal SIG31 to the storage unit 22. It is a part to do.

The operation of the memory bus conversion device according to the second embodiment will be described.
FIG. 8 is a time chart illustrating the operation of the memory bus conversion device according to the second embodiment.
This figure shows the operation of reading data from the ROM 5 (FIG. 7).
In order from the top of the figure, (a) shows the passage of time expressed by a clock cycle common to all items, (b) shows the control signal SIG21, (c) shows the address signal SIG20, and (d) shows the data signal SIG22. (E) shows the address load signal SIG23, (f) shows the data latch signal SIG24, (g) shows the ROM read signal SIG27, (h) shows the ROM address signal SIG26, and (i) shows the ROM data signal SIG28. , (J) represents the bus width conversion data signal SIG31, respectively.

  As a premise for the explanation of the operation, it is assumed that the CAS latency is set to 11, the ROM burst length is set to 4, the start cycle is set to 3, and the burst cycle is set to 2 for the memory bus conversion device 4 (FIG. 7) when the mode register is set. To do. Further, it is assumed that the bit number of the SDRAM 41 is 64 bits and the bit number of the ROM 5 is 32 bits. The description will be given below in the order of clock cycles.

Clock 40
The memory controller 2 (FIG. 6) changes the control signal SIG21 to READ and at the same time changes to the address (A0) from which the address signal SIG20 is read. The signal converter 31 (FIG. 7) recognizes the READ command and turns on the address load signal.

Clock 41
The address conversion unit 21 (FIG. 7) recognizes that the address load signal SIG23 is turned on, and outputs the address A0 to the ROM 5 (FIG. 6) (ROM address signal SIG26). The ROM 5 (FIG. 6) outputs data D0 corresponding to the address A0 after a predetermined time has elapsed (ROM data signal SIG28).

Clock 43
The signal converter 20 (FIG. 7) turns on the data latch signal SIG24 in accordance with the start cycle set at the time of the mode register setting instruction.
Clock 44
The address conversion unit 21 (FIG. 7) recognizes that the data latch signal SIG24 is turned on, increments the ROM address signal SIG26 to A0 + 1, and outputs it to the ROM 5 (FIG. 6). The bit width conversion unit 30 (FIG. 7) recognizes that the data latch signal SIG24 is turned on and stores the data D0 (ROM data signal SIG28).

Clock 45
The signal converter 31 (FIG. 7) turns on the data latch signal SIG24 in accordance with the burst cycle set at the time of the mode register setting instruction.
Clock 46
The address conversion unit 21 (FIG. 7) recognizes that the data latch signal SIG24 is turned on and increments the ROM address signal SIG26 to A0 + 2, and the bit width conversion unit 30 (FIG. 7) stores the data D1 (ROM) Data signal SIG28).

Clock 47
The signal converter 31 (FIG. 7) turns on the data latch signal SIG24 in accordance with the burst cycle set at the time of the mode register setting instruction. Since the bit width conversion unit 30 stores the ROM data signal SIG28 twice (data D0 and data D1) in accordance with the specification of the bus width conversion specification signal SIG30, the data D0D1 is stored as the bus width conversion data signal SIG31 in the storage unit 22 (FIG. 7), and the storage unit 22 (FIG. 7) temporarily holds this data D0D1.

Clock 48
The address conversion unit 21 (FIG. 7) recognizes that the data latch signal SIG24 is turned on, increments the ROM address signal SIG26 to A0 + 3, and outputs it to the ROM 5 (FIG. 6). The bit width conversion unit 30 (FIG. 7) recognizes that the data latch signal SIG24 is turned on and stores the data D2 (ROM data signal SIG28).

Clock 49
The signal converter 31 (FIG. 7) turns on the data latch signal SIG24 in accordance with the burst cycle set at the time of the mode register setting instruction.
Clock 50
The address conversion unit 21 (FIG. 7) recognizes that the data latch signal SIG24 is turned on and increments the ROM address signal SIG26 to A0 + 4, and the bit width conversion unit 30 (FIG. 7) turns on the data latch signal SIG24. Recognizing this, the data D3 is stored (ROM data signal SIG28). Since the data is read from the ROM 5 (FIG. 1) as many times as the ROM burst length set at the time of the mode register setting command, the ROM read signal SIG27 is turned off.

Clock 51
Since the bit width conversion unit 30 stores the ROM data signal SIG28 twice (data D2 and data D3) in accordance with the specification of the bus width conversion specification signal SIG30, the data D2D3 is stored as the bus width conversion data signal SIG31 in the storage unit 22 ( 7), the storage unit 22 (FIG. 7) temporarily holds this data D2D3. Since the number of clocks that have elapsed since the memory controller 2 (FIG. 6) issued the READ instruction and the CAS latency set at the time of the mode register setting instruction match, the output control unit 23 (FIG. 7) is stored in the storage unit 22 (FIG. 7). Latch data D0D1 is read out as a latch data signal SIG29 and sent to the bus 7 as a data signal SIG22.

Clock 52
The output control unit 23 (FIG. 7) reads the latch data D2D3 from the storage unit 22 (FIG. 7) as the latch data signal SIG29 and sends it to the bus 7 as the data signal SIG22.
Clock 53
Since the burst length set at the time of the mode register setting instruction matches the amount of data output as the data signal SIG22, the access is terminated.

  As described above, the memory bus conversion device 40 (FIG. 7) according to the present embodiment includes the bit width conversion unit 30 and the bit width storage means 31-1, so that the data width of the SDRAM and the data width of the ROM. Even if they are different, it is possible to control with one memory controller.

  The memory bus converter according to the present invention is applicable to all information processing systems using SDRAM and ROM.

1 is a block diagram illustrating a configuration of an information processing system according to a first embodiment. 1 is a block diagram illustrating a configuration of a memory bus conversion device according to a first embodiment. It is explanatory drawing (the 1) of mode setting. It is explanatory drawing (the 2) of mode setting. 3 is a time chart illustrating an operation of the memory bus conversion device according to the first embodiment. It is a block diagram which shows the structure of the information processing system of Example 2. FIG. FIG. 6 is a block diagram illustrating a configuration of a memory bus conversion device according to a second embodiment. 6 is a time chart illustrating an operation of the memory bus conversion device according to the second embodiment.

Explanation of symbols

4 Memory Bus Conversion Device 7 Bus 8 Bus 20 Signal Conversion Unit 21 Address Conversion Unit 22 Storage Unit 23 Output Control Unit SIG20 Address Signal SIG21 Control Signal SIG22 Data Signal SIG23 Address Load Signal SIG24 Data Latch Signal SIG26 ROM Address Signal SIG27 ROM Read Signal SIG28 ROM data signal SIG29 Latch data signal

Claims (5)

A bus conversion device in which a first memory is connected to one bus and a second memory based on a control protocol different from that of the first memory is connected to the other bus,
An address conversion unit that converts address information received from the one bus into address information to be sent to the second memory;
A signal converter for converting a control signal received from the one bus into a control signal to be sent to the second memory;
A storage unit for temporarily storing data received from the second memory;
An output control unit that reads out data stored in the storage unit and outputs data based on the control protocol of the first memory.   The first memory is SDRAM, the second memory is ROM, and the control protocol of the second memory is the control protocol of the first memory, the operation speed, the access method, and the signal amplitude level. 2. The memory bus conversion device according to claim 1, wherein at least one of them is different.   The data is received and stored from the second memory, and each time data is received, the received data is carried by the bit width of the second memory, and the bit width of the received data is that of the first memory. The memory bus conversion device according to claim 1, further comprising a bit width conversion unit that collectively sends all accepted data to the storage unit when the bit width matches.   The signal conversion unit stores the bit width of the second memory, compares the bit width of the first memory, and compares the bit width of the received data with the bit width of the first memory. 4. The memory bus conversion device according to claim 3, wherein the number of data receptions is calculated, and the number of receptions is specified in the bit width conversion unit. An information processing system comprising the memory bus conversion device according to any one of claims 1 to 4.

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