JP2006135660A - Association memory and packet transfer device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the generation of noises by inhibiting the rapid increase of a power consumption. <P>SOLUTION: A retrieval control unit carries out retrievals in parallel by first and second retrieval-key storage sections receiving a plurality of retrieval keys on the basis of an operation clock, a plurality of retrieval tables 122-1 and 2 presetting address conditions, a retrieval-key distributor 121 making a plurality of the retrieval keys correspond to a plurality of the retrieval tables 122-1 and 2 and a plurality of tables to which a plurality of the retrieval keys are made to correspond. The retrieval control unit successively starts the retrievals regarding the retrieval keys made to correspond to a plurality of the tables 122-1 and 2. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an associative memory (CAM = Contents Addressable Memory) for performing a high-speed route table search and a network device using the CAM.

  Routers and switches constituting an IP (Internet Protocol) network perform a routing search for determining a packet destination and a flow table search for detecting a flow to which the packet belongs.

  In such a network device, a path using an associative memory (CAM = Contents Addressable Memory) that inputs an address to be searched as a search key (bit string) and outputs an address corresponding to the search key input in a preset table. A table search method is widely adopted.

  In recent years, speeding up of associative memory (hereinafter referred to as CAM) search has been studied due to an increase in the size of a network and an increase in traffic. As an increase in the speed of CAM, there is a method of improving the amount of data input to the CAM. In order to increase the amount of input data per unit clock time, different data is generated at both the rising edge and falling edge of the clock signal. There is a Double Data Rate (hereinafter referred to as DDR) method.

As another speedup, there is known a technique in which search processing capability per unit time is improved by performing CAM search processing in parallel (for example, Patent Document 1). In this method, the storage area of the CAM is divided into a plurality of banks, the input search key is divided into upper bits and lower bits, and the upper bits and lower bits are searched simultaneously in the plurality of banks.
US Pat. No. 6,374,326

  However, in the conventional example of Patent Document 1, the search operation timings of a plurality of banks performing parallel search are the same timing. In this case, all banks of the CAM are searched at the same time, and when the search frequency increases from a state where no search is performed at all, the current consumption greatly increases, and the power supply in the CAM accompanying the increase in the current consumption There is a possibility that noise becomes large and the search operation of CAM may not be performed correctly due to this noise.

  In addition, DDR as described above is known regarding CAM input. However, in the conventional example of Patent Document 1, the timing at which processing is performed when DDR is applied to search key input is described. However, in the case of applying a general SDR (Single Data Rate), even if the search processing is improved by parallelization, the bandwidth of the input is not expanded, so that it is not possible to improve the performance of the entire CAM. There's a problem.

  The present invention has been made in view of these problems, and balances the input bandwidth of the search key to the CAM and the search performance of the CAM, thereby improving the overall performance of the CAM while consuming the search at the time of execution. An object of the present invention is to suppress power supply noise caused by a sudden increase in current and prevent malfunction of the CAM.

  The present invention relates to a search key receiving unit that receives a plurality of search keys based on an operation clock, a plurality of search tables in which address conditions are set in advance, and a search key distribution that associates the plurality of search keys with the plurality of search tables. And a search control unit that executes a search in parallel with the plurality of tables associated with the plurality of search keys, wherein the search control unit is associated with the plurality of tables. The search is sequentially started.

  The search key receiving unit sequentially receives the plurality of search keys at a rising edge and a falling edge of the operation clock.

  Therefore, the present invention achieves the speed of the associative memory by sequentially starting a plurality of search tables with different search keys and then processing in parallel, thereby starting a plurality of search processes sequentially. Therefore, the power consumption of the associative memory can be increased in stages, and the induction of noise caused by the rapid increase in power consumption can be suppressed and stable search processing can be realized.

  In addition, since the search key is input by DDR, the amount of data (search key) that can be input to the search table per unit time can be increased, and the processing capability of the associative memory can be further improved.

  Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

  FIG. 1 shows a router using a CAM (Contents Addressable Memory) of the present invention, and the general operation of the router will be described below with reference to FIGS.

  FIG. 1 shows a block diagram of a router 200 of the present invention. The router 200 receives N input lines 201-i (i = 1 to N) for receiving packets from the network 1, and N output lines 202-i (i = 1 to N) for transmitting packets to the network 1. N interface units 210-i (i = 1 to N) that process packets to be transmitted and received, one packet relay processing unit 250 that couples the interface units 210-i, and each interface unit 210-i It comprises a processor 280 for controlling. The processor 280 receives a command from the control terminal 10.

  The interface unit 210-i includes a packet reception circuit 230 that performs packet reception processing, a next hop IP address of the packet based on a destination IP address of the input (received) packet, and a line number (output) that outputs the packet. A route table search unit 100 that outputs the information to the packet reception circuit 230, a packet transmission circuit 270 that performs transmission processing of the packet received from the packet relay processing unit 250, and a MAC address. And an ARP (Address Resolution Protocol) table search unit 220 indicating the correspondence between IP addresses.

  When a packet is input from the input line 201-i, the packet receiving circuit 230 adds an internal header portion to the header of the received packet and accumulates the packet, and at the same time, determines the destination IP address in the header as the route table search unit 100. Send to.

  The routing table search unit 100 obtains an output line number that is an output line number that outputs a packet input from the destination IP address and a next hop IP address that is an IP address of a next hop (router or terminal) that receives the packet. The determination is made and transmitted to the packet receiving circuit 230 as packet output line information.

  The packet receiving circuit 230 writes the output line number and the next hop IP address in the packet output line information in the internal header part, and transmits them to the packet relay processing part 250.

  The packet relay processing unit 250 that has received the packet transmits the packet to the packet transmission circuit 270 of the interface unit 210-i corresponding to the output line number. The packet transmission circuit 270 accumulates this packet and transmits the next hop IP address of the internal header part to the ARP table search unit 220 at the same time.

  The ARP table search unit 220 determines the MAC address corresponding to the next hop IP address and transmits it to the packet transmission circuit 270 as MAC address information.

  Upon receiving the MAC address information, the packet transmission circuit 270 writes the MAC address in this information as a destination MAC address and the MAC address of the input / output line of the interface unit 210-i as a source MAC address in the packet, The packet that has been stored by deleting the part is transmitted to the output line 202-i.

  Next, FIG. 2 shows a block diagram of the route table search unit 100 of the present invention. In the routing table search unit 100, a destination IP address storage unit 180 that stores a destination IP address is connected to the packet receiving circuit 220 via the signal line 21, and the destination IP address storage unit 180 is connected to the search control unit 110. The search result of the search control unit 110 is connected to the packet receiving circuit 230 via the signal line 22.

  The search control unit 110 has a CAM 120 for setting the IP address condition of the route entry. From the information (search key) stored in the destination IP address storage unit 180, the next hop IP address of the packet input to the router 200 Determine the output line number.

  The route table search unit 100 of the present invention logically divides the storage area of one CAM 120 into a plurality of (for example, two) tables (search groups), and divides the first search group (search table) 122-1. And a second search group (search table) 122-2, a plurality of search keys (for example, destination IP addresses) are searched in parallel for matching with a preset address condition. Here, “parallel” means that there are at least 0.5 clock periods in which two or more processes are simultaneously progressing, not only when the process start and end times coincide.

  The CAM 120 has a plurality of entries for storing a multi-bit matching condition. When a search key is input, the matching condition (address condition) in the entry is compared with the search key, and the address of the matching entry is the smallest. The address value is output at high speed.

  When the address condition to be matched is determined by the CAM 120, the next hop IP address and the output line number corresponding to the address condition matching the search key are read from the search result holding table 160, and the search process is terminated.

  The route table search unit 100 transmits the next hop IP address and the output line number corresponding to the search result as packet output line information to the packet receiving circuit 230, and the packet receiving circuit 230 sends a packet based on the packet output line information. The packet is transmitted to the packet relay processing unit 250.

  FIG. 3 is a block diagram of the CAM 120 of the present invention.

  The CAM 120 is connected to the search control unit 110 via a signal line (data line) 25 that transmits a search key such as an IP address. The search control unit 110 synchronizes with the operation clock of the memory clock signal line 27 and performs DDR (Doble (Data Rate), a plurality of destination IP addresses stored in the destination IP address storage unit 180 are transmitted to the CAM 120 as search keys. The CAM 120 searches the first search group 122-1 and the second search group 122-2 in parallel with the received plurality of search keys, and searches the search result by DDR in synchronization with the clock of the memory clock signal line 27. It transmits to the control part 110. The CAM 120 is supplied with a clock from the search control unit 110 via the memory clock signal line 27 and synchronizes each unit of the CAM 120.

Further, the CAM 120 is connected to the search control unit 110 via a signal line 28 that transmits information indicating the type of search. As will be described later, the search control unit 110 receives a search type (mode) via the signal line 28. ) (Hereinafter referred to as search type information) is transmitted to the CAM 120, and the CAM 120 switches the search mode according to the received search type information.

The storage area of the CAM 120 is logically divided into a plurality of search groups, and here, a case where the storage area is composed of two of the first search group 122-1 and the second search group 122-2 is shown.

  The CAM 120 includes a search key distribution unit 121 that receives a search key and search type information from the search control unit 110 and distributes a plurality of search keys to the first search group 122-1 and the second search group 122-2. Here, as will be described later, the search key received from the signal line 25 receives one search key at the rising (Rise) edge of the operation clock of the clock line 27, and is also one at the falling edge (Fall) of the clock. Data transfer is performed by the DDR that receives one search key.

  The search key distribution unit 121 includes a first search group 122-1 including a plurality of data storage blocks 123a-i (where i = 1 to n) and a plurality of data storage blocks 123b-i (where i = 1 to 1). The search key received by DDR is input to the second search group 122-2 having n) according to the search type information, and a parallel matching search is started. By performing this parallel search, it is possible to reduce the delay due to the search process compared to the case where the search process is sequentially performed on the search key received at high speed using DDR, and the processing result is high-speed. Can be output.

  The first search group 122-1 is connected to a hit address generation circuit 124-1, which generates an address condition that matches the search key. Similarly, the second search group 122-2 sets the address condition that matches the search key. Connected to the hit address generation circuit 124-2 to be generated, the search results performed in the first and second search groups 122-1, 2 are generated.

  The search results of the two hit address generation circuits 124-1 and 124-2 are sent to the search result output unit 125. The search result output unit 125 transmits two search results to the search control unit 110 via the signal line 26 by DDR.

  Here, each data storage block 123a-i, 123b-i of the first search group 122-1 and the second search group 122-2 is configured as shown in FIG. 4, and each data storage block is data A0i (i = 1 to n) and a mask A0i (i = 1 to n).

  Each search group 122-1, 2 is configured with a predetermined data width w and the number of data storage blocks, for example, with a data width w = 72 bits and a data storage block number = 64K. The number of entries in the CAM 120 in this case is obtained by multiplying the number of data storage blocks by the number of search groups. In the above case, the number of entries is 128K. On the other hand, in the conventional parallel search processing, when trying to perform the same search processing, two 72-bit search keys input by DDR are combined into a 144-bit search key according to the data width of 144-bit CAM. In some cases, the 144-bit search key is duplicated and input to two 144-bit CAMs, and the search is performed by masking 72 bits of the 144-bit data width that are not to be searched by each CAM. In this case, of the data width of each CAM, 72 bits that are masked as a result are useless data storage areas not involved in the search. Compared to this prior art, in the CAM described with reference to FIG. 4, it is not necessary to secure a useless data storage area, and the number of entries or the number of parallel stages can be increased with a CAM having the same capacity.

  Next, FIG. 5 is a block diagram showing details of the search key distribution unit 121. The search key distribution unit 121 includes a search type determination unit 1211 that receives the search type information from the search control unit 110 and instructs the first or second search group to execute a search corresponding to the search type information. .

  Further, the search type determination unit 1211 acquires the data of the rising edge of the clock signal from the data line 25 as the first search key, and sends the first search key to the first search key storage unit 1212 to be stored in the first search group. Command to transmit to 122-1. In addition, the search type determination unit 1211 acquires the data of the falling edge of the clock signal from the data line 25 as the second search key, and performs the second search for the second search key to the second search key storage unit 1213 to be stored. Command to send to group 122-2.

  In addition, the search type determination unit 1211 switches the search mode performed in parallel between the first search group 122-1 and the second search group 122-2 in accordance with the search type information received from the search control unit 110.

  This search mode includes, for example, a parallel mode in which a plurality of search keys are input from the data line 25 and the search is performed in parallel in the first search group 122-1 and the second search group 122-2; For example, a single mode in which one search key is input and a search is executed in either the first search group 122-1 or the second search group 122-2 is performed. By performing this mode switching, parallel processing is performed for high-speed searching when search processing is intensively required, and power consumption is reduced without using one search group when search processing is not necessary. can do.

  The search control unit 110 outputs a search key to the data line 25 and outputs search type information to the signal line 28.

  When the search type information received from the signal line 28 indicates the parallel mode, the search type determination unit 1211 sends the received search key to the first search group 122 in the first search key storage unit 1212 and the second search key storage unit 1213. -1 and the second search group 122-2 are instructed to output them respectively. Thereafter, the search type determination unit 1211 instructs the first and second search groups 122-1 and 122-2 to execute a search. In addition, the search type determination unit 1211 notifies the search result output unit 125 of the type of search currently being performed. The search result output unit 125 determines how to handle the output of the hit address generation circuit 124-1 or 124-2 according to the search type information from the search type determination unit 1211. As described above, when the search type determination unit 1211 notifies the search result output unit 125 of the search type, and the search key reception and parallel search processing by DDR is performed, the search result output unit 125 adjusts accordingly. The result can be output by DDR, and the search result can be output without delay.

  FIG. 6 is a block diagram showing details of the search result output unit 125. The search result output unit 125 receives the search type information from the search type determination unit 1211 of FIG. 5, and in response to a command from the search type determination unit 1251 that determines the search mode and the search type determination unit 1251, The first search result storage unit 1252 that outputs the first search result received from the hit address generation circuit 124-1, and the first search result received from the hit address generation circuit 124-2 in response to a command from the search type determination unit 1251. The second search result storage unit 1253 is configured to output 2 search results.

  If the search type information is the parallel mode, the search type determination unit 1251 instructs the two search result storage units 1252 and 1253 to transmit the search result to the search control unit 110 by DDR, and sets the single mode. In this case, an instruction is issued to output the search result from either the first search result storage unit 1252 or the second search result storage unit 1253.

  The first and second search result storage units 1252 and 1253 are connected to the signal line 26 on the output side. In the parallel mode, the first search result storage unit 1252 is synchronized with the clock of the memory clock signal line 27. Then, the first search result is sent to the signal line 26 at the rising edge, and the second search result accumulation unit 1253 sends the second search result to the signal line 26 at the falling edge in synchronization with the clock of the memory clock signal line 27. send.

  On the other hand, when the search type determination unit 1251 determines that the mode is the single mode, the output of one of the search result storage units that has acquired the output of the hit address generation circuit 124-1 or 124-2 is transmitted from the signal line 26.

  Next, an example of processing performed by the CAM 120 will be described with reference to FIG. The flowchart in FIG. 7 is executed every time a search key is input to the CAM 120.

  First, in S1, the search type determination unit 1211 of the search key distribution unit 121 receives the search operation type (search type information) from the signal line 28 from the search control unit 110, and starts the search process.

  In S2, the search type determination unit 1211 instructs the first search key storage unit 1212 and the second search key storage unit 1213 to store the received search key.

  In S3, the first search key storage unit 1212 that has received the search key storage instruction acquires and stores the first search key from the data line 25 at the timing of the rising edge of the memory operation clock signal. The first search key is output to one search group 122-1.

  In S4, the second search key storage unit 1213 that has received the search key storage instruction acquires and stores the second search key from the data line 25 at the falling edge timing of the memory operation clock signal, and stores the second search key. The second search key is output to the search group 122-2.

  In S5, the search type determination unit 1211 instructs the first search group 122-1 and the second search group 122-2 to execute a search. Further, the search key distribution unit 121 transmits the search type information to the search result output unit 125. By notifying the search result output unit of the search type in this way, when the search key reception by DDR and the parallel search processing are performed, the search result output unit may output the result by DDR accordingly. The search result can be output without delay.

  In S6, the first search group 122-1 and the second search group 122-2 perform the comparison of the input first search key and second search key in parallel, respectively. In this embodiment, the data A0-i and the data B0-i of the first search group 122-1 and the second search group 122-2 are the same, and the mask A0-i and the mask B0-i have the same contents. However, depending on the purpose of the search, the content may not necessarily be the same.

  The first search group 122-1 and the second search group 122-2 respectively compare the address condition set in each entry with each search key in parallel. The first search group 122-1 outputs the search result to the hit address generation circuit 124-1, and the second search group 122-2 outputs the search result to the hit address generation circuit 124-2. In the hit address generation circuits 124-1 and 124-2, address conditions that match the first and second search keys are generated and output to the search result output unit 125.

    In S7, the search result output unit 125 that has received the search type information from the search key distribution unit 121 instructs the first search result storage unit 1252 and the second search result storage unit 1253 to store the search results. As shown in FIG. 6, the search results corresponding to the first search key are stored in the first search result accumulation unit 1252 and the search results from the hit address generation circuits 124-1 and 124-1 and 124-1 and 12-2 correspond to the second search key. The search result to be stored is stored in the second search result accumulation unit 1253.

  In S8, the first search result storage unit 1252 that has received the search result storage instruction receives the search result corresponding to the first search key from the signal line 26 at the timing of the rising edge of the memory operation clock signal. Output to.

  Next, in S9, the second search result accumulation unit 1253 that has received the search result storage instruction sends the search result corresponding to the second search key from the signal line 26 at the timing of the falling edge of the memory operation clock signal. Output to the search control unit 110.

  As a result of the above processing, the two search keys input from the search control unit 110 are searched in parallel in the first search group 122-1 and the second search group 122-2, and the search result output unit 125 is searched. Is output to the search control unit 110 by DDR. By outputting in DDR in this way, the result of search key reception and parallel search processing by DDR can be output without delay.

  The operation of the CAM 120 will be described with reference to the timing chart of FIG.

  At the time point C1 when the clock rises, the search type determination unit 1211 of the search key distribution unit 121 acquires the first search key (key 1 in the figure), and the search type determination is made at C2 when the next clock falls. The unit 1211 obtains the second search key (key 2 in the figure).

  The first and second search keys input to the first search key storage unit 1212 and the second search key storage unit 1213 are the first search group 122-1 and the second search group 122- at the time of C3 and C4. 2 respectively.

  In the first search group 122-1, the first search key is searched in two clocks C3 to C7, and in the second search group 122-2, the second search key is searched in two clocks C4 to C8. Accordingly, the first search group 122-1 and the second search group 122-2 of the CAM 120 execute search processing in parallel during the period from C4 to C7. Note that the search processing of the first search group 122-1 and the second search group 122-2 is executed in two steps for each clock. When the search processing load is low, the search processing can be completed in one clock.

  In C7 to C8, an address condition corresponding to the search result of the first search key is generated and transferred from the hit address generation circuit 124-1 to the search result output unit 125. Similarly, in C8 to C9, an address condition corresponding to the search result of the second search key is generated and transferred from the hit address generation circuit 124-2 to the search result output unit 125.

  The search result of the first search key is output to the signal line 26 at the time when the clock of the C9 rises, and the search result of the second search key is output to the signal line 26 at the time of the fall of the clock of C10. The

  As described above, in the CAM 120 of the present invention, one storage area is divided into two search groups, and the contents of each entry of each search group are set to the same data and mask, so that two different search keys are parallelized. Can be processed. As a result, the apparent performance of the CAM 120 can be improved.

  That is, in the example of FIG. 8, 4.5 clocks are required from input to output of one search key, and the time required for processing two search keys is 5 clocks. In contrast to the fact that 9 clocks are required to process two search keys that require 4.5 clocks, the apparent performance (search processing capability) is improved by about 80%. As a result, the present invention can provide a high-speed and low-cost CAM.

  Next, since a large amount of power is required for the search operation of the CAM, the power consumption of the CAM increases drastically when the search is simultaneously started in a plurality of tables (banks) as in the above-described conventional example. For this reason, noise is generated in the CAM. That is, in the conventional example, since the search processing is started simultaneously with a plurality of tables, the power consumption of the CAM increases rapidly, and noise is induced because the power consumption peak is reached at once.

  On the other hand, in the CAM 120 of the present invention, as shown in FIG. 8, the power consumption of the first search group 122-1 increases at the time C3 when the search process for the first search key is started. Thereafter, at time C4 when the search process for the second search key is started, the power consumption of the second search group 122-2 increases. Therefore, the increase in power consumption of the CAM 120 accompanying the start of the search process is performed in two stages.

  Therefore, in the present invention, by sequentially operating a plurality of search tables of the CAM 120, it is possible to prevent the power consumption from reaching a peak at once, and to increase the power consumption step by step, thereby suppressing the occurrence of noise. It becomes.

  As described above, according to the present invention, since the plurality of search tables are sequentially operated and then processed in parallel, the speed of the CAM 120 can be increased, and the data storage block can be used without waste. A large-capacity CAM 120 can be provided. Furthermore, since a plurality of search processes are started sequentially, the power consumption of the CAM 120 can be prevented from suddenly reaching a peak, noise can be prevented, and a stable search process can be realized.

<Modification 1>
FIG. 9 shows a first modification example in which the mask is deleted from each of the data storage blocks 123a-i and 123b-i constituting the two search groups set in the CAM 120 to make only the data. The configuration is the same as in the above embodiment.

  If the search key does not need to be masked, only the data (address condition) needs to be stored in each entry as shown in FIG. 12, and a storage area for storing the mask becomes unnecessary. The number of entries can be increased.

  In the above-described embodiment, an example in which search keys are input to the CAM 120 by DDR one by one has been described. However, a plurality of search keys may be combined into one word so that the CAM 120 receives the word by word. In this case, the CAM 120 may extract a plurality of search keys from one word and sequentially input the plurality of search keys to each search group.

  As described above, according to the present invention, the search resource of the CAM and the input band of the search key between the CAM and the search control device can be effectively used, and the routing table search can be performed at high speed. It can be applied to a packet transfer apparatus such as.

The block diagram of the router which shows one Embodiment of this invention. The block diagram which shows the structure of the routing table search part of a router. The block diagram which shows the structure of CAM of a route table search part. Explanatory drawing which shows an example of the search group of CAM. The block diagram which shows the detail of the search key distribution part of CAM. The block diagram which shows the detail of the search result output part of CAM. The flowchart which shows an example of the procedure of the control performed by CAM. The timing chart which shows an example of the control performed by CAM. Explanatory drawing which shows a 1st modification and shows an example of the search group of CAM.

Explanation of symbols

100 Route table search unit 120 CAM
121 Search Key Distribution Unit 122-1 First Search Group 122-2 Second Search Group 124-1, Hit Address Generation Circuit 125 Search Result Output Unit

Claims (8)

A search key receiving unit for receiving a plurality of search keys based on an operation clock;
A plurality of search tables in which address conditions are set in advance;
A search key distribution unit that associates the plurality of search keys with the plurality of search tables;
An associative memory comprising: a search control unit that performs a search in parallel with the plurality of tables associated with the plurality of search keys;
The associative memory, wherein the search control unit sequentially starts searching for search keys associated with the plurality of tables.   2. The content addressable memory according to claim 1, wherein the search control unit sequentially starts searching for search keys associated with the plurality of search tables at a rising edge and a falling edge of the operation clock.   2. The content addressable memory according to claim 1, wherein the search key receiving unit sequentially receives the plurality of search keys at a rising edge and a falling edge of the operation clock. The search key distribution unit includes a search type setting unit for setting a search type for changing a search table associated with the search key,
The search key receiving unit includes a search type signal receiving unit that receives a signal indicating the search type,
The associative memory according to claim 1, wherein the search type setting unit changes a search table that associates the search key based on a signal received by the search type signal receiving unit. An input line for entering packets;
Multiple output lines that output packets;
The destination address that matches a destination address of a packet input to the input line, comprising a plurality of destination address conditions that specify a matching condition for each bit of the destination address and a route entry in which forwarding information is set for each destination address condition A route table search unit that searches for a condition, and sets a transfer destination of a packet that matches the destination address condition in transfer information corresponding to the destination address condition;
A packet transfer unit for transferring the packet to any one of the plurality of output lines corresponding to the transfer information;
In a packet transfer device comprising:
The route table search unit
An associative memory having a plurality of entries for setting the destination address condition;
A search processing unit for comparing a destination address of the input packet with an entry in the associative memory and searching for a matching destination address condition;
A transfer information setting unit that sets transfer information of the packet based on a destination address condition uniquely corresponding to the destination address of the packet searched by the search processing unit,
The associative memory is
A search key receiving unit that receives a plurality of search keys from the input line based on an operation clock;
A plurality of search tables in which the destination address condition is set;
A search key distribution unit that associates the plurality of search keys with the plurality of search tables;
A search control unit that performs a search in parallel with the plurality of tables associated with the plurality of search keys,
The packet transfer apparatus, wherein the search control unit sequentially starts searching for search keys associated with the plurality of tables.   6. The packet transfer apparatus according to claim 5, wherein the search control unit sequentially starts searching for search keys associated with the plurality of search tables at a rising edge and a falling edge of the operation clock. .   6. The packet transfer apparatus according to claim 5, wherein the search key receiving unit sequentially receives the plurality of search keys at a rising edge and a falling edge of the operation clock. The search key distribution unit includes a search type setting unit for setting a search type for changing a search table associated with the search key,
The search key receiving unit includes a search type signal receiving unit that receives a signal indicating the search type,
6. The packet transfer apparatus according to claim 5, wherein the search type setting unit changes a search table for associating the search key based on a signal received by the search type signal receiving unit.

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