JP2006135058A - Method for forming copper wiring layer and method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for forming a copper wiring layer by which copper wiring having no thinning and an optional section area, and to provide a method for manufacturing a semiconductor device. <P>SOLUTION: A base insulating film 2, a base barrier layer 3, and a copper seed layer 4 are formed in sequence on a substrate 1, and then a wiring groove 6 pattern made of a photo resist layer 5 is formed on the copper seed layer 4. A copper wiring layer 7 is formed on the exposed copper seed layer 4 on the bottom of the wiring groove 6 (Diagram (a)), and a protection layer 8 is formed on the layer 7. Then, the layer 8 is used as a mask, and the photo resist layer 5, the copper seed layer 4 and the base barrier layer 3 are etched in sequence to form a pattern made of the copper wiring layer 7 shown in Diagram (e). An interlayer insulating layer is formed on the surface to prevent the dispersion of copper from the layer 7. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for forming a copper wiring layer capable of low resistance and fine wiring and a method for manufacturing a semiconductor device, and particularly suitable for manufacturing a display device represented by a liquid crystal display device, a semiconductor device such as ULSI, and the like. It is a simple method.

  In general, wiring and electrodes using aluminum (Al) and its alloys are mainly used as wiring materials in semiconductor devices represented by LSI and ULSI. However, due to recent demands for miniaturization and thinning due to improved integration, and demands for improved operation speed, etc., the resistance is lower than that of Al wiring and the characteristics such as electromigration and stress migration are high. Adoption of copper (Cu) as a material for next-generation wiring and electrodes has been studied.

  Furthermore, in the field of display devices represented by liquid crystal display devices, etc., there is an increase in wiring length due to an increase in display area, and due to demands for monolithic mounting with various additional functions such as a driver circuit for driving and a memory in a pixel. As with the semiconductor field, there is an increasing demand for low resistance wiring.

For fine copper wiring processing, masking technology by PEP (Photo Engraving Process, so-called photolithography), RIE (Reactive Ion Etching) method, etc., as well as Al wiring formation technology Even if this etching technique is simply combined, it has been difficult to realize. In other words, the vapor pressure of the copper halide is very low compared to the halide of Al and is difficult to evaporate. Therefore, when etching copper using an etching technique such as RIE, the substrate temperature is set to 200 to 300 degrees Celsius. There are many problems for practical application. Further, it is necessary to use a mask made of SiO ₂ or SiNx instead of a normal photoresist mask.

Therefore, as a method for forming a copper wiring layer, for example, a method for forming a copper wiring layer using a damascene method disclosed in Patent Document 1 or Patent Document 2 has been proposed. This damascene method is a method of forming a copper wiring layer by the following process. First, a silicon oxide layer is formed as an insulating layer on a substrate, and a wiring groove having a desired wiring pattern is formed in advance on the insulating layer. Next, in order to prevent copper from diffusing into the silicon oxide layer, a diffusion preventing layer such as TaN, Ta, or TiN is formed as a base layer of the copper wiring layer.

Various methods such as PVD (Physical Vapor Depositon) method such as sputtering method, plating method, or CVD (Chemical Vapor Depositon) method using an organic metal material so as to embed a wiring groove on this diffusion prevention layer Using this technique, a copper thin layer serving as a copper wiring layer is embedded in the groove and formed over the entire surface of the insulating layer. Thereafter, the copper thin layer is polished using a polishing method such as CMP (Chemical Mechanical Polishing) or etch back until the lower insulating layer is exposed from the substrate surface side (opening end surface of the groove portion). A wiring pattern made of copper that is removed and embedded in the trench is formed. Further, the damascene method is to form an insulating layer or metal layer having a diffusion preventing function on a copper wiring.

JP 2001-189295 A Japanese Patent Laid-Open No. 11-135504

  However, the damascene method including the technique disclosed in Patent Document 1 has the following problems. The damascene method includes a film forming process for forming a metal diffusion preventing layer, a metal seed layer, a metal wiring layer, and a polishing stopper film, a photolithography process, in addition to a groove processing process for forming a groove for embedding at least a wiring. Further, an etching process and a polishing process are necessary, and the manufacturing process becomes complicated, which increases the manufacturing cost.

  In order to reduce the wiring resistance, it is necessary to increase the cross-sectional area of the wiring. However, due to the limitation of integration, if a groove or via hole with a high aspect ratio (that is, a narrow width and diameter) is used, Copper embedding is reduced. Further, a CMP process or the like of removing unnecessary portions after forming a thin copper layer on the entire surface of the substrate takes a long processing time and deteriorates the throughput.

  Furthermore, a large-sized CMP apparatus corresponding to a large-diameter semiconductor wafer size such as 12 inches in diameter has been developed. A manufacturing apparatus for a display device using a square glass substrate having a larger area than the semiconductor wafer is as follows. Not put into practical use. Further, in the case of a display device, for example, a large liquid crystal display device, the copper thin layer portion used as the wiring is compared with the area of the glass substrate even if the entire surface polishing by CMP or the removal by the etching method is possible. And so small that most of the deposited thin copper layer is removed and discarded. As a result, the utilization efficiency of expensive copper as a material becomes very poor, and the product price increases due to the high cost.

  The inventor has developed a resource-saving process for improving the utilization efficiency of copper materials, a process for forming a fine copper wiring layer, and a process for forming a copper plating layer even in the case of a large substrate (display screen). . For example, the formation of a copper plating layer on a large substrate (display screen) is being considered to apply a selective electroless copper plating process using a resist. In the process of forming an electroless copper plating film, a copper seed layer is formed before the electroless copper plating film is formed, so that a low ratio of the wiring thickness of about 400 nm used in a display device such as a liquid crystal is low. A copper wiring thin film having a resistance value can be formed, and a method of etching an unnecessary portion of the copper seed layer after removing the resist has been developed.

However, as a method for etching the copper seed layer, for example, an etching method for a large substrate (display screen) is preferable because etching using a copper etching solution can be performed without limitation on the size of the substrate. However, etching with a copper etchant has a narrow wiring width, and in the case of wiring with a narrow wiring interval, an etching residue tends to be generated at the bottom of the wiring or at the corner of the wiring, and etching with a desired shape cannot be performed. The inability to form an etching groove of a desired shape has a problem that a portion having a reduced cross-sectional area is formed in the formed wiring.

That is, the formation of a thin wire using an etching method with a copper etchant not only does not take a current capacity, but also may cause a disconnection, which is one factor of yield deterioration. Further, the step of etching the copper seed layer other than the region in contact with the copper wiring layer has a problem that the thickness of the copper wiring is reduced and the surface is roughened because the surface of the copper wiring thin film is simultaneously etched.

  The present invention has been made in view of the above points, and provides a method of forming a copper wiring layer and a method of manufacturing a semiconductor device that can form a copper wiring having a desired cross-sectional area without any thinning.

In order to solve the above problems, a method for forming a copper wiring layer and a method for manufacturing a semiconductor device of the present invention include:
It was solved as follows.

The method for forming a copper wiring layer according to the present invention includes a step of forming a copper seed layer on a substrate, a step of forming a copper wiring layer having a predetermined pattern on the metal seed layer, and a contact with the copper wiring layer. A step of forming a protective layer on at least the copper wiring layer when removing the copper seed layer other than the region to be formed, and the copper seed layer other than the region in contact with the copper wiring layer using the protective layer as a mask And a dry etching process.

  The copper wiring layer forming method is characterized by a step of forming a base barrier layer before forming the copper seed layer, and dry etching the copper seed layer other than a region in contact with the copper wiring layer And a step of dry etching the underlying barrier layer.

  The copper wiring layer forming method is characterized in that, after etching the copper seed layer other than a region in contact with the copper wiring layer, capping that covers the copper seed layer and the exposed surface of the copper wiring layer. Forming a metal layer.

  A feature of the method for forming a copper wiring layer includes a step of etching the protective layer after dry etching the copper seed layer or the underlying barrier layer other than the region in contact with the copper wiring layer. It is.

  A feature of the method of forming a copper wiring layer is that a copper wiring layer having a predetermined pattern is formed by forming a resist layer on the copper seed layer thicker than the copper wiring layer; and Forming a wiring groove in the shape of the copper wiring layer; forming a copper layer in the wiring groove shallower than a depth of the wiring groove; and removing the resist layer to form a copper wiring layer; It consists of

A feature of the method of forming a copper wiring layer is that the copper seed layer is mainly oriented in (111). A feature of the method of forming a copper wiring layer is that the average crystal grain size of the copper seed layer is at least 0.25 μm or more.

  In the method for manufacturing a semiconductor device of the present invention, a source region, a drain region, and a channel region are formed on a semiconductor substrate, a gate electrode is formed on the channel region via a gate insulating film, and the source electrode, the drain electrode, and the gate are formed. In forming the electrodes and their wiring layers, a step of forming a copper seed layer containing copper as a main component, a step of forming a copper wiring layer of a predetermined pattern on the copper seed layer, and at least the copper Forming a protective layer on the wiring layer; and dry etching the copper seed layer and the underlying barrier layer other than the region bonded to the copper wiring layer using the protective layer as a mask. It is characterized by.

  According to the method of the present invention, it is possible to form a copper wiring having a desired cross-sectional area without any thinning.

  Hereinafter, a first embodiment of a method for forming a copper wiring layer of the present invention will be described in detail with reference to FIG. 1 and FIG. FIG. 1 is a cross-sectional view for explaining a process up to a process of forming a wiring trench in order of processes. FIG. 2 is a cross-sectional view for explaining the process of forming a wiring pattern in the wiring groove formed by the process of FIG. In FIG. 1 and FIG. 2, the same reference numerals are given to the same parts, and duplicate explanations are omitted. In this specification, the copper wiring layer includes, in an integrated circuit, a display device, and the like, circuit elements such as an electrical wiring for electrically connecting transistors and electrodes and terminals of transistors.

  The substrate may be a conductor, an insulator, or a semiconductor. On the substrate 1 such as a glass substrate, as shown in FIG. 1A, a base insulating layer 2 such as a SiN (silicon nitride) film is provided with a film thickness of 300 nm, for example, in order to prevent the penetration of impurities from the substrate 1. This SiN film can be formed by, for example, a plasma CVD method. A base barrier layer 3 is formed on the base insulating layer 2 as shown in FIG. The underlying barrier layer 3 is a barrier metal made of at least one layer such as Ta, TaN, TiN, TaSiN or the like that suppresses copper diffusion and improves adhesion with the underlying insulating layer 2.

These barrier metals are formed on the base insulating layer 2 by a sputtering method to a thickness of about 30 nm, for example. Further, a metal seed layer containing copper as a main component, for example, a copper seed layer 4 is formed on the base barrier layer 3 as shown in FIG. The copper seed layer 4 is formed by sputtering, for example. The copper seed layer 4 is formed to a thickness of, for example, 30 nm to 300 nm. The copper seed layer 4 is preferably a layer mainly composed of copper having a crystal plane whose crystal orientation is mainly oriented to (111) and an average crystal grain size of 0.25 μm or more.

  Next, a photoresist layer 5 is formed on the copper seed layer 4 as shown in FIG. The film formation method of the photoresist layer 5 is, for example, a spin coating method, and the film thickness of the photoresist layer 5 is, for example, 1.2 μm. The film thickness of the photoresist layer 5 is preferably thicker than the thickness of the copper wiring layer formed in a later step.

The substrate 1 on which the photoresist layer 5 has been applied and cured is carried into an exposure apparatus, projected onto the photoresist layer 4 using an exposure mask having a predetermined electrode pattern or a desired wiring formation pattern, and exposed. The After the exposure, next, a development process is performed on the photoresist layer 5 to form a pattern of the wiring groove 6 in the wiring pattern region in the photoresist layer 5 as shown in FIG. The surface of the copper seed layer 4 is exposed on the bottom surface of the wiring groove 6.
For example, the groove width of the wiring groove 6 is 1 μm.

Next, on the exposed copper seed layer 4 of the wiring trench 6, a metal wiring layer containing copper as a main component, for example, a copper wiring layer 7 is formed as shown in FIG. As a method for forming the copper wiring layer 7, it is desirable to use an electroless plating method so that the substrate 1 can be uniformly formed even on a rectangular substrate having a side size exceeding 1 meter. The thickness of the copper wiring layer 7 is, for example, 400 nm which is shallower than the depth of the wiring groove 6. In the electroless plating process of copper, the surface of the photoresist layer 4 where copper is exposed is not plated, but is formed only on the surface of the exposed copper seed layer 4 as shown in FIG. The

At this time, the copper (plating) wiring layer 7 formed on the copper seed layer 4 is epitaxially grown. For this reason, when the crystal orientation of the copper seed layer 4 is mainly (111) and the average crystal grain size of the copper seed layer 4 is larger, the average crystal grain size of the copper (plating) wiring layer 7 is larger and lower. This is desirable because a copper (plating) wiring layer 7 having a specific resistance can be obtained. As a pretreatment for forming the copper wiring layer 7 by the electroless plating method, it is desirable to add a cleaning process for removing oxides on the surface of the copper seed layer 4.

The film formation method of the copper wiring layer 7 is, for example, a plating method described below. When the substrate to be plated is large, electroless plating is effective. As an electroless plating bath for forming the copper wiring layer 7 containing very thin copper as a main component, it is desirable to use, for example, a neutral electroless plating bath using a cobalt salt as a reducing agent. The composition of the neutral electroless plating bath is, for example, cobalt sulfate or cobalt nitrate as a reducing agent, copper sulfate or copper nitrate as a copper salt, ethylenediamine as a complexing agent, ascorbic acid or complexing agent as a reducing agent, and the like. For example, 2,2′-bipyridyl may be used as an agent, and hydrochloric acid may be used as a reaction initiator. Since the neutral electroless plating bath using a cobalt salt as a reducing agent has a pH range of about 6 to 7, in addition to being able to use a normal photoresist, it does not contain harmful substances or alkali metals. There is an advantage that it can be applied to the manufacturing process of the thin film transistor.

Formation of the copper wiring layer 7 containing copper as a main component by electroless plating enables a thin film to be formed on a glass substrate for a liquid crystal display device having a size of 1 meter or more as the substrate 1. It is important that the average crystal grain size of the copper wiring layer 7 having copper as a main component for obtaining a specific resistance of 2.5 μΩcm or less is 0.25 μm or more even in a sub-μm order thin film. Furthermore, electroless plating of the copper wiring layer 7 only in the wiring groove 6 is a manufacturing method having a resource saving effect because copper is not formed on an unnecessary portion.

  Subsequently, only on the copper wiring layer 7, the surface of the copper wiring layer 7 is etched, roughened, or copper is diffused during the next etching process as shown in FIG. A protective layer 8 is deposited to prevent it. The protective layer 8 is, for example, a protective layer 8 mainly composed of cobalt, and a cobalt boron (CoB) layer is formed on the copper wiring layer 7 to a thickness of, for example, 50 nm by an electroless plating method. The protective layer 8 is desirably formed selectively on the surface of the copper wiring layer 7 without using a palladium (Pd) catalyst by using a plating bath containing dimethylamine borane as a reducing agent. As the protective layer 8, nickel boron (NiB) mainly containing nickel, NiWB, NiP, NiWP, or the like may be used in addition to CoB, CoWB, CoP, and CoWP. The laminated film thickness of the copper wiring layer 7 and the protective layer 8 after forming the protective layer 8 is thinner than the depth of the wiring groove 6. Since Pd diffuses into Cu in the subsequent heat treatment step and increases the specific resistance, it is desirable to selectively form it on the surface of the copper wiring layer 7 without using a Pd catalyst, but the protective layer 8 is formed in the subsequent step. Needless to say, the Pd catalyst may be selectively formed on the surface of the copper wiring layer 7 when the etching is removed. In that case, since Pd may remain as a residue when the protective layer 8 is removed by etching, it is desirable to use a Pd removing solution.

  As another film forming example of the protective layer 8, after removing the photoresist layer 5 by forming a metal layer such as Ti, Ta, Co, Ni, Cr or an insulating layer on the entire surface by sputtering or the like and using the lift-off method. It may be formed only on the surface of the copper wiring layer 7.

  Next, the photoresist layer 5 is removed as shown in FIG. After removing the photoresist layer 5, the exposed copper seed layer 4 that is not in contact with the copper wiring layer 7 is removed by etching as shown in FIG. The removal process of the copper seed layer 4 is removed by a dry etching method using the protective layer 8 as a mask. The dry etching method for the copper seed layer 4 is, for example, a sputter etching method using magnetic field inductively coupled plasma using argon gas.

During this dry etching process, the upper surface of the copper wiring layer 7 is protected by the protective layer 8, so that the surface is not roughened. As the thickness of the copper wiring layer 7 increases, the copper seed layer 43 that has been sputter-etched and removed from the side wall of the copper wiring layer 7 tends to be re-deposited. At this time, it is desirable to use a protective layer 8 having a sufficiently slow sputter etching rate than the copper seed layer 4. The dry etching method for the copper seed layer 4 includes, for example, a process of generating copper oxide (Cu2O) by oxygen plasma using a 1: 1 mixed gas of oxygen and hexafluoroacetylacetone, and the generated copper oxide. It is also possible to use a method in combination with a process of reducing and removing the compound with hexafluoroacetylacetone.

Since the copper seed layer 4 is formed to be sufficiently thinner than the copper wiring layer 7, it is etched faster and in a shorter time than the exposed side wall surface of the copper wiring layer 7 is etched. In order to increase the dry etching rate of the copper seed layer 4, it is desirable to raise the temperature of the substrate 1, but it is desirable to carry out at a temperature as low as possible in order to suppress contamination due to copper diffusion. In the method of forming the copper wiring layer 7 of this embodiment, the copper wiring layer 7 is not etched, but only the thin copper seed layer 4 is etched, so that it can be performed in a short time without raising the temperature of the substrate 1. .

Next, as shown in FIG. 2E, the exposed portion of the underlying barrier layer 3 is removed by dry etching using the protective layer 8 as a mask to form the copper wiring layer 7. The dry etching of the underlying barrier layer 3 may be performed using, for example, CF4 gas and O2 gas as etching gases when a barrier metal Ta-based one is used as the underlying barrier layer 3.

The copper wiring layer 7 containing copper as a main component has easy diffusibility. Therefore, in order to prevent the diffusion of copper, an interlayer such as a material having a copper diffusion barrier property such as SiN, SiC, or benzocyclobutene (BCB) is provided on the copper wiring layer 7 as shown in FIG. It is desirable to form the insulating layer 9 so as to cover the surface of the copper wiring layer 7.

  The method for forming a copper wiring layer of this embodiment can selectively form fine metal wiring mainly composed of copper. The copper wiring layer 7 can obtain a specific resistance of 2.5 μΩcm or less even in a sub-μm order thin film having a wiring film thickness of about 200 to 1000 nm. Furthermore, the low specific resistance copper wiring layer 7 can be formed even on a large substrate 1 of 1 meter or more.

The film thickness of the copper wiring layer 7 mainly composed of copper is as thin as 200 to 1000 nm. Even such a copper wiring layer 7 composed mainly of ultra-thin copper enables a low resistance wiring of 2.5 μΩcm or less.

  That is, in normal electrolytic copper plating or electroless copper plating layer formation, since the wiring thickness is as thick as about 1 to 30 μm, the plating film thickness increases and the crystal grain size increases. On the other hand, the wiring such as the liquid crystal display device requires a thin film on the order of sub-μm, so that the copper wiring layer 7 cannot be made thick. The specific resistance of the copper (plating) wiring layer 7 can be reduced by increasing the crystal grain size of the copper (plating) wiring layer 7.

The present inventor has found that the crystallinity of the copper seed layer 4 is particularly affected in the formation of a wiring having a thin copper (plating) wiring layer 7 as in a liquid crystal display device. That is, in order to obtain a low specific resistance of 2.5 μΩcm or less with a thin film of sub-μm order, the copper (plating) wiring is made by setting the crystal grain size (average crystal grain size) of the copper seed layer 4 to 0.25 μm or more. It has been found that the crystal grain size of the layer 7 can be increased. The ability to increase the crystal grain size of the copper (plating) wiring layer 7 makes it possible to obtain a low resistance copper (plating) wiring layer 7.

In the formation of the copper wiring layer 7 using the above-described neutral electroless plating bath for reducing the cobalt salt, the crystal orientation of the copper wiring layer 7 depends on the crystal orientation of the copper seed layer 4 and the copper wiring layer 7 When the film thickness is as thin as about 300 nm, the average crystal grain size of the copper wiring layer 7 is substantially equal to that of the copper seed layer 4. That is, by selecting the crystal grain size of the copper seed layer 4 to be a crystal grain size for obtaining a low specific resistance of 2.5 μΩcm or less, wiring with a low specific resistance is made possible even with the extremely thin copper wiring layer 7.

Formation of the copper wiring layer 7 by electroless copper plating with a low specific resistance of 2.5 μΩcm or less is to form the copper wiring layer 7 having a large crystal grain size. In a manufacturing method of a display device such as a liquid crystal display device, the crystal grain size is increased by increasing the wiring thickness due to the unevenness before and after the copper wiring, the coverage of the insulating layer after the wiring is formed, and the requirement for reducing the surface unevenness of the substrate 1. You can't make it bigger.

The solution to this problem is to obtain a copper wiring layer 7 by low resistance copper plating by increasing the crystal grain size of the copper seed layer 4. That is, in order to obtain a low specific resistance of 2.5 μΩcm or less with a thin film on the order of sub-μm, the crystal grain size of the metal (copper) seed layer 4 is set to an average crystal grain size of about 0.25 μm or more. Plating) The crystal grain size of the wiring layer 7 can be increased. The fact that the crystal grain size of the copper (plating) wiring layer 7 can be increased is that the low resistance copper (plating) wiring layer 7 can be obtained. Thus, the crystallinity of the copper seed layer 4 is important in order to obtain a copper (plating) wiring layer 7 having a low specific resistance of 2.5 μΩcm or less with a thin film on the order of sub μm.

Here, the average crystal grain size is a value obtained by excluding a twin boundary of 60 degrees with respect to the copper seed layer 4 having a crystal orientation of (111) using an electron backscattering (EBSP) method. The average crystal grain size is an average value of diameters obtained by spherical approximation from the crystal grain area.

In the above embodiment, the means for increasing the average crystal grain size of the copper seed layer 4 depends on the film quality of the underlying barrier layer 3, but is heated (annealed) at a temperature, eg, 450 degrees Celsius for a time, eg, 10 minutes. It is also possible to use a method of enlarging the average crystal grain size of the copper seed layer 4.

In the above embodiment, the average crystal grain size of the copper seed layer 4 and the copper wiring layer 7 is as follows. When the average crystal grain size of the copper seed layer 4 (A) is 0.166 μm, the average crystal grain size of the copper (plating) wiring layer 7 formed by electroless plating on the copper seed layer 4 (A) is 0. 160 μm.

The copper seed layers 4 (B) and (C) are copper seed layers 4 (B) and (C) formed on a base metal layer made of Ta. The copper seed layers 4 (B) and (C) The average crystal grain size is 0.284 μm and 0.462 μm. The average crystal grain sizes of the copper wiring layers 7 formed on the copper seed layers 4 (B) and (C) by electroless plating are 0.298 μm and 0.456 μm, respectively.

The copper seed layer 4 (D) is formed on the base metal layer made of TaSiN as the base barrier layer 3, and the average crystal grain size of the copper seed layer 4 (D) is 0.425 μm. The average crystal grain size of the copper (plating) wiring layer 7 formed by electroless plating on the copper seed layer 4 (D) is 0.394 μm. Thus, it can be seen that the average crystal grain sizes of the copper seed layer 4 and the copper wiring layer 7 are substantially equal.

The average crystal grain size of the underlying copper seed layer 4 and the average grain size of the copper wiring layer 7 are substantially equal, and the specific resistance of the copper wiring layer 7 is larger when the average crystal grain size of the copper seed layer 4 is larger. It turns out that it is low. That is, it can be seen that the average crystal grain size of the copper seed layer 4 may be increased in order to form the copper wiring layer 7 having a low specific resistance. In other words, in order to obtain the copper wiring layer 7 having a desired specific resistance, it can be obtained by forming the copper seed layer 4 having a size corresponding to the average crystal grain size.

  Next, referring to FIG. 4, an embodiment in which a layer having a copper diffusion preventing property is formed on the surface of the copper wiring layer 7 in order to enhance the copper diffusion preventing property from the copper wiring layer 7 will be described. explain. The same parts as those in FIGS. 1 to 3 are denoted by the same reference numerals, and detailed description thereof will be omitted because it is duplicated. Since the above embodiment and the steps up to FIG. 3A are the same, the steps after FIG. 3A are shown in FIG.

FIG. 4A is a cross-sectional view showing a state in which the copper wiring layer 7 is selectively formed in FIG. After removing the copper seed layer 4 and the underlying barrier layer 3 using the protective film 8 as a mask, the first copper diffusion prevention layer is formed. This copper diffusion preventing layer prevents copper from diffusing from the copper wiring layer 7 formed on the surface (including side surfaces) of the protective film 8, the copper wiring layer 7, the copper seed layer 4, and the underlying barrier layer 3. A layer for suppressing, for example, a capping metal layer 10 (FIG. 4B). As this capping metal layer 10, it is desirable to form a capping metal layer 10 (for example, CoB, NiB, etc.) mainly composed of cobalt or nickel by an electroless plating method. The first copper diffusion prevention layer desirably covers at least the exposed surface of the copper wiring layer 7.

  On the capping metal layer 10, a barrier layer, for example, an interlayer insulating layer 9 such as SiN, SiC, BCB or the like is further provided in FIG. Form as shown in c).

In the above embodiment, a barrier layer mainly composed of cobalt or nickel may be formed on the upper surface portion of the copper wiring layer 7 as the protective layer 8 in the dry etching process.

When the protective layer 8 is formed of titanium by the lift-off method, the capping metal layer 10 is not formed on the surface of the protective film by the electroless plating method as described above. Therefore, the protective layer 8 is etched in the step of FIG. After the removal, it is desirable to form the capping metal layer 10 by electroless plating as shown in FIG. Thereafter, a double structure copper diffusion preventing layer can be formed by forming an interlayer insulating film 9 on the surface.

  Next, an embodiment in which the adhesiveness between the base insulating layer 2 and the copper seed layer 4 is increased without using the base barrier layer 3 will be described with reference to FIGS. 5 and 6. The same parts as those in FIGS. 1 to 4 are denoted by the same reference numerals, and detailed description thereof will be omitted because it is duplicated.

  As shown in FIG. 5A, a base insulating film layer 2 is provided on a substrate, for example, a glass substrate 1, and a copper seed layer 4 is formed on the base insulating film layer 2 as shown in FIG. 5B. A copper alloy seed layer 12 containing copper, but containing at least one metal of Mg, Ta, Ti, Ta, Mo, Mn, Al, W, and Zr is provided. This copper alloy seed layer 12 is formed by forming an oxide layer of an additive metal having a barrier property at least at the interface with the base insulating layer 2, for example, MgO, TiO2, Ta2O5, etc. Adhesion with the layer 2 is improved.

  On the copper alloy seed layer 12 thus formed, the copper wiring layer 7 can be formed using a process similar to that of the embodiment of FIGS. That is, a photoresist layer 5 is provided on the copper alloy seed layer 12, and the photoresist layer 5 has a wiring groove 6 formed in a wiring pattern as shown in FIG.

  Next, after the surface oxide layer is removed on the exposed copper alloy seed layer 12 in the wiring groove 6, a copper wiring layer 7 is formed as shown in FIG. A protective layer 8 is formed on the copper wiring layer 7 as shown in FIG. Using this protective layer 8 as a mask, the photoresist layer 5 is etched as shown in FIG. Further, the copper alloy seed layer 12 exposed using the protective layer 8 as a mask is etched as shown in FIG. 6D to form the copper wiring layer 7. Further, as shown in FIG. 6E, an interlayer insulating layer 9 made of a material having a barrier property against the diffusion of copper from the copper wiring layer 7 is formed on and between the copper wiring layers 7. In this way, the copper wiring layer 7 is formed.

  The means for suppressing the diffusion of copper from the copper wiring layer 7 is not limited to a single layer formed by the interlayer insulating layer 9 but may be a double layer. An embodiment of a double layer is as shown in FIG. That is, after the copper wiring layer 7 is formed as shown in FIG. 6D, the exposed surface including the side surfaces of the protective layer 8, the copper wiring layer 7, and the copper alloy seed layer 12 is illustrated. As shown in FIG. 7B, a first layer is formed by coating a material layer that suppresses copper diffusion. The material layer for suppressing copper diffusion is, for example, the capping metal layer 10. The capping metal layer 10 is made of, for example, CoB, CoWB, NiB, NiWB or the like mainly containing cobalt or nickel by an electroless plating method. On the first capping metal layer 10 thus formed, a second interlayer insulating layer 9 is formed as shown in FIG. 7C to form a double structure copper diffusion prevention layer. .

  The copper diffusion prevention layer having a double structure is formed by removing the protective layer 8 formed on the copper wiring layer 7 in the step of FIG. A first capping metal layer 10 is formed on the side surface of the copper alloy seed layer 12. Next, as shown in FIG. 7D, a second interlayer insulating layer 9 such as SiN, SiC, or BCB may be formed on the first capping metal layer 10.

  The copper wiring layer 7 formed in this way is not only a semiconductor integrated circuit and an LCD, but also an organic ELD, for example, a signal line, a power supply line, a scanning line and a TFT formed on a substrate of an active matrix type organic ELD. Needless to say, the present invention can be applied to electrodes, peripheral wiring, and wiring in a peripheral driving circuit formed on the same substrate. According to the wiring formation method of the above embodiment, a metal wiring mainly composed of copper can be selectively formed, and a fine wiring pattern required for the wiring of the peripheral drive circuit can be formed.

Next, an embodiment of a method for manufacturing a semiconductor device of the present invention will be described with reference to FIGS. The same parts as those in FIGS. 1 to 6 are denoted by the same reference numerals, and detailed description thereof will be omitted because it is duplicated. In this embodiment, an example of a manufacturing method of a semiconductor device in which a TFT is manufactured and then wired will be described.

  First, the manufacturing process S of the crystallization substrate 18 shown in FIG. 9 is performed. A substrate 1, for example, a glass substrate made of quartz, non-alkali glass, or the like is transported and positioned at a predetermined position in the plasma CVD apparatus chamber (step-1). On the glass substrate, a base insulating layer 2 such as a silicon nitride layer is vapor-phase grown by plasma CVD (step-2).

Next, on the silicon nitride film, a non-single crystal semiconductor layer made of an amorphous silicon layer or a polycrystalline silicon layer to be crystallized, for example, an amorphous silicon layer 38 has a thickness of 30 nm to 300 nm, for example, about 200 nm. Then, vapor phase growth is performed by a plasma CVD method (step-3).

  Next, on the amorphous silicon layer 38, a cap layer 39 having a transparency and a heat storage function with respect to incident light to form a large grain size crystallization region, for example, a silicon oxide layer having a thickness of 10 nm by plasma CVD. The film is formed to ˜1000 nm, for example, 260 nm. The cap layer 39 is made of an insulating layer and has a heat storage function, and is a film for relaxing the temperature drop rate of the non-single-crystal semiconductor layer when crystallizing by irradiation with laser light. In this way, the crystallization substrate 18 is manufactured (step-4).

Next, the crystallization step T is performed. First, the manufactured substrate 18 to be crystallized is placed in alignment with a predetermined position of the substrate sample stage 19 of the crystallization apparatus 20. An excimer laser beam having a light intensity distribution with a reverse peak pattern at a predetermined crystallization position of the substrate 18 to be crystallized conveyed to the crystallization apparatus 20 is transmitted through the silicon oxide layer as the cap layer 39 to be amorphous. The porous silicon layer 38 is irradiated (step-5), and a crystallized region having a large grain size is formed in the irradiated region (step-6).

The excimer laser light is, for example, a KrF excimer laser and has an energy density of 500 mJ / cm ² . Position information for crystallization is stored in advance in a computer. This computer automatically moves sequentially to the crystallization position in the crystallized substrate 18 and positions it, irradiates the laser beam for crystallization, performs crystallization, and ends the crystallization step T.

That is, in the crystallization step T, the surface of the cap layer 39 is irradiated with excimer pulse laser light having a reverse peak light intensity distribution R by using a phase modulation excimer laser crystallization method. The irradiated region of the amorphous silicon layer 38 is heated to a high temperature and melted by laser irradiation with pulsed laser light. At this time, the high temperature heats the base insulating layer 2 and the cap layer 39 and accumulates heat in the base insulating layer 2 and the cap layer 39. The melting region is cooled during the period of interruption of the pulsed laser beam, and the solidification position slowly moves in the lateral direction (horizontal direction) due to the heat storage, so that crystal growth occurs and a crystallization region with a large grain size is formed.

As a result, a part or the whole of the amorphous silicon layer 38 is converted into a crystallized semiconductor thin film. Irradiation with the pulse laser beam having the light intensity distribution R having the reverse peak shape may be performed once, but may be performed a plurality of times so that the same part or a part of the region overlap, and the irradiation with the pulse laser light and the flash lamp Light irradiation may be combined.

  Next, a semiconductor device such as a TFT is formed on the semiconductor thin film after the crystallization process. A silicon oxide layer (SiO 2) that is a cap layer 39 is formed on the surface of the substrate 18 to be crystallized after the crystallization process is completed.

  In this embodiment, the silicon oxide layer of the cap layer 39 formed to form a TFT in the large grain size crystallization region is removed (step-7). The crystalline silicon layer 38 after the crystallization process is exposed on the surface of the crystallized substrate 18 where the cap layer 39 has been etched.

Next, a semiconductor device such as a TFT (thin film transistor) manufacturing process is performed on the glass substrate after the crystallization process. First, the glass substrate is transferred into a plasma CVD reaction chamber, and a gate insulating layer 40 is formed on the exposed surface of the crystalline silicon layer film 38 of the transferred glass substrate as shown in FIG. For this purpose, a silicon oxide film is formed (step-8). The gate insulating layer 40 is a silicon oxide film having a thickness of, for example, 30 nm.

  Next, a gate electrode 41 made of MoW is formed at a predetermined wiring pattern position of the gate insulating layer 40 (step-9).

Impurity ions for forming a source region and a drain region are ion-implanted at a high concentration into the crystallization region using the formed gate electrode 41 as a mask. As the impurity ions, for example, phosphorus is ion-implanted in the case of an N-channel transistor, and boron is ion-implanted in the case of a P-channel transistor. Thereafter, annealing is performed in a nitrogen atmosphere (for example, at 550 degrees Celsius for 1 hour) to activate the impurities and form the source region S and the drain region D in the crystallization region. As a result, a channel region C in which carriers move is formed between the formed source region S and drain region D (step-10).

  Next, an interlayer insulating layer 9 made of a laminate of SiO 2 and SiN or BCB is formed on the gate insulating layer 40 and the gate electrode 41. A source electrode 43 and a drain electrode 44 are formed in the interlayer insulating layer 9, and contact holes for forming wirings 45 and 46 are formed in the electrodes 43 and 44, respectively (step-11).

  Next, the source and drain electrodes 43 and 44 and the wirings 45 and 46 are formed in the formed contact holes with the laminated structure of the base barrier layer 3, the copper seed layer 4, and the copper wiring layer 7 described in FIGS. 1 and 2. Form a film. Further, a wiring composed of a base barrier layer 3, a copper seed layer 4, and a copper wiring layer 7 having a predetermined pattern is formed on the interlayer insulating layer 9 by using a photolithography technique to form a thin film transistor (TFT) and a semiconductor. A device is manufactured (step-12). Next, a passivation layer 13 made of SiN or a laminate of SiN and BCB is formed on the TFT, and contact holes are formed at desired positions such as electrode pads (step-13).

  Next, the above-described crystallization step T will be specifically described with reference to FIGS. 9 and 10. The crystallization apparatus 20 includes an illumination system 15, a phase modulation element 16 provided on the optical axis of the illumination system 15, an imaging optical system 17 provided on the optical axis of the phase modulation element 16, It comprises a substrate sample stage 19 that supports a crystallized substrate 18 provided on the optical axis of the imaging optical system 17.

The illumination system 15 is an optical system shown in FIG. 10 and includes, for example, a light source 21 and a homogenizer 22. The light source 21 includes a XeCl excimer laser light source 21 that supplies light having a wavelength of 308 nm. The light source 21 may be an excimer laser such as a KrF excimer laser light source that emits pulsed light having a wavelength of 308 nm or an ArF laser that emits pulsed light having a wavelength of 193 nm. Further, the light source 21 may be a YAG laser light source. The light source 21 may be any other suitable light source that outputs energy for melting a non-single crystal semiconductor film such as the amorphous silicon layer 38. A homogenizer 22 is provided on the optical axis of the laser light emitted from the light source 21.

The homogenizer 22 includes, for example, a beam expander 23, a first fly-eye lens 24, a first condenser optical system 25, a second fly-eye lens 26, and a second condenser optical on the optical axis of the laser light from the light source 21. A system 27 is provided. The homogenizer 22 equalizes the light intensity of the laser light emitted from the light source 21 and the incident angle to the phase modulation element 16 within the cross section of the light beam.

That is, in the illumination system 15, the laser light incident from the light source 21 is magnified by the beam expander 23 and then enters the first fly-eye lens 24. A plurality of light sources are formed on the rear focal plane of the first fly-eye lens 24, and light beams from the plurality of light sources pass through the incident surface of the second fly-eye lens 26 via the first condenser optical system 25. Illuminate in a superimposed manner. As a result, a larger number of light sources are formed on the rear focal plane of the second fly-eye lens 26 than on the rear focal plane of the first fly-eye lens 24. Light beams from a number of light sources formed on the rear focal plane of the second fly-eye lens 26 are incident on the phase modulation element 16 via the second condenser optical system 27 and are illuminated in a superimposed manner.

As a result, the first fly-eye lens 24 and the first condenser optical system 25 of the homogenizer 22 constitute a first homogenizer, and perform a homogenization process on the incident angle of the laser light incident on the phase modulation element 16. The second fly-eye lens 24 and the second condenser optical system 27 constitute a second homogenizer, and the laser light whose incident angle from the first homogenizer is uniformized by the second homogenizer on the phase modulation element 16. The light intensity is uniformized at each position in the plane. In this way, the illumination system 22 forms laser light having a substantially uniform light intensity distribution, and this laser light enters the phase modulation element 16.

  The phase modulation element 16, for example, a phase shifter is an optical element that phase-modulates the light emitted from the homogenizer 22 and emits a laser beam having a reverse peak-shaped minimum light intensity distribution. In the inverse peak-shaped light intensity minimum distribution, the horizontal axis is the place (position on the irradiated surface), and the vertical axis is the light intensity (energy). An optical system for obtaining a reverse peak-shaped minimum light intensity distribution includes a concavo-convex pattern formed on a transparent substrate such as quartz glass, and a line-and-space pattern and an area modulation pattern.

The phase shifter adds a step (unevenness) to a transparent body, for example, a quartz substrate, causes diffraction and interference of laser light at the boundary of the step, and imparts a periodic spatial distribution to the laser light intensity. The phase shifter is, for example, a case where a phase difference of 180 degrees is added on the left and right with the stepped portion x = 0 as a boundary. In general, when the wavelength of the laser beam is λ, a transparent medium having a refractive index n is formed on a transparent substrate to give a phase difference of 180 degrees. The film thickness t of the transparent medium is t = λ / 2 (n -1). If the refractive index of the quartz substrate is 1.46, the wavelength of the XeC1 excimer laser light is 308 nm. Therefore, in order to add a phase difference of 180 degrees, a step of 334.8 nm is formed by a method such as photoetching. .

When the SiN _x film is formed as a transparent medium by PECVD, LPCVD, etc., if the refractive index of the SiN _x film is 2.0, the SiN _x film is formed on the quartz substrate at 154 nm, and photoetching is performed. A step should be added. For example, the intensity of laser light that has passed through a phase shifter with a phase difference of 180 degrees shows a pattern of periodic strength (line and space).

In this embodiment, the mask in which the steps themselves are formed periodically is a periodic phase shifter. Both the width of the phase shift pattern and the distance between patterns are, for example, 3 μm. The phase difference does not necessarily need to be 180 degrees, and may be a phase difference that can realize the strength and weakness of the laser beam.

The laser light phase-modulated by the phase modulation element 16 is incident on the crystallized substrate 18 through the imaging optical system 17. Here, the imaging optical system 17 optically conjugates the pattern surface of the phase modulation element 16 and the crystallized substrate 18. In other words, the height position of the substrate sample stage 19 is set so that the crystallized substrate 18 is set to a surface optically conjugate with the pattern surface of the phase modulation element 16 (image surface of the imaging optical system 17). It is corrected. The imaging optical system 17 includes an aperture stop 33 between the positive lens group 31 and the positive lens group 32. The imaging optical system 17 is an optical lens that forms an image on the crystallized substrate 18 by reducing the image of the phase modulation element 16 at the same magnification or reduction, for example, 1/5.

  The aperture stop 33 has a plurality of aperture stops having different sizes of openings (light transmission portions). The plurality of aperture stops 33 may be configured to be replaceable with respect to the optical path. Alternatively, the aperture stop 33 may have an iris stop that can continuously change the size of the opening. In any case, the size of the aperture of the aperture stop 33 (and consequently the image-side numerical aperture NA of the imaging optical system 4) is a required light intensity distribution on the semiconductor film of the crystallized substrate 18, as will be described later. Is set to generate. The imaging optical system 17 may be a refractive optical system, a reflective optical system, or a refractive / reflective optical system.

Further, as shown in FIG. 9, a crystallized substrate 18 is formed on a glass plate 2 for liquid crystal display, for example, as a base insulating layer 2 by chemical vapor deposition (CVD) or sputtering, as a silicon oxide layer, a layer to be crystallized. As a result, a silicon oxide layer is sequentially formed as an amorphous silicon layer 38 and a cap layer 39.

The amorphous silicon layer 38 is a film to be crystallized, and is selected to have a film thickness of, for example, 30 to 250 nm. The cap layer 39 stores heat generated when the amorphous silicon layer 38 is melted during the crystallization process, and this heat storage action contributes to the formation of a crystallized region having a large grain size. The cap layer 39 is an insulating film such as a silicon oxide film (SiO ₂ ) and has a thickness of 100 nm to 400 nm, for example, 300 nm.

The substrate 18 to be crystallized is automatically transported onto the substrate sample stage 19 of the crystallization apparatus 20, positioned and placed at a predetermined position, and held by a vacuum chuck, an electrostatic chuck or the like. .

  Next, the crystallization process will be described with reference to FIGS. The pulsed laser light emitted from the laser light source 21 enters the homogenizer 22, and the light intensity is made uniform and the incident angle to the phase modulation element 16 is made uniform within the beam diameter of the laser light. That is, the homogenizer 22 spreads the laser beam incident from the light source 21 in the horizontal direction to form a linear (for example, a line length of 200 mm) laser beam, and further makes the light intensity distribution uniform. For example, a plurality of X direction cylindrical lenses are arranged in the Y direction to form a plurality of light beams arranged in the Y direction, each light beam is redistributed by another X direction cylindrical lens, and similarly, a plurality of Y direction cylindrical lenses are A plurality of light beams arranged in the direction and in the X direction are formed, and each light beam is redistributed by another Y-direction cylindrical lens.

The laser beam is a XeCl excimer laser beam with a wavelength of 308 nm, and the pulse duration of one shot is 20 to 200 ns. When the phase modulation element 16 is irradiated with pulsed laser light under the above conditions, the pulsed laser light incident on the periodically formed phase modulation element 16 causes diffraction and interference at the stepped portion. As a result, the phase modulation element 16 generates a strong and weak light intensity distribution in a reverse peak pattern that changes periodically.

The intensity distribution of the intensity of the reverse peak pattern outputs a laser beam intensity that melts the amorphous silicon layer 38 from the minimum light intensity to the maximum light intensity. The pulsed laser light that has passed through the phase modulation element 16 is focused on the crystallized substrate 18 by the imaging optical system 17 and enters the amorphous silicon layer 38.

  That is, the incident pulse laser beam is almost transmitted through the cap layer 39 and absorbed by the amorphous silicon layer 38. As a result, the irradiated region of the amorphous silicon layer 38 is heated and melted. This melting heat is stored in the cap layer 39 and the silicon oxide film of the base insulating layer 2.

  When the irradiation of the pulse laser beam is in the cut-off period, the irradiated region tries to cool down at high speed, but the heat is stored in the cap layer 39 provided on the front and back surfaces and the silicon oxide film of the base insulating layer 2. The temperature drop rate becomes extremely gradual. At this time, the temperature of the irradiated region is lowered according to the light intensity distribution of the reverse peak pattern generated by the phase modulation element 16, and the crystals grow sequentially in the horizontal direction.

In other words, the solidification position in the melted region in the irradiated region gradually moves from the low temperature side to the high temperature side. That is, the crystal grows laterally from the crystal growth start position toward the crystal growth end position.
In this way, the crystallization process using one-pulse laser light is completed. The crystallized region thus crystal-grown is large enough to form one or a plurality of TFTs.

  The crystallization apparatus 20 automatically irradiates the crystallization region of the next amorphous silicon layer 38 with a pulsed laser beam according to a program stored in advance to form a crystallization region. Movement to the next crystallization position can be performed by relatively moving the crystallized substrate 18 and the light source 21, for example, by moving the substrate sample stage 19.

  When the region to be crystallized is selected and alignment is completed, the next pulse laser beam is emitted. By repeating such shots of laser light, the crystallized substrate 18 can be crystallized over a wide range. In this way, the crystallization process is completed.

  In this embodiment, not only a semiconductor device but also an LCD, an organic EL display device (OLED), for example, a signal line, a power line, a scanning line, and an electrode in a TFT formed on a substrate of an active matrix type organic OLED, and the periphery It can be easily applied to wiring, wiring in a peripheral drive circuit formed on the same substrate, and the like.

  As described above, according to the embodiment, a low resistance copper wiring having a specific resistance of, for example, 2.5 μΩcm or less can be realized. In particular, a semiconductor device such as a thin film transistor or a thin film transistor circuit can be formed.

It is a figure for demonstrating embodiment of this invention method, and is a principal part expanded sectional view for demonstrating the intermediate process to a wiring pattern formation process in order of a process. FIG. 3 is an enlarged cross-sectional view of a main part for explaining a step of forming a copper wiring layer subsequent to the step of FIG. 1 in order of steps. FIG. 3 is an enlarged cross-sectional view of a main part for explaining steps up to a step of forming an interlayer insulating film next to the step of FIG. 2. It is a principal part expanded sectional view for demonstrating other embodiment of the copper diffusion suppression structure of FIG. It is a principal part expanded sectional view for demonstrating other embodiment of FIG. 1 to process order. FIG. 6 is an enlarged cross-sectional view of a main part for explaining the steps up to the next interlayer insulating film forming step in the step of FIG. 5 in order of steps; It is a principal part expanded sectional view for demonstrating other embodiment of the copper diffusion suppression structure of FIG. 6 to process order. It is a process flow figure for explaining an embodiment of a manufacturing method of a semiconductor device of the present invention in order of a process. It is an optical block diagram of the crystallization apparatus for demonstrating the crystallization process of FIG. It is an optical block diagram for demonstrating the structure of the illumination system of FIG. FIG. 9 is a cross-sectional view for explaining the structure of a semiconductor device manufactured by the process of FIG. 8.

Explanation of symbols

1: substrate, 2: underlying insulating layer, 3: underlying barrier layer, 4: copper seed layer,
5: Photoresist layer, 6: Wiring groove, 7: Copper wiring layer, 8: Protective layer, 9: Interlayer insulating layer, 10: Capping metal layer, 12: Copper alloy seed layer, 13: Passivation layer, 15: Illumination system, 16: Phase modulation element, 17: Imaging optical system, 18: Substrate to be crystallized, 19: Substrate sample stage, 20: Crystallizer, 21: Light source, 22: Homogenizer, 23: Beam expander, 24: First Fly eye lens, 25: first condenser lens optical system, 26: second fly eye lens, 27: second condenser optical system, 31, 32: positive lens group, 33: aperture stop, 38: amorphous silicon layer, 39: cap layer, 40: gate insulating layer, 41: gate electrode, 43: source electrode, 44: drain electrode, 45, 46: wiring.

Claims (10)

Forming a copper seed layer on the substrate;
Forming a copper wiring layer having a predetermined pattern on the copper seed layer;
In removing the copper seed layer other than the region in contact with the copper wiring layer,
Forming a protective layer on at least the copper wiring layer;
Dry etching the copper seed layer using the protective layer as a mask;
A method for forming a copper wiring layer, comprising: Forming a base barrier layer between the substrate and the copper seed layer;
The method for forming a copper wiring layer according to claim 1, further comprising: a step of dry etching the base barrier layer after the copper seed layer is dry etched using the protective layer as a mask. Forming a capping metal layer for preventing copper diffusion on the exposed surface of the copper seed layer and the copper wiring layer after etching the copper seed layer using the protective layer as a mask. 3. The method for forming a copper wiring layer according to claim 1, wherein the copper wiring layer is formed. Forming an interlayer insulating layer for preventing diffusion of copper on the exposed surfaces of the copper seed layer and the copper wiring layer after etching the copper seed layer using the protective layer as a mask. 3. The method for forming a copper wiring layer according to claim 1, wherein the copper wiring layer is formed. 2. The method for forming a copper wiring layer according to claim 1, further comprising a step of etching the protective layer after dry etching the copper seed layer using the protective layer as a mask. 3. The method for forming a copper wiring layer according to claim 2, further comprising a step of etching the protective layer after dry etching the copper seed layer and the underlying barrier layer using the protective layer as a mask. The formation of the copper wiring layer having a predetermined pattern includes a step of forming a resist layer on the copper seed layer to be thicker than the copper wiring layer;
Forming a wiring groove in the shape of the copper wiring layer, the resist layer;
Forming a copper wiring layer in the etching groove shallower than the depth of the wiring groove;
The method for forming a copper wiring layer according to any one of claims 1 to 6, further comprising: etching the resist layer to form a copper wiring layer.   The method for forming a copper wiring layer according to claim 1, wherein the copper seed layer is mainly oriented in (111).   The method for forming a copper wiring layer according to claim 1, wherein an average crystal grain size of the copper seed layer is at least 0.25 μm or more. After forming a source region, a drain region, and a channel region on a semiconductor substrate and forming a gate insulating film on the channel region, when forming a gate electrode, a source electrode, a drain electrode, and their wiring layers,
Forming a copper seed layer mainly composed of copper;
Forming a copper wiring layer having a predetermined pattern on the copper seed layer;
Forming a protective layer on the copper wiring layer;
And a step of removing the copper seed layer using the protective layer as a mask.

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