JP2006133948A - Arbitration device and arbitration method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To aim to build a logic verification environment in which execution of a complex request to a competitive resource can be arbitrarily and reliably generated so as to verify operations of an arbitration device for arbitrating requests in a system in which multiple processors independently perform access to the competitive resource. <P>SOLUTION: A waiting time control section 108 stops an operation of a request control section 120 by using operation stop time acquired by an operation stop time acquisition section 110 from an operation stop time storage section 113, and sets a waiting time stored at a waiting time storage section 107 by using sequence control time acquired by a sequence control time acquisition section 109 from a sequence control time storage section 112. In the request control section 120, a request acceptance section 104 accepts a request from a request output section 2 selected in accordance with its priority and waiting time, and a request execution section 105 executes the request. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an arbitration device and an arbitration method.

  In a system in which a plurality of processors (for example, CPU (Central Processing Unit)) independently access competing resources (for example, a data flow control circuit and a shared memory), arbitration is generally performed by a round robin method. (For example, Patent Document 1).

The features of the round robin method are as follows.
(1) Arbitrate equally.
(2) The time interval from the end of a certain request operation to the reception of the next request is always constant.

  FIG. 7 shows an operation example of the arbitration device using the round robin method. Currently, four processors A, B, C, and D can output requests (requests) to one resource, and each processor has 1 so that {processor D> processor C> processor B> processor A}. Priority 4 is assigned. Of these, the case where the processor C with priority 2 and the processor B with priority 3 are outputting requests will be described.

First, the arbitrating device acquires the priority order of each processor (S701), and checks whether or not a request is output in order from the processor D having the priority order 1. Since the processor D having the current priority level 1 is not outputting a request and the processor C having the priority level 2 is outputting a request, the request from the processor C is accepted (S703) and executed (S706). . Thereafter, the priority order is updated as follows (S707), and the priority order of each processor is {processor D> processor B> processor A> processor C}.
(1) The priority of a processor having a higher priority than the processor that has accepted the request is not changed.
(2) The priority of the processor that has accepted the request is changed to the lowest order.
(3) The priorities of the processors having lower priorities than the processor from which the request has been accepted are each changed to a higher priority.
JP 11-73397 A

  In the system as described above, a plurality of requests are mixed for competing resources, and complicated control is performed. Therefore, sufficient logic verification is required. Conventionally, as a general method for performing logical verification of competing resources, a test environment similar to that of an actual system has been simulated and simulated, so the request issuing operation for competing resources is shown in FIG. I could only expect the simple behavior shown in.

However, when performing logical verification of competing resources, the following is required for the request issue operation.
(1) Adjust the request interval.
(2) Change the order of received requests.

  In the implementation by the conventional round robin method, as shown in FIG. 5B, it is impossible to generate an arbitrary access required for a test for performing logic verification of competing resources, and only an insufficient test is performed. I can't.

  An object of the present invention is to construct a logic verification environment that can arbitrarily and reliably generate a complicated request for a competing resource.

The arbitration device of the present invention
In an arbitration device that arbitrates a request for requesting access to the resource by a plurality of arithmetic devices that access a common resource,
A request control unit that selects the arithmetic device, receives a request from the selected arithmetic device, and executes the request;
A waiting time control unit that controls the waiting time of each of the computing devices until the request control unit accepts the request;
The request control unit
A priority storage unit for storing the priority of each of the arithmetic devices when receiving a request;
A priority order acquisition unit for acquiring the priority order stored in the priority order storage unit;
A request receiving unit that selects the computing device based on the priority order acquired by the priority order obtaining unit and the waiting time controlled by the waiting time control unit, and receives a request of the selected computing device;
A request execution unit that executes the request received by the request reception unit.

  According to the present invention, it is possible to construct a logic verification environment that can arbitrarily and reliably execute a complicated request for a competing resource.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of a system including an arbitration device 1 according to the present embodiment.

  In a system in which a plurality of request output units 2 independently access the contention resource unit 3, all request output units 2 access the contention resource unit 3 via the arbitration device 1.

  In FIG. 1, the contention resource unit 3 is a module composed of resources (for example, a data flow control circuit and a shared memory) in which a plurality of requests compete, and A to D of the request output unit 2 are independent of each other to the contention resource unit 3 The arbitration device 1 is a module that arbitrates a large number of requests from the request output unit 2 to the competing resource unit 3 and, in many cases, independently of each other. The arbitration device 1 is configured by a logic circuit or a combination of a processor on the logic circuit, a memory, firmware stored in the memory, and the like. In the arbitrating device 1, what will be described as “˜storage unit” below includes a register, a volatile memory, a nonvolatile memory, and the like.

  In the present embodiment, an operation stop time storage unit 113 that stores a waiting time (operation stop time) until the next transaction execution to the competing resource unit 3 and a sequence for storing a waiting time (request for order control) until a request is returned. The control time storage unit 112 is mounted on a volatile memory as a control table 111 as shown in FIG. 2, for example. The control table 111 is a timing information table for arbitrarily and reliably generating a complicated request operation to the competing resource unit 3, and includes two elements of an operation stop time t_wait and an order control time r_wait as one entry. , PMAX entries.

  The operation stop time setting unit 115 sets t_wait, and the sequence control time setting unit 114 sets r_wait. The timing for setting the control table 111 may be during the operation of the arbitration device 1 or before the operation of the arbitration device 1 is started. When t_wait and r_wait are set in advance before the operation of the arbitrating device 1, it is possible to omit the operation stop time setting unit 115 and the sequence control time setting unit 114. t_wait and r_wait are set as the number of clock cycles, for example.

  The operation stop time acquisition unit 110 and the sequence control time acquisition unit 109 hold a table pointer p. The table pointer p is a pointer that designates an entry in the control table 111, and is stored in a register shared by the operation stop time acquisition unit 110 and the sequence control time acquisition unit 109, for example. The operation stop time acquisition unit 110 acquires t_wait from the control table 111 with reference to the table pointer p. Further, the order control time acquisition unit 109 acquires r_wait from the control table 111 with reference to the table pointer p.

  In the arbitration device 1, the request control unit 120 that performs a request arbitration operation includes a priority acquisition unit 101, a priority storage unit 102, a request reception unit 104, a request execution unit 105, a waiting time acquisition unit 106, and a waiting time storage unit 107. Consists of

  The waiting time control unit 108 uses the t_wait provided from the operation stop time acquisition unit 110 to stop the operation of the request control unit 120 or stores the waiting time using the r_wait provided from the sequence control time acquisition unit 109. The waiting time stored in the unit 107 is set.

  In the request control unit 120, the waiting time storage unit 107 holds a waiting time counter of each request output unit 2.

  The priority order acquisition unit 101 acquires the priority order setting value of each request output unit 2 held by the priority order storage unit 102. The waiting time acquisition unit 106 acquires the waiting time from the waiting time storage unit 107. The request receiving unit 104 determines which request output unit 2 will receive the request next based on the priority and the waiting time, and receives the request. The request received by the request receiving unit 104 is executed by the request execution unit 105.

  When the request is executed, the request output unit 2 accesses the contention resource unit 3 and performs processing using the contention resource unit 3. The request execution unit 105 updates the priority setting value of each request output unit 2 held by the priority storage unit 102 after execution of the request.

  FIG. 3 is a block diagram illustrating a configuration example of the request control unit 120.

  Request signals output from the respective request output units 2 are transmitted to the combinational circuit 117 through the tristate gate 116. Also, t_wait and r_wait output from the waiting time control unit 108 are transmitted to the combinational circuit 117 for t_wait and to the waiting counter 118 for r_wait. t_wait notifies the time for stopping the operation of the combinational circuit 117, and r_wait notifies the time to be added to one of the wait counters corresponding to each request output unit 2.

  The tristate gate 116 passes the request signal if the connected wait counter is 0, and blocks the request signal if the wait counter is other than 0.

  The combinational circuit 117 is a circuit that performs arbitration by the round robin method. When a request signal is received from any one of the request output units 2, the combinational circuit 117 receives the request according to the priority order and accepts that the request has been accepted. The signal is transmitted to the request output unit 2. The request output unit 2 that has received the acceptance notification signal accesses the contention resource unit 3.

  FIG. 4 is a flowchart showing the operation of the arbitration device 1 according to the present embodiment.

  Currently, four request output units 2A, B, C, D can output requests to the competing resource unit 3, and {request output unit 2D> request output unit 2C> request output unit 2B> request output unit 2A} It is assumed that priorities 1 to 4 are assigned to the request output units 2 so that Of these, the case where the request output unit 2C with priority 2 and the request output unit 2B with priority 3 output a request will be described.

  First, a pointer p indicating an entry in the control table 111 and a waiting time counter corresponding to each of the request output units 2A, B, C, and D are initialized to 0 (S401).

  If there is a request from any of the request output units 2, the priority order of each request output unit 2 is acquired (S701). Wait if there is no request. In this example, since the request output units 2B and C issue a request, the priority order is acquired.

  It is confirmed whether or not requests are output in order from the request output unit 2D having the priority 1. The request output unit 2D that is currently at priority 1 does not output a request, and the request output unit 2C at priority 2 outputs a request, so the waiting time set for the request output unit 2C is 0. It is determined whether it is.

If the waiting time counter is 0, the request from the request output unit 2C is accepted (S404) and executed (S407). Thereafter, the priority order is updated as follows (S408), and the priority order of each request output unit 2 is {request output unit 2D> request output unit 2B> request output unit 2A> request output unit 2C}.
(1) The priority of the request output unit 2 having a higher priority than the request output unit 2 that has accepted the request is not changed.
(2) The priority of the request output unit 2 that has received the request is changed to the lowest order.
(3) The priority of the request output unit 2 having a lower priority than the request output unit 2 that has received the request is changed to one higher order.

  Next, when the waiting time counter corresponding to each request output unit 2 has a waiting time of 1 or more, 1 is subtracted from the waiting time counter value (S409). In all the waiting time counters, the minimum value of the waiting time is 0. For example, when the first request is executed after the initial state, no waiting time counter is subtracted.

  Using the pointer p indicating the entry in the control table 111, the entry p is extracted from the control table 111. One entry consists of {r_wait, t_wait}. This r_wait is set to a waiting time counter value corresponding to the currently accepted request output unit 2C (S410). This has the effect of changing the priority.

  Next, the operation of the request control unit 120 is stopped for the number of cycles described in t_wait (S411). This has the effect of adjusting each request interval to the contention resource unit 3.

  A pointer p indicating an entry in the control table 111 is added to obtain a pointer for the next entry (S412). When p reaches pMAX, it returns to p = 0 (S413). At this time, the process may be terminated, or the process may be repeated from the step of confirming whether there is a request from any of the first request output units 2.

  With the above operation, it is possible to arbitrarily and reliably generate a complicated request to the competing resource unit 3.

  In the present embodiment, when the control table 111 is pMAX = 1, r_wait = 0, t_wait = 0, the operation of the arbitration device 1 is the operation of the round robin method. Therefore, the arbitration device 1 can be used not only for the logic verification environment but also for the actual environment. Therefore, if the arbitration device 1 for the actual environment is configured similarly to the present embodiment, and the control table 111 is set as pMAX = 1, r_wait = 0, t_wait = 0, the arbitration device 1 is put into practical use. It becomes possible. In addition, when any trouble occurs in the arbitration device 1, the arbitration device 1 can be verified by adjusting the above three values, and there is no need to use another device for verification.

  In the present embodiment, the example in which four request output units 2 output requests to one competing resource unit 3 has been described. However, when there are two or more competing resource units 3, two, Even when there are three or five or more request output units 2, arbitration can be performed in the same manner as described above. For example, when there are two competing resource units 3, there is a method in which the arbitrating device 1 includes two control tables 111 for each competing resource unit 3.

  In this embodiment, the sequence control time r_wait and the operation stop time t_wait are used as the control table entries. However, only one of r_wait and t_wait may be used. When only r_wait is used, the operation stop time acquisition unit 110, the operation stop time storage unit 113, and the operation stop time setting unit 115 of FIG. 1 are not necessary. When only t_wait is used, the wait time acquisition unit 106 of FIG. The storage unit 107, the sequence control time acquisition unit 109, the sequence control time storage unit 112, and the sequence control time setting unit 114 are not necessary.

Embodiment 2. FIG.
FIG. 6 is a block diagram illustrating a configuration of a system including the arbitrating device 1 according to the present embodiment.

  In FIG. 6, the random number generation unit 119 includes two random number generators. One random number generator generates the operation stop time described in the first embodiment as a random number, and the other random number generator generates the sequence control time desired to be described in the first embodiment as a random number.

  Other configurations and operations of the arbitration device 1 according to the present embodiment are the same as those described in the first embodiment.

  As described above, in Embodiment 1, the timing of receiving and executing a request is controlled using t_wait and r_wait included in each entry of the control table 111. In this embodiment, for example, FIG. The timing is controlled using a random number generated by a random number generator having the indicated p as a variable.

  In the present embodiment, since a random number generator is used instead of the control table 111, the configuration and setting method are simplified as compared with the first embodiment, and execution of complicated requests for competing resources is more reliably performed. Can be generated.

The construction method of the logic verification environment of the competing resource unit described in the first to third embodiments has the following elements.
(1) In order to perform logic verification of the contention resource unit by arbitrating N request output units that issue requests to the contention resource unit and N requests to perform logic verification of the designed contention resource unit A request control unit that can arbitrarily and reliably generate complex operations required for the system.
(2) A control table for the request control unit to arbitrarily and reliably generate a complicated operation.
The control table is composed of a plurality of entries, with two elements of a waiting time until the next transaction execution to the competing resource unit and a waiting time until the return of request acceptance as one entry.

  In addition, the logical verification environment construction method holds a control table, and every time a request is received, the priority order other than the corresponding acceptance request number is changed, the waiting time is subtracted, and the entry of the control table is By making the request control unit quiesce for the number of cycles of waiting time until the next transaction execution shown, it has been improved to facilitate test verification of the contention arbitration circuit.

  In addition, the construction method of the logic verification environment is not only suitable for the construction of the logic verification environment, but also makes it possible to design a request control unit that allows for implementation in the real environment. Specifically, it includes a request control unit that can perform an operation that is completely equivalent to a request control unit that can be designed by a conventional method, according to the set value of the control table.

1 is a block diagram illustrating a configuration of a system including an arbitration device according to Embodiment 1. FIG. An example of a control table. The block diagram which shows the structural example of a request control part. 4 is a flowchart showing the operation of the arbitration device according to the first embodiment. The timing chart which shows the operation example of an arbitration apparatus. It is a block diagram which shows the structure of the system provided with the arbitration apparatus which concerns on Embodiment 2. FIG. The flowchart which shows operation | movement of the conventional arbitration apparatus.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Arbitration apparatus, 2 Request output part, 3 Contention resource part, 101 Priority acquisition part, 102 Priority order storage part, 104 Request reception part, 105 Request execution part, 106 Wait time acquisition part, 107 Wait time storage part, 108 Wait Time control unit, 109 sequence control time acquisition unit, 110 operation stop time acquisition unit, 111 control table, 112 sequence control time storage unit, 113 operation stop time storage unit, 114 sequence control time setting unit, 115 operation stop time setting unit, 116 3-state gate, 117 combinational circuit, 118 wait counter, 119 random number generation unit, 120 request control unit.

Claims (7)

In an arbitration device that arbitrates a request for requesting access to the resource by a plurality of arithmetic devices that access a common resource,
A request control unit that selects the arithmetic device, receives a request from the selected arithmetic device, and executes the request;
A waiting time control unit that controls the waiting time of each of the computing devices until the request control unit accepts the request;
The request control unit
A priority storage unit for storing the priority of each of the arithmetic devices when receiving a request;
A priority order acquisition unit for acquiring the priority order stored in the priority order storage unit;
A request receiving unit that selects the computing device based on the priority order acquired by the priority order obtaining unit and the waiting time controlled by the waiting time control unit, and receives a request of the selected computing device;
An arbitration device comprising: a request execution unit that executes a request received by the request reception unit. The arbitration device further includes:
An operation stop time storage unit that stores an operation stop time at which the request control unit stops operation; and
An operation stop time acquisition unit for acquiring the operation stop time stored in the operation stop time storage unit,
The waiting time control unit
The arbitration device according to claim 1, wherein the operation of the request control unit is stopped based on the operation stop time acquired by the operation stop time acquisition unit. The arbitration device further includes:
An order control time storage unit for storing an order control time for controlling an order in which the request receiving unit selects an arithmetic device;
An order control time acquisition unit for acquiring the order control time stored in the order control time storage unit;
A waiting time storage unit for storing the waiting time set by the waiting time control unit;
A waiting time acquisition unit for acquiring the waiting time stored in the waiting time storage unit,
The waiting time control unit
Set a waiting time based on the sequence control time acquired by the sequence control time acquisition unit,
The request receiving unit
The arbitration device according to claim 1, wherein the arithmetic device is selected based on the priority order acquired by the priority order acquisition unit and the waiting time acquired by the waiting time acquisition unit. The arbitration device further includes:
A random number generator for generating random numbers,
The waiting time control unit
The arbitration device according to claim 1, wherein the waiting time is controlled based on the random number generated by the random number generation unit. In an arbitration method using an arbitration device in which a plurality of arithmetic devices that access a common resource arbitrate a request for requesting access to the resource,
A request control step of selecting the arithmetic device, receiving a request from the selected arithmetic device, and executing the request;
A waiting time control step for controlling the waiting time of each of the computing devices until the request is received in the request control step,
The request control step includes
A priority order storing step for storing the priority order of each of the computing devices when receiving a request;
A priority acquisition step of acquiring the priority stored in the priority storage step;
A request receiving step of selecting the arithmetic device based on the priority acquired in the priority order acquisition step and the waiting time controlled in the waiting time control step, and receiving a request of the selected arithmetic device;
A mediation method comprising: a request execution step of executing the request received in the request reception step. The arbitration method further includes:
An operation stop time storage step of storing an operation stop time for stopping the operation of the request control step;
An operation stop time acquisition step of acquiring the operation stop time stored in the operation stop time storage step,
The waiting time control step includes
The arbitration method according to claim 5, wherein the operation of the request control step is stopped based on the operation stop time acquired in the operation stop time acquisition step. The arbitration method further includes:
An order control time storing step for storing an order control time for controlling the order in which the computing devices are selected in the request receiving step;
An order control time acquisition step of acquiring the order control time stored in the order control time storage step;
A waiting time storing step for storing the waiting time set in the waiting time control step;
A waiting time acquisition step of acquiring the waiting time stored in the waiting time storage step,
The waiting time control step includes
Set a waiting time based on the sequence control time acquired in the sequence control time acquisition step,
The request acceptance process includes:
The arbitration method according to claim 5 or 6, wherein the arithmetic device is selected based on the priority order acquired in the priority order acquisition step and the waiting time acquired in the waiting time acquisition step.

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