JP2006121609A - Receiver, reception signal detecting circuit, and synchronizing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a receiver accelerating processing of determining presence/absence of a communication signal, a reception signal detecting circuit used therefor and a synchronizing circuit used therefor. <P>SOLUTION: The receiver is provided with: a first differentiation circuit 5, for which a time constant is set to a value dividing a cycle with 2π or more, for differentiating an envelope signal of a radio signal with a pulse periodically; a second differentiation circuit 6, for which a time constant is set to a value dividing the cycle with 2π or less; an integration circuit 8 for integrating a differentiation signal for a first integration period; and a control unit 12 which judges that the radio signal is not received when an integration value of a differentiation signal of the first differentiation circuit 5 is zero, or judges that the radio signal is received when the integration value is not zero. The control unit 12 changes a timing of the first integration period with a variation corresponding to the integration value of the differentiation signal of the second differentiation circuit 6 when it is judged that the radio signal is received, and restores data using a data restoration unit 11 when the integration value is a positive value. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a receiving device that receives a radio signal of ultra-wideband communication, a received signal detection circuit that detects the presence or absence of a radio signal, and a synchronization circuit that performs pulse synchronization.

  In recent years, attention has been paid to an ultra wide band (UWB) communication system that performs ultra-wideband communication using a pulse signal sequence composed of pulse signals synchronized with a predetermined cycle timing as one of high-speed wireless transmission systems. Yes. In one aspect of UWB communication, communication is performed without using a carrier wave and using a pulse signal sequence made up of extremely fine pulse signals such as a pulse width of 1 nsec or less (see, for example, Patent Document 1).

  FIG. 10 is a block diagram showing a UWB communication receiving apparatus 100 according to the background art. A receiving apparatus 100 illustrated in FIG. 10 includes an antenna 101 that receives a UWB communication signal transmitted from a transmitting apparatus using UWB communication, an amplifier 102 that amplifies the UWB communication signal received by the antenna 101, and a UWB that uses the transmitting apparatus. A decoder source 103 for generating a decode control signal corresponding to the same known PN (Pseudorandom Noise) code used to generate the communication signal, and a waveform substantially equivalent to each pulse of the received signal; An adjustable time base 104 for generating a periodic timing signal including a pulse train of a template signal, and a decoding time modulator for generating a decoded signal temporally coincident with a known PN code of a transmission apparatus based on the decoding control signal and the periodic timing signal 105 and the correlation between the received signal amplified by the amplifier 102 and the decoded signal And a correlator 106 that generates a correlation voltage, a low-pass filter 107 that feeds back the correlation voltage to the adjustable time base 104, and a demodulator 108 that removes subcarriers from the correlation voltage and restores received data. Yes.

  The correlator 106 can demodulate the received signal by obtaining a correlation between the received signal amplified by the amplifier 102 and the decoded signal temporally matched with the known PN code of the transmitting apparatus. It can be done.

  The receiving apparatus 100 configured as described above synchronizes the transmitted pulse signal and the reception timing on the receiving apparatus 100 side in order to receive the pulse signal arranged on the time axis in synchronization with a predetermined cycle timing. It is necessary to perform pulse synchronization.

FIG. 11 is an explanatory diagram for explaining a method of achieving pulse synchronization according to the background art. First, as shown in FIG. 11, the communication signal of UWB communication includes a pulse P100 for establishing pulse synchronization at a constant period, for example, 200 nsec. On the other hand, the receiving apparatus 100 receives a UWB communication signal only in a predetermined period, for example, a 10 nsec window period, and gradually shifts the timing of the window period by 10 nsec until the pulse P100 is received within the window period. While searching for the timing of the pulse P100. When the pulse P100 is received within the window period, the pulse synchronization is performed by acquiring the timing of the window period as the synchronization timing.
Japanese National Patent Publication No. 10-508725

  By the way, in the receiving apparatus 100 as described above, when a communication signal is not transmitted, there is a need to stop the operation of the receiving circuit and reduce power consumption. Therefore, in the receiving apparatus 100 as described above, in order to detect the presence / absence of transmission of a communication signal, an operation for searching for the timing of the pulse P100 is performed in the same manner as the above-described operation for synchronizing the pulse, and the pulse P100 is not detected. In this case, it may be determined that the communication signal is not transmitted, and for example, the operation of the demodulator 108 is stopped to reduce power consumption.

  However, in such a method, in order to detect the presence / absence of a communication signal, it is necessary to search the timing of the pulse P100 while gradually shifting the timing of the window period. was there. For example, when the pulse P100 has a cycle of 200 nsec and the window period is 10 nsec, the presence or absence of a communication signal is determined unless the pulse P100 is searched by shifting the timing of the window period up to 19 times as shown in FIG. I can't.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a receiving device, a received signal detecting circuit, and a synchronizing circuit capable of speeding up the process for determining the presence or absence of a communication signal. To do.

  In order to achieve the above object, a receiving apparatus according to the first means of the present invention includes a receiving unit that receives a radio signal having a pulsed signal at a predetermined period, and a radio signal received by the receiving unit. And a first differential signal obtained by differentiating the envelope signal acquired by the detection unit, and a time constant of the detector is equal to or greater than a value obtained by dividing the period by 2π. 1 differential circuit, an integration circuit that integrates the first differential signal for a first integration period that is a partial period in the period, and when the integration value by the integration circuit is zero, the radio signal is It is determined that the wireless signal is received by the receiving unit when it is determined that the wireless signal is not received by the receiving unit, and the integrated value by the integrating circuit is not zero. Z A data restoration unit that restores data from a radio signal received by the reception unit, and a control unit that operates the data restoration unit when the determination unit determines that the radio signal is received by the reception unit It is characterized by providing these.

  Further, in the above-described receiving device, a second differential signal obtained by differentiating the envelope signal acquired by the detection unit is generated, and a second constant whose time constant is less than or equal to a value obtained by dividing the period by 2π. A circuit further comprising: when the determination unit determines that the wireless signal is received by the reception unit, the control unit causes the integration circuit to integrate the second differential signal, and the integration value is If it is a negative value, the timing of the first integration period is changed by a change amount corresponding to the integral value, and if the integral value is a positive value, the data restoration unit restores the data. It is characterized by letting.

  In the above-described receiving device, the integration circuit integrates the differential signal for a second integration period different from the first integration period during the period, and the control unit performs the determination by the determination unit. When it is determined that a radio signal is received by the receiving unit, the integration circuit further integrates the second differential signal for a second integration period delayed from the first integration period, and the second If the value obtained by subtracting the integration value in the second integration period from the integration value in the first integration period is a positive value, the timing of the first integration period is changed in the advance direction, and the negative value may be used. For example, the timing of the first integration period is changed in the delay direction.

  Further, the received signal detection circuit according to the second means of the present invention includes a receiving unit that receives a radio signal having a pulsed signal at a predetermined period, and an envelope signal of the radio signal received by the receiving unit. A detection unit to acquire, a first differentiation circuit that generates a differential signal obtained by differentiating the envelope signal acquired by the detection unit, and whose time constant is equal to or greater than a value obtained by dividing the cycle by 2π, and the cycle An integration circuit that integrates the differential signal for an integration period that is a part of the period, and when the integration value by the integration circuit is zero, it is determined that the wireless signal is not received by the reception unit, and the integration And a determination unit that determines that the wireless signal is received by the reception unit when the integrated value by the circuit is not zero.

  The synchronization circuit according to the third means of the present invention acquires a radio signal having a pulsed signal at a predetermined cycle, and an envelope signal of the radio signal received by the receiver A second differential circuit that generates a second differential signal obtained by differentiating the envelope signal acquired by the detection unit, and whose time constant is equal to or less than a value obtained by dividing the period by 2π; An integration circuit that integrates the second differential signal for a first integration period, which is a part of the period, and a change amount corresponding to the integration value when the integration value of the integration circuit is a negative value And a control unit that changes the timing of the first integration period and determines that synchronization is achieved when the integration value is a positive value.

  In the reception device and the reception signal detection circuit having such a configuration, the reception unit receives a radio signal having a pulsed signal at a predetermined cycle, the detection unit acquires an envelope signal of the radio signal, and the time constant is A differential signal obtained by differentiating the envelope signal acquired by the detector by the first differentiating circuit having a period equal to or greater than the value obtained by dividing the period by 2π is generated. Then, the integration circuit integrates the differential signal for the integration period which is a part of the period, and the determination unit determines that the wireless signal is not received by the reception unit when the integration value is zero, When the integrated value is not zero by the determination unit, it is determined that the wireless signal is received by the reception unit. Thereby, since the presence / absence of reception of the radio signal can be detected without performing the search operation of the pulse signal in the radio signal, the process for determining the presence / absence of the communication signal can be speeded up.

  Further, in the synchronization circuit having such a configuration, a radio signal having a pulsed signal is received at a predetermined period by the reception unit, an envelope signal of the radio signal is acquired by the detection unit, and a time constant is equal to 2π. A differential signal obtained by differentiating the envelope signal acquired by the detection unit is generated by the second differentiating circuit which is equal to or less than the value divided by the The differential signal is integrated. When the integration value of the integration circuit is a negative value by the control unit, the timing of the first integration period is changed by a change amount corresponding to the integration value, and the integration value is a positive value. In this case, since it is determined that the synchronization has been achieved, the synchronization processing for synchronizing the timing of the pulse signal and the first integration period can be speeded up.

  Embodiments according to the present invention will be described below with reference to the drawings. In addition, the structure which attached | subjected the same code | symbol in each figure shows that it is the same structure, The description is abbreviate | omitted.

(First embodiment)
FIG. 1 is a block diagram showing an example of the configuration of a receiving apparatus according to an embodiment of the present invention. 1 includes an antenna 2 that is an example of a receiving unit that receives a radio signal, an amplifier 3 that amplifies a radio signal SA received by the antenna 2 and outputs the amplified signal as a received signal SB, and an amplifier 3 A diode detection circuit 4 that is an example of a detection unit that acquires the envelope signal SC of the output reception signal SB, and a first differentiation circuit 5 that differentiates the envelope signal SC acquired by the diode detection circuit 4 (first Differentiation circuit) and second differentiation circuit 6 (second differentiation circuit), first differentiation signal SD (first differentiation signal) obtained by the first differentiation circuit 5 and second differentiation circuit 6 obtained by the second differentiation circuit 6. A switching unit 7 that outputs one of the two differential signals SE (second differential signal) to the integration circuit 8; an integration circuit 8 that integrates the signal output from the switching unit 7 to generate an integration signal SF; Integration signal SF obtained by the integration circuit 8 The AD converter 9 that performs analog-digital conversion and outputs the integrated value to the control unit 12, the control unit 12, and the correlation value in the UWB radio signal are acquired based on the envelope signal SC obtained by the diode detection circuit 4. For example, the decoder source 103, the adjustable base 104, the decode time modulator 105, the correlator 106, the low pass filter 107, and the demodulator 108 in the receiving apparatus 100 according to the background art are configured in the same manner as the data recovery based on the correlation value. A data restoration unit 11.

  The control unit 12 is configured using, for example, a state machine or a microcomputer, and controls operations of the switching unit 7, the integration circuit 8, and the data restoration unit 11. Further, when the integral value output from the AD converter 9 is zero, the control unit 12 determines that the UWB wireless signal is not received by the antenna 2 and the integral value output from the AD converter 9 is zero. Otherwise, it also functions as a determination unit that determines that the UWB wireless signal is received by the antenna 2. The receiving apparatus 1 shown in FIG. 1 receives a UWB wireless signal having a pulsed signal at a timing synchronized with a preset period T, for example, a 200 nsec period.

FIG. 2 is a circuit diagram illustrating an example of a detailed configuration of the first differentiation circuit 5 and the second differentiation circuit 6. In the first differentiating circuit 5 shown in FIG. 2, the output terminal of the diode detection circuit 4 is connected to the ground via the capacitor C1 and the resistor R1, and the connection point between the capacitor C1 and the resistor R1 is connected to the input terminal of the switching unit 7. By being connected, a CR differentiation circuit is configured. The constant τ1 when the first differentiating circuit 5, so as to satisfy the following condition equation (1), the resistance value R ₁ of the capacitor C ₁ and the resistor R1 of the capacitor C1 is set.
τ1 = C ₁ · R ₁ ≧ T / (2 × π) (1)
Here, when the first differentiating circuit 5 is considered as a high-pass filter, the cut-off frequency fc1 is fc1 = 1 / (2π · C ₁ · R ₁ ) (2)
It becomes.

In the second differentiating circuit 6 shown in FIG. 2, the output terminal of the diode detection circuit 4 is connected to the ground via the capacitor C2 and the resistor R2, and the connection point between the capacitor C2 and the resistor R2 is the input of the switching unit 7. A CR differentiation circuit is configured by being connected to the terminals. The constant τ2 time of the second differentiating circuit 6, so as to satisfy the following condition equation (3), the capacitance C ₂ of capacitor C2 and the resistance value R ₂ of the resistor R2 is set.
τ2 = C ₂ · R ₂ ≦ T / (2 × π) (3)
Here, when the second differentiating circuit 6 is considered as a high-pass filter, the cutoff frequency fc2 is fc2 = 1 / (2π · C ₂ · R ₂ ) (4)
It becomes.

  The switching unit 7 is a so-called multiplexer, and in response to a control signal from the control unit 12, the first differential signal SD obtained by the first differentiation circuit 5 and the second differentiation signal SE obtained by the second differentiation circuit 6. Either one is output to the integrating circuit 8. In this case, in the receiving apparatus 1 shown in FIG. 1, the antenna 2, the amplifier 3, the diode detection circuit 4, the first differentiation circuit 5, the switching unit 7, the integration circuit 8, the AD converter 9, and the control unit 12 detect the received signal. It corresponds to an example of a circuit, and an antenna 2, an amplifier 3, a diode detection circuit 4, a second differentiation circuit 6, a switching unit 7, an integration circuit 8, an AD converter 9, and a control unit 12 correspond to an example of a synchronization circuit. Yes.

  The first differentiation circuit 5, the second differentiation circuit 6, and the switching unit 7 may be configured as a differentiation circuit 13 shown in FIG. The differentiating circuit 13 shown in FIG. 3 is another example of the configuration of the first differentiating circuit 5, the second differentiating circuit 6, and the switching unit 7. The output terminal of the diode detection circuit 4 is connected via a capacitor C3 and a resistor R3. The connection point between the capacitor C3 and the resistor R3 is connected to the input terminal of the switching unit 7. A series circuit of a switching unit 7 that is a switch and a resistor R4 is connected in parallel with the resistor R3.

In this case, when the switching unit 7 is turned off according to the control signal from the control unit 12, the capacitor C <b> 3 and the resistor R <b> 3 function as the first differentiation circuit 5. When the switching unit 7 is turned on in response to a control signal from the control unit 12, a series circuit of a capacitor C3 and a parallel circuit of the resistor R3 and the resistor R4 functions as the second differentiation circuit 6. The constant τ2 time constant τ1 and the second differentiating circuit 6 when the first differentiating circuit 5, the following equation (5) the resistance value of the capacitance C ₃ of the capacitor C3 so as to satisfy the condition (6) resistor R3 R ₃ and a resistance value R ₄ of the resistor R ₄ are set.
τ1 = C ₃ · R ₃ ≧ T / (2 × π) (5)
τ2 = C ₃ · {(R ₃ · R ₄ ) / (R ₃ + R ₄ )}
≦ T / (2 × π) (6)
Thereby, the circuit structure of the 1st differentiation circuit 5, the 2nd differentiation circuit 6, and the switch part 7 can be simplified.

  Next, the operation of the receiving apparatus 1 configured as described above will be described. FIG. 4 is a signal waveform diagram for explaining an example of the operation of the receiving apparatus 1. The vertical axis indicates the signal level and the horizontal axis indicates time. First, when UWB communication is not performed, the signal level of the radio signal SA received by the antenna 2 is zero, and the radio signal SA does not include the pulse P1. Then, the signal level of the reception signal SB obtained by amplifying the radio signal SA by the amplifier 3 is zero, the signal level of the envelope signal SC acquired from the reception signal SB by the diode detection circuit 4 is also zero, and the envelope is generated by the first differentiation circuit 5. The signal level of the first differential signal SD obtained by differentiating the line signal SC is also zero. Then, the first differential signal SD is output to the integrating circuit 8 by the switching unit 7 in accordance with a control signal from the control unit 12.

  On the other hand, in the integration interval signal SG for controlling the operation of the integration circuit 8, the control unit 12 outputs a pulse P <b> 2 to the integration circuit 8 at a cycle T interval. The pulse width of the pulse P2 is a part of the period T and is larger than the pulse width of the pulse P1 of the radio signal SA, and is set to 10 nsec, for example.

  Next, the integration circuit 8 integrates the first differential signal SD output from the switching unit 7 as the integration signal SF during a period in which the pulse P2 is received at a high level. Since the signal level of the first differential signal SD is now zero, the signal level of the integration signal SF is also zero. Further, the signal level of the integration signal SF is acquired by the control unit 12 as an integration value converted into a digital value by the AD converter 9. In this case, the integrated value zero is acquired by the control unit 12.

  In this way, when the UWB communication is not executed, and therefore the signal level of the radio signal SA received by the antenna 2 is zero and the radio signal SA does not include the pulse P1, the control unit 12 An integral value of zero is obtained. Then, if the integrated value is zero, the control unit 12 determines that the UWB wireless signal is not received by the antenna 2, and the operation of the data restoration unit 11 that does not need to be operated is kept in a stopped state.

  As a result, the control unit 12 can detect a state in which no UWB wireless signal is received by the antenna 2, and the control unit 12 can detect a state in which the UWB wireless signal is not received by the antenna 2. Therefore, the power consumption of the receiving apparatus 1 can be reduced.

  Next, when the UWB communication is started at timing T1, the pulse P1 is received as the radio signal SA by the antenna 2, the pulse P1 of the radio signal SA is amplified by the amplifier 3, and the diode detection is performed as the pulse P3 of the received signal SB. The pulse P4 is generated from the envelope of the pulse P3 by the diode detection circuit 4 and output to the first differentiation circuit 5 as the envelope signal SC.

When the pulse P4 of the envelope signal SC is differentiated by the first differentiation circuit 5, the first differential signal SD becomes a positive voltage at the rising edge of the pulse P4, and the first differential signal SD becomes a negative voltage at the falling edge of the pulse P4. (−ΔV). The signal level of the first differential signal SD gradually increases according to the time constant τ1 of the first differential circuit 5. In this case, the time constant τ1 of the first differentiating circuit 5 is set to be equal to or greater than the value obtained by dividing the period T by 2π. Then, the first differential signal SD that has become −ΔV at the fall of the pulse P4 remains a negative voltage after the period T has elapsed, that is, at the timing when the next pulse P4 is input to the first differential circuit 5. . The signal level v (t) of the first differential signal SD after the elapse of time t is given by the following equation (7).
v (t) = − ΔV · e ^{− (t /} τ ¹⁾ (7)
For example, if the time constant τ1 is T / 2π, the signal level v (T) at the timing when the next pulse P4 is input to the first differentiating circuit 5 is −0.002ΔV, and has a negative voltage value. It is not zero. For example, if the time constant τ1 is T, the signal level v (T) at the timing when the next pulse P4 is input to the first differentiating circuit 5 is −0.368ΔV, and has a negative voltage value. Absent. Therefore, when the pulse P1 is received as the radio signal SA by the antenna 2, the signal level of the first differential signal SD has a positive voltage value at the timing synchronized with the pulse P1, and at the timing not synchronized with the pulse P1. The signal level of the first differential signal SD has a negative voltage value.

  Next, the first differential signal SD is output to the integration circuit 8 by the switching unit 7 according to the control signal from the control unit 12, and the pulse P2 in the integration interval signal SG from the control unit 12 is high by the integration circuit 8. During the period received at the level, the first differential signal SD output from the switching unit 7 is integrated as the integration signal SF. In FIG. 4, the timing of the pulse P2 in the integration interval signal SG is synchronized with the timing of the pulse P1 in the radio signal SA. Then, since the first differential signal SD has a positive voltage value at the timing of the pulse P2, the signal level of the integration signal SF also becomes a positive value. Then, the signal level of the integration signal SF is acquired by the control unit 12 as an integration value converted into a digital value by the AD converter 9. In this case, an integral value having a positive value is acquired by the control unit 12.

  In this way, the UWB communication is executed and thus the radio signal SA received by the antenna 2 includes the pulse P1 having the period T, and the timing of the pulse P2 in the integration interval signal SG is synchronized with the timing of the pulse P1 in the radio signal SA. If so, a positive integral value is acquired from the AD converter 9 by the control unit 12. Then, if the integrated value from the AD converter 9 is not zero by the control unit 12, it is determined that the UWB wireless signal is received by the antenna 2, and the data restoration unit 11 performs the response according to the control signal from the control unit 12. Be operated.

  Further, if the integrated value from the AD converter 9 is a positive value, the control unit 12 determines that the timing of the pulse P2 in the integration interval signal SG is synchronized with the timing of the pulse P1 in the radio signal SA, and the control is performed. The timing of the pulse P2 is supplied from the unit 12 to the data restoration unit 11 as the pulse synchronization timing, and the data restoration unit 11 performs pulse synchronization based on the pulse synchronization timing supplied from the control unit 12, and from the diode detection circuit 4 The data is restored based on the envelope signal SC.

  On the other hand, FIG. 5 is a waveform diagram showing an example of a signal waveform when the timing of the pulse P2 in the integration interval signal SG and the timing of the pulse P1 in the radio signal SA are not synchronized. In FIG. 5, the timing of the pulse P2 in the integration interval signal SG is not synchronized with the timing of the pulse P1 in the radio signal SA. Then, since the first differential signal SD has a negative voltage value at the timing of the pulse P2, the signal level of the integration signal SF also becomes a negative value.

  Then, the signal level of the integration signal SF is acquired by the control unit 12 as an integration value having a negative value converted into a digital value by the AD converter 9. In this way, the UWB communication is executed and thus the radio signal SA received by the antenna 2 includes the pulse P1 having the period T, and the timing of the pulse P2 in the integration interval signal SG is synchronized with the timing of the pulse P1 in the radio signal SA. If not, a negative integral value is acquired from the AD converter 9 by the control unit 12. Then, if the integrated value from the AD converter 9 is not zero by the control unit 12, it is determined that the UWB wireless signal is received by the antenna 2, and the data restoration unit 11 performs the data restoration unit 11 according to the control signal from the control unit 12. Be operated.

  Thereby, the control unit 12 determines that the UWB radio signal is not received by the antenna 2 if the integral value from the AD converter 9 is zero without performing the search operation of the pulse P1 in the radio signal SA. If the integrated value from the AD converter 9 is not zero, it can be determined that the UWB wireless signal is received by the antenna 2, so that the process for determining the presence or absence of a communication signal can be speeded up.

  Further, if the integrated value from the AD converter 9 is a negative value, the control unit 12 determines that the timing of the pulse P2 in the integration interval signal SG is not synchronized with the timing of the pulse P1 in the radio signal SA. In order to synchronize the timing of P2 with the timing of pulse P1, that is, to achieve pulse synchronization, the following operation is performed.

  FIG. 6 is a waveform diagram for explaining an example of the operation of the receiving apparatus 1 for achieving pulse synchronization. First, the pulse P1 is received as the radio signal SA by the antenna 2, the pulse P1 of the radio signal SA is amplified by the amplifier 3, and is output to the diode detection circuit 4 as the pulse P3 of the reception signal SB, and the pulse P3 is output by the diode detection circuit 4 A pulse P4 is generated from the first envelope and is output to the first differentiating circuit 5 as the envelope signal SC.

Then, when the pulse P4 of the envelope signal SC is differentiated by the second differentiation circuit 6, the second differential signal SE becomes a positive voltage at the rising edge of the pulse P4, and the second differential signal SE becomes a negative voltage at the falling edge of the pulse P4. (−ΔV). Then, the signal level of the second differential signal SE gradually increases in accordance with the time constant τ 2 of the second differential circuit 6. In this case, the time constant τ2 of the second differentiation circuit 6 is set to be equal to or less than the value obtained by dividing the period T by 2π, and the signal level v (2) of the second differentiation signal SE after the elapse of time t from the fall of the pulse P4. t) is given by equation (8) below.
v (t) = − ΔV · e ^{− (t /} τ ²⁾ (8)
For example, if the time constant τ2 is T / 2π, v (t) gradually changes from −ΔV to −0.002 · ΔV between the fall of the pulse P4 and the rise of the next pulse P4. To do. That is, the signal level of the second differential signal SE changes according to the timing between the falling edge of the pulse P4 and the rising timing of the next pulse P4.

  Next, in response to the control signal from the control unit 12, the switching unit 7 outputs the second differential signal SE output from the second differential circuit 6 to the integration circuit 8, and the integration circuit 8 outputs the second differential signal SE from the control unit 12. During a period when the pulse P2 in the integration interval signal SG is received at a high level, the second differential signal SE output from the switching unit 7 is integrated as the integration signal SF.

  Then, as described above, since the signal level of the second differential signal SE changes according to the timing from the falling edge of the pulse P4 to the rising timing of the next pulse P4, according to the timing of the pulse P2. The signal level Vsf of the integration signal SF changes. That is, when the timing of the pulse P2 is delayed from the timing of the pulse P4, the absolute value of the signal level Vsf increases if the timing of the pulse P2 is close to the timing of the pulse P4, and the timing of the pulse P2 is far from the timing of the pulse P4. For example, the absolute value of the signal level Vsf decreases. In this case, the signal level Vsf of the integration signal SF is negative.

  Then, the signal level Vsf of the integration signal SF is acquired by the control unit 12 as an integration value converted into a digital value by the AD converter 9. Therefore, when the timing of the pulse P2 is delayed from the timing of the pulse P4, if the timing of the pulse P2 is close to the timing of the pulse P4, the absolute value of the integrated value (negative polarity) of the AD converter 9 increases, If the timing is far from the timing of the pulse P4, the absolute value of the integral value (negative polarity) of the AD converter 9 decreases.

  Further, the amount of time for which the timing of the pulse P2 is advanced so as to synchronize the timing of the pulse P2 with the timing of the pulse P4 is decreased or increased by the control unit 12 according to the increase or decrease of the absolute value in the integral value of the AD converter 9. . Then, the synchronization process for synchronizing the timing of the pulse P2 with the timing of the pulse P4 by the control unit 12 is repeated over a plurality of periods T, whereby the timing of the pulse P2 is synchronized with the timing of the pulse P4. .

  Thus, in the pulse synchronization process for synchronizing the timing of the pulse P4, that is, the timing of the pulse P1 of the radio signal SA received by the antenna 2 and the timing of the pulse P2, the timing of the pulse P1 and the pulse P2 is controlled by the control unit 12. Since the correction amount of the timing of the pulse P2 can be changed according to the amount of deviation, the pulse synchronization processing can be speeded up.

  Note that the control unit 12 has shown an example in which the amount of time for advancing the timing of the pulse P2 is increased or decreased in accordance with the increase or decrease of the absolute value in the integral value of the AD converter 9, but in the integral value of the AD converter 9 You may make it increase / decrease the amount of time which delays the timing of the pulse P2 according to increase / decrease in an absolute value.

  Next, the operation of the receiving apparatus 1 when the timing of the pulse P2 is synchronized with the timing of the pulse P4 as described above will be described. FIG. 7 is a waveform diagram for explaining an example of the operation of the receiving apparatus 1 when the timing of the pulse P2 is synchronized with the timing of the pulse P4. As shown in FIG. 7, when the timing of the pulse P2 is synchronized with the timing of the pulse P4, the second differential signal SE has a positive voltage value at the timing of the pulse P2 in the integration interval signal SG. Then, the second differential signal SE output from the second differentiation circuit 6 is output to the integration circuit 8, and the period during which the pulse P2 in the integration interval signal SG from the control unit 12 is received at a high level by the integration circuit 8, As a result of integrating the second differential signal SE output from the switching unit 7 as the integration signal SF, the integration signal SF becomes positive.

  Further, the signal level Vsf of the integration signal SF is acquired by the control unit 12 as an integration value converted into a digital value by the AD converter 9 and if the integration value from the AD converter 9 is a positive value, the integration interval signal is obtained. It is determined that the timing of the pulse P2 in SG and the timing of the pulse P1 in the radio signal SA are synchronized, and the timing of the pulse P2 is supplied from the control unit 12 to the data restoration unit 11 as a pulse synchronization timing. Pulse synchronization is performed based on the pulse synchronization timing supplied from the control unit 12, and data is restored based on the envelope signal SC from the diode detection circuit 4.

  Note that the amount of time for which the timing of the pulse P2 is advanced (delayed) in accordance with the integrated value of the AD converter 9 is obtained by, for example, an experiment using an actual machine, and this is a table of timing correction amounts for the integrated value of the AD converter 9. Data may be stored in advance in a non-illustrated non-volatile memory provided in the control unit 12 or the like. Further, the control unit 12 can obtain a positive integration value from the AD converter 9 even if the pulse synchronization process is repeatedly executed for a predetermined number of cycles T based on the table data thus obtained. If this is not the case, that is, if pulse synchronization cannot be achieved, fine adjustment may be performed by increasing or decreasing the correction amount based on the table data.

(Second Embodiment)
Next, a receiving apparatus according to the second embodiment of the present invention will be described. The configuration of the receiving device 1a according to the second embodiment is shown in FIG. 1 as with the receiving device 1 according to the first embodiment. The receiving device 1a according to the second embodiment and the receiving device 1 according to the first embodiment differ in the operation of the pulse synchronization processing of the control unit 12. Since other configurations and operations are the same as those of the receiving apparatus 1 according to the first embodiment, description thereof will be omitted, and pulse synchronization processing of the receiving apparatus 1a according to the present embodiment will be described below.

  FIG. 8 is a waveform diagram for explaining an example of the pulse synchronization processing of the receiving apparatus 1a shown in FIG. Note that the processing for determining the presence / absence of a radio signal by the control unit 12 and the data restoration processing by the data restoration unit 11 are the same as those of the receiving apparatus 1 shown in FIG. First, similarly to the receiving apparatus 1 shown in FIG. 1, the second differential signal SE output from the second differential circuit 6 is output to the integrating circuit 8 by the switching unit 7 in accordance with the control signal from the control unit 12. .

  Next, in the integration interval signal SG for controlling the operation of the integration circuit 8 by the control unit 12, the pulse P5 having the same pulse width as the pulse P2 within the period T is generated from the pulse P2 together with the pulse P2 having the period T. The signal is output to the integrating circuit 8 at a timing delayed by the time T2. The time T2 is, for example, T / 2 and is shorter than the period T. Then, the integration circuit 8 integrates the second differential signal SE output from the switching unit 7 for the period in which the pulse P2 and the pulse P5 in the integration interval signal SG from the control unit 12 are received at a high level, Further, the integrated value converted into a digital value by the AD converter 9 is output to the control unit 12.

Then, the control unit 12 acquires the integration value S _f1 integrated in the period of the pulse P2 by the integration circuit 8 and the integration value S _f2 integrated in the period of the pulse P5 by the integration circuit 8, and the difference value Sdiff is obtained. , Sdiff = S _f1 −S _f2 . Then, since the second differential signal SE is expressed by an exponential function as shown in Expression (8), the difference value Sdiff varies depending on the timing of the pulses P2 and P5, that is, the deviation time of the pulse P2 with respect to the pulse P4. It becomes. Further, as shown in FIG. 8, when there is no pulse P4 between the pulse P2 and the pulse P5, the difference value Sdiff is a positive value. On the other hand, as shown in FIG. 9, when there is a pulse P4 between the pulse P2 and the pulse P5, the difference value Sdiff is a negative value.

  Next, when the difference value Sdiff is a positive value by the control unit 12, the amount of movement of time is smaller than the delay of the advance of the pulse P2, so the timing of the pulse P4 is advanced by advancing the timing of the pulse P4. The amount of time for which the timing of the pulse P2 is advanced in order to synchronize with the timing is increased or decreased according to the increase or decrease of the absolute value in the difference value Sdiff. On the other hand, when the difference value Sdiff is a negative value by the control unit 12, the amount of time movement is less than the delay of the pulse P2, so that the timing of the pulse P2 is delayed to the timing of the pulse P4. The amount of time to delay the timing of the pulse P2 to be synchronized is increased or decreased according to the increase or decrease of the absolute value in the difference value Sdiff.

  Then, the synchronization process for synchronizing the timing of the pulse P2 with the timing of the pulse P4 by the control unit 12 is repeated over a plurality of periods T, whereby the timing of the pulse P2 is synchronized with the timing of the pulse P4. .

  Thus, in the pulse synchronization processing for synchronizing the timing of the pulse P4, that is, the timing of the pulse P1 of the radio signal SA received by the antenna 2 and the timing of the pulse P2, the control unit 12 causes the pulse P2 to be synchronized with the difference value Sdiff. Since the timing correction amount and the correction direction can be changed, the pulse synchronization processing can be speeded up.

It is a block diagram which shows an example of a structure of the receiver which concerns on one Embodiment of this invention. It is a circuit diagram which shows an example of the detailed structure of the 1st differentiation circuit and 2nd differentiation circuit which are shown in FIG. It is a circuit diagram which shows an example of the detailed structure of the 1st differentiation circuit shown in FIG. 1, a 2nd differentiation circuit, and a switch part. It is a signal waveform diagram for demonstrating an example of operation | movement of the receiver shown in FIG. It is a signal waveform diagram for demonstrating an example of operation | movement of the receiver shown in FIG. It is a signal waveform diagram for demonstrating an example of operation | movement of the receiver shown in FIG. It is a signal waveform diagram for demonstrating an example of operation | movement of the receiver shown in FIG. It is a signal waveform diagram for demonstrating an example of operation | movement of the receiver shown in FIG. It is a signal waveform diagram for demonstrating an example of operation | movement of the receiver shown in FIG. It is a block diagram which shows the structure of the receiver which concerns on background art. It is explanatory drawing for demonstrating operation | movement of the receiver which concerns on background art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,1a Receiver 2 Antenna 3 Amplifier 4 Diode detection circuit 5 1st differentiation circuit 6 2nd differentiation circuit 7 Switching part 8 Integration circuit 9 AD converter 11 Data restoration part 12 Control part 13 Differentiation circuit C1, C2, C3 Capacitor P1 , P2, P3, P4, P5 Pulse R1, R2, R3, R4 Resistance SA Radio signal SB Reception signal SC Envelope signal SD First differential signal SE Second differential signal SF Integration signal SG Integration interval signal T Period

Claims (5)

A receiving unit for receiving a radio signal having a pulsed signal at a predetermined period;
A detector for acquiring an envelope signal of a radio signal received by the receiver;
A first differentiation circuit that generates a first differential signal obtained by differentiating the envelope signal acquired by the detection unit and whose time constant is equal to or greater than a value obtained by dividing the period by 2π;
An integration circuit that integrates the first differential signal for a first integration period that is a part of the period;
When the integration value by the integration circuit is zero, it is determined that the wireless signal is not received by the reception unit, and when the integration value by the integration circuit is not zero, the wireless signal is received by the reception unit. A determination unit that determines that the
A data restoration unit for restoring data from a radio signal received by the reception unit based on an integration value by the integration circuit;
A control unit that operates the data restoration unit when the determination unit determines that the wireless signal is received by the reception unit;
A receiving apparatus comprising: A second differential circuit that generates a second differential signal obtained by differentiating the envelope signal acquired by the detection unit and whose time constant is equal to or less than a value obtained by dividing the period by 2π;
The control unit causes the integration circuit to integrate the second differential signal when the determination unit determines that the wireless signal is received by the reception unit, and the integration value is a negative value. The timing of the first integration period is changed by a change amount corresponding to the integration value, and the data recovery unit restores the data when the integration value is a positive value. The receiving device according to claim 1. The integrating circuit integrates the differential signal for a second integration period different from the first integration period during the period;
When the determination unit determines that the wireless signal is received by the reception unit, the control unit further adds a second integration period to the integration circuit for a second integration period delayed from the first integration period. 2 is integrated, and if the value obtained by subtracting the integration value in the second integration period from the integration value in the first integration period is a positive value, the timing of the first integration period is advanced. 3. The receiving apparatus according to claim 2, wherein the timing of the first integration period is changed in the delay direction if the value is negative. A receiving unit for receiving a radio signal having a pulsed signal at a predetermined period;
A detector for acquiring an envelope signal of a radio signal received by the receiver;
A first differentiating circuit that generates a differential signal obtained by differentiating the envelope signal acquired by the detection unit and whose time constant is equal to or greater than a value obtained by dividing the period by 2π;
An integration circuit that integrates the differential signal for an integration period that is a part of the period;
When the integration value by the integration circuit is zero, it is determined that the wireless signal is not received by the reception unit, and when the integration value by the integration circuit is not zero, the wireless signal is received by the reception unit. A determination unit that determines that the
A received signal detection circuit comprising: A receiving unit for receiving a radio signal having a pulsed signal at a predetermined period;
A detector for acquiring an envelope signal of a radio signal received by the receiver;
A second differential circuit that generates a second differential signal obtained by differentiating the envelope signal acquired by the detection unit and whose time constant is equal to or less than a value obtained by dividing the period by 2π;
An integration circuit that integrates the second differential signal for a first integration period that is a partial period in the cycle;
When the integration value of the integration circuit is a negative value, the timing of the first integration period is changed by a change amount corresponding to the integration value, and when the integration value is a positive value, A control unit that determines that the
A synchronization circuit comprising:

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