JP2006121285A - Maximum likelihood decoding method and maximum likelihood decoding device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable a partial response maximum likelihood decoding operating on media noise without increasing a constraint length. <P>SOLUTION: A maximum likelihood decoding method uses two or more partial response signals having different frequency characteristics. Here, the partial response signals meet conditions that: <1> a signal amplitude becomes 0 at a frequency where a transfer function of a channel is 0; <2> a signal amplitude becomes 0 at a frequency a half as high as the frequency of a channel clock; <3> the signal amplitude of a 1st partial response is not 0 and the signal amplitude of a 2nd partial response is 0 at a frequency which is 0; and <4> restraint lengths that the partial responses have are equal to each other. For example, when the transfer function of the channel is 0 at a frequency 1/3 as high as the frequency of a clock, a PR (1, 2, 2, 1) and a PR (1, 0, 0, -1) each including four bits affecting the partial responses are combined. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a decoding technique for reproducing, for example, information recorded on a recording medium and decoding the original information, and more particularly to a partial response maximum likelihood decoding method and a maximum likelihood decoding apparatus that effectively act on media noise.

JP 2004-39130 A JP 2004-39139 A ISOM / ODS2002 Technical Digest Post-Deadline Papers p16 Jpn. J. Appl. Phys. Vol. 42 (2003) Part 1, No. 2B, 28 February 2003 954-955

As optical discs, for example, optical discs such as CD (Compact Disc) and DVD (Digital Versatile Disc) are widely used. In recent years, Blu-ray Disc (HD) and HD-DVD (High Definition DVD) are used as high-density optical discs. Etc. are being developed.
As a magnetic disk system, the increase in capacity of HDD (Hard Disc Drive) is particularly remarkable.
In general, a reproducing apparatus in a recording / reproducing technique using various recording media such as an optical disk and a magnetic disk generally includes a head or a pickup that reads a signal recorded on the recording medium as a reproduction signal, and a decoding that decodes data from the read reproduction signal. Configured by the device.
Along with the increase in recording density in the recording / reproducing technology using these optical disks and magnetic disks, a partial response maximum likelihood decoding method with high decoding accuracy is adopted in a decoding apparatus that decodes data from a reproduction signal.

Partial Response Maximum Likelihood (PRML) is a partial response generated from a partial response that associates a data string with a predetermined level in units of multiple bits and all possible data strings. This is a technique in which the maximum likelihood decoding that selects the data string whose reference signal is closest to the actual reproduction signal is fused.
In particular, in optical disks and magnetic disks, the characteristics of the communication channel, called transfer function, when reproducing bit information as a reproduction signal are just equivalent to weighting and adding multiple pieces of bit information. The partial response method is used as an effective method.

In the partial response based on such a method of adding a plurality of bit information with weights, if the weights are an integer ratio such as 1, 2, 2, 1, for example, PR (1, 2, 2 , 1), the types of partial responses are classified.
Here, the numbers in PR such as 1, 2, 2, 1 represent what is called an impulse response in the transmission path of the partial response, and the impulse response has a 1-bit width. This means the time change of the output signal when a pulse is issued.
That is, it means that the output of the reproduction signal is 0001221 when bit information is input as in 0001000.

Usually, this partial response is used such that it is close to the characteristics of the transfer function and the weight ratio is represented by a simple integer ratio.
For example, in a 25 GB / INCH ² Blu-ray disc having the highest recording density in the current optical disc medium, the transfer function is gradually reduced as the frequency increases with an amplitude of 1 at a frequency of 0, and at the time of 1 × speed playback. The transfer function becomes 0 at 22 MHz which is 1/3 of the reproduction channel clock frequency of 66 MHz.
Therefore, an actual reproduction system often employs PR (1, 2, 2, 1) which is a partial response in which the amplitude becomes 0 at a frequency of 1/3 of the channel clock frequency.
For other reasons such as sampling theorem and waveform equalization, it is also desirable that the amplitude be 0 at a frequency half the channel clock frequency, but PR (1, 2, 2, 1) is The condition that the amplitude becomes zero is also satisfied at a frequency half the channel clock frequency.

In addition, when the current optical disk medium is improved to standardize a 35 GB / INCH ² Blu-ray disk having a higher recording density, the transfer function at this recording density is assumed to be an amplitude 1 at a frequency of 0 and as the frequency increases. The transfer function becomes 0 at 16.5 MHz which is 1/4 of the reproduction channel clock frequency 66 MHz at the time of 1 × speed reproduction.
Therefore, in an actual reproduction system, it is considered necessary to employ PR (1, 2, 2, 2, 1) which is a partial response in which the amplitude becomes zero at a quarter of the channel clock frequency. It has been.
It should be noted that PR (1, 2, 2, 2, 1) also satisfies the condition that the amplitude is zero even at a frequency half that of the channel clock frequency, like PR (1, 2, 2, 1). .

By the way, this partial response maximum likelihood decoding method is an information bit detection method that is effective under the condition that the reproduced signal is a signal obtained by adding noise to the partial response signal.
Also, at this time, white noise that normally occurs flat regardless of frequency is assumed as noise, and when the noise is actually white, the conventional partial response maximum likelihood decoding method is the optimal method. Is known as.

  However, as pointed out in Patent Documents 1 and 2 and Non-Patent Documents 1 and 2, the noise of the reproduction signal from the recording medium is not necessarily white, and if it is a media noise that is noise inherent to the recording medium Rather, it is natural to think that the noise is non-white and has frequency characteristics similar to the channel response.

Therefore, considering that the noise has the same frequency characteristics as the channel response, the relationship between the media noise and the noise on the signal is examined.
When the media noise of the kth bit is ε (k) and the kth channel response is c (k), the noise n (i) on the ith signal is
n (i) = Σc (i−k) ε (k)
It becomes. Note that Σ is the sum of k from 0 to all.

In partial response maximum likelihood decoding, the error rate of the bit detection output and the difference (differential) metric between adjacent paths are closely related. For this reason, a new index related to the standard deviation of the differential metric called dM-SAM jitter or MLSE jitter has been introduced as an index representing the performance of the reproduction system.
Here, the difference metric between adjacent paths is a metric between a correct path and a path with only one error.
That is, the difference metric dM is the metric Mc of the correct path.
Mc = Σn (i) ²
(Where Σ is the sum of all i), and the metric Me of the path with only one error is
Me = Σ (c (i) −n (i)) ²
Is the difference when
dM = Σ | c (i) | ² −2Σn (i) · c (i)
It is. However, Σ is an addition for all i.

Also, the SAM jitter j is calculated using a detectable amount dM and a known amount Σ | c (i) | ²
j = √ (V (dM) / (2 · Σ | c (i) | ² ))
It is represented by However, V (dM) represents the dispersion of dM. However, Σ is an addition for all i.
Also, if SAM jitter j is a random variable that cannot be detected, n (i),
j = √ (V (n) · 2√Σ | c (i) | ² ) / (2 · Σ | c (i) | ² )
= √ (V (n) / (2 · Σ | c (i) | ² ))
It is expressed. However, V (n) represents the variance of n. Also, Σ is an addition for all i.
In this calculation, n is white noise, and Σ | c (i) | ² represents the power of the carrier.
This means that the SAM jitter j represents the reciprocal of the carrier noise ratio.

By the way, as described above, when the noise on the signal is caused by the media noise and has the same frequency characteristic as the frequency characteristic of the channel, ε is a random variable instead of n. Become. At this time, the differential metric dM is
dM = Σ | c (i) | ² −2Σε (k) Σc (i−k) · c (i)
It becomes. However, the first Σ and the third Σ are added for i, and the second Σ is added for k.
In this case, since ε (k) is an independent random variable, SAM jitter j is
j = √ (V (ε) · 2√Σ | Σc (i−k) · c (i) | ² ) / (2 · Σ | c (i) | ² )
It becomes. However, the first Σ represents the sum related to k, and the second and third Σ represent the sum related to i.

In this case, for example, the function relating to c (k) ψ (c) = √ (Σ | Σc (ik) · c (i) | ² ) / (2 · Σ | c (i) ｜ ² )
(Where the first Σ is for k and the second Σ is all for i), the SAM jitter j is
j = √V (ε) · ψ (c)
It can be expressed as

Here, the difference between the system where the system noise represented by n (k) is dominant and the system where the media noise represented by ε (k) is dominant is that the system noise is dominant. When multiple channel responses are prepared, there is system noise, but when media noise is dominant, the same media noise becomes the source of signal noise when multiple channel responses are prepared. It is a point.
In other words, when system noise is dominant, if multiple channel responses are used, it is necessary to consider new system noise each time. However, when media noise is dominant, there are multiple channel responses. Since the signal noise is related to each other, it means that there is a possibility that the SAM jitter value and thus the bit error rate may be reduced depending on the combination.

The maximum likelihood decoding method in each of the above documents is a method in which the bit error rate is reduced based on the relevance of media noise components included in partial responses obtained from such different channels.
And in the said literature, the method of implement | achieving the above using a partial response signal and its differential partial response signal is proposed, for example.
When this method is applied to the current Blu-ray Disc (25 GB / INCH ² ), PR (1, ^{2, 2} , 1) and its derivative PR (1, 1, 0, -1, -1) are combined. It is.
When applied to a high-density Blu-ray disc (35 GB / INCH ² ), PR (1, 2, 2, 2, 1) and its derivative PR (1, 1, 0, 0, −1, − 1) are combined.

The methods of these documents calculate metrics for two partial responses, add the obtained metrics to each other in a variable ratio, and use a Viterbi detection circuit based on the obtained metrics. In this method, maximum likelihood bit detection is performed.
According to this method, the coefficient ψ (c) that determines the SAM jitter in the system in which the media noise is dominant is recalculated.
ψ (c) = √ (Σ | ΣΣc (n, i−k) · c (n, i) | ² ) / (2 · ΣΣ | c (n, i) | ² )
It becomes. However, c (n, ≡) means the nth partial response among a plurality of partial responses, and i means that it represents the ith of the impulse response as before.
The first Σ represents the sum for k, the second and fourth Σ represent the sum for n, and the third and fifth Σ represent the sum for i.

In the example using a partial response and its differential response, two partial responses are used, and therefore, only n = 0 and 1 can be considered as the partial response numbers. Then, in the case of PR (1, 2, 2, 1),
c (0,0) = 1,
c (0,1) = 2,
c (0,2) = 2,
c (0,3) = 1,
And
c (1,0) = 1,
c (1,1) = 1,
c (1,2) = 0,
c (1,3) =-1,
c (1,4) =-1,
It becomes.
However, for c (1, i), since the metric is multiplied by k, the above is first multiplied by √k instead.
Since the same applies to PR (1, 2, 2, 2, 1), the description is omitted.

Using this to calculate ψ,
ψ (k) = √ (36 k ² +112 k + 262) / (4 k ² +10)
It becomes.
It can easily be seen that this function has a minimum value at a certain value k ₀ where k> 0. On the other hand, when k = 0, PR (1, 1, 0, -1, -1) is not added.
This means that in a system in which media noise is dominant, a metric obtained from PR (1, 2, 2, 1) is used instead of PR (1, 2, 2, 1). It is better to use the metric obtained by adding the metric obtained from PR (1, 1, 0, −1, −1) with an appropriate ratio k _0.
j = √V (ε) · ψ (k)
Therefore, the bit error rate can be reduced.

It can be easily understood that the magnitude of this improvement is not only the improvement as the jitter value, but also the degree of improvement in the SN ratio, considering that the SAM jitter j is the reciprocal of the SN ratio. This degree is usually close to about 1 dB to 2 dB in many cases.
The magnitude of this improvement is, for example, very large as an effect of widening the system margin and the like because the skew margin can be increased by about 0.05.

The method described above is a method applied when bit information is detected from a recording medium such as an optical disk or a magnetic disk in which media noise is dominant as described above.
However, when such a method is used, the following problems occur.
Normally, in PRML using PR (1, 2, 2, 1), it is sufficient to use a 6-state 7-level (10-branch) Viterbi detection circuit using 3-bit states. 1 and 0, -1, -1), there is a problem that it is necessary to use a 10-state 16-branch Viterbi detection circuit.
The same is true for PR (1, 2, 2, 2, 1), where it has been sufficient to use a 10-state, 16-branch Viterbi detection circuit. , -1) is the same in that it is necessary to use a Viterbi detection circuit with 16 states and 25 branches.

  Such an increase in the number of states and the number of branches is not desirable because the processing becomes complicated in both hardware and software. In particular, when implemented in hardware, making the circuit complicated is difficult to realize, and is not desirable from the viewpoint of energy saving. In particular, since the Viterbi detection circuit is originally complicated, it is necessary to simplify the processing as much as possible.

The problems in the conventional technology described so far are summarized as follows.
In a reproduction system for reproducing a recording medium such as an optical disk or a magnetic disk, noise is composed of random system noise and non-random media noise. Therefore, the conventional partial response maximum likelihood decoding that exhibits a large effect on random noise does not necessarily exhibit the optimal effect. Therefore, there is a need to realize a maximum likelihood decoding method that is effective for non-random noise, and as shown in the above document, the differential partial partial is compared with the conventional maximum likelihood decoding method using a metric from a partial response. A maximum likelihood decoding method that additionally uses a metric from the response has been proposed.
However, since this method complicates the circuit and increases the circuit scale, there is a problem that an effect corresponding to the difficulty level is not obtained.

  In view of such a situation, the present invention proposes a maximum likelihood decoding method and a maximum likelihood decoding device that can act on media noise without complicating the Viterbi detection circuit, and PR (1, 2, 2, 1) In PRML such as PR (1, 2, 2, 2, 1), a method of acting on media noise without increasing the number of states and the number of branches is proposed. In other words, an object is to realize a partial response maximum likelihood decoding method that acts on media noise without increasing the constraint length.

  The maximum likelihood decoding method of the present invention is a maximum likelihood decoding method for detecting bit information from a reproduction signal acquired from a recording medium or a transmission medium. Then, a waveform equalization process is performed on the reproduction signal to obtain a first partial response signal, a waveform equalization process is performed on the reproduction signal, and the first partial response signal is obtained. A second waveform equalization step for obtaining a second partial response signal having a frequency characteristic different from that of the response signal; a first metric generation step for generating a metric for the first partial response signal; Maximum likelihood decoding step of performing maximum likelihood decoding using a second metric generation step for generating a metric for a partial response signal, a metric by the first metric generation step, and a metric by the second metric generation step With. In this case, the first and second partial response signals obtained by the first and second waveform equalization steps have both signal amplitudes of 0 at a frequency at which the channel transfer function becomes 0, and half the frequency of the channel clock. When the frequency is 0 and the frequency is 0, the first partial response signal has a signal amplitude of 0 and the second partial response signal has a signal amplitude of 0. The constraint lengths of the partial responses of the first and second waveform equalization steps are equal.

  The maximum likelihood decoding apparatus of the present invention is a maximum likelihood decoding apparatus that detects bit information from a reproduction signal acquired from a recording medium or a transmission medium. Then, a waveform equalization process is performed on the reproduction signal to obtain a first partial response signal, and a waveform equalization process is performed on the reproduction signal to obtain the first partial response signal. A second waveform equalizing means for obtaining a second partial response signal having a frequency characteristic different from that of the signal; a first metric generating means for generating a metric for the first partial response signal; and the second partial response signal. Second metric generation means for generating a metric for the response signal; metric by the first metric generation means; and maximum likelihood decoding means for performing maximum likelihood decoding using the metric by the second metric generation means; Is provided. In this case, the first and second partial response signals obtained by the first and second waveform equalization means have both signal amplitudes of 0 at a frequency at which the channel transfer function becomes 0, which is half the frequency of the channel clock. The signal amplitude becomes 0 at both frequencies. When the frequency is 0, the signal amplitude of the first partial response signal is not 0, and the signal amplitude of the second partial response signal is 0. Further, the constraint lengths of the partial responses of the first and second waveform equalizing means are equal.

That is, the maximum likelihood decoding method and the maximum likelihood decoding apparatus of the present invention use two or more partial response signals having different frequency characteristics, and the plurality of partial response signals include:
1. The signal amplitude becomes zero at the frequency at which the channel transfer function becomes zero.
2. The signal amplitude is zero at half the frequency of the channel clock.
3. When the frequency is 0, the signal amplitude of the first partial response is not 0, and the signal amplitude of the second partial response is 0.
4). Each partial response has the same constraint length (= the number of bits affecting the partial response).
The one that satisfies the condition is used.
For example, when the transfer function of the channel is 0 at 1/3 of the clock frequency, PR (1, 2, 2, 1) such that the number of bits affecting the partial response is four. What is necessary is just to combine PR (1, 0, 0, -1). This corresponds to the case of a Blu-ray disc (recording density is 25 GB / INCH ² ) which is an example of an optical disc recording medium.
Further, when the channel transfer function is 0 at 1/4 of the clock frequency, PR (1, 2, 2, 2, 1) in which the number of bits affecting the partial response is five. ) And PR (1, 0, 0, 0, −1) may be combined. This corresponds to the case of a Blu-ray disc (recording density 35 GB / INCH ² ).
In general, where n is a constraint length and n−1 constants a (k),
The kth value of the first partial response is a (k) + a (k−1),
The kth value of the second partial response is a (k) -a (k-1).
What is necessary is just to combine two characterized by this. However, it is assumed that a (−1) = 0.

In the present invention, maximum likelihood decoding using two partial responses satisfying the above four conditions is realized.
If such a maximum likelihood decoding method is used, a bit reproduction rate higher than that of the conventional maximum likelihood decoding method can be realized in a system to which noise having the same frequency characteristics as the channel is added. Such noise is suitable for a system that generates noise unique to a medium such as a recording medium, and it can be expected to supply a simpler and more reliable apparatus for recording and reproducing information on the recording medium than in the past.

  According to the present invention, it is possible to remove the increase in the constraint length, which is the biggest problem that complicates the circuit and increases the circuit scale in the conventional method. Therefore, unlike the conventional method, there is an effect that it is possible to realize partial response maximum likelihood decoding that is effective for non-random noise without complicating the circuit and greatly increasing the circuit scale.

Hereinafter, embodiments of the present invention will be described in the following order.
[1. Concept of the present invention applied to the embodiment]
[2. First Embodiment]
[3. Second Embodiment]
[4. Summary]

[1. Concept of the present invention applied to the embodiment]

First, the concept of the present invention applied to the embodiment will be described.
The conventional maximum likelihood decoding methods shown in the above Patent Documents 1 and 2 and Non-Patent Documents 1 and 2 use a partial response signal and its differential partial response signal, and each has a metric for each of these two partial response signals. Calculate and add the obtained metrics in an appropriate combination at a predetermined ratio. The metric obtained by addition is subjected to maximum likelihood decoding by the Viterbi detection circuit.
Such a method can improve the SAM jitter and the bit error rate as described above. The reason for this will now be considered from the viewpoint of frequency characteristics.

  FIG. 16 is a graph showing the frequency characteristics of the original partial response signal (first partial response signal) and its differential partial response signal (second partial response signal), which are the above two partial response signals. . However, PR (1, 2, 2, 1) and its derivative PR (1, 1, 0, -1, -1) are handled here, the former being a solid line and the latter being a dotted line. It is represented by

If these two are taken apart from the relationship of differentiation, there are the following features.
<1> The frequency at which the transfer function of the channel is 0, and the amplitude frequency characteristic is 0,
<2> The amplitude frequency characteristic is 0 at half the frequency of the channel clock,
<3> When the frequency is 0, the first partial response is not 0, and the second partial response is 0.
Of these, the condition <1> and the condition <2> prevent noise during equalization and sampling, and are not necessarily required if the media noise is completely dominant. Since there is system noise, it is a necessary condition to fully demonstrate the effect even at that time.
On the other hand, the condition <3> is a condition necessary for bringing the noise characteristics closer to white.

As explained at the beginning of this specification, the maximum likelihood decoding method assumes white noise that occurs flat as a noise regardless of frequency, and when the noise is white, The response maximum likelihood decoding method is known as an optimal method.
Since the frequency characteristic of this noise is actually sufficient if it is the frequency characteristic immediately before the maximum likelihood decoding method, it may not be the frequency characteristic of the noise in the reproduced signal, and therefore the metric calculated from the reproduced signal. What is necessary is to consider the frequency characteristics in the.

The frequency characteristic of noise in the first partial response is assumed to be noise having the frequency characteristic of c0 (ω), and the frequency characteristic of noise in the second partial response is assumed to be noise having the frequency characteristic of c1 (ω). That is, the frequency characteristic of the solid line in FIG. 16 represents c0 (ω), and the frequency characteristic of the dotted line in FIG. 16 represents c1 (ω).
At this time, c0 (ω) is symmetrical and c0 (0) ≠ 0, but c1 (ω) is antisymmetric and c1 (0) = 0.
If these two are added together, the frequency characteristics of the synthesized noise on the left and right c (ω) = c0 (w) + c1 (w)
Is white in one of the two regions of ω <0 and ω> 0, but one of the two regions is not white, so that the effect cannot be exhibited.

The frequency characteristic of the dotted line in FIG. 17 represents c (ω), but the flat part on the right side of the figure decreases while the flat part on the left side of the figure increases. I understand. That is, one is white, but the other is not white.
However, when adding by metric, the frequency characteristics of the synthesized noise are
| C (ω) | = √ (| c0 (ω) | ² + | c1 (ω) | ² )
Thus, the frequency characteristics are bilaterally symmetric, and the two regions ω <0 and ω> 0 are both whiter than when nothing is done.
The frequency characteristic of the solid line in FIG. 17 represents | c (ω) |, but it can be seen that it is flat as a whole as compared with c (ω). Thus, if the configuration is such that c0 (ω) and c1 (ω) are squared and added, the overall frequency characteristic can be flattened.

By combining the two metrics in the above manner, it can be seen that the frequency characteristics of noise within the metric are whitened, and as a result, the effect of maximum likelihood decoding is easily exhibited, and the error rate is reduced. It turns out that it leads to improvement.
Here, the point is that the conditions necessary for realizing the above whitening are the three conditions mentioned above. Therefore, the channels of c0 and c1 are not necessarily in the relationship between differentiation and integration. There is no need to be.
That is, it is important to find two signals that satisfy the first three conditions.

Therefore, generalizing the conventional method,
<1> The frequency at which the transfer function of the channel is 0, and the amplitude frequency characteristic is 0,
<2> The amplitude frequency characteristic is 0 at half the frequency of the channel clock,
<3> When the frequency is 0, the first partial response is not 0 and the second partial response is 0.
It becomes.
Furthermore, in the present invention, as a condition for reducing the circuit scale and logic complexity,
<4> The constraint lengths of the first and second partial responses are equal.
Add the condition.

In this way, for PR (1, 2, 2, 1), when the constraint length is 4 and the frequency is 0, the channel clock frequency is 1/2 and 1/3. Sometimes it is necessary to look for a partial response with an amplitude of zero. Such a partial response is only PR (1, 0, 0, −1).
That is, when the first partial response is PR (1, 2, 2, 1), PR (1, 0, 0, −1) is appropriate for the second partial response.
In PR (1, 2, 2, 2, 1), when the constraint length is 5 and the frequency is 0, the amplitude is 1/4 and 1/3 of the frequency of the channel clock. It is sufficient to search for a partial response such that becomes 0, and such a partial response is only PR (1, 0, 0, 0, −1).
That is, when the first partial response is PR (1, 2, 2, 2, 1), PR (1, 0, 0, 0, −1) is appropriate for the second partial response.

  More generally, the constraint length is n, and the kth value of the first partial response is a (k) + a (k−1) for n−1 constants a (k). Yes, a partial response in which the kth value of the second partial response is a (k) -a (k-1) may be combined. However, it is assumed that a (−1) = 0.

  In a system to which noise having the same frequency characteristics as the channel is added by performing maximum likelihood decoding using two partial responses that satisfy the above four conditions, the bit reproduction rate is higher than that of the conventional maximum likelihood decoding method. Can be realized. Such noise is suitable for a system that generates noise inherent to a medium such as a recording medium, and it can be expected to supply a simpler and more reliable apparatus than the conventional in recording and reproducing information on a recording medium.

In addition, the effect | action by such a method can be theoretically analyzed as follows as improvement of S / N ratio.
That is, in the case of PR (1, 2, 2, 1),
c (0,0) = 1,
c (0,1) = 2,
c (0,2) = 2,
c (0,3) = 1,
c (1,0) = 1,
c (1,1) = 0,
c (1,2) = 0,
c (1,3) =-1,
And for PR (1,2,2,2,1)
c (0,0) = 1,
c (0,1) = 2,
c (0,2) = 2,
c (0,3) = 2,
c (0,4) = 1,
c (1,0) = 1,
c (1,1) = 0,
c (1,2) = 0,
c (1,3) = 0,
c (1,4) =-1,
As
ψ (c) = √ (Σ | ΣΣc (n, i−k) · c (n, i) | ² ) / (2 · ΣΣ | c (n, i) | ² )
You can ask for.
However, the first Σ represents a sum related to k, the second and fourth Σs represent a sum related to n, and the third and fifth Σs represent a sum related to i.
Also, in actuality, for c (1, i), the above value is multiplied by √k in consideration of multiplying k by a metric.

In this way, for PR (1, 2, 2, 1), ψ (k) is
ψ (k) = √ (6k ² + 36k + 262) / (2k + 10)
It becomes.
ψ (k) has a minimum value at k = 43/3. At this time, ψ (43/3) = √ (39/29).
On the other hand, in the conventional PRML, k = 0 is substituted into ψ, and ψ (0) = √ (131/50).
Therefore, the SAM jitter when two partial responses are prepared is compared to the SAM jitter value when the partial response is not prepared.
ψ (43/3) / ψ (0) = 72%
It becomes the size of.
Furthermore, since the SAM jitter is also the reciprocal of the SN ratio, the improvement degree of the SN ratio can be calculated.
This can be done by using the ratio of the values of ψ (k) in the case of k = 0 when no new term is added and the case where k = 43/3 is added and optimized. The improvement value can be calculated directly.
At this time, the improvement ratio of the SN ratio is 20 · Log 10 (ψ (0) / ψ (43/3)) = 1.4 dB.
As described above, when this method is used in the media noise dominant method, the SAM jitter and the SN ratio are improved, and the bit error rate can be reduced.

Similarly, for PR (1, 2, 2, 2, 1), ψ (k) is
ψ (k) = √ (6k ² + 52k + 646) / (2k + 14)
It becomes.
ψ (k) has a minimum value when k = 29. At this time, ψ (29) = √ (25/18).
On the other hand, since ψ (0) = √ (323/98), compared to the case where two partial responses are not prepared, the SAM jitter is
ψ (29) / ψ (0) = 65%.
When a new term is not added, that is, when the value of ψ (k) is compared between k = 0 and k =, an improved value of the SN ratio can be directly calculated.
At this time, the improvement ratio of the SN ratio is 20 · Log 10 (ψ (0) / ψ (29)) = 1.9 dB.

As described above, it is theoretically proved that the use of the partial response maximum likelihood decoding method of the present invention can improve the SAM jitter, SN ratio, and bit error rate in a system in which media noise is dominant. The

[2. First Embodiment]

FIG. 1 is a block diagram showing a schematic configuration of a recorded information reproducing apparatus to which the maximum likelihood decoding method according to the present embodiment is applied.
The recorded information reproducing apparatus in the present embodiment AD-converts a recording medium 1 on which recording information is recorded, a pickup 2 that reads a signal recorded on the recording medium 1 as a reproduced signal, and a reproduced signal read by the pickup 2 And an AD converter 3 for sampling, and a maximum likelihood decoding device 4 for decoding a data string from a sample string of a reproduction signal from the AD converter 3. The maximum likelihood decoding device 4 has a configuration as the maximum likelihood decoding device of the present invention.

FIG. 2 is a block diagram showing a configuration of maximum likelihood decoding apparatus 4 that implements the maximum likelihood decoding method according to the present embodiment.
The maximum likelihood decoding device 4 includes a first waveform equalizer 11, a second waveform equalizer 13, a first metric generator 12, a second metric generator 14, a third metric generator 15, and a Viterbi decoder 16. Consists of.

The reproduction signal input from the AD converter 3 to the maximum likelihood decoding device 4 in FIG. 2 is input to the waveform equalizers 11 and 13.
From the waveform equalizer 11, the equalized signal u _n which is equalized to a predetermined target partial response PR (1, 2, 2, 1) is output, is input to the first metric generator 12.
From the waveform equalizer 13, a predetermined target partial response PR (1, 0, 0, -1) is output equalized signal v _n equalized in, is input to the second metric generator 14.
The first metric generator 12 generates a metric based on PR (1, 2, 2, 1) that is the first predetermined response, and outputs this as the first metric.
The second metric generator 14 generates a metric based on the second predetermined response PR (1, 0, 0, −1), and outputs this as the second metric.
A plurality of first metrics output from the first metric generator 12 and a plurality of second metrics output from the second metric generator 14 are input to the third metric generator 15. The third metric generator 14 outputs a metric generated based on a predetermined relationship between the first and second metrics.
The Viterbi decoder 16 receives the metric output from the third metric generator 15, performs decoding by the Viterbi algorithm, and outputs the obtained decoded bit data.

FIG. 3 shows the configuration of the waveform equalizers 11 and 13 of FIG.
The waveform equalizers 11 and 13 form a filter including flip-flops 31A to 31D, amplifiers 32A to 32D, and an adder 33.
The reproduced signal input to the waveform equalizer 11 (13) is delayed by one channel clock by the flip-flop 31A, further delayed by one clock by the flip-flop 31B, and further delayed by one clock by the flip-flop 31C. The clock is further delayed by one clock by 31D.
The reproduction signal output from the flip-flop 31A is multiplied by Ka by the amplifier 32A, the reproduction signal output from the flip-flop 31B is multiplied by Kb by the amplifier 32B, and the reproduction signal output from the flip-flop 31C is Kc by the amplifier 32C. The reproduced signal output from the flip-flop 31D is multiplied by Kd by the amplifier 32D and output.
The four reproduction signals output from the amplifiers 32A, 32B, 32C, and 32D are added by the adder 33.
The output of the adder 33 is output from the waveform equalizer 11 (13) as an equalized signal.

Here, the coefficients Ka, Kb, Kc, and Kd of the amplifiers 32A, 32B, 32C, and 32D are adjusted so as to minimize the noise of the equalized signal.
Specifically, in the case of the waveform equalizer 11, the partial response class has a characteristic of PR (1, 2, 2, 1), and in the case of the waveform equalizer 13, the partial response class is set to PR ( Approximate the characteristics of (1, 0, 0, -1).
The coefficient adjustment may be performed using an automatic equalization coefficient adjustment algorithm such as an LMS algorithm.
In this example, there are four coefficients Ka, Kb, Kc, and Kd. The number of coefficients can be increased by increasing the number of flip-flops and multipliers. is there.

FIG. 4 shows the configuration of the first metric generator 12 shown in FIG.
The first metric generator 12 includes reference value registers 41A to 41J that hold predicted sample values, metric registers 42A to 42J, subtractors 43A to 43J, and multipliers 44A to 44J. .
This first metric generator 12, the equalized signal u _n obtained through the waveform equalizer 11 in FIG. 2 is input, it is supplied to the subtracters 43A～43J.

The reference value register 41A stores a reference level ra ₀₀₀₀ corresponding to the data string 0000.
The reference value register 41B stores a reference level ra ₀₀₀₁ corresponding to the data string 0001.
The reference value register 41C stores a reference level ra ₁₀₀₀ corresponding to the data string 1000.
The reference value register 41D stores a reference level ra ₁₀₀₁ corresponding to the data string 1001.
The reference value register 41E stores a reference level ra ₀₀₁₁ corresponding to the data string 0011.
The reference value register 41F stores a reference level ra ₁₁₀₀ corresponding to the data string 1100.
The reference value register 41G stores a reference level ra ₀₁₁₀ corresponding to the data string 0110.
The reference value register 41H stores a reference level ra ₀₁₁₁ corresponding to the data string 0111.
The reference value register 41I stores a reference level ra ₁₁₁₀ corresponding to the data string 1110.
The reference value register 41J stores a reference level ra ₁₁₁₁ corresponding to the data string 1111.
Here, since the partial response class is PRA (1, 2, 2, 1), the original bit value is ± 1/2, and each reference level is
ra ₀₀₀₀ = -3,
ra ₀₀₀₁ = -2,
ra ₁₀₀₀ = -2
ra ₁₀₀₁ = -1,
ra ₀₀₁₁ = 0,
ra ₁₁₀₀ = 0,
ra ₀₁₁₀ = + 1,
ra ₀₁₁₁ = + 2,
ra ₁₁₁₀ = +2,
ra ₁₁₁₁ = +3,
It becomes.

The reference value register 41A to the metric register 42A,
The reference value register 41B to the metric register 42B,
The reference value register 41C to the metric register 42C,
The reference value register 41D to the metric register 42D,
The reference value register 41E to the metric register 42E,
The reference value register 41F to the metric register 42F,
The reference value register 41G to the metric register 42G,
The reference value register 41H to the metric register 42H,
The reference value register 41I to the metric register 42I,
The reference value register 41J to the metric register 42J,
In each process, a subtracter (43A to 43J) and a multiplier (44A to 44J) are prepared.

The reference levels (ra ₀₀₀₀ , ra ₀₀₀₁ , ra ₁₀₀₀ , ra ₁₀₀₁ , ra ₀₀₁₁ , ra ₁₁₀₀ , ra ₀₁₁₀ , ra ₀₁₁₁ , ra ₁₁₁₀ , ra ₁₁₁₁ ) of the reference value registers 41A to 41J are supplied to the subtracters 43A to 43J, respectively. They are, respectively in the subtracters 43A～43J, the equalized signal u _n inputted, outputs an error of the reference levels obtained from the respective reference value register 41A～41J.
The error signals output from the subtracters 43A to 43J are supplied to multipliers 44A to 44J, and the multipliers 44A to 44J output signals obtained by squaring the input error signals. An absolute value calculator may be provided in place of the multiplier.

Outputs of the multipliers 44A to 44J are supplied to the metric registers 42A to 42J and are held as calculated metrics.
That is, the metric registers 42A, metric ma ₀₀₀₀ is stored between the reference level ra ₀₀₀₀ and equalized signal _{u n (ma 0000 = (u} n -ra 0000) 2).
The metric register 42B, metrics ma ₀₀₀₁ between the reference level ra ₀₀₀₁ and equalized signal u _n is stored _{(ma 0001 = (u n -ra} 0001) 2).
The metric register 42C, metrics ma ₁₀₀₀ between the reference level ra ₁₀₀₀ and equalized signal u _n is stored _{(ma 1000 = (u n -ra} 1000) 2).
The metric register 42D, metrics ma ₁₀₀₁ between the reference level ra ₁₀₀₁ and equalized signal u _n is stored _{(ma 1001 = (u n -ra} 1001) 2).
The metric register 42E, metrics ma ₀₀₁₁ between the reference level ra ₀₀₁₁ and equalized signal u _n is stored _{(ma 0011 = (u n -ra} 0011) 2).
The metric register 42F, metrics ma ₁₁₀₀ between the reference level ra ₁₁₀₀ and equalized signal u _n is stored _{(ma 1100 = (u n -ra} 1100) 2).
The metric register 42G, metrics ma ₀₁₁₀ between the reference level ra ₀₁₁₀ and equalized signal u _n is stored _{(ma 0110 = (u n -ra} 0110) 2).
The metric register 42H, metrics ma ₀₁₁₁ between the reference level ra ₀₁₁₁ and equalized signal u _n is stored _{(ma 0111 = (u n -ra} 0111) 2).
The metric register 42I, metrics ma ₁₁₁₀ between the reference level ra ₁₁₁₀ and equalized signal u _n is stored _{(ma 1110 = (u n -ra} 1110) 2).
The metric register 42J, metrics ma ₁₁₁₁ between the reference level ra ₁₁₁₁ and equalized signal u _n is stored _{(ma 1111 = (u n -ra} 1111) 2).

  The first metric generator 12 calculates the first metric with the above configuration, and outputs the values stored in the metric registers 42A to 42J for each channel bit clock.

FIG. 5 shows the configuration of the second metric generator 14 of FIG.
The second metric generator 14 includes reference value registers 51A to 51J that hold predicted sample values, metric registers 52A to 52J, subtracters 53A to 53J, and multipliers 54A to 54J. .
This second metric generator 14, the equalized signal v _n obtained through the waveform equalizer 13 in FIG. 2 is input, it is supplied to the subtracters 53A～53J.

The reference value register 51A stores a reference level rb ₀₀₀₀ corresponding to the data string 0000.
The reference value register 51B stores a reference level rb ₀₀₀₁ corresponding to the data string 0001.
The reference value register 51C stores a reference level rb ₁₀₀₀ corresponding to the data string 1000.
The reference value register 51D stores a reference level rb ₁₀₀₁ corresponding to the data string 1001.
The reference value register 51E stores a reference level rb ₀₀₁₁ corresponding to the data string 0011.
The reference value register 51F stores a reference level rb ₁₁₀₀ corresponding to the data string 1100.
The reference value register 51G stores a reference level rb ₀₁₁₀ corresponding to the data string 0110.
The reference value register 51H stores a reference level rb ₀₁₁₁ corresponding to the data string 0111.
The reference value register 51I stores a reference level rb ₁₁₁₀ corresponding to the data string 1110.
The reference value register 51J stores a reference level rb ₁₁₁₁ corresponding to the data string 1111.
Here, since the partial response class is PRB (1, 2, 2, 1), the original bit value is ± 1/2, and each reference level is
rb ₀₀₀₀ = 0
rb ₀₀₀₁ = −1
rb ₁₀₀₀ = 1
rb ₁₀₀₁ = 0
rb ₀₀₁₁ = 0
rb ₁₁₀₀ = 1
rb ₀₁₁₀ = 0
rb ₀₁₁₁ = −1
rb ₁₁₁₀ = 1
rb ₁₁₁₁ = 0
It becomes.

The reference value register 51A to the metric register 52A,
The reference value register 51B to the metric register 52B,
The reference value register 51C to the metric register 52C,
The reference value register 51D to the metric register 52D,
The reference value register 51E to the metric register 52E,
The reference value register 51F to the metric register 52F,
The reference value register 51G to the metric register 52G,
The reference value register 51H to the metric register 52H,
The reference value register 51I to the metric register 52I,
The reference value register 51J to the metric register 52J,
In each of the steps, one subtracter (53A to 53J) and one multiplier (54A to 54J) are prepared.

The reference levels (rb ₀₀₀₀ , rb ₀₀₀₁ , rb ₁₀₀₀ , rb ₁₀₀₁ , rb ₀₀₁₁ , rb ₁₁₀₀ , rb ₀₁₁₀ , rb ₀₁₁₁ , rb ₁₁₁₀ , rb ₁₁₁₁ ) of the reference value registers 51 A to 51 J are supplied to the subtracters 53 A to 53 J, respectively. They are, respectively in the subtracters 53A～53J, the equalized signal v _n input, and outputs the error of the reference levels obtained from the respective reference value register 51A～51J.
The error signals output from the subtracters 53A to 53J are supplied to the multipliers 54A to 54J, and the multipliers 54A to 54J output a signal obtained by squaring the input error signal. An absolute value calculator may be provided in place of the multiplier.

Outputs of the multipliers 54A to 54J are supplied to the metric registers 52A to 52J and are held as calculated metrics.
That is, the metric registers 52A, metric mb ₀₀₀₀ between the reference level rb ₀₀₀₀ and equalized signal v _n are stored _{(mb 0000 = (v n -rb} 0000) 2).
The metric register 52B, metric mb ₀₀₀₁ between the reference level rb ₀₀₀₁ and equalized signal v _n are stored _{(mb 0001 = (v n -rb} 0001) 2).
The metric register 52C, metric mb ₁₀₀₀ between the reference level rb ₁₀₀₀ and equalized signal v _n are stored _{(mb 1000 = (v n -rb} 1000) 2).
The metric register 52D stores a metric mb ₁₀₀₁ between the equalized signal v _n and the reference level rb ₁₀₀₁ (mb ₁₀₀₁ = (v _n −rb ₁₀₀₁ ) ² ).
The metric register 52E stores a metric mb ₀₀₁₁ between the equalized signal v _n and the reference level rb ₀₀₁₁ (mb ₀₀₁₁ = (v _n −rb ₀₀₁₁ ) ² ).
The metric register 52F stores a metric mb ₁₁₀₀ between the equalized signal v _n and the reference level rb ₁₁₀₀ (mb ₁₁₀₀ = (v _n −rb ₁₁₀₀ ) ² ).
The metric register 52G stores a metric mb ₀₁₁₀ between the equalized signal v _n and the reference level rb ₀₁₁₀ (mb ₀₁₁₀ = (v _n −rb ₀₁₁₀ ) ² ).
The metric register 52H, metric mb ₀₁₁₁ between the reference level rb ₀₁₁₁ and equalized signal v _n are stored _{(mb 0111 = (v n -rb} 0111) 2).
The metric register 52I stores a metric mb ₁₁₁₀ between the equalized signal v _n and the reference level rb ₁₁₁₀ (mb ₁₁₁₀ = (v _n −rb ₁₁₁₀ ) ² ).
The metric register 52J stores a metric mb ₁₁₁₁ between the equalized signal v _n and the reference level rb ₁₁₁₁ (mb ₁₁₁₁ = (v _n −rb ₁₁₁₁ ) ² ).

  The second metric generator 14 calculates the second metric with the above configuration, and outputs the values stored in the metric registers 52A to 52J for each channel bit clock.

FIG. 6 shows the configuration of the third metric generator 15 of FIG.
The third metric generator 15 includes 10 metrics {ma} output from the metric registers (42A to 42J) of the first metric generator 12 and the metric registers (52A to 52J) of the second metric generator 14. The ten metrics {mb} that have been output are input, and ten metrics {m} obtained from the metric registers 61A to 61J are output.

A first metric ma ₀₀₀₀ and a second metric mb ₀₀₀₀ are input to the metric register 61A, and a third metric m ₀₀₀₀ = ma ₀₀₀₀ + k * mb ₀₀₀₀ is stored with a predetermined constant k as a coefficient.
A first metric ma ₀₀₀₁ and a second metric mb ₀₀₀₁ are input to the metric register 61B, and a third metric m ₀₀₀₁ = ma ₀₀₀₁ + k * mb ₀₀₀₁ is stored with a predetermined constant k as a coefficient.
The first metric ma ₁₀₀₀ and the second metric mb ₁₀₀₀ are input to the metric register 61C, and a third metric m ₁₀₀₀ = ma ₁₀₀₀ + k * mb ₁₀₀₀ is stored with a predetermined constant k as a coefficient.
A first metric ma ₁₀₀₁ and a second metric mb ₁₀₀₁ are input to the metric register 61D, and a third metric m ₁₀₀₁ = ma ₁₀₀₁ + k * mb ₁₀₀₁ is stored with a predetermined constant k as a coefficient.
The metric register 61E receives a first metric ma ₀₀₁₁ and a second metric mb _{0011, and} stores a third metric m ₀₀₁₁ = ma ₀₀₁₁ + k * mb ₀₀₁₁ with a predetermined constant k as a coefficient.
A first metric ma ₁₁₀₀ and a second metric mb ₁₁₀₀ are input to the metric register 61F, and a third metric m ₁₁₀₀ = ma ₁₁₀₀ + k * mb ₁₁₀₀ is stored with a predetermined constant k as a coefficient.
A first metric ma ₀₁₁₀ and a second metric mb ₀₁₁₀ are input to the metric register 61G, and a third metric m ₀₁₁₀ = ma ₀₁₁₀ + k * mb ₀₁₁₀ is stored with a predetermined constant k as a coefficient.
The metric register 61H receives a first metric ma ₀₁₁₁ and a second metric mb _{0111, and} stores a third metric m ₀₁₁₁ = ma ₀₁₁₁ + k * mb ₀₁₁₁ with a predetermined constant k as a coefficient.
The metric register 61I receives a first metric ma ₁₁₁₀ and a second metric mb _{1110, and} stores a third metric m ₁₁₁₀ = ma ₁₁₁₀ + k * mb ₁₁₁₀ with a predetermined constant k as a coefficient.
A first metric ma ₁₁₁₁ and a second metric mb ₁₁₁₁ are input to the metric register 61J, and a third metric m ₁₁₁₁ = ma ₁₁₁₁ + k * mb ₁₁₁₁ is stored with a predetermined constant k as a coefficient.

  With the above configuration, the third metric generator 15 outputs the metric values stored in the metric registers 61A to 61J for each channel bit clock.

Next, the Viterbi decoder 16 will be described.
The Viterbi decoder 16 shown in FIG. 2 includes a path metric updater 70 in FIG. 7 and a path memory updater 80 in FIG.
First, the path metric updater 70 of FIG. 7 will be described.
As shown in FIG. 7, the path metric updater 70 in the Viterbi decoder 16 includes path metric registers 71A to 71J, path metric registers 72A to 72J, and flip-flops 73A to 73J.

The path metric register 71A stores the path metric pm ₀₀₀₀ of the surviving path in the state s ₀₀₀₀ .
In the path metric register 72A, a smaller value is selected from the path metrics pm ₀₀₀₀₀ = pm ₀₀₀₀ + m ₀₀₀₀ and pm ₁₀₀₀₀ = pm ₁₀₀₀ + m ₀₀₀₀ of the path reaching the state s ₀₀₀₀ . Here, the metric m ₀₀₀₀ for calculating the path metric value is input from the third metric generator 15. The value of the path metric register 72A latched by the flip-flop 73A is updated as the value of the path metric register 71A.
The path metric register 71B stores the path metric pm ₀₀₀₁ of the surviving path in the state s ₀₀₀₁ . In the path metric register 72B, a smaller value is selected from the path metrics pm ₀₀₀₀₁ = pm ₀₀₀₀ + m ₀₀₀₁ and pm ₁₀₀₀₁ = pm ₁₀₀₀ + m ₀₀₀₁ for the path leading to the state s ₀₀₀₁ . A metric m ₀₀₀₁ for calculating a path metric value is input from the third metric generator 15. The value of the path metric register 72B latched by the flip-flop 73B is updated as the value of the path metric register 71B.
The path metric register 71C, the path metric pm ₁₀₀₀ of the survival path in state s ₁₀₀₀ is stored. The path metric register 72C, the path metric pm ₁₁₀₀₀ = pm ₁₁₀₀ + m ₁₀₀₀ path leading to the state s ₁₀₀₀ is stored. A metric m ₁₀₀₀ for calculating a path metric value is input from the third metric generator 15. The value of the path metric register 72C latched by the flip-flop 73C is updated as the value of the path metric register 71C.
The path metric register 71D stores the path metric pm ₁₀₀₁ of the surviving path in the state s ₁₀₀₁ . The path metric register 72D stores a path metric pm ₁₁₀₀₁ = pm ₁₁₀₀ + m ₁₀₀₁ of the path leading to the state s ₁₀₀₁ . A metric m ₁₀₀₁ for calculating a path metric value is input from the third metric generator 15. The value of the path metric register 72D latched by the flip-flop 73D is updated as the value of the path metric register 71D.
The path metric register 71E stores the path metric pm ₀₀₁₁ of the surviving path in the state s ₀₀₁₁ . In the path metric register 72E, a smaller value is selected from the path metrics pm ₀₀₀₁₁ = pm ₀₀₀₁ + m ₀₀₁₁ and pm ₁₀₀₁₁ = pm ₁₀₀₁ + m ₀₀₁₁ of the path reaching the state s ₀₀₁₁ . A metric m ₀₀₁₁ for calculating a path metric value is input from the third metric generator 15. The value of the path metric register 72E latched by the flip-flop 73E is updated as the value of the path metric register 71E.
The path metric register 71F stores the path metric pm ₁₁₀₀ of the surviving path in the state s ₁₁₀₀ . In the path metric register 72F, a smaller value is selected from the path metrics pm ₀₁₁₀₀ = pm ₀₁₁₀ + m ₁₁₀₀ and pm ₁₁₁₀₀ = pm ₁₁₁₀ + m ₁₁₀₀ of the path reaching the state s ₁₁₀₀ . A metric m ₁₁₀₀ for calculating a path metric value is input from the third metric generator 15. The value of the path metric register 72F latched by the flip-flop 73F is updated as the value of the path metric register 71F.
The path metric register 71G stores the path metric pm ₀₁₁₀ of the surviving path in the state s ₀₁₁₀ . The path metric register 72G stores a path metric pm ₀₀₁₁₀ = pm ₀₀₁₁ + m _{0110 for} the path leading to the state s ₀₁₁₀ . A metric m ₀₁₁₀ for calculating a path metric value is input from the third metric generator 15. The value of the path metric register 72G latched by the flip-flop 73G is updated as the value of the path metric register 71G.
The path metric register 71H stores the path metric pm ₀₁₁₁ of the surviving path in the state s ₀₁₁₁ . The path metric register 72H stores a path metric pm ₀₀₁₁₁ = pm ₀₀₁₁ + m ₀₁₁₁ of the path to the state s ₀₁₁₁ . A metric m ₀₁₁₁ for calculating a path metric value is input from the third metric generator 15. The value of the path metric register 72H latched by the flip-flop 73H is updated as the value of the path metric register 71H.
The path metric register 71I stores the path metric pm ₁₁₁₀ of the surviving path in the state s ₁₁₁₀ . In the path metric register 72I, a smaller value is selected from the path metrics pm ₀₁₁₁₀ = pm ₀₁₁₁ + m ₁₁₁₀ and pm ₁₁₁₁₀ = pm ₁₁₁₁ + m ₁₁₁₀ of the path leading to the state s ₁₁₁₀ . A metric m ₁₁₁₀ for calculating a path metric value is input from the third metric generator 15. The value of the path metric register 72I latched by the flip-flop 73I is updated as the value of the path metric register 71I.
The path metric register 71J stores the path metric pm ₁₁₁₁ of the surviving path in the state s ₁₁₁₁ . In the path metric register _72J , a smaller value is selected from the path metrics pm ₀₁₁₁₁ = pm ₀₁₁₁ + m ₁₁₁₁ and pm ₁₁₁₁₁ = pm ₁₁₁₁ + m ₁₁₁₁ of the path leading to the state s ₁₁₁₁ . A metric m ₁₁₁₁ for calculating a path metric value is input from the third metric generator 15. The value of the path metric register 72J latched by the flip-flop 73J is updated as the value of the path metric register 71J.

  FIG. 8 shows a path memory updater 80 in the Viterbi decoder 16. The path memory updater 80 includes path memory registers 81A to 81J, path memory registers 82A to 82J, and flip-flops 83A to 83J.

The path memory register 81A, a path memory M ₀₀₀₀ of the survival path in state s ₀₀₀₀ is stored. In the path memory register 82A, a path memory having a path metric that decreases in the path memories M ₀₀₀₀ and M ₁₀₀₀ of the two paths up to the state s ₀₀₀₀ is selected, and the selected memory value is doubled to 0. to add. The value of the path memory register 82A latched by the flip-flop 83A is stored as the value of the path memory register 81A.
The path memory register 81B, a path memory M ₀₀₀₁ of the survival path in state s ₀₀₀₁ is stored. In the path memory register 82B, a path memory having a path metric that decreases in the path memory M ₀₀₀₀ and M ₁₀₀₀ of the two paths leading to the state s ₀₀₀₁ is selected, and the selected memory value is doubled to 1 to add. The value of the path memory register 82B latched by the flip-flop 83B is stored as the value of the path memory register 81B.
The path memory register 81C, a path memory M ₁₀₀₀ of the survival path in state s ₁₀₀₀ is stored. In the path memory register 82C, it is added to 0 the path memory M ₁₁₀₀ 2-fold to the path leading to the state s _1000. The value of the path memory register 82C latched by the flip-flop 83C is stored as the value of the path memory register 81C.
The path memory register 81D, a path memory M ₁₀₀₁ of the survival path in state s ₁₀₀₁ is stored. In the path memory register 82D, the path memory M ₁₁₀₀ of the path reaching the state s ₁₀₀₁ is doubled and 1 is added. The value of the path memory register 82D latched by the flip-flop 83D is stored as the value of the path memory register 81D.
The path memory register 81E, the path memory M ₀₀₁₁ of the survival path in state s ₀₀₁₁ is stored. In the path memory register 82E, a path memory having a path metric that decreases in the path memories M ₀₀₀₁ and M ₁₀₀₁ of the two paths leading to the state s ₀₀₁₁ is selected, and the selected memory value is doubled to 1 Is added. The value of the path memory register 82E latched by the flip-flop 83E is stored as the value of the path memory register 81E.
The path memory register 81F stores the path memory M ₁₁₀₀ of the surviving path in the state s ₁₁₀₀ . In the path memory register 82F, a path memory having a path metric that reduces the path metric is selected from the path memories M ₀₀₀₁ and M ₁₀₀₁ of the two paths that reach the state s ₁₁₀₀ , and the selected memory value is doubled to 0. Is added. The value of the path memory register 82F latched by the flip-flop 83F is stored as the value of the path memory register 81F.
The path memory register 81G stores the path memory M ₀₁₁₀ of the surviving path in the state s ₀₁₁₀ . In the path memory register 82G, the path memory M ₀₀₁₁ of the path reaching the state s ₀₁₁₀ is doubled and 0 is added. The value of the path memory register 82G latched by the flip-flop 83G is stored as the value of the path memory register 81G.
The path memory register 81H stores the path memory M ₀₁₁₁ of the surviving path in the state s ₀₁₁₁ . In the path memory register 82H, the path memory M ₀₀₁₁ of the path reaching the state s ₀₁₁₁ is doubled and 1 is added. The value of the path memory register 82H latched by the flip-flop 83H is stored as the value of the path memory register 81H.
The path memory register 81I, path memory M ₁₁₁₀ of the survival path in state s ₁₁₁₀ is stored. In the path memory register 82I, a path memory having a path metric having a smaller path metric is selected from the path memories M ₀₁₁₁ and M ₁₁₁₁ of the two paths leading to the state s ₁₁₁₀ , and the selected memory value is doubled to 0. to add. The value of the path memory register 82I latched by the flip-flop 83I is stored as the value of the path memory register 81I.
The path memory register 81J, the path metric M ₁₁₁₁ of the survival path in state s ₁₁₁₁ is stored. In the path memory register 82J, a path memory having a path metric that decreases the path metric is selected from the path memories M ₀₁₁₁ and M ₁₁₁₁ of the two paths leading to the state s ₁₁₁₁ , and the selected memory value is doubled to 1 to add. The value of the path memory register 82J latched by the flip-flop 83J is stored as the value of the path memory register 81J.

  The MSB of any of the path memory registers 82A to 82J in the path memory updater 80 of FIG. 8 is output to the outside as decoded data. As described above, the decoded bit information is output from the Viterbi decoder 16 to which the third metric is input, and the partial response maximum likelihood decoding is realized.

  In this example, the reference value is composed of a 4-bit partial response, but the reference value may be a partial response value composed of less than 4 bits. The reference value may be a partial response value composed of more than 4 bits.

Further, the reference value in this example may be given by a learning type table that adaptively feeds back the sampling level according to the decoded data. FIG. 9 shows a configuration example when an adaptation table is prepared.
That is, the bit information output from the Viterbi decoder 16 is supplied to the adaptive level control units 17 and 18.
The adaptive level control units 17 and 18 store the bit string obtained by the Viterbi detection with the length of the constraint length, and classify the sample values of the reproduction signal delayed at the same timing for each stored pattern. In this way, it is possible to successively obtain actual reproduction signal sample values for the reference level value corresponding to each branch.
The adaptive PRML is realized by averaging the actual sample values or sequentially updating the reference level values by low-pass filtering or the like.
The reference level value sequentially updated by the adaptive level control unit 17 is substituted as the reference level value stored in the reference value registers 41A to 41J of the first metric generator 12, and the adaptive level control unit The value of the reference level that has been sequentially updated in 18 is substituted as the value of the reference level stored in the reference value registers 51A to 51J of the second metric generator 14.

[3. Second Embodiment]

Subsequently, a configuration using PR (1, 2, 2, 2, 1) will be described as a second embodiment.
FIG. 2 is a block diagram showing the configuration of the maximum likelihood decoding device 4 that realizes the maximum likelihood decoding method in this example.
In this case, the maximum likelihood decoding device 4 includes a first waveform equalizer 21, a second waveform equalizer 23, a first metric generator 22, a second metric generator 24, a third metric generator 25, a Viterbi. It is constituted by the decoder 26.
The reproduced signal input to the maximum likelihood decoding device 4 is input to the waveform equalizers 21 and 23.
From the waveform equalizer 21, an equalized signal u _n equalized to a predetermined target partial response PR (1, 2, 2, 2, 1) is output and input to the first metric generator 22. .
From the waveform equalizer 23, an equalized signal v _n equalized to a predetermined target partial response PR (1, 0, 0, 0, −1) is output and input to the second metric generator 24. The
The first metric generator 22 generates a metric based on PR (1, 2, 2, 2, 1) which is a first predetermined response, and outputs it as a first metric.
In the second metric generator 24, a metric is generated based on PR (1, 0, 0, 0, −1) which is a second predetermined response and is output as a second metric.
In the third metric generator 25, the plurality of first metrics output from the first metric generator 22 and the plurality of second metrics output from the second metric generator 24 are input, and a predetermined relationship is established. A metric generated based on is output.
The Viterbi decoder 26 receives the metric output from the third metric generator 25, and the Viterbi decoder 26 outputs decoded bit data decoded by the Viterbi algorithm.

The configuration of the waveform equalizers 21 and 23 in this case is the same as that shown in FIG. 3 and repeated explanation is avoided, but the coefficients Ka to Kd of the amplifiers 32A to 32D in FIG. The noise is adjusted so as to be minimized. Specifically, in the waveform equalizer 21, the partial response class has a PR (1, 2, 2, 2, 1) characteristic, and the waveform In the equalizer 23, the partial response class is brought closer to the characteristic of PR (1, 0, 0, 0, −1). The coefficient adjustment may be performed using an automatic equalization coefficient adjustment algorithm such as an LMS algorithm.
Of course, the number of coefficients can be increased by increasing the number of flip-flops and multipliers.

FIG. 11 shows the configuration of the first metric generator 22 shown in FIG.
The first metric generator 22 includes reference value registers 45A to 45P that hold predicted sample values, metric registers 46A to 46P, subtractors 47A to 47P, and multipliers 48A to 48P.
This first metric generator 22, equalized signal u _n obtained through the waveform equalizer 21 in FIG. 10 are input, it is supplied to the subtracters 47A～47P.

The reference value register 45A stores a reference level ra ₀₀₀₀₀ corresponding to the data string 00000.
The reference value register 45B stores a reference level ra ₀₀₀₀₁ corresponding to the data string 00001.
The reference value register 45C stores a reference level ra ₀₀₀₁₁ corresponding to the data string 0101.
The reference value register 45D stores a reference level ra ₁₀₀₀₀ corresponding to the data string 10000.
The reference value register 45E stores a reference level ra ₁₀₀₀₁ corresponding to the data string 10001.
The reference value register 45F stores a reference level ra ₁₀₀₁₁ corresponding to the data string 10011.
The reference value register 45G stores a reference level ra ₀₀₁₁₀ corresponding to the data string 00110.
The reference value register 45H stores a reference level ra ₀₀₁₁₁ corresponding to the data string 00111.
The reference value register 45I stores a reference level ra ₁₁₀₀₀ corresponding to the data string 11000.
The reference value register 45J stores a reference level ra ₁₁₀₀₁ corresponding to the data string 11001.
The reference value register 45K stores a reference level ra ₀₁₁₀₀ corresponding to the data string 01100.
The reference value register 45L stores a reference level ra ₀₁₁₁₀ corresponding to the data string 01110.
The reference value register 45M stores a reference level ra ₀₁₁₁₁ corresponding to the data string 01111.
The reference value register 45N stores a reference level ra ₁₁₁₀₀ corresponding to the data string 11100.
The reference value register 45O stores a reference level ra ₁₁₁₁₀ corresponding to the data string 11110.
The reference value register 45P stores a reference level ra ₁₁₁₁₁ corresponding to the data string 11111.
Here, since the partial response class is PR (1, 2, 2, 2, 1), the original bit value is ± 1/2, and each reference level is
ra ₀₀₀₀₀ = -4,
ra ₀₀₀₀₁ = -3,
ra ₀₀₀₁₁ = -1,
ra ₁₀₀₀₀ = -3,
ra ₁₀₀₀₁ = -2,
ra ₁₀₀₁₁ = 0,
ra ₀₀₁₁₀ = 0,
ra ₀₀₁₁₁ = + 1
ra ₁₁₀₀₀ = -1,
ra ₁₁₀₀₁ = 0,
ra ₀₁₁₀₀ = 0
ra ₀₁₁₁₀ = +2,
ra ₀₁₁₁₁ = +3,
ra ₁₁₁₀₀ = +1,
ra ₁₁₁₁₀ = +3,
ra ₁₁₁₁₁ = +4,
It becomes.

Reference value register 45A to metric register 46A,
The reference value register 45B to the metric register 46B,
The reference value register 45C to the metric register 46C,
The reference value register 45D to the metric register 46D,
Reference value register 45E to metric register 46E,
Reference value register 45F to metric register 46F,
Reference value register 45G to metric register 46G,
Reference value register 45H to metric register 46H,
Reference value register 45I to metric register 46I,
The reference value register 45J to the metric register 46J,
Reference value register 45K to metric register 46K,
Reference value register 45L to metric register 46L,
Reference value register 45M to metric register 46M,
Reference value register 45N to metric register 46N,
Reference value register 45O to metric register 46O,
The reference value register 45P to the metric register 46P,
In each process, a subtracter (47A to 47P) and a multiplier (48A to 48P) are prepared.

Reference levels of the reference value registers 45A to 45P (ra ₀₀₀₀₀ , ra ₀₀₀₀₁ , ra ₀₀₀₁₁ , ra ₁₀₀₀₀ , ra ₁₀₀₀₁ , ra ₁₀₀₁₁ , ra ₀₀₁₁₀ , ra ₀₀₁₁₁ , ra ₁₁₀₀₀ , ra ₁₁₀₀₁ , ra ₀₁₁₀₀ , ra ₀₁₁₁₀ , ra ₀₁₁₁₁ , ra _11100, ra _11110, ra ₁₁₁₁₁₎ is supplied to each of subtractors 47A～47P, respectively referenced in the subtracters 47A～47P, the equalized signal u _n input, obtained from each reference value register 45A~45P Output level error.
The error signals output from the subtractors 47A to 47P are supplied to multipliers 48A to 48P, and the multipliers 48A to 48P output a signal obtained by squaring the input error signal. An absolute value calculator may be provided in place of the multiplier.

The outputs of the multipliers 48A to 48P are supplied to the metric registers 46A to 46P and held as calculated metrics.
That is, the metric registers 46A, metric ma ₀₀₀₀₀ is stored between the reference level ra ₀₀₀₀₀ and equalized signal _{u n (ma 00000 = (u} n -ra 00000) 2).
The metric register 46B, metrics ma ₀₀₀₀₁ between the reference level ra ₀₀₀₀₁ and equalized signal u _n is stored _{(ma 00001 = (u n -ra} 00001) 2).
The metric register 46C, metrics ma ₀₀₀₁₁ between the reference level ra ₀₀₀₁₁ and equalized signal u _n is stored _{(ma 00011 = (u n -ra} 00011) 2).
The metric register 46D, metrics ma ₁₀₀₀₀ between the reference level ra ₁₀₀₀₀ and equalized signal u _n is stored _{(ma 10000 = (u n -ra} 10000) 2).
The metric register 46E, metrics ma ₁₀₀₀₁ between the reference level ra ₁₀₀₀₁ and equalized signal u _n is stored _{(ma 10001 = (u n -ra} 10001) 2).
The metric register 46F, metrics ma ₁₀₀₁₁ between the reference level ra ₁₀₀₁₁ and equalized signal u _n is stored _{(ma 10011 = (u n -ra} 10011) 2).
The metric register 46G, metrics ma ₀₀₁₁₀ between the reference level ra ₀₀₁₁₀ and equalized signal u _n is stored _{(ma 00110 = (u n -ra} 00110) 2).
The metric register 46H, metrics ma ₀₀₁₁₁ between the reference level ra ₀₀₁₁₁ and equalized signal u _n is stored _{(ma 00111 = (u n -ra} 00111) 2).
The metric register 46I, metrics ma ₁₁₀₀₀ between the reference level ra ₁₁₀₀₀ and equalized signal u _n is stored _{(ma 11000 = (u n -ra} 11000) 2).
The metric register 46 J, metrics ma ₁₁₀₀₁ between the reference level ra ₁₁₀₀₁ and equalized signal u _n is stored _{(ma 11001 = (u n -ra} 11001) 2).
The metric register 46K, metrics ma ₀₁₁₀₀ between the reference level ra ₀₁₁₀₀ and equalized signal u _n is stored _{(ma 01100 = (u n -ra} 01100) 2).
The metric register 46L, metrics ma ₀₁₁₁₀ between the reference level ra ₀₁₁₁₀ and equalized signal u _n is stored _{(ma 01110 = (u n -ra} 01110) 2).
The metric register 46M, metrics ma ₀₁₁₁₁ between the reference level ra ₀₁₁₁₁ and equalized signal u _n is stored _{(ma 01111 = (u n -ra} 01111) 2).
The metric register 46N, metrics ma ₁₁₁₀₀ between the reference level ra ₁₁₁₀₀ and equalized signal u _n is stored _{(ma 11100 = (u n -ra} 11100) 2).
The metric registers 46o, metrics ma ₁₁₁₁₀ between the reference level ra ₁₁₁₁₀ and equalized signal u _n is stored _{(ma 11110 = (u n -ra} 11110) 2).
The metric register 46P, metrics ma ₁₁₁₁₁ between the reference level ra ₁₁₁₁₁ and equalized signal u _n is stored _{(ma 11111 = (u n -ra} 11111) 2).

  The first metric generator 22 calculates the first metric with the above configuration, and outputs the values stored in the metric registers 46A to 46P for each channel bit clock.

FIG. 12 shows the configuration of the second metric generator 24 of FIG.
The second metric generator 24 includes reference value registers 55A to 55P that hold predicted sample values, metric registers 56A to 56P, subtractors 57A to 57P, and multipliers 58A to 58P. .
This second metric generator 24, equalized signal v _n obtained through the waveform equalizer 23 in FIG. 10 are input, it is supplied to the subtracters 57A～57P.

The reference value register 55A stores a reference level rb ₀₀₀₀₀ corresponding to the data string 00000.
The reference value register 55B stores a reference level rb ₀₀₀₀₁ corresponding to the data string 00001.
The reference value register 55C stores a reference level rb ₀₀₀₁₁ corresponding to the data string 0101.
The reference value register 55D stores a reference level rb ₁₀₀₀₀ corresponding to the data string 10000.
The reference value register 55E stores a reference level rb ₁₀₀₀₁ corresponding to the data string 10001.
The reference value register 55F stores a reference level rb ₁₀₀₁₁ corresponding to the data string 10011.
The reference value register 55G stores a reference level rb ₀₀₁₁₀ corresponding to the data string 00110.
The reference value register 55H stores a reference level rb ₀₀₁₁₁ corresponding to the data string 00111.
The reference value register 55I stores a reference level rb ₁₁₀₀₀ corresponding to the data string 11000.
The reference value register 55J stores a reference level rb ₁₁₀₀₁ corresponding to the data string 11001.
The reference value register 55K stores a reference level rb ₀₁₁₀₀ corresponding to the data string 01100.
The reference value register 55L stores a reference level rb ₀₁₁₁₀ corresponding to the data string 01110.
The reference value register 55M stores a reference level rb ₀₁₁₁₁ corresponding to the data string 01111.
The reference value register 55N stores a reference level rb ₁₁₁₀₀ corresponding to the data string 11100.
The reference value register 55O stores a reference level rb ₁₁₁₁₀ corresponding to the data string 11110.
The reference value register 55P stores a reference level rb ₁₁₁₁₁ corresponding to the data string 11111.
Here, since the partial response class is PR (1, 2, 2, 2, 1), the original bit value is ± 1/2, and each reference level is
rb ₀₀₀₀₀ = 0,
rb ₀₀₀₀₁ = -1,
rb ₀₀₀₁₁ = -1,
rb ₁₀₀₀₀ = 1,
rb ₁₀₀₀₁ = 0,
rb ₁₀₀₁₁ = 0,
rb ₀₀₁₁₀ = 0,
rb ₀₀₁₁₁ = -1,
rb ₁₁₀₀₀ = + 1,
rb ₁₁₀₀₁ = 0,
rb ₀₁₁₀₀ = 0,
rb ₀₁₁₁₀ = 0,
rb ₀₁₁₁₁ = -1,
rb ₁₁₁₀₀ = + 1,
rb ₁₁₁₁₀ = + 1
rb ₁₁₁₁₁ = 0,
It becomes.

The reference value register 55A to the metric register 56A,
The reference value register 55B to the metric register 56B,
The reference value register 55C to the metric register 56C,
A reference value register 55D to a metric register 56D,
The reference value register 55E to the metric register 56E,
The reference value register 55F to the metric register 56F,
The reference value register 55G to the metric register 56G,
Reference value register 55H to metric register 56H,
The reference value register 55I to the metric register 56I,
The reference value register 55J to the metric register 56J,
The reference value register 55K to the metric register 56K,
The reference value register 55L to the metric register 56L,
The reference value register 55M to the metric register 56M,
A reference value register 55N to a metric register 56N,
Reference value register 55O to metric register 56O,
The reference value register 55P to the metric register 56P,
In each of the processes, one subtracter (57A to 57P) and one multiplier (58A to 58P) are prepared.

Reference levels (RB ₀₀₀₀₀ , rb ₀₀₀₀₁ , rb ₀₀₀₁₁ , rb ₁₀₀₀₀ , rb ₁₀₀₀₁ , rb ₁₀₀₁₁ , rb ₀₀₁₁₀ , rb ₀₀₁₁₁ , rb ₁₁₀₀₀ , rb ₁₁₀₀₁ , rb ₀₁₁₀₀ , rb ₀₁₁₁₀ , rb ₀₁₁₁₁ , rb _11100, rb _11110, rb ₁₁₁₁₁₎ is supplied to each of subtractors 57A～57P, respectively in the subtracters 57A～57P, the equalized signal v _n input, reference obtained from each reference value register 55A~55P Output level error.
The error signals output from the subtracters 57A to 57P are supplied to multipliers 58A to 58P, and the multipliers 58A to 58P output a signal obtained by squaring the input error signal. An absolute value calculator may be provided in place of the multiplier.

The outputs of the multipliers 58A to 58P are supplied to the metric registers 56A to 56P and held as calculated metrics.
That is, the metric registers 56A, metric mb ₀₀₀₀₀ between the reference level rb ₀₀₀₀₀ and equalized signal v _n are stored _{(mb 00000 = (v n -rb} 00000) 2).
The metric register 56B, metric mb ₀₀₀₀₁ between the reference level rb ₀₀₀₀₁ and equalized signal v _n are stored _{(mb 00001 = (v n -rb} 00001) 2).
The metric register 56C stores a metric mb ₀₀₀₁₁ between the equalized signal v _n and the reference level rb ₀₀₀₁₁ (mb ₀₀₀₁₁ = (v _n −rb ₀₀₀₁₁ ) ² ).
The metric register 56D, metric mb ₁₀₀₀₀ between the reference level rb ₁₀₀₀₀ and equalized signal v _n are stored _{(mb 10000 = (v n -rb} 10000) 2).
The metric register 56E, metric mb ₁₀₀₀₁ between the reference level rb ₁₀₀₀₁ and equalized signal v _n are stored _{(mb 10001 = (v n -rb} 10001) 2).
The metric register 56F stores a metric mb ₁₀₀₁₁ between the equalized signal v _n and the reference level rb ₁₀₀₁₁ (mb ₁₀₀₁₁ = (v _n −rb ₁₀₀₁₁ ) ² ).
The metric register 56G, metric mb ₀₀₁₁₀ between the reference level rb ₀₀₁₁₀ and equalized signal v _n are stored _{(mb 00110 = (v n -rb} 00110) 2).
The metric register 56H, metric mb ₀₀₁₁₁ between the reference level rb ₀₀₁₁₁ and equalized signal v _n are stored _{(mb 00111 = (v n -rb} 00111) 2).
The metric register 56I stores a metric mb ₁₁₀₀₀ between the equalized signal v _n and the reference level rb ₁₁₀₀₀ (mb ₁₁₀₀₀ = (v _n −rb ₁₁₀₀₀ ) ² ).
The metric register 56J, metric mb ₁₁₀₀₁ between the reference level rb ₁₁₀₀₁ and equalized signal v _n are stored _{(mb 11001 = (v n -rb} 11001) 2).
The metric register 56K, metric mb ₀₁₁₀₀ between the reference level rb ₀₁₁₀₀ and equalized signal v _n are stored _{(mb 01100 = (v n -rb} 01100) 2).
The metric register 56L, metric mb ₀₁₁₁₀ between the reference level rb ₀₁₁₁₀ and equalized signal v _n are stored _{(mb 01110 = (v n -rb} 01110) 2).
The metric register 56M, metric mb ₀₁₁₁₁ between the reference level rb ₀₁₁₁₁ and equalized signal v _n are stored _{(mb 01111 = (v n -rb} 01111) 2).
The metric register 56N stores a metric mb ₁₁₁₀₀ between the equalized signal v _n and the reference level rb ₁₁₁₀₀ (mb ₁₁₁₀₀ = (v _n −rb ₁₁₁₀₀ ) ² ).
The metric register 56O stores a metric mb ₁₁₁₁₀ between the equalized signal v _n and the reference level rb ₁₁₁₁₀ (mb ₁₁₁₁₀ = (v _n −rb ₁₁₁₁₀ ) ² ).
The metric register 56P stores a metric mb ₁₁₁₁₁ between the equalized signal v _n and the reference level rb ₁₁₁₁₁ (mb ₁₁₁₁₁ = (v _n −rb ₁₁₁₁₁ ) ² ).

  The second metric generator 24 calculates the second metric with the above configuration, and outputs the values stored in the metric registers 56A to 56P for each channel bit clock.

FIG. 13 shows the configuration of the third metric generator 25 of FIG.
The third metric generator 25E includes 16 metrics {ma} output from the metric registers 46A to 46P of the first metric generator 22 and 16 output from the metric registers 56A to 56P of the second metric generator 24. 16 metrics {mb} are input, and 16 metrics {m} obtained from the metric registers 62A to 62P are output.

A first metric ma ₀₀₀₀₀ and a second metric mb ₀₀₀₀₀ are input to the metric register 62A, and a third metric m ₀₀₀₀₀ = ma ₀₀₀₀₀ + k * mb ₀₀₀₀₀ is stored with a predetermined constant k as a coefficient.
The metric register 62B receives a first metric ma ₀₀₀₀₁ and a second metric mb _{00001, and} stores a third metric m ₀₀₀₀₁ = ma ₀₀₀₀₁ + k * mb ₀₀₀₀₁ with a predetermined constant k as a coefficient.
The first metric ma ₀₀₀₁₁ and the second metric mb ₀₀₀₁₁ are input to the metric register 62C, and a third metric m ₀₀₀₁₁ = ma ₀₀₀₁₁ + k * mb ₀₀₀₁₁ is stored with a predetermined constant k as a coefficient.
A first metric ma ₁₀₀₀₀ and a second metric mb ₁₀₀₀₀ are input to the metric register 62D, and a third metric m ₁₀₀₀₀ = ma ₁₀₀₀₀ + k * mb ₁₀₀₀₀ is stored with a predetermined constant k as a coefficient.
The metric register 62E receives a first metric ma ₁₀₀₀₁ and a second metric mb _{10001, and} stores a third metric m ₁₀₀₀₁ = ma ₁₀₀₀₁ + k * mb ₁₀₀₀₁ with a predetermined constant k as a coefficient.
The metric register 62F receives a first metric ma ₁₀₀₁₁ and a second metric mb _{10011, and} stores a third metric m ₁₀₀₁₁ = ma ₁₀₀₁₁ + k * mb ₁₀₀₁₁ with a predetermined constant k as a coefficient.
The metric register 62G receives a first metric ma ₀₀₁₁₀ and a second metric mb _{00110, and} stores a third metric m ₀₀₁₁₀ = ma ₀₀₁₁₀ + k * mb ₀₀₁₁₀ with a predetermined constant k as a coefficient.
A first metric ma ₀₀₁₁₁ and a second metric mb ₀₀₁₁₁ are input to the metric register 62H, and a third metric m ₀₀₁₁₁ = ma ₀₀₁₁₁ + k * mb ₀₀₁₁₁ is stored with a predetermined constant k as a coefficient.
The metric register 62I receives a first metric ma ₁₁₀₀₀ and a second metric mb _{11000, and} stores a third metric m ₁₁₀₀₀ = ma ₁₁₀₀₀ + k * mb ₁₁₀₀₀ with a predetermined constant k as a coefficient.
The metric register 62J receives the first metric ma ₁₁₀₀₁ and the second metric mb _{11001, and} stores a third metric m ₁₁₀₀₁ = ma ₁₁₀₀₁ + k * mb ₁₁₀₀₁ with a predetermined constant k as a coefficient.
The metric register 62K receives the first metric ma ₀₁₁₀₀ and the second metric mb _{01100, and stores a} third metric m ₀₁₁₀₀ = ma ₀₁₁₀₀ + k * mb ₀₁₁₀₀ with a predetermined constant k as a coefficient.
A first metric ma ₀₁₁₁₀ and a second metric mb ₀₁₁₁₀ are input to the metric register 62L, and a third metric m ₀₁₁₁₀ = ma ₀₁₁₁₀ + k * mb ₀₁₁₁₀ is stored with a predetermined constant k as a coefficient.
A first metric ma ₀₁₁₁₁ and a second metric mb ₀₁₁₁₁ are input to the metric register 62M, and a third metric m ₀₁₁₁₁ = ma ₀₁₁₁₁ + k * mb ₀₁₁₁₁ is stored with a predetermined constant k as a coefficient.
The metric register 62N receives the first metric ma ₁₁₁₀₀ and the second metric mb _{11100, and} stores a third metric m ₁₁₁₀₀ = ma ₁₁₁₀₀ + k * mb ₁₁₁₀₀ with a predetermined constant k as a coefficient.
The metric register 62O receives a first metric ma ₁₁₁₁₀ and a second metric mb _{11110, and} stores a third metric m ₁₁₁₁₀ = ma ₁₁₁₁₀ + k * mb ₁₁₁₁₀ with a predetermined constant k as a coefficient.
The metric register 62P receives a first metric ma ₁₁₁₁₁ and a second metric mb _{11111, and} stores a third metric m ₁₁₁₁₁ = ma ₁₁₁₁₁ + k * mb ₁₁₁₁₁ with a predetermined constant k as a coefficient.

  According to the above configuration, the third metric generator 25 outputs the metric values of the metric registers 62A to 62P for each channel bit clock.

The Viterbi decoder 26 shown in FIG. 10 includes the path metric updater 70 in FIG. 14 and the path memory updater 80 in FIG. 8 described above.
As shown in FIG. 14, the path metric updater 70 in the Viterbi decoder 26 includes path metric registers 75A to 75J, path metric registers 76A to 76J, and flip-flops 77A to 77J.

The path metric register 75A stores the path metric pm ₀₀₀₀ of the surviving path in the state s ₀₀₀₀ . In the path metric register 76A, a smaller value is selected from the path metrics pm ₀₀₀₀₀ = pm ₀₀₀₀ + m ₀₀₀₀₀ and pm ₁₀₀₀₀ = pm ₁₀₀₀ + m ₁₀₀₀₀ for the path leading to the state s ₀₀₀₀ . Here, the metrics m ₀₀₀₀₀ and m ₁₀₀₀₀ for calculating the path metric value are input from the third metric generator 25 described above. The value of the path metric register 76A latched by the flip-flop 77A is stored as the value of the path metric register 75A.
The path metric register 75B stores the path metric pm ₀₀₀₁ of the surviving path in the state s ₀₀₀₁ . In the path metric register 76B, a smaller value is selected from the path metrics pm ₀₀₀₀₁ = pm ₀₀₀₀ + m ₀₀₀₀₁ and pm ₁₀₀₀₁ = pm ₁₀₀₀ + m ₁₀₀₀₁ of the path leading to the state s ₀₀₀₁ . Metrics m ₀₀₀₀₁ and m ₁₀₀₀₁ for calculating a path metric value are input from the third metric generator 25. The value of the path metric register 76B latched by the flip-flop 77B is stored as the value of the path metric register 75B.
The path metric register 75C, the path metric pm ₁₀₀₀ of the survival path in state s ₁₀₀₀ is stored. The path metric register 76C, the path metric pm ₁₁₀₀₀ = pm ₁₁₀₀ + m ₁₁₀₀₀ path leading to the state s ₁₀₀₀ is stored. A metric m ₁₁₀₀₀ for calculating a path metric value is input from the third metric generator 25. The value of the path metric register 76C latched by the flip-flop 77C is stored as the value of the path metric register 75C.
The path metric register 75D stores the path metric pm ₁₀₀₁ of the surviving path in the state s ₁₀₀₁ . The path metric register 76D stores the path metric pm ₁₁₀₀₁ = pm ₁₁₀₀ + m ₁₁₀₀₁ of the path leading to the state s ₁₀₀₁ . A metric m ₁₁₀₀₁ for calculating a path metric value is input from the third metric generator 25. The value of the path metric register 76D latched by the flip-flop 77D is stored as the value of the path metric register 75D.
The path metric register 75E stores the path metric pm ₀₀₁₁ of the surviving path in the state s ₀₀₁₁ . In the path metric register 76E, a smaller value is selected from the path metrics pm ₀₀₀₁₁ = pm ₀₀₀₁ + m ₀₀₀₁₁ and pm ₁₀₀₁₁ = pm ₁₀₀₁ + m ₁₀₀₁₁ of the path leading to the state s ₀₀₁₁ . Metrics m ₀₀₀₁₁ and m ₁₀₀₁₁ for calculating a path metric value are input from the third metric generator 25. The value of the path metric register 76E latched by the flip-flop 77E is stored as the value of the path metric register 75E.
The path metric register 75F stores the path metric pm ₁₁₀₀ of the surviving path in the state s ₁₁₀₀ . In the path metric register 76F, a smaller value is selected from the path metrics pm ₀₁₁₀₀ = pm ₀₁₁₀ + m ₀₁₁₀₀ and pm ₁₁₁₀₀ = pm ₁₁₁₀ + m ₁₁₁₀₀ of the path reaching the state s ₁₁₀₀ . Metrics m ₀₁₁₀₀ and m ₁₁₁₀₀ for calculating a path metric value are input from the third metric generator 25. The value of the path metric register 76F latched by the flip-flop 77F is stored as the value of the path metric register 75F.
The path metric register 75G stores the path metric pm ₀₁₁₀ of the surviving path in the state s ₀₁₁₀ . The path metric register 76G stores the path metric pm ₀₀₁₁₀ = pm ₀₀₁₁ + m ₀₀₁₁₀ of the path to the state s ₀₁₁₀ . A metric m ₀₀₁₁₀ for calculating a path metric value is input from the third metric generator 25. The value of the path metric register 76G latched by the flip-flop 77G is stored as the value of the path metric register 75G.
The path metric register 75H stores the path metric pm ₀₁₁₁ of the surviving path in the state s ₀₁₁₁ . The path metric register 76H stores the path metric pm ₀₀₁₁₁ = pm ₀₀₁₁ + m ₀₀₁₁₁ of the path to the state s ₀₁₁₁ . A metric m ₀₀₁₁₁ for calculating a path metric value is input from the third metric generator 25. The value of the path metric register 76H latched by the flip-flop 77H is stored as the value of the path metric register 75H.
The path metric register 75I stores the path metric pm ₁₁₁₀ of the surviving path in the state s ₁₁₁₀ . In the path metric register 76I, a smaller value is selected from the path metrics pm ₀₁₁₁₀ = pm ₀₁₁₁ + m ₀₁₁₁₀ and pm ₁₁₁₁₀ = pm ₁₁₁₁ + m ₁₁₁₁₀ of the path leading to the state s ₁₁₁₀ . Metrics m ₀₁₁₁₀ and m ₁₁₁₁₀ for calculating a path metric value are input from the third metric generator 25. The value of the path metric register 76I latched by the flip-flop 77I is stored as the value of the path metric register 75I.
The path metric register 75J stores the path metric pm ₁₁₁₁ of the surviving path in the state s ₁₁₁₁ . In the path metric register 76J, a smaller value is selected from the path metrics pm ₀₁₁₁₁ = pm ₀₁₁₁ + m ₀₁₁₁₁ and pm ₁₁₁₁₁ = pm ₁₁₁₁ + m ₁₁₁₁₁ of the path leading to the state s ₁₁₁₁ . Metrics m ₀₁₁₁₁ and m ₁₁₁₁₁ for calculating a path metric value are input from the third metric generator 25. The value of the path metric register 76J latched by the flip-flop 77J is stored as the value of the path metric register 75J.

The Viterbi decoder 26 includes such a path metric updater 70 and the path memory updater 80 described with reference to FIG.
Then, any MSB of the path memory registers 82A to 82J in the path memory updater 80 of FIG. 8 is output to the outside as decoded data. As described above, the decoded bit information is output from the Viterbi decoder 26 to which the third metric is input, and partial response maximum likelihood decoding is realized.

Also in this example, the reference value may be given by a learning table that adaptively feeds back the sampling level according to the decoded data. FIG. 15 shows a configuration example when an adaptation table is prepared.
That is, the bit information output from the Viterbi decoder 26 is supplied to the adaptive level control units 27 and 28.
The adaptive level control units 27 and 28 store the bit string obtained by the Viterbi detection with the length of the constraint length, and classify the sample values of the reproduction signal delayed at the same timing for each stored pattern. In this way, it is possible to successively obtain actual reproduction signal sample values for the reference level value corresponding to each branch.
The adaptive PRML is realized by averaging the actual sample values or sequentially updating the reference level values by low-pass filtering or the like.
The reference level value sequentially updated by the adaptive level control unit 27 is substituted as the reference level value stored in the reference value registers 45A to 45P of the first metric generator 22, and the adaptive level control unit 28 also updates the reference level value. The value of the reference level that has been sequentially updated is substituted as the value of the reference level stored in the reference value registers 55A to 55P of the second metric generator 24.

[4. Summary]

As described above, in a reproduction system for reproducing a recording medium such as an optical disk or a magnetic disk, noise is composed of random system noise and non-random media noise. Therefore, the conventional PRML that exhibits a large effect on random noise does not necessarily exhibit the optimal effect. Therefore, it has become necessary to realize a maximum likelihood decoding method that is effective for non-random noise.
As a method for solving such a problem, a maximum likelihood decoding method using a metric from the differential partial response in addition to the conventional maximum likelihood decoding method using a metric from the partial response has been proposed.
However, since this method complicates the circuit and increases the circuit scale, it has not always been adopted in that an effect corresponding to the difficulty level is not obtained.
Here, when the maximum likelihood decoding apparatus according to the above-described embodiment is used, it is possible to remove the increase in the constraint length, which is the biggest problem that complicates the circuit and increases the circuit scale in the conventional method.
Therefore, according to this embodiment, it is possible to provide a maximum likelihood decoding method that is effective for non-random noise without complicating the circuit and greatly increasing the circuit scale.
Note that the maximum likelihood decoding method and the maximum likelihood decoding apparatus of the present invention as typified by the above embodiments have not only the optical disc but also a magnetic disc such as an HDD and the frequency characteristics of the noise as the frequency characteristics of the channel. It can be used generally for all systems.

It is a block diagram of the reproducing | regenerating apparatus which has the maximum likelihood decoding apparatus of embodiment of this invention. It is a block diagram of the maximum likelihood decoding apparatus of target response PR (1, 2, 2, 1) of 1st Embodiment. It is a block diagram of the waveform equalizer of the maximum likelihood decoding apparatus of 1st, 2nd embodiment. It is a block diagram of the 1st metric generator of a 1st embodiment. It is a block diagram of the 2nd metric generator of a 1st embodiment. It is a block diagram of the 3rd metric generator of a 1st embodiment. It is a block diagram of the path metric updater of a 1st embodiment. It is a block diagram of a path memory updater according to the first and second embodiments. It is a block diagram at the time of using together adaptive PRML in 1st Embodiment. It is a block diagram of the maximum likelihood decoding apparatus of target response PR (1, 2, 2, 2, 1) of 2nd Embodiment. It is a block diagram of the 1st metric generator of a 2nd embodiment. It is a block diagram of the 2nd metric generator of a 2nd embodiment. It is a block diagram of the 3rd metric generator of a 2nd embodiment. It is a block diagram of the path metric updater of a 2nd embodiment. It is a block diagram at the time of using adaptive PRML together in 2nd Embodiment. It is explanatory drawing of the frequency characteristic c0 ((omega)) of the partial response target PR (1221), and the frequency characteristic c1 ((omega)) of the differential target PR (110-1-1). It is explanatory drawing of the frequency characteristic of c0 ((omega)) + c1 ((omega)), and the frequency characteristic of (root) (c0 ((omega)) < ² > + c1 ((omega)) ² ).

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Recording medium, 4 Maximum likelihood decoding apparatus, 11, 13, 21, 23 Waveform equalizer, 12, 22 1st metric generator, 14, 24 2nd metric generator, 15, 25 3rd metric generator, 16 , 26 Viterbi decoder

Claims (8)

A maximum likelihood decoding method for detecting bit information from a reproduction signal acquired from a recording medium or a transmission medium,
A waveform equalization process is performed on the reproduction signal, and a first waveform equalization step for obtaining a first partial response signal;
A waveform equalization process is performed on the reproduction signal, and a second waveform equalization step for obtaining a second partial response signal having a frequency characteristic different from that of the first partial response signal;
A first metric generation step for generating a metric for the first partial response signal;
A second metric generation step for generating a metric for the second partial response signal;
A maximum likelihood decoding step for performing maximum likelihood decoding using the metric from the first metric generation step and the metric from the second metric generation step;
With
The first and second partial response signals by the first and second waveform equalization steps are:
At the frequency at which the channel transfer function is 0, both signal amplitudes are 0,
At half the frequency of the channel clock, both signal amplitudes are 0,
At a frequency of 0, the first partial response signal has a signal amplitude that is not 0, and the second partial response signal has a signal amplitude of 0,
A maximum likelihood decoding method, wherein the partial lengths of the partial responses of the first and second waveform equalization steps are equal. The partial response of the first waveform equalization step is PR (1, 2, 2, 1),
2. The maximum likelihood decoding method according to claim 1, wherein the partial response of the second waveform equalization step is PR (1, 0, 0, −1). The partial response of the first waveform equalization step is PR (1, 2, 2, 2, 1),
2. The maximum likelihood decoding method according to claim 1, wherein the partial response of the second waveform equalization step is PR (1, 0, 0, 0, −1). For n-1 constants a (k), where n is the constraint length,
The kth value of the first partial response in the first waveform equalization step is a (k) + a (k−1),
2. The maximum likelihood decoding method according to claim 1, wherein the kth value of the second partial response in the second waveform equalization step is a (k) -a (k-1). A maximum likelihood decoding device for detecting bit information from a reproduction signal acquired from a recording medium or a transmission medium,
First waveform equalization means for performing waveform equalization processing on the reproduction signal and obtaining a first partial response signal;
Waveform equalization processing is performed on the reproduction signal, and second waveform equalization means for obtaining a second partial response signal having a frequency characteristic different from that of the first partial response signal;
First metric generation means for generating a metric for the first partial response signal;
Second metric generation means for generating a metric for the second partial response signal;
Maximum likelihood decoding means for performing maximum likelihood decoding using the metric by the first metric generation means and the metric by the second metric generation means;
With
The first and second partial response signals by the first and second waveform equalization means are:
At the frequency at which the channel transfer function is 0, both signal amplitudes are 0,
At half the frequency of the channel clock, both signal amplitudes are 0,
At a frequency of 0, the first partial response signal has a signal amplitude that is not 0, and the second partial response signal has a signal amplitude of 0,
A maximum likelihood decoding apparatus, wherein the partial lengths of the partial responses of the first and second waveform equalization means are equal. The partial response of the first waveform equalization means is PR (1, 2, 2, 1),
6. The maximum likelihood decoding apparatus according to claim 5, wherein the partial response of the second waveform equalization means is PR (1, 0, 0, −1). The partial response of the first waveform equalization means is PR (1, 2, 2, 2, 1),
6. The maximum likelihood decoding apparatus according to claim 5, wherein the partial response of the second waveform equalizing means is PR (1, 0, 0, 0, −1). For n-1 constants a (k), where n is the constraint length,
The kth value of the first partial response in the first waveform equalization means is a (k) + a (k−1),
6. The maximum likelihood decoding apparatus according to claim 5, wherein the kth value of the second partial response in the second waveform equalization means is a (k) -a (k-1).

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