JP2006121029A - Solid electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that control of big current with low driving voltage is difficult, since the electric charge which can be induced at a gate insulating film with the insulation breakdown voltage of an MOSFET is restricted conventionally in the MOSFET that uses SiO<SB>2</SB>as the gate insulation film, for example. <P>SOLUTION: This solid electronic apparatus has a gate electrode 3 to which control voltage is applied, a source electrode 4, and a drain electrode 5 where a conducting state is controlled by the control voltage. The solid-state electronic apparatus is provided with a channel layer 1, which generates a channel between the source electrode and the drain electrode, and the gate insulating film 2 provided in between the gate electrode and the channel layer, and which consists of dielectric material where an equivalent specific inductive capacity is large. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a solid-state electronic device, and more particularly to a solid-state electronic device that enables a large current control using a dielectric material having a large relative dielectric constant equivalent to a gate insulating film.

FIG. 1 is a diagram schematically showing an example of a conventional solid-state electronic device, and shows a general n-channel MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor). In FIG. 1, reference numeral 101 is a p-type silicon wafer (channel layer), 111 is an n ⁺ source region, 112 is an n ⁺ drain region, 113 is a channel, 102 is a gate insulating film, 103 is a gate electrode, and 104 is a source electrode. Reference numeral 105 denotes a drain electrode.

As shown in FIG. 1, the conventional transistor (MOSFET) uses a silicon oxide film (silicon dioxide: SiO ₂ ) as the gate insulating film 102 and has a source when a positive voltage is applied to the gate electrode 103. A semiconductor (oxide conductor) such as silicon is used as the channel layer 101 for generating and conducting a channel (electrons) 113 between the electrode 104 and the drain electrode 105.

  For example, silicon used as the channel layer 101 of the MOSFET has a limit on the number of carriers, and the current that can be controlled is naturally limited. Further, in order to flow a large current between the source electrode 104 and the drain electrode 105, it is necessary to apply a high voltage to the gate electrode 103. However, a large current is allowed to flow by being limited by the withstand voltage of the gate insulating film 102. Can not. However, as a future integrated circuit element, as a solid-state electronic device that realizes a finer and faster switching operation, it is important how large charges can be controlled at high speed.

  Conventionally, a semiconductor device comprising a transparent switching element having two connection electrodes of a transparent material and an intervening transparent channel region of a semiconductor material provided with a transparent gate electrode of a conductive material separated from the channel region by a transparent insulating layer Has been proposed (see, for example, Patent Document 1).

  In addition, conventionally, a transparent material such as glass, sapphire, or plastic is used as a substrate, and zinc oxide (ZnO) is used as a transparent channel layer, and an element capable of taking a monovalent valence as a gate insulating layer Alternatively, a transparent transistor using a transparent insulating material such as insulating ZnO doped with a group V element has also been proposed (see, for example, Patent Document 2).

Further, a ferroelectric transparent thin film transistor using PZT [Pb (Zr _X , Ti _1-X ) O ₃ ] as a gate insulating film and tin oxide (SnO ₂ : Sb) as a channel layer has been proposed. (For example, refer nonpatent literature 1).

Conventionally, a ferroelectric field effect transistor having an SRTO [SrRu _X Ti _1-X O ₃ ] channel has also been proposed (see, for example, Non-Patent Document 2). Furthermore, conventionally, even _{Ag / PLZT [Pb 1-Y} La y (Zr X Ti 1-Z) 1-Y / 4 O 3] / LSCO [La X Sr 1-X CuO 4] ferroelectric field effect transistor proposed (For example, see Non-Patent Document 3).

Japanese National Patent Publication No. 11-505377 JP 2000-150900 A Published by N.W. Prins et al, “A Ferroelectric Transparent Thin-Film Transistor”, APPl. Phys. Lett. 68 (25), June 17, 1996. AG Schrott et al., "Ferroelectric Field Effect Transistor with a SrRuXTi1-XO3 Channel", VOL.82, NO.26, 2003 Published June 30, IV Grekhov et al, “Strongly Modulated Conductance in Ag / PLZT / LSCO Ferroelectric Field Effect Transistor”, Ioffe Published by Institute, Russia, 2001

As described above, the conventional MOSFET (thin film transistor), for example, to use the oxide conductor such as ZnO as a channel layer 101, the mobility of charge in the channel is small, furthermore, Si0 ₂ or the like as the gate insulating film 102 Since a relatively thick paraelectric film is used, the on-state current of the transistor (solid-state electronic device) is small. Specifically, the charge density which can be induced in the gate insulating film of Si0 ₂ is limited to 3.5μC / cm ² by the dielectric strength (10MV / cm).

By the way, in recent years, a transistor using a high dielectric constant material (high-K) as a gate insulating film has also been proposed. However, since such a transistor has a low withstand voltage (dielectric withstand voltage deterioration), the charge that can be controlled is reduced. density, for example, about 5.0μC / cm ^2, it does not become large dramatically compared to transistor using Si0 ₂ gate insulating film. This limit can also be applied to the above-described silicon (Si) MOSFET, and is an important factor in determining the limit value of the on-current of the transistor.

  Further, various transistors using a ferroelectric material have been proposed in the past, but a large current was not controlled with a low driving voltage. That is, a conventional transistor using a ferroelectric material is not based on the idea of controlling a huge charge amount by using a large charge amount of the ferroelectric material.

  An object of the present invention is to provide a solid-state electronic device capable of controlling a large current with a low driving voltage in view of the above-described problems of the related art.

  According to a first aspect of the present invention, there is provided a solid-state electronic device having a gate electrode to which a control voltage is applied, and a source electrode and a drain electrode whose conduction state is controlled by the control voltage, the source electrode and A channel layer that generates a channel between the drain electrodes, and a gate insulating film that is provided between the gate electrode and the channel layer and is made of a dielectric material having a large equivalent relative dielectric constant. A featured solid state electronic device is provided.

  According to a second aspect of the present invention, there is provided a solid-state electronic device having a gate electrode to which a control voltage is applied, and a source electrode and a drain electrode whose conduction state is controlled by the control voltage, the source electrode and A channel layer formed of indium tin oxide [ITO] that generates a channel between the drain electrodes, and a dielectric material having a large equivalent relative dielectric constant provided between the gate electrode and the channel layer A solid-state electronic device is provided.

  According to the present invention, a solid-state electronic device capable of controlling a large current with a low driving voltage can be provided.

The solid-state electronic device according to the present invention uses an oxide conductive material having a high carrier concentration for the channel layer and a ferroelectric having a large relative dielectric constant equivalent to the gate insulating film as a control of the channel layer for amplification. Use body material. As a result, the number of carriers that can be controlled is greatly increased as compared with a solid-state electronic device that uses a conventional semiconductor as a channel layer, so that a large current can be controlled with a driving voltage that is much lower than in the conventional case. This leads to the realization of a solid-state electronic device capable of a finer and faster switching operation as a future integrated circuit element.
Hereinafter, embodiments of a solid-state electronic device according to the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 2 is a diagram schematically showing a configuration of an embodiment of a solid-state electronic device according to the present invention. In FIG. 2, reference numeral 1 is a channel layer, 2 is a gate insulating film, 3 is a gate electrode, 4 is a source electrode, and 5 is a drain electrode.

  The solid-state electronic device (transistor) of the present embodiment shown in FIG. 2 uses a dielectric material having a large equivalent relative dielectric constant as the gate insulating film 2, and oxide conductivity having a high carrier concentration as the channel layer 1. Use materials.

Here, as the ferroelectric material is greater equivalent dielectric constant to be used as the gate insulating film 2, for _{example, PZT (Pb (Zr X,} Ti 1-X) O 3], BLT [Bi 4-X La _X Ti ₃ O ₁₂ ], SBT [SrBi ₂ Ta ₂ O ₉ ] or BIT [Bi ₄ Ti ₃ O ₁₂ ], and a paraelectric material (high dielectric constant) used as the gate insulating film 2 having a large relative dielectric constant. For example, BST [Ba _X Sr _1-X TiO ₃ ] is used as the body material) When a ferroelectric material is used as the gate insulating film 2, a data holding function is provided by the hysteresis characteristics of the ferroelectric material. Further, in order to use a ferroelectric material as the gate insulating film 2 as a simple switching element, a voltage level control signal (ON or OFF) corresponding to the hysteresis characteristic of the ferroelectric material is used. Transition state Different gate voltages of the level) is required of order.

Examples of the oxide conductive material having a high carrier concentration used as the channel layer 1 include indium tin oxide [ITO], LSCO [La _x Sr _1-x CuO ₄ ], tin oxide [SnO ₂ ], and oxidation. There is zinc [ZnO] or indium oxide [In ₂ O ₃ ]. In addition, since ITO etc. used as a channel layer have optical transparency (transparency), the property of this transparent channel layer can also be utilized positively.

And according to the solid-state electronic device of a present Example, it becomes possible to control a big electric current with a low drive voltage.
FIG. 3 is a diagram showing PE characteristics (PE hysteresis characteristics) for explaining the solid-state electronic device shown in FIG. 2 in comparison with a conventional solid-state electronic device.

As shown in characteristic curve L11 of FIG. 3, the Si0 ₂ in the relative dielectric constant that is used as a gate insulating film of the conventional transistor (MOSFET) as small as 3.9 (εr = 3.9), 3, There is almost no difference from the X axis. As described above, the charge density can be induced in the Si0 _2, the breakdown voltage (10 MV / cm: In Figure 3, an electric field of up to 1.5 MV / cm only not plotted) by the 3.5μC / cm ² Limited.

Further, as for hafnia (HfO ₂ : hafnium oxide) which has been attracting attention as a high dielectric constant gate insulating film in place of SiO ₂ in recent years, for example, the relative dielectric constant of HfO ₂ is 20 (εr = 20). as shown in the third characteristic curve L12, in FIG. 3, it is only expressed slightly larger than the Si0 ₂ characteristic curve L11. The characteristic curve L13 in FIG. 3 is drawn assuming a substance having a relative dielectric constant of 100 (εr = 100).

On the other hand, in the case of a ferroelectric material (specifically, PZT) used as the gate insulating film 2 in the solid-state electronic device according to the present embodiment, for example, only an electric field of 0.5 MV / cm is applied. It can be seen that a charge density greater than about 50 μC / cm ² can be obtained.

Therefore, for example, by using ITO as the channel layer 1, the carrier concentration is 10 ²¹ cm ^-3 , the mobility is 50 cm ² / V · s, and the n-type having a large band gap (3.75 eV). A semiconductor (solid-state electronic device) can be configured. Needless to say, a p-type semiconductor can be configured similarly.

  4 is a diagram for explaining the operation principle of the solid-state electronic device shown in FIG. 2, and FIG. 4 (a) shows a state in which a positive voltage is applied to the gate electrode 3 to make it conductive (ON). FIG. 4B shows a state in which a negative voltage is applied to the gate electrode 3 to cut off (off) it.

As shown in FIG. 4A, when a positive voltage is applied to the gate electrode 3, a large electric field is applied to the channel layer 1 made of, for example, ITO via the gate insulating film 2 made of, for example, PZT. And carriers (electrons) are accumulated (see reference numeral 1a). As a result, a current I _D flows from the drain electrode 5 to the source electrode 4 (I _D > 0: ON state).
At this time, even if the voltage applied to the gate electrode 3 is zero, the on-state is maintained by the residual polarization of PZT (ferroelectric material), and the data holding function is provided.

Next, as shown in FIG. 4B, when a negative voltage is applied to the gate electrode 3, a reverse electric field is applied to the channel layer (ITO) 1 through the gate insulating film (PZT) 2. The channel layer is depleted (see symbol 1b). As a result, conduction between the drain electrode 5 and the source electrode 4 is interrupted (I _D ≈0: off state).

FIG. 5 is a diagram for explaining conditions required for the solid-state electronic device shown in FIG. Here, the elementary charge amount is q (1.602 × 10 ⁻¹⁹ coulomb), the voltage applied to the gate electrode 3 is V _G , and the charge density due to the ferroelectric material (gate insulating film 2) is P (V _G ). , Channel layer (ITO) 1 thickness d, carrier concentration N _D , vacuum dielectric constant ε ₀ , ferroelectric material relative dielectric constant ε _S , potential of channel Fermi level and intrinsic Fermi level The difference is φ _B and the carrier concentration of the channel layer 1 is N _D. As described above, the ferroelectric material used as the gate insulating film 2 may be a paraelectric material having a large relative dielectric constant.

First, since the gate insulating film 2 needs to control carriers in the carrier layer 1, the carrier concentration N _D of the channel layer 1 needs to satisfy the following conditional expression [1].
N _D <{P (V _G )} / (qd) (1)

Furthermore, since the thickness d of the carrier layer 1 needs to be smaller than the maximum depletion region width W _m , the thickness d of the carrier layer 1 needs to satisfy the following conditional expression [A].
d <W _m ...... [A]
The maximum depletion region width W _m is represented by the following formula [B].
W _m = {(4ε ₀ ε _S φ _B ) / (qN _D )} ^1/2 ...... [B]

When the condition of the carrier concentration N _{D is obtained} from the above equations [A] and [B], the following conditional equation [2] is obtained.
N _D <(4ε ₀ ε _S φ _B ) / qd ² ...... [2]
Therefore, the carrier concentration N _D needs to satisfy the above conditional expressions [1] and [2] simultaneously.

In FIG. 5, a curve L21 indicates conditional expression [1], and a curve L22 indicates conditional expression [2]. Since the carrier concentration N _D needs to satisfy the conditional expressions [1] and [2] at the same time, it must be included in the common region of the lower region of the curve L21 and the lower region of the curve L22. In the case of FIG. 5, since the lower region of the curve L21 (conditional expression [1]) is also satisfied as long as it is the region that satisfies the conditional expression [2], the lower region of the curve L22 (conditional expression [1]) is also satisfied. The lower region of the curve L22 is sufficient.

Here, the large current flows, the channel layer (ITO) 1 as a solid-state electronic device which is in an appropriate thickness, for example, a thickness d of about 8nm channel layer 1, a carrier concentration N _D of about 1 × The condition of 10 ¹⁹ cm ⁻³ (region P in FIG. 5) may be satisfied. Specifically, the charge density Pr of the ferroelectric material used as the gate insulating film 2 is 15 μC / cm ² , and φ _B of the channel layer (ITO) is E _g /2q=1.875 V, E _g = 3.75 eV, A solid-state electronic device can be configured with a relative dielectric constant ε _S of 4.

Here, as the solid-state electronic device according to the present invention, the charge density of the gate insulating film 2 is larger than, for example, 10 μC / cm ² , and the carrier concentration of the channel layer 1 is, for example, 1 × 10 ¹⁸ cm ^−3. Higher than that.

Thus, according to the solid-state electronic device of the present embodiment, by using a dielectric material (for example, a ferroelectric material such as PZT or BLT) that can induce a large amount of charge even at a low voltage, for the gate insulating film. , for example, it is possible to control the amount of charge of more than 10 times in 1/100 of an applied electric field of conventional transistor using Si0 ₂ gate insulating film (MOSFET).

  FIG. 6 is a diagram for schematically explaining the process of experimentally producing the solid-state electronic device shown in FIG. Note that BLT (and PZT) was used as the gate insulating film, and ITO was used as the channel layer.

First, as shown in FIG. 6A, a gate electrode (Pt (40 nm) / Ti (10 nm)) is vacuum-deposited on an SiO ₂ / Si substrate 6 using, for example, an E-gun vapor deposition apparatus. Bottom gate) 3 was formed, and as shown in FIG. 6B, a BLT (or PZT) gate insulating film 2 was formed by a sol-gel method. Here, BLT (Bi _3.35 La _0.75 Ti ₃ O ₁₂ ) was formed by a sol-gel method, for example, at a temperature of 750 ° C. for 30 minutes and a thickness of 200 nm. PZT (Pb _1.2 Zr _0.4 Ti _0.6 O ₃ ) was formed by a sol-gel method, for example, at a temperature of 600 ° C. for 15 minutes and a thickness of 210 nm. The gate insulating film 2 is not limited to the ferroelectric materials BLT and PZT. For example, other ferroelectric materials such as SBT and BIT, or a paraelectric material having a large relative dielectric constant such as BST. It may be as described above.

Next, as shown in FIG. 6C, an ITO (10 wt% SnO ₂ ) channel layer 1 was formed on the gate insulating film 2 such as BLT by RF sputtering, for example. Here, the channel layer 1 was formed with an ITO film thickness of 5 to 15 nm, a film forming pressure of 0.52 to 1.32 Pa, a sputtering power of 75 W, and a substrate temperature of 300 ° C. Further, as shown in FIG. 6D, the source electrode 4 and the drain electrode are formed on the channel layer 1 by, for example, vacuum-depositing Pt (30 nm) / Ti (30 nm) using an E-gun deposition apparatus. Then, as shown in FIG. 6E, the device region was separated by RIE and wet etching (HF: HCl mixed solution) to produce a solid-state electronic device (transistor).

  In the above, the deposition temperature of ITO used as the channel layer 1 is about 200 to 300 ° C., and the crystallization temperature of other ferroelectric materials such as SBT and BIT used as the gate insulating film 2 is 550 to 750. Since the gate insulating film 2 having a high processing temperature is formed after forming the gate insulating film 2 having a high processing temperature, a solid-state electronic device is formed as a bottom gate structure capable of obtaining a good interface by forming the channel layer 1 having a low processing temperature. It has become.

  FIG. 6F is a schematic view of the experimentally manufactured solid-state electronic device as viewed from above. The source electrode 4 and the drain electrode 5 are formed as 120 μm × 120 μm, for example (with a channel width W of 120 μm). In addition, the channel length L is, for example, 40 μm (or 80, 120 μm). Needless to say, as the actual manufacture of the solid-state electronic device according to the present invention, it is possible to apply various manufacturing methods and design rules that are already known, and to manufacture the solid-state electronic device finely and integrated.

  FIG. 7 is a diagram showing the P-E hysteresis characteristics of PZT and BLT in an experimentally manufactured solid-state electronic device. FIG. 7A is a diagram of the solid-state electronic device experimentally manufactured as shown in FIG. FIG. 7A is a diagram showing an example of the PE hysteresis characteristic of a gate insulating film made of PZT. FIG. 7A is a diagram showing a gate insulating film in a solid-state electronic device manufactured in the same manner as shown in FIG. It is a figure which shows an example of the PE hysteresis characteristic of what was comprised.

Figure 8 is a graph illustrating the characteristics of the solid state electronic device of the prototyped PZT / ITO structure experimentally, 8 (a) is a diagram showing a relationship between the drain current I _D and the gate voltage V _G, FIG. 8 (b) is a diagram showing a relationship between the drain current I _D and the drain voltage V _D. Note that the channel width is 120 μm (W = 120 μm), the channel length is 40 μm (L = 40 μm), and FIG. 8A shows the case where the drain voltage is 3 V (V _D = 3 V). .

As shown in FIGS. 8A and 8B, for example, when the gate voltage is 3 V (V _G = V _D = 3 V), the on-current is about 10 ⁻⁴ A, and the on / off ratio is 10 ^4. The field effect mobility μ _FE is 1.0 cm ² / V · s, and the memory window is about 2V.

Figure 9 is a graph illustrating the characteristics of the solid state electronic device of the BLT / ITO structure prototyped experimentally, 9 (a) is a diagram showing a relationship between the drain current I _D and the gate voltage V _G, FIG. 9 (b) is a diagram showing a relationship between the drain current I _D and the drain voltage V _D. The channel width is 120 μm (W = 120 μm), the channel length is 40 μm (L = 40 μm), and FIG. 9A shows the case where the drain voltage is 2V (V _D = 2V). .

As shown in FIGS. 9A and 9B, for example, when the operating voltage is 8 V (V _G = V _D = 8 V), the on-current is about 1 mA, the on / off ratio is about 10 ³ , the electric field The effective mobility μ _FE is 4.0 cm ² / V · s, and the memory window is about 4V. Since the channel length L of this prototype BLT / ITO solid-state electronic device is 40 μm, it can be seen that a much larger on-current may be obtained by miniaturization as compared with a conventional MOSFET.

  Furthermore, as described above, by using a ferroelectric material (PZT, BLT) as the gate insulating film, it is also possible to use the solid-state electronic device as a nonvolatile memory. Note that the prototype solid-state electronic device is merely a prototype, and is improved in the dielectric material (ferroelectric material) as the gate insulating film and the oxide conductive material as the channel layer, or the solid-state electronic device. It is considered that various characteristics of the solid-state electronic device are further improved by improving the manufacturing process.

Next, the on-current of the solid-state electronic device having the PZT / ITO structure and the BLT / ITO structure will be described. First, the carrier concentration per unit area of ITO is n (V _G ), the carrier concentration (donor concentration) of ITO is N _D , the thickness of ITO is d, the carrier mobility is μ, the channel width is W, the channel length Is L, the drain voltage is V _D , the elementary charge is e, the electric field is E, and the charge density is P (V _G ).
n (V _G ) = N _D + P (V _G ) / ed ...... [3]
I _D (V _G ) = e · n (V _G ) · μE · S
= E · n (V _G ) · μV _D / L · W · d
= E (W / L) V _D μd {N _D + P (V _G ) / ed} [4]
Is established.

Here, in the case of PZT, when N _D = 1 × 10 ¹⁹ cm ⁻³ , μ = 1.0 cm ² / V · s, d = 10 nm, and the drain voltage is 3 V (V _D = 3 V), the drain current is Since it is ˜0.1 mA (I _D = 0.1 mA), P = 20 μC / cm ² .

In the case of BLT, when N _D = 1 × 10 ¹⁹ cm ⁻³ , μ = 4.0 cm ² / V · s, d = 10 nm, and the drain voltage is 8 V (V _D = 8 V), the drain current is Since 1 mA (I _D = 1 mA), P = 10 μC / cm ² .

Therefore, as in the solid-state electronic device of the present invention, the ferroelectric material in the gate insulating film (PZT, BLT) when using the maximum charge that can be induced to Si0 ₂ being used as a gate insulating film of a conventional MOSFET density (3.5μC / cm ²⁾ much greater charge density than _{(P (V G) = 10~20μC} / cm 2) can be obtained, as a result, it can be seen that it is possible to control a large oN current .

FIG. 10 is a diagram showing the characteristics of an experimentally manufactured BLT / ITO structure solid-state electronic device. The drain current-drain voltage (I _D −) improved by post-annealing after forming a channel layer made of ITO. V _D ) characteristics.

In the solid-state electronic device having the I _D -V _D characteristics shown in FIG. 10, first, a bottom gate of Pt / Ti is formed on a SiO ₂ / Si substrate, and a ferroelectric layer (BLT) is deposited to 200 nm by a sol-gel method. Further, ITO serving as a channel layer is deposited by RF sputtering to a thickness of about 10 nm, and Pt / Ti is evaporated on the ITO layer to form a source electrode and a drain electrode. Here, the solid-state electronic device performs post-annealing at 300 ° C. for 15 minutes after depositing ITO at room temperature. The channel width is 120 μm (W = 120 μm) and the channel length is 40 μm (L = 40 μm).

As shown in FIG. 10, the I _D -V _D characteristics of the solid-state electronic device fabricated in this way show good transistor characteristics in which the drain current I _D is saturated by applying the drain voltage V _D. Yes. The dotted line in FIG. 10 indicates the I _D -V _D characteristics shown in FIG. 9B, and it can be seen that the characteristics are greatly improved by the post-annealing process after the channel layer made of ITO is formed. Specifically, it can be seen that when the operating voltage is 8 V (gate voltage V _G = 8 V), a very large on-current of about 2.5 mA can be obtained.

Figure 11 is a diagram for explaining the data holding function of the solid-state electronic device BLT / ITO structure prototyped experimentally, FIG. 11 (a) shows the relationship between the drain current I _D and the gate voltage V _G FIG. 11B is a diagram showing data retention characteristics which are the relationship between the drain current _ID and the elapsed time. The channel width is 120 μm (W = 120 μm) and the channel length is 40 μm (L = 40 μm). FIG. 11B shows data retention characteristics when the holding voltage (gate voltage) is 0 V (V _G = 0 V) and the drain voltage is 4 V (V _D = 4 V).

As shown in FIG. 11 (a), solid-state electronic device of BLT / ITO structure, by using a ferroelectric material (BLT) as a gate insulating film, for example, a 4V voltage of about a gate voltage V _G after the oN state is applied to, even when the gate voltage V _G and 0V, as shown in FIG. 11 (b), the residual polarization of BLT in the gate insulating film, for example, 10 ³ sec. It can be seen that the ON state is maintained (data retention) as it is over the above time. By utilizing this data retention characteristic, the solid-state electronic device of this embodiment can be configured as a nonvolatile memory.

FIG. 12 is a diagram schematically showing the configuration of another embodiment of the solid-state electronic device according to the present invention.
As shown in FIG. 12, the solid-state electronic device of this embodiment is configured as a top gate structure in which the gate electrode 3, the source electrode 4 and the drain electrode 5 are provided on the surface portion of the solid-state electronic device (element). .

That is, the solid-state electronic device of this embodiment includes, for example, an electrode 40 that substantially functions as a source electrode and an electrode that functions as a drain electrode on a channel layer 1 made of ITO formed on a SiO ₂ / Si substrate 6. 50, and a gate insulating film 2 made of, for example, BLT is provided on the channel layer 1 and the electrodes 40 and 50. Further, on the gate insulating film 2, a gate electrode 3, a source electrode 4 and a drain electrode are provided. 5 is provided. Vias 41 and 51 are formed in the gate insulating film 2 for the electrodes 40 and 50 so that the electrodes 40 and 50 and the source electrode 4 and the drain electrode 5 are electrically connected to each other. It has become.

  Thus, since the gate electrode 3, the source electrode 4 and the drain electrode 5 are all provided on the surface portion of the solid-state electronic device, the solid-state electronic device of this embodiment applies the same technique as that of the conventional MOSFET. Wiring and the like can be performed.

Note that the solid-state electronic device according to the present invention is not limited to the configuration of FIG. 2 described above or FIG. 12 described above. Further, for example, after forming a gate insulating film made of BLT or after forming a channel layer made of ITO, an annealing process is performed at a predetermined temperature, whereby characteristics as a ferroelectric (for example, PE) (Hysteresis characteristics) or characteristics of the solid-state electronic device (for example, I _D -V _D characteristics) can be further improved.

FIG. 13 is a diagram for explaining a first example in an embodiment of the solid-state electronic device according to the present invention. FIG. 13 (a) shows a channel width W of 25 μm in FIG. FIG. 13B shows the drain current-drain voltage (I _D -V _D ) characteristics of the solid-state electronic device formed with the channel length L of 5 μm. FIG. 13B shows the on-current normalized by the channel width W. A plot of length L is shown. In FIG. 13B, all of PP1 to PP3 have a channel width W of 120 μm, PP1 has a channel length L of 120 μm, PP2 has a channel length L of 80 μm, PP3 has a channel length L of 40 μm, , PP4 shows a case where the channel width W is 25 μm and the channel length L is 5 μm.

As described with reference to FIGS. 6A to 6F, the solid-state electronic device according to the first example forms a ferroelectric film first because of the difference in crystallization temperature between the ferroelectric and ITO. The bottom gate structure is formed. That is, first, a bottom gate 3 of Pt / Ti was formed on a SiO ₂ / Si substrate 6, and a ferroelectric layer (gate insulating film) 2 was deposited by 230 nm by a sol-gel method. The ferroelectric was BLT (Bi / La = 3.35 / 0.75) and crystallized at a temperature of 750 ° C. for 30 minutes. Next, about 10 nm of ITO serving as the channel layer 1 was deposited by RF sputtering. The film forming temperature was 300 ° C. Further, a source electrode 4 and a drain electrode 5 made of Pt / Ti were formed on the channel layer 1 to produce a transistor (solid-state electronic device). As described above, the channel width W was 25 μm and the channel length L was 5 μm.

As shown in FIG. 13A, the I _D -V _D characteristics of a miniaturized solid-state electronic device having a channel length L of 5 μm and a channel width W of 25 μm show typical transistor characteristics. At an operating voltage of 8 V, an on-current of about 2.3 mA is obtained, which is 2.3 mA / 25 μm when normalized (on-current I / channel width W) as shown in FIG. = 92 μA / μm (≈0.1 mA / μm: PP4).

  That is, as shown in FIG. 13B, the on-current due to the miniaturized solid-state electronic device is compared with the channel length L dependency (PP1, PP2, PP3) of the on-state current of the solid-state electronic devices manufactured so far. Increase (PP4) was confirmed. This value of 0.1 mA / μm is comparable to Si-MOSFETs with the same channel length although the operating voltage is as high as 8 V, and further improvement in characteristics such as an increase in on-current is expected due to further miniaturization. it can.

  14A and 14B are diagrams for explaining a second example in one embodiment of the solid-state electronic device according to the present invention. FIG. 14A shows a schematic configuration, and FIG. 14B shows light including a substrate. The measurement result of the transmittance is shown.

The solid-state electronic device of the second example uses a transparent synthetic quartz substrate instead of the SiO ₂ / Si substrate as the substrate 6 in FIG. 14A, and further each electrode (gate electrode 3, source electrode 4 and drain). By using the same transparent ITO as the channel layer 1 instead of Pt / Ti as the electrode 5), a transparent solid-state electronic device is formed.

  First, ITO was deposited on the synthetic quartz substrate 6 by RF sputtering, the gate electrode 3 was formed by patterning, and a ferroelectric layer (gate insulating film) 2 was deposited by 230 nm by a sol-gel method. Ferroelectric material was BLT (Bi / La = 3.35 / 0.75) and crystallized at a temperature of 750 ° C. for 30 minutes. Next, about 10 nm of ITO serving as the channel layer 1 was deposited by RF sputtering. The film forming temperature was 300 ° C. and the film forming pressure was 0.52 Pa. A source electrode 4 and a drain electrode 5 made of ITO were further formed on the channel layer 1 to produce a solid electronic device.

  As shown in FIG. 14B, it can be seen that the solid-state electronic device of the second example has a light transmittance of more than 50% with respect to visible light such as 400 nm to 800 nm. FIG. 14B shows the light transmittance including the synthetic quartz substrate 6, and it is considered that the light transmittance is further improved by improving the substrate 6.

Figure 15 is a diagram for explaining the data holding function of the second example of an embodiment of a solid-state electronic device according to the present invention, 15 (a) shows an I _D -V _G characteristics, FIG. 15 (b ) Indicates data retention characteristics. Incidentally, I _D -V _G characteristics of FIG. 15 (a), the channel width W of a channel length L of 5μm at 25 [mu] m, and is intended drain voltage of the solid-state electronic device when the 2V, FIG. 15 ( The data retention characteristics of b) are those when the write voltage is ± 7V and the retention voltage is 0V.

As shown in FIG. 15A, the solid-state electronic device of the second example has a hysteresis characteristic of drain current accompanying the polarization inversion of the ferroelectric material, and has an on / off ratio of 5 digits or more. It can be seen that Note that I _D -V _D characteristics are also good, and it can be applied as a transparent transistor, for example, as a thin film transistor (TFT) of a liquid crystal display panel, or in various system-on-panels.

  Further, as shown in FIG. 15B, the solid-state electronic device of the second example has a data retention characteristic that retains data even after one hour, for example. It is considered that this data retention characteristic can be made longer by various improvements.

Incidentally, as described above, when a ferroelectric material is used as the gate insulating film 2, it has a data retention function due to the hysteresis characteristics of the ferroelectric material. That is, the hysteresis appears in the I _D -V _G characteristics of the solid-state electronic device. This may be undesirable, for example, when the solid state electronic device is used as a switching element, which limits the degree of freedom in design.

FIG. 16 is a view for explaining a third example in one embodiment of the solid-state electronic device according to the present invention, and shows the PE characteristic of a BST [Ba _0.7 Sr _0.3 TiO ₃ ] capacitor. Here, as a firing method of the BST capacitor, temporary firing was performed at a temperature of 400 ° C. for 10 minutes, and further, main firing was performed at a temperature of 700 ° C. for 60 minutes. The relative dielectric constant εr of BST [Ba _0.7 Sr _0.3 TiO ₃ ] is about 240.

That is, the solid-state electronic device of the third example uses ITO as the channel layer 1 and gate-insulates BST [Ba _0.7 Sr _0.3 TiO ₃ ], which is a paraelectric material having a large relative dielectric constant (εr≈240). It is a transistor having a BST / ITO structure used as the film 2.

FIG. 17 is a diagram showing characteristics of the third example in one embodiment of the solid-state electronic device according to the present invention. FIGS. 17 (a) and 17 (b) show I at a drain voltage of 4V (V _D = 4V). shows a _D -V _G characteristics and I _D -V _D characteristic. Note that the solid-state electronic device of the third example also has the same configuration as that of FIG.

First, a Pt / Ti bottom gate 3 was formed on a SiO ₂ / Si substrate 6, and a BST (gate insulating film) 2 of about 230 nm was formed by a sol-gel method. The crystallization was performed at 700 ° C. for 60 minutes in an O ₂ atmosphere. The ITO (channel layer) 1 was formed by RF sputtering at a film forming temperature of 300 ° C. and a film forming pressure of 0.5 Pa. Furthermore, Pt / Ti was vapor-deposited on the channel layer 1 to form a source electrode 4 and a drain electrode 5 to produce a solid-state electronic device.

As shown in FIG. 17 (a), solid-state electronic device of the present third example, some hysteresis I _D -V _G characteristics (a direction opposite to the case of the ferroelectric gate, hysteresis due to charge injection) However, it is considered that there is no problem when used as a switching element. In addition, as shown in FIG. 17B, the solid-state electronic device of the third example can realize a transistor operation at a relatively low voltage, and can obtain an on / off ratio of 4 digits or more. You can see that In the BST / ITO transistor of the third example, the charge amount used is 10 μC / cm ² , which is larger than the maximum induced charge amount of SiO ₂ .

  As described above, the solid-state electronic device according to the present invention is necessary by changing the element size such as the channel width and the channel length, or changing the material and composition of the substrate, the gate insulating film, and the channel layer. It is possible to have various characteristics.

  The present invention can be widely applied as a solid-state electronic device (transistor), but is particularly suitable for a solid-state electronic device that controls a large current with a low driving voltage. In addition, since the solid-state electronic device using a ferroelectric material as a gate insulating film has a data retention function, the solid-state electronic device of the present invention can be applied as, for example, a nonvolatile memory. Furthermore, the solid-state electronic device of the present invention can also be applied as a power device that controls a large current.

It is a figure which shows an example of the conventional solid-state electronic device roughly. It is a figure which shows schematically the structure of one Example of the solid-state electronic device which concerns on this invention. It is a figure which shows the PE characteristic (PE hysteresis characteristic) for demonstrating comparing the solid-state electronic device shown in FIG. 2 with the conventional solid-state electronic device. It is a figure for demonstrating the principle of operation of the solid-state electronic device shown in FIG. It is a figure for demonstrating the conditions required for the solid-state electronic device shown in FIG. It is a figure for demonstrating schematically the process which produced the solid-state electronic device shown in FIG. 2 experimentally. It is a figure which shows the PE hysteresis characteristic of PZT and BLT in the experimentally manufactured solid-state electronic device. It is a figure which shows the characteristic in the solid-state electronic device of the PZT / ITO structure experimentally produced. It is a figure which shows the characteristic in the solid-state electronic device of the BLT / ITO structure experimentally produced as an experiment. It is a figure which shows the characteristic in the solid-state electronic device of the BLT / ITO structure experimentally produced as an experiment. It is a figure for demonstrating the data holding function of the solid electronic device of the BLT / ITO structure experimentally produced as an experiment. It is a figure which shows schematically the structure of the other Example of the solid-state electronic device which concerns on this invention. It is a figure for demonstrating the 1st example in one Example of the solid-state electronic device which concerns on this invention. It is a figure for demonstrating the 2nd example in one Example of the solid-state electronic device which concerns on this invention. It is a figure for demonstrating the data holding function of the 2nd example in one Example of the solid-state electronic device which concerns on this invention. It is a figure for demonstrating the 3rd example in one Example of the solid-state electronic device which concerns on this invention. It is a figure which shows the characteristic of the 3rd example in one Example of the solid-state electronic device which concerns on this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,101 Channel layer 2,102 Gate insulating film 3,103 Gate electrode 4,104 Source electrode 5,105 Drain electrode 6 Substrate 40, 50 Electrode 41, 51 Via

Claims (11)

A solid-state electronic device having a gate electrode to which a control voltage is applied, and a source electrode and a drain electrode whose conduction state is controlled by the control voltage,
A channel layer for generating a channel between the source electrode and the drain electrode;
And a gate insulating film provided between the gate electrode and the channel layer and made of a dielectric material having a high equivalent relative dielectric constant.   2. The solid state electronic device according to claim 1, wherein the channel layer is made of an oxide conductive material having a high carrier concentration. 3. The solid-state electronic device according to claim 2, wherein the channel layer is formed of indium tin oxide [ITO], LSCO [La _X Sr _1-X CuO ₄ ], tin oxide [SnO ₂ ], zinc oxide [ZnO], or oxide. A solid-state electronic device characterized in that it is indium [In ₂ O ₃ ]. A solid-state electronic device having a gate electrode to which a control voltage is applied, and a source electrode and a drain electrode whose conduction state is controlled by the control voltage,
A channel layer formed of indium tin oxide [ITO] that creates a channel between the source electrode and the drain electrode;
And a gate insulating film provided between the gate electrode and the channel layer and made of a dielectric material having a high equivalent relative dielectric constant. 5. The solid-state electronic device according to claim 1, wherein an elementary charge amount is q, a voltage applied to the gate electrode is V _G , a charge density due to the dielectric material is P (V _G ), and the channel The layer thickness is d, the carrier concentration is N _D , the vacuum dielectric constant is ε ₀ , the relative dielectric constant of the dielectric material is ε _S , and the potential difference between the channel Fermi level and the intrinsic Fermi level is φ _B. The carrier concentration N _D of the channel layer is determined so as to satisfy the following conditional expressions [1] and [2]:
N _D <{P (V _G )} / (qd) (1)
N _D <(4ε ₀ ε _S φ _B ) / qd ² ...... [2]
A solid-state electronic device. 5. The solid-state electronic device according to claim 1, wherein a charge density of the gate insulating film is larger than 10 μC / cm ² and a carrier concentration of the channel layer is higher than 1 × 10 ¹⁸ cm ^−3. Solid-state electronic device characterized.   5. The solid state electronic device according to claim 1, wherein the gate insulating film is made of a ferroelectric material. In the solid-state electronic device according to claim 7, wherein the gate insulating _{film, PZT (Pb (Zr X,} Ti 1-X) O 3], BLT [Bi 4-X La X Ti 3 O 12], SBT [SrBi ₂ Ta ₂ O ₉ ] or BIT [Bi ₄ Ti ₃ O ₁₂ ].   8. The solid-state electronic device according to claim 7, wherein the solid-state electronic device is a transistor having a data holding function.   5. The solid state electronic device according to claim 1, wherein the gate insulating film is made of a paraelectric material. In the solid-state electronic device according to claim 10, wherein the gate insulating film, solid-state electronic device which is a _{BST [Ba X Sr 1-X} TiO 3].

Images