JP2006109525A - Digital broadcasting receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform a decoding efficiently, when a compression video signal and a compression audio signal are contained in a data signal and a compressed format is equal in decoding of the data signal, by which multiplexing is carried out along with the compression video signal and the compressed audio signal of digital broadcasting. <P>SOLUTION: The data signal, separated by a demultiplexer 21, is stored to a data decoder 45 of a memory 40. A CPU 30 analyzes the stored data signal, and compressed video signal or compression audio signal is contained in the analyzed data signal. When it is a compressed format equal to the compression video signal or the compression audio signal by which those compressed format is multiplexed to a digital broadcasting signal, the data signal which the CPU has analyzed is stored in a decoder buffer 51. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a digital broadcast receiver that receives a digital broadcast signal in which a compressed video signal, a compressed audio signal, and an associated data signal are multiplexed, and a CPU and decoder used therefor.

FIG. 9 is a diagram showing a general configuration of a conventional digital broadcast receiver that receives a digitally compressed digital broadcast defined by the ISO / IEC 13818 standard and generally abbreviated as MPEG2.
The digital broadcast receiver shown in FIG. 1 includes a tuner / FEC (Forward Error Correctioner) 10, an antenna 11, a demultiplexer 20, a CPU 30, a memory 40, a decoder buffer 50, and a video decoder 60. , Data selectors 70 and 90, an audio decoder 80, a CPU interface 100, a display 110, a speaker 120, and a data bus 130.
Digital broadcast radio waves received by the antenna 11 are amplified and detected by the tuner / FEC 10, and then subjected to FEC (error correction) to become a digital signal, which is sent to the demultiplexer 20. The demultiplexer 20 separates the digital broadcast signal obtained by multiplexing the compressed video signal, the compressed audio signal, and the data signal obtained from the tuner / FEC 10, supplies the compressed video signal and the compressed audio signal to the decoder buffer 50, and converts the data signal to the data. The data is supplied to the memory 40 via the bus 130.
The decoder buffer 50 is a buffer that holds a compressed video signal and a compressed audio signal. The video decoder 60 reads the compressed video signal from the decoder buffer 50, performs decoding according to PTS (Presentation Time Stamp), and sends the decoding result to the selector 70. The audio decoder 80 reads the compressed audio signal from the decoder buffer 50, performs decoding according to PTS, and sends the decoding result to the selector 90. The memory 40 accumulates the data signal and stores a program executed by the CPU 30 described later. The CPU 30 executes a plurality of programs such as a data decoder 42, an OSD (On Screen Display) 43, a system control 44, etc. expanded in an execution program area 41 of the memory 40 in a time-sharing manner, and sends them to a data bus 130 described later. Supply data signals. The data decoder 42 analyzes the header portion of the data signal, and decodes the data signal according to the type of data indicated there. The OSD 43 performs calculations for drawing necessary for displaying the OSD. The system control 44 controls the entire digital broadcast receiver.
The CPU interface 100 obtains the video signal and the audio signal decoded by the data decoder 42 of the program executed by the CPU 30 from the data bus 130 and supplies them to the selector 70 or the selector 90 according to the signal type. A control signal is sent to 90. Under the control of the CPU 30, the selector 70 selects the output of the video decoder 60 when outputting the main broadcast, and selects the video signal supplied from the CPU interface 100 when outputting the video signal included in the data signal. , And supplied to the display 110 described later. Under the control of the CPU 30, the selector 90 selects the output of the audio decoder 80 when outputting the main broadcast, and selects the audio signal supplied from the CPU interface 100 when outputting the audio signal included in the data signal. , And supplied to a speaker 120 described later. The display 110 displays the video signal supplied from the selector 70. The speaker 120 outputs the audio signal supplied from the selector 90. The data bus 130 is a path for transmitting a data signal processed by the CPU 30 to each unit in the digital broadcast receiver.
With the above configuration, when a data signal is multiplexed on a digital broadcast signal, the data signal is software decoded by the data decoder 42 to obtain a display or audio output.

  An example of a digital broadcast receiver that decodes a digital broadcast signal in which a compressed video signal, a compressed audio signal, and a data signal associated therewith are decoded is disclosed in Japanese Patent Application Laid-Open No. 07-264562.

JP 07-264562 A

  With the improvement of digital compression technology, the proportion of the compressed video / audio signal in the digital broadcast transmission path is reduced, and more data signals can be transmitted.

  For this reason, not only data centered on conventional character data but also video and audio data such as video clips and sound effects can be transmitted, and more diverse data can be transmitted.

  At this time, it is possible to transmit video and audio data by data broadcasting without compression, but it is better to transmit more data as a data signal after being compressed like a video / audio signal of digital broadcasting. Can be transmitted.

  However, in the conventional digital broadcast receiver shown in FIG. 9, all data signal decoding is processed by the data decoder 42. For this reason, after the data decoder 42 analyzes the data signal, the data decoder 42 uses the same video compression method as the compressed video signal or the compressed audio signal multiplexed by digital broadcasting. 60, it is necessary to perform the same decoding process as the audio decoder 80. Even when a compressed still image is sent, it is more efficient to decode the compressed video signal with a video decoder.

  As digital compression technology improves, decoding processing of compressed video signals and compressed audio signals becomes complicated, and the processing load on the data decoder 42 in the CPU 30 increases. Since the CPU 30 executes other programs such as the OSD 43 and the system control 44 in a time-sharing manner, an increase in processing load on the data decoder 42 affects the operation of the entire digital broadcast receiver. A specific example that affects this is OSD drawing. When the decoding of the data signal is started, the priority of the OSD drawing process is lowered, so that switching of the OSD screen takes longer than before. For example, when data broadcasting is selected from a menu indicated by the OSD, the OSD operation becomes slow as the decoding of the data signal starts. Thus, the influence on the user is great.

  On the other hand, when the data signal is decoded, the video decoder 60 and the audio decoder 80 do not select the decoding results in the selectors 70 and 90, respectively.

  As described above, when the compressed video signal or the compressed audio signal included in the data signal is decoded and output, the load on the CPU 30 becomes heavy, but the decoding processing in the video decoder 60 and the audio decoder 80 is not output, and the digital broadcast reception is performed. The utilization efficiency of the entire device in the machine is poor.

  An object of the present invention is to provide a digital broadcast receiver that reduces an increase in processing load on a CPU.

  In order to solve the above problems, for example, the invention disclosed in the claims may be carried out.

  According to the present invention, the processing load can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  First, a first embodiment of the present invention will be described.

  FIG. 1 is a diagram showing a first digital broadcast receiver according to the present invention.

  As shown in the figure, this digital broadcast receiver includes a tuner / FEC 10, an antenna 11, a demultiplexer 21, a CPU 30, a memory 40, a decoder buffer 51, a video decoder 61, and selectors 70, 71, 90. , 91, audio decoder 81, CPU interface 101, display 110, speaker 120, and data bus 130. Among these components, the tuner / FEC 10, the antenna 11, the CPU 30, the memory 40, the selectors 70 and 90, and the data bus 130 are the same as those of the digital broadcast receiver shown in FIG. Is omitted.

  The demultiplexer 21 separates the compressed video signal, the compressed audio signal, and the digital signal obtained by multiplexing the data obtained from the tuner / FEC 10, and supplies the compressed video signal to the selector 71 and the compressed audio signal to the selector 91. The data signal is supplied to the memory 40 via the data bus 130. The data decoder 45 executed by the CPU 30 analyzes the data signal and determines the type of the data signal included.

  When the content of the data signal is a video signal, the presence / absence and type of the compression are checked, and when the video signal has the same compression method as the compressed video signal multiplexed with the digital broadcast signal, the data signal is written to the decoder buffer 51. , The data is sent to the selector 71 via the CPU interface 101, and in the case of other data, software decoding is performed by the data decoder 45, and the video signal is displayed via the data bus 130 and the CPU interface 101 for display on the display 110. Send to 70.

  If the content of the data signal is an audio signal, the presence / absence and type of the compression are checked. If the audio signal has the same compression method as the compressed audio signal multiplexed on the digital broadcast signal, the data bus 130 is written to the decoder buffer 51. The data is sent to the selector 91 via the CPU interface 101, and in the case of other data, software decoding is performed by the data decoder 45, and the audio signal is output via the data bus 130 and the CPU interface 101 for output from the speaker 120. Send to.

  When the content of the data signal is neither an audio signal nor a video signal like character data, the data decoder 45 performs software decoding and outputs the decoded video signal to the selector 70 via the data bus 130 and the CPU interface 101. To do. The CPU interface 101 obtains the video or audio signal processed by the data decoder 45 of the program executed by the CPU 30 from the data bus 130 and supplies it to any of the selectors 70, 71, 90, 91 under the control of the CPU 30. Is selected to output either the main broadcast or the data broadcast, and a control signal is sent to the selectors 70, 71, 90, 91. In addition, a plurality of compressed video signals or compressed audio signals may be multiplexed on the data signal. In this case, the data decoder 45 supplies the compressed video signal to the selector 71 and also performs the decoding process of the plurality of channels by performing the decoding process of the video signal compressed by the CPU 30 itself. For example, when data based on MPEG4 and data based on MPEG2 are multiplexed on the data signal, the data decoder 45 supplies the data based on MPEG2 to the selector 71 and also the CPU 30 decodes the data based on MPEG4. Thus, parallel decoding processing can be performed by the CPU and the decoder of the present invention.

  Under the control of the CPU 30, the selector 71 controls the compressed video signal multiplexed with the digital broadcast signal sent from the demultiplexer 21 when decoding the main broadcast, and the CPU interface when decoding the compressed video signal included in the data signal. The compressed video signal supplied by 101 is output to the decoder buffer 51. Under the control of the CPU 30, the selector 91 controls the compressed audio signal multiplexed with the digital broadcast signal sent from the demultiplexer 21 when decoding the main broadcast, and the CPU interface when decoding the compressed audio signal included in the data signal. The compressed audio signal supplied by 101 is output to the decoder buffer 51.

  The decoder buffer 51 is a buffer that holds video or audio signals input from the selectors 71 and 91. The video decoder 61 reads the compressed video signal from the decoder buffer 51, performs decoding processing according to PTS, and outputs the decoding result to the selector 70. The audio decoder 81 reads the compressed audio signal from the decoder buffer 51, performs decoding processing according to PTS, and outputs the decoding result to the selector 90.

  By adopting the above-described configuration, the present invention uses the video decoder 61 and the audio decoder 81 for the decoding process of the compressed video signal and the compressed audio signal that have been decoded by the data decoder 45 in the related art. Can reduce the processing load.

  Next, a second embodiment of the present invention will be described.

  FIG. 2 is a diagram showing a second digital broadcast receiver according to the present invention, and is a diagram focusing on the method of using the decoder buffer 51 in FIG.

  In this figure, the same parts as those in FIG.

  In the figure, a decoder buffer 51 includes a video decoder buffer 52 which is an area for storing a compressed video signal and an audio decoder buffer 53 which is an area for storing a compressed audio signal. Here, the video decoder buffer 52 occupies either the compressed video signal multiplexed in the digital broadcast or the compressed video signal included in the data signal in a time division manner. Similarly, the audio decoder buffer 53 occupies either a compressed audio signal multiplexed in the digital broadcast or a compressed audio signal included in the data signal in a time division manner.

  The video decoder 61 reads data from the video decoder buffer 52 in which the compressed video signal in the decoder buffer 51 is stored, and decodes the data. Similarly, the audio decoder 81 reads data from the audio decoder buffer 53 in which the compressed audio signal in the decoder buffer 51 is stored, and decodes the data.

  In this embodiment, the compressed video signal multiplexed in the digital broadcast and the compressed video signal included in the data signal are exclusively placed in the same area, so that it is not necessary to increase the memory capacity due to the data signal decoding process.

  Since the video decoder 61 and the audio decoder 81 do not need to distinguish between main broadcast data and data broadcast data in the decoder buffer 51, a video decoder and an audio decoder for decoding only the existing main broadcast data. Can be used to configure a digital broadcast receiver capable of decoding data broadcasts.

  Next, a third embodiment of the present invention will be described.

  FIG. 3 is a diagram showing a third digital broadcast receiver according to the present invention.

  As shown in the figure, this digital broadcast receiver is different from the digital broadcast receiver shown in FIG. 2 in that the CPU interface 102 and VD 141 (Video Data; an abbreviation of video data transmitted on the video data line). VRA 142 (Video Read Address: an abbreviation for video read address data transmitted on the video read address line), VWA 143 (Video Write Address: an abbreviation for video write address data transmitted on the video write address line), VS144 (Video Start: abbreviation of video start data transmitted on the video start line), AD151 (Audio data: abbreviation of audio data transmitted on the audio data line), and ARA152 (Audio Read Address: audio read address) Audio lead address data transmitted on the data line AWA 153 (Audio Write Address: an abbreviation for audio write address data transmitted on the audio write address data line) and AS 154 (Audio Start: an abbreviation for audio start data transmitted on the audio start line) The video buffer interface 62, the video decoding unit 63, the audio buffer interface 82, and the audio decoding unit 83 are the same. Therefore, the same parts are denoted by the same reference numerals and description thereof is omitted.

  When writing the compressed video signal included in the data signal to the video decoder buffer 52 in the decoder buffer 51, the CPU interface 102 sends the write address to the video buffer interface 62 described later using the VWA 143.

  The video buffer interface 62 reads data at the address designated by the VRA 142 from the video decoder buffer 52 to the video decoder 61 using the VD 141. Further, it holds the write address for the decoder buffer 51 of the CPU 30 sent from the VWA 143.

In the case of audio data, the data is read into the audio decoder 81 in the same manner.
That is, when writing the compressed audio signal included in the data signal in the audio decoder buffer 53 in the decoder buffer 51, the CPU interface 102 sends the write address to the audio buffer interface 82 described later using the AWA 153.
The audio buffer interface 82 reads the data at the address specified by the ARA 152 from the audio decoder buffer 53 to the audio decoder 81 using the AD 151. Further, the CPU 30 holds the write address for the decoder buffer 51 of the CPU 30 sent from the AWA 153.

  Here, both the video decoder and the audio decoder can determine whether or not the data stored in the buffer is exhausted by checking the address of writing and reading to the buffer. Here, the case of an audio signal will be described as an example.

  FIG. 4 is a diagram showing the transition of the data amount in the buffer. The horizontal axis of the graph shows the passage of time, and the vertical axis shows the difference between the AWA 153 and the ARA 152. The lower part of the graph shows the processing of the CPU 30 and the audio decoding unit 83 at the same time. Here, the difference between the AWA 153 and the ARA 152 on the vertical axis corresponds to the remaining data amount in the audio decoder buffer 53.

  After receiving the data signal in the memory 40, the CPU 30 analyzes the data signal. When the compression format is the same as that of the main broadcast, the CPU 30 decodes the data signal.

  Here, the decoding process of the compressed audio signal is divided into three parts (a), (b), and (c), and each part will be described.

  Part (a): The compressed audio signal included in the data signal is written into the audio decoder buffer 53 from the CPU 30 via the CPU interface 102. Since the CPU 30 executes other programs such as OSD and control of the entire system in addition to data decoding, the CPU 30 intermittently via the data bus 130 by a transfer method such as DMA (Direct Memory Access). Transfer compressed audio signals. At this time, since the audio buffer interface 82 does not perform reading, the compressed audio signal in the decoder buffer 51 increases monotonously.

  Part (b): a state in which a predetermined amount of compressed audio signal is accumulated in the audio decoder buffer 53 and waiting for decoding to start.

  Part (c): When the CPU 30 instructs the audio decoder 81 to start decoding via the AS 154, the decoding is started and the compressed audio signal is consumed by decoding the compressed audio signal in the buffer. When the audio decoder 81 performs decoding, the difference between the AWA 153 and the ARA 152 is reduced. The audio decoder 81 determines that the data is depleted when the difference between the two becomes 0, and stops the decoding process. Alternatively, it is possible to perform decoding repeatedly by resetting the ARA 152 to 0 and restarting the reading of the compressed audio signal in the decoder buffer 51. Alternatively, decoding can be resumed from the middle by resetting the ARA 152 to a predetermined address held when writing to the decoder buffer 51.

In any case, since the CPU 30 only needs to start processing using the AS 154 for the audio decoder 81, the decoding control of the compressed audio signal is easy.
The same applies to the decoding of the compressed video signal.

  In data broadcasting, the amount of data to be decoded at one time is shorter than that of the main broadcasting, and when the decoded data is repeatedly decoded, the same data must be frequently transferred to the decoder buffer 51.

  In the present embodiment, when all the compressed video / audio signals included in the data signal can be stored in the decoder buffer 51, only the process of storing the compressed video / audio signal in the decoder buffer 51 is performed first, and then the decoder There is no need to intermittently supply compressed video / audio signals to the buffer 51. Therefore, the data bus 130 can be effectively used for transferring data other than the decoding result of the data decoder, for example, OSD data. This is particularly effective in applications such as data broadcasting and background music repetition.

  Next, a fourth embodiment of the present invention will be described.

  FIG. 5 is a diagram showing a fourth digital broadcast receiver according to the present invention.

  As shown in the figure, the digital broadcast receiver differs from the digital broadcast receiver shown in FIG. 3 in a video buffer progress interrupt 160 and an audio buffer progress interrupt 170, and the others are the same. Therefore, the same parts are denoted by the same reference numerals and description thereof is omitted. The changed part is described below.

  The video buffer progress interrupt 160 is generated when the VRA 142 equals the address held in the video buffer interface 62 through the VWA 143. Similarly, the audio buffer progress interrupt 170 is sent to the audio buffer interface 82 through the AWA 153, Occurs when ARA 152 is equal.

  FIG. 6 is a diagram showing a data amount and processing of each unit at the time of repeated decoding of the digital broadcast receiver. An explanation will be given by taking an example of decoding a compressed audio signal included in a data signal.

  Part (d): The compressed audio signal is accumulated in the decoder buffer 51 and waiting for decoding to start.

  Part (e): When the CPU 30 instructs the audio decoder 81 to start decoding via the AS 154, the decoding starts, and the audio buffer progresses when one of the addresses held in the audio buffer interface 82 through the AWA 153 matches the ARA 152. An interrupt is supplied to the CPU 30 through the interrupt 170, and the audio decoder 81 stops decoding.

  Since the audio buffer progress interrupt 170 causes the CPU 30 to know that the audio decoder 81 has stopped decoding the compressed audio signal in the decoder buffer 51, the CPU 30 again after the arbitrary time (f) and again at the (g) portion. Decoding is started by AS154.

  In FIG. 6, since the address held by the audio buffer interface 82 is the address last written to the decoder buffer 51 by the CPU 30, an interrupt is generated only when data is depleted, but a plurality of addresses being written are held. By doing so, it is possible to stop and restart decoding at an arbitrary point.

  In the present embodiment, the CPU 30 can freely set the decoding restart timing and the number of repetitions, so that it is possible to cope with an application that requires synchronization with the main broadcast.

  Next, a fifth embodiment of the present invention will be described.

  FIG. 7 is a diagram showing a fifth digital broadcast receiver according to the present invention.

  As shown in the figure, this digital broadcast receiver differs from the digital broadcast receiver shown in FIG. 5 in that VSS (Video start / stop) 145 and ASS (Audio start / stop: Audio start). Stop) 155, video frame pulse interrupt 161, and audio frame pulse interrupt 171. The others are the same. Therefore, the same parts are denoted by the same reference numerals and description thereof is omitted. The changed part is described below. The VSS 145 starts and stops the decoding process of the video decoder 61 according to a control signal from the CPU 30. Similarly, the ASS 155 starts and stops the decoding process of the audio decoder 81 according to the control signal of the CPU 30. The video frame pulse interrupt 161 is generated when the decoding of one frame of the compressed video signal is completed, and notifies the CPU 30 of it. Similarly, the audio frame pulse interrupt 171 is generated when the decoding of one frame of the compressed audio signal is completed and notifies the CPU 30 of it.

  FIG. 8 is a diagram showing decoding control in this embodiment.

  An explanation will be given by taking an example of decoding a compressed audio signal included in a data signal.

  The CPU 30 sends a control signal to the ASS 155 at point (h) to start decoding, and receives an interrupt from the audio decoder 81 every time one frame of data ends.

  Then, at the point (i) determined by the program of the data decoder 45, a control signal is sent to the ASS 155 to stop the decoder.

  Then, the decoding process of the audio decoder 81 is resumed by sending a control signal to the ASS 155 again at the point (j).

  In the present embodiment, a method has been shown in which the remaining amount of the buffer can be measured using a frame pulse when the number of frames of the compressed audio signal transferred by the CPU 30 is grasped in advance. The effect is the same as in the fourth embodiment.

  Next, a sixth embodiment of the present invention will be described.

  FIG. 10 is a diagram showing a sixth digital broadcast receiver according to the present invention.

  As shown in the figure, the digital broadcast receiver differs from the digital broadcast receiver shown in FIG. 1 in a video data line 210, an audio data line 220, and a CPU data line 230, and the others are the same. Therefore, the same parts are denoted by the same reference numerals and description thereof is omitted.

  In this embodiment, a video decoder, an audio decoder, and a CPU are integrated in a package 200.

  The video data line 210 reads the compressed video signal from the memory 40 using the data bus 130. Similarly, the audio data line 220 reads the compressed audio signal from the memory 40 using the data bus 130. The CPU data line 230 is a line for the CPU to read and write data in the memory.

  The data signal separated by the demultiplexer 21 is supplied to the CPU 30. The data decoder 45 executed by the CPU 30 analyzes the data signal, determines the type of the included data signal, and stores it in the memory 40. If the content of the data signal is a video signal and can be decoded by the video decoder, the CPU 30 supplies the data signal to the video decoder 61 via the video data line 210 and performs a decoding process. Similarly, when the content of the data signal is an audio signal and can be decoded by the audio decoder, the CPU 30 supplies the data signal to the audio decoder 81 via the audio data line 220 to perform the decoding process.

  In the present embodiment, a method of using a video decoder and an audio decoder when decoding a data signal in a circuit in which a video decoder, an audio decoder, and a CPU are integrated has been shown.

  According to the embodiment described in the above specification, the video decoder for decoding the main broadcast provided in advance is not based on software for decoding the compressed video signal and the compressed audio signal included in the data signal. Since the CPU processing is reduced because the audio decoder is used, not only the processing speed of the conventional function is improved and the cost of the CPU is reduced, but also new processing can be added.

  In addition, for example, when a receiver has a communication function and a data signal is obtained from a network such as the Internet as well as a demultiplexer, an effect of reducing the number of external parts can be obtained by processing the communication function by software using a CPU. It is done.

It is a block diagram which shows 1st embodiment of this invention. It is a block diagram which shows 2nd embodiment of this invention. It is a block diagram which shows 3rd embodiment of this invention. It is a figure showing transition of the total data amount in a decoder buffer at the time of decoding. It is a block diagram which shows 4th embodiment of this invention. It is a figure showing transition of the total amount of data in a decoder buffer when performing repeated reproduction using an audio buffer progress interrupt. It is a block diagram which shows 5th embodiment of this invention. It is a figure showing transition of the total data amount in a decoder buffer when performing decoding stop and restart using an audio frame pulse interruption. It is a block diagram which shows the structure of the conventional digital broadcast receiver. It is a block diagram which shows the 6th embodiment of this invention.

Explanation of symbols

10 ... Tuner / FEC
11 ... Antenna 21 ... Demultiplexer 30 ... CPU
DESCRIPTION OF SYMBOLS 40 ... Memory 51 ... Decoder buffer 52 ... Video decoder buffer 53 ... Audio decoder buffer 61 ... Video decoder 71 ... Selector 81 ... Audio decoder 91 ... Selector 101 ... CPU interface

Claims (7)

A demultiplexer for respectively separating a digital broadcast signal in which a compressed video signal, a compressed audio signal, and a data signal associated therewith are multiplexed;
A decoder buffer for storing the compressed video signal and the compressed audio signal separated by the demultiplexer;
A video decoder for decoding the compressed video signal in the decoder buffer;
An audio decoder for decoding the compressed audio signal in the decoder buffer;
A memory for storing the data signal separated by the demultiplexer;
A CPU for analyzing the data signal stored in the memory,
The CPU includes a compressed video signal or a compressed audio signal in the analyzed data signal and the compression format is the same as the compressed video signal or the compressed audio signal multiplexed with the digital broadcast signal. And a data signal analyzed by the CPU is stored in the decoder buffer.   The CPU performs a decoding process on the analyzed data when the content of the analyzed data signal is a data signal that is not in a compression format equal to a compressed video signal or a compressed audio signal multiplexed with a digital broadcast signal. The digital broadcast receiver according to claim 1.   The decoder buffer occupies and exclusively uses the compressed video signal and the compressed audio signal separated by the demultiplexer and the compressed video signal and the compressed audio signal included in the data signal in a time division manner. The digital broadcast receiver according to claim 1 or 2.   The video decoder and the audio decoder hold a write address when the compressed video signal and the compressed audio signal included in the data signal are stored in the decoder buffer, and read out the decoder buffer of the video decoder and the audio decoder. 2. The decoding of the compressed video signal and the compressed audio signal stored in the decoder buffer or the progress of decoding is detected from a difference from an address, and decoding is stopped, restarted, or repeated. 2. A digital broadcast receiver according to 2 or 3.   The video decoder and the audio decoder generate an interrupt signal for the CPU when the compressed video signal and the compressed audio signal stored in the decoder buffer are depleted or decoding progress, and the CPU receives the interrupt signal. 4. A digital broadcast receiver according to claim 1, wherein the decoding is controlled.   The video decoder and the audio decoder generate a frame pulse interrupt signal to the CPU, and the CPU receives the frame pulse interrupt signal and counts the number of frames related to the frames of the compressed video signal and the compressed audio signal. 4. The digital broadcast receiver according to claim 1, wherein decoding is controlled by performing the control. A demultiplexer for respectively separating a digital broadcast signal in which a compressed video signal, a compressed audio signal, and a data signal associated therewith are multiplexed;
A decoder buffer for storing the compressed video signal and the compressed audio signal separated by the demultiplexer;
A video decoder for decoding the compressed video signal in the decoder buffer;
A display for displaying the video signal decoded by the video decoder;
An audio decoder for decoding the compressed audio signal in the decoder buffer;
A speaker for outputting an audio signal decoded by the audio decoder;
A memory for storing the data signal separated by the demultiplexer;
A CPU for analyzing the data signal stored in the memory,
The CPU includes a compressed video signal or a compressed audio signal in the analyzed data signal and the compression format is the same as the compressed video signal or the compressed audio signal multiplexed with the digital broadcast signal. And a data signal analyzed by the CPU is stored in the decoder buffer.

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