JP2006108489A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device capable of preventing a damage caused in the case of dicing from influencing a semiconductor chip. <P>SOLUTION: The manufacturing method of the semiconductor device includes the steps of forming a first groove to a dicing region in one of X and Y axial directions at a border between semiconductor chip regions and the dicing regions, in one of the X and Y axial directions in a semiconductor wafer with the dicing regions extended in X and Y axes between the semiconductor chip regions; forming a second groove to the other dicing region at the border between the semiconductor chip regions and the dicing region in the other of the X and Y axial directions; and dicing the dicing region in the one of the X and Y axial directions in a way of including the first groove, and dicing the dicing region in the other of the X and Y axial directions in a way of including the second groove. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a dicing method for cutting a semiconductor chip from a semiconductor wafer.

  In recent years, with the progress of semiconductor element miniaturization technology, in highly integrated semiconductor devices, not only the delay of the semiconductor element but also the delay of the wiring part (wiring delay) has come to determine the maximum operating speed of the semiconductor device. . In order to reduce the wiring delay of the semiconductor device, a low-k film, which is an insulating film having a low dielectric constant, has been used as an interlayer insulating film of the semiconductor device.

  However, this low-k film has low physical strength and low adhesion strength to the silicon oxide film, silicon nitride film, etc., and occurs in the semiconductor device, particularly during dicing. There was a problem that film peeling occurred due to damage.

  As such a dicing method for preventing the peeling of the low-k film of the semiconductor device having the low-k film in the interlayer insulating film, for example, the following dicing method is known (see, for example, Patent Document 1). .

  In Patent Document 1, first, a blade using a resin as a main binder is cut from the side of the semiconductor substrate on which the low-k film is laminated to at least a depth at which the semiconductor substrate is exposed, and then exposed. A so-called step-cut dicing method is disclosed in which the semiconductor substrate is completely cut by an electroforming (electrodeposition) blade, and the semiconductor substrate on which the low-k film is laminated is divided into individual chips.

  According to the above prior art, when using a blade that uses resin as the main binder when cutting low-k films, damage can be suppressed and low-k film peeling can be suppressed. It is supposed to be possible.

  However, although the occurrence of damage can be suppressed as compared with the case of using a normal blade, there is a possibility that the low-k film exposed from the cutting surface may be peeled off due to damage from the blade during dicing.

  As mentioned above, when cutting the dicing area with a blade, damage occurs in the dicing area, the damage is transmitted to the semiconductor chip area, film peeling occurs in the low-k film in the semiconductor chip area, There arises a problem that the reliability of the semiconductor device is lowered.

Also, a metal pattern (hereinafter simply referred to as a metal pattern) of a TEG (test element group) pad for acquiring manufacturing process data, element data, and the like of the semiconductor device is formed in the dicing region. Also, in order to increase the number of semiconductor chips taken from one semiconductor wafer, the dicing area is minimized, and the metal pattern covers most of the width direction of the dicing area, and the dicing is performed in the X-axis direction and the Y-axis direction. More and more cases are arranged at intersections of regions.
JP 2003-197564 A

  An object of the present invention is to provide a method for manufacturing a semiconductor device capable of suppressing a decrease in reliability of the semiconductor device.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, in which a semiconductor wafer having a dicing region extending in an X-axis direction and a Y-axis direction between semiconductor chip regions Forming a first groove on the one axial dicing region side of the boundary with the axial dicing region, and the other boundary between the semiconductor chip region and the other axial dicing region. Forming a second groove on the dicing region side, dicing the one axial dicing region to include the first groove, and the other axial direction to include the second groove And a step of dicing the dicing region.

  According to the present invention, it is possible to provide a highly reliable manufacturing method of a semiconductor device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  A method of manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a schematic diagram of a semiconductor wafer according to Embodiment 1 of the present invention. FIG. 1B is a partial schematic view of a semiconductor wafer when reduced projection exposure is performed with one shot of four chips.

  First, as shown in FIG. 1A, on a main surface of a semiconductor wafer 1, for example, a plurality of planar semiconductor chip regions 2 are regularly arranged so that a dicing region 3 is sandwiched between adjacent semiconductor chip regions 2. ing. In each semiconductor chip region 2, an integrated circuit such as a memory circuit or a logic circuit is formed. Each dicing region 3 is a boundary region that is arranged in the X-axis direction and the Y-axis direction and is arranged at a predetermined interval between the semiconductor chip regions 2 and the semiconductor chip regions 2 adjacent to each other, and is cut in a dicing process described later. It is an area to be done. The width of the dicing region 3, that is, the interval between the adjacent semiconductor chip regions 2 is, for example, about 30 to 300 μm.

  At the center of the dicing area 3, as shown in FIGS. 1B and 2, a test element group (TEG) for testing the electrical characteristics of the integrated circuit formed in the alignment mark and the semiconductor chip area 2 is provided. A pattern forming region in which a metal pattern such as a pad for forming is formed is provided. Further, groove regions 6XA and 6XB and groove regions 6YA and 6YB for forming grooves are formed on both sides of the central portion of the dicing region 3 in each X-axis direction and Y-axis direction. It is provided in the vicinity of the boundary line with the region 2.

  A metal pattern 5 is formed in at least one of the dicing regions 3 in the X-axis direction and the Y-axis direction. Here, the case where the metal pattern 5 is a TEG pattern made of a metal such as copper or aluminum formed in a straight line is illustrated.

  A plurality of TEG patterns 5 are arranged on the semiconductor wafer 1 and are formed in the same direction. For example, as shown in FIG. 1B, the three TEG patterns 5 are all formed at the center in the width direction of the dicing region 3 in the Y-axis direction. Further, the TEG pattern 5 is often longer than the length of one side of the semiconductor chip region 2 and is formed so as to include the intersection of the dicing regions 3 in the X-axis and Y-axis directions as shown in FIG.

  Then, a groove 7 in the X-axis direction is formed in the trench areas 6XA and 6XB, and a groove 8 in the Y-axis direction is formed in the trench areas 6YA and 6YB. The groove 7 in the X-axis direction and the groove 8 in the Y-axis direction are linearly formed in the dicing region 3 at the boundary with the semiconductor chip region 2 in the dicing region 3 so as to open the center of the dicing region 3. However, the groove 7 in the X-axis direction and the groove 8 in the Y-axis direction may be grooves that are narrower than the widths of the trench regions 6XA, 6XB, 6YA, and 6YB, and the trench regions 6XA, 6XB, A groove may be formed so as to protrude from the inside of the dicing region (in the direction in which the semiconductor chip region 2 is not formed) from 6YA and 6YB. For example, as shown in FIG. 3, the groove 7 in the X-axis direction is narrower than the width of each trench area 6XA, 6XB, and the groove 8 in the Y-axis direction is narrower than the width of each trench area 6YA, 6YB. 2 is formed near the boundary line.

  In addition, after forming the groove 7 in the X-axis direction in the trench areas 6XA and 6XB and forming the groove 8 in the Y-axis direction in the trench areas 6YA and 6YB, the groove 7 in the X-axis direction is included by a blade device or the like. By dicing the dicing area 3 in the X-axis direction and dicing the dicing area 3 in the Y-axis direction so as to include the groove 8 in the Y-axis direction, damage caused by dicing during dicing is transmitted to the semiconductor chip area 2. This makes it difficult to prevent the low-k film 102 from peeling off in the semiconductor chip region 2.

  As shown in FIG. 4, each trench area 6XA, 6XB, 6YA, 6YB and the semiconductor chip area 2 where the X-axis direction groove 7 and the Y-axis direction groove 8 are formed are formed on the semiconductor substrate 100, as shown in FIG. A first interlayer insulating film 101, a low-k film 102, a diffusion prevention film 103, a passivation film 104, and the like are stacked. The first interlayer insulating film 101 is a film having a low dielectric constant, for example, an insulating film such as SiO 2.

  The groove 7 in the X-axis direction and the groove 8 in the Y-axis direction are formed so as to remove both the interface between the low-k film 102 and the upper and lower diffusion prevention films 103. FIG. 4 is a cross-sectional view taken along the line A-A ′ of FIG. 3.

  Next, a method for forming the groove 7 in the X-axis direction and the groove 8 in the Y-axis direction will be described with reference to FIG.

  First, after forming an integrated circuit in the semiconductor chip region 2 on the semiconductor wafer 1, as shown in FIG. 5A, each of the trench regions 6YA and 6YB in the dicing region 3 in the Y-axis direction is respectively formed using a laser. As the Y-axis direction groove 8 which is the first groove, a Y-axis direction groove 8YA and a Y-axis direction groove 8YB are formed. Either the Y-axis direction groove 8YA or the Y-axis direction groove 8YB formed in the groove area 6YA and the groove area 6YB may be formed first or simultaneously.

  Next, as shown in FIG. 5 (b), the X-axis grooves 7XA and 6XB in the X-axis dicing area 3 are each formed as a second groove X-axis groove 7 by using a laser. Direction groove 7XA and X-axis direction groove 7XB are formed. Either the X-axis direction groove 7XA or the X-axis direction groove 7XB formed in the trench areas 6XA and 6XB may be formed first or simultaneously.

  In forming the X-axis direction groove 7 and the Y-axis direction groove 8, as described above, after forming the Y-axis direction groove 8 in the Y-axis direction dicing region 3 in which the TEG pattern 5 is formed, It is important to form the groove 7 in the X-axis direction in the dicing region 3 in the X-axis direction. That is, first, when the groove 7 in the X-axis direction is formed in the trench area 6XA and 6XB in the X-axis direction where the TEG pattern 5 is not formed, the TEG pattern 5 and the trench area 6XA or the trench area 6XB are obtained. Damage occurs to the interlayer film and the like in the dicing region 3 around the overlapping portion. This damage occurs when a laser beam is used to irradiate a boundary portion between a portion having metal and a portion not having metal.

  Damage caused by the laser generated in the dicing region 3 extends not only to the dicing region 3 in the X-axis direction but also to the semiconductor chip region 2. When laser damage is transmitted to the semiconductor chip region 2, the low-k film 102 is peeled off or a crack is generated in the semiconductor chip region 2. Moisture permeates from the location where the film peeling or cracking occurs, causing corrosion or the like in the wiring layer 105 in the semiconductor chip region 2, thereby reducing the reliability of the semiconductor device.

  However, as in this example, first, as shown in FIG. 5A, the trench areas 6YA and 6YB of the dicing area 3 in the Y-axis direction where the TEG pattern 5 is formed are irradiated with laser, A groove 8 in the Y-axis direction is formed in advance between the TEG pattern 5 and the semiconductor chip region 2. Thereafter, as shown in FIG. 5B, the X-axis direction groove 7XA and the X-axis direction groove 7XB are formed in the trench areas 6XA and 6XB of the dicing area 3 in the X-axis direction where the TEG pattern 5 is not disposed. When the TEG pattern 5 and the trench area 6XA or the trench area 6XB overlap with each other, even if the dicing area 3 is damaged by the laser, the Y already formed in the trench areas 6YA and 6YB Since the TEG pattern 5 and the semiconductor chip region 2 are physically separated by the groove 8YA in the axial direction and the groove 8YB in the Y-axis direction, damage caused by the laser is hardly transmitted to the semiconductor chip region 2.

  Finally, after forming the groove 7 in the X-axis direction and the groove 8 in the Y-axis direction in the order as described above, the dicing region 3 in the X-axis direction is formed so as to include the groove 7 in the X-axis direction by a normal blade device. Dicing is performed, the dicing region 3 in the Y-axis direction is diced so as to include the groove 8 in the Y-axis direction, and each semiconductor chip is cut out from the semiconductor wafer 1.

  In this dicing, the dicing area 3 is damaged by dicing. However, the groove 7 in the X-axis direction or the groove 8 in the Y-axis direction is formed in advance between the dicing area 3 and the semiconductor chip area 2. Therefore, the progress of damage due to dicing is prevented by the groove 7 in the X-axis direction or the groove 8 in the Y-axis direction, and is difficult to be transmitted to the semiconductor chip region 2.

  At this time, dicing is performed so that the blade of the blade device does not protrude outside the grooves 7 and 8 (on the semiconductor chip region 2 side). When the blade comes into contact with the inner wall of the groove 7 and the groove 8 on the semiconductor chip region 2 side, the low-k film 102 in the dicing region 3 is damaged, and the semiconductor chip region 2 is peeled off. It becomes.

  As described above, according to the present embodiment, the dicing damage generated in the dicing region 3 is not easily transmitted to the semiconductor chip region 2 by the X-axis direction groove 7 and the Y-axis direction groove 8. Therefore, it is possible to suppress a decrease in reliability due to film peeling or the like in 2 and to manufacture a highly reliable semiconductor device.

  Further, when the X-axis direction groove 7 and the Y-axis direction groove 8 are formed in the dicing region using a laser, the Y-axis direction groove 8 which is the same direction as the direction in which the TEG pattern 5 is formed is formed. Thereafter, if the grooves are formed in the order of forming the groove 7 in the X-axis direction, which is a direction orthogonal to the TEG pattern 5, damage due to the laser is difficult to be transmitted to the semiconductor chip region 2, so that the film in the semiconductor chip region 2 is peeled off. It is possible to suppress a decrease in reliability due to the above.

  In the above embodiment, the semiconductor wafer 1 having the metal pattern 5 in the dicing region 3 has been described. However, the present invention can be applied to the semiconductor wafer 1 that does not have the TEG pattern (metal pattern) 5. In this case, the order of forming the groove 7 in the X-axis direction and the groove 8 in the Y-axis direction is not limited, and either may be formed first.

  First, after forming a groove 7 in the X-axis direction and a groove 8 in the Y-axis direction in the dicing area 3, the dicing area 3 in the X-axis direction is diced so as to include the groove 7 in the X-axis direction by a blade device or the like. Then, the dicing region 3 in the Y-axis direction is diced so as to include the groove 8 in the Y-axis direction, and each semiconductor chip is cut out from the semiconductor wafer 1. At the time of dicing, damage due to dicing occurs in the dicing area 3, but since the groove 7 in the X-axis direction and the groove 8 in the Y-axis direction are formed in the dicing area 3 in advance, the damage due to dicing is caused by the semiconductor chip area 2. Can be prevented.

  A method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. The semiconductor device manufacturing method shown in the first embodiment is different in that a dummy metal pattern 10 other than the TEG pattern 5 is formed in the dicing region 3 except for the periphery of the TEG pattern 5. The same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. FIG. 6 is a partially enlarged plan view of a semiconductor wafer after forming grooves by a laser according to Embodiment 2 of the present invention.

  As shown in FIG. 6, a dicing region 3 is formed between the semiconductor chip regions 2, and a trench region for forming a groove is formed on both sides of the central portion of each dicing region 3 in each X-axis direction and Y-axis direction. 6XA and 6XB, and trench areas 6YA and 6YB are provided in the vicinity of the boundary line with the semiconductor chip area 2 in the dicing area 3, respectively. A TEG pattern 5 is formed in the dicing region 3 in the Y-axis direction. Further, a groove 7 is formed in the trench areas 6XA and 6XB, and a groove 8 is formed in the trench areas 6YA and 6YB.

  A dummy metal pattern 10 is formed in the dicing region 3 where the TEG pattern 5 is not formed, except for the periphery of the TEG pattern 5, and hatching is illustrated in FIG. .

  The dummy metal pattern 10 will be described with reference to FIG. FIG. 7 is a cross-sectional view taken along line B-B ′ of FIG. 6. In the dicing region 3 of FIG. 7, the dummy metal pattern 10 is formed in the same layer as the one wiring layer 105 in the wiring layer 105 in the semiconductor chip region 2. The semiconductor device shown in FIG. 7 has two wiring layers, but the dummy metal pattern 10 is formed in the same layer as the upper wiring layer 105.

  Further, if the dummy wiring pattern 10 and the TEG pattern 5 are connected, a short circuit occurs when an inspection is performed using the TEG pattern 5, so that the TEG pattern 5 and the dummy wiring pattern 10 are electrically connected. It is formed in the dicing region 3 so as not to be performed.

  In the present embodiment, the dummy metal pattern 10 is formed in the same layer as the wiring layer 105 in the semiconductor chip region 2 so that the dummy metal pattern 10 can be easily disposed in the manufacturing process, but the dicing region in the semiconductor chip region 2 is formed. 3, the dummy metal pattern 10 may be formed as long as it is not electrically connected to the TEG pattern 5.

  A method of forming the X-axis direction groove 7 and the Y-axis direction groove 8 in the semiconductor device having the dummy metal pattern 10 in the dicing region 3 will be described with reference to FIG.

  First, an integrated circuit is formed in the semiconductor chip region 2 on the semiconductor wafer 1. When the wiring layer 105 is formed in the semiconductor chip region 2, the dummy metal pattern 10 is formed in a region other than the region where the TEG pattern 5 is formed in the dicing region 3. The TEG pattern 5 and the dummy metal pattern 10 are usually formed at the same time, but either may be formed first.

  Next, as shown in FIG. 8A, the Y-axis direction grooves 8YA and 6YB in the Y-axis direction dicing area 3 are respectively formed as Y-axis direction grooves 8 as first grooves by using a laser. Direction groove 8YA and Y-axis direction groove 8YB are formed. Either the Y-axis direction groove 8YA or the Y-axis direction groove 8YB formed in the groove area 6YA and the groove area 6YB may be formed first or simultaneously.

  Next, as shown in FIG. 8B, the X-axis grooves 7XA and 6XB in the X-axis dicing area 3 are respectively formed as X-axis grooves 7 as second grooves by using a laser. Direction groove 7XA and X-axis direction groove 7XB are formed. Either the X-axis direction groove 7XA or the X-axis direction groove 7XB formed in the trench areas 6XA and 6XB may be formed first or simultaneously.

  In forming the X-axis direction groove 7 and the Y-axis direction groove 8, as described above, after forming the Y-axis direction groove 8 in the Y-axis direction dicing region 3 in which the TEG pattern 5 is formed, It is important to form the groove 7 in the X-axis direction in the dicing region 3 in the X-axis direction. That is, first, when the groove 7 in the X-axis direction is formed in the trench area 6XA and 6XB in the X-axis direction where the TEG pattern 5 is not formed, the TEG pattern 5 and the trench area 6XA or the trench area 6XB are obtained. Damage occurs to the interlayer film and the like in the dicing region 3 around the overlapping portion. Therefore, the grooves are formed in the order of the groove 7 and the groove 8.

  This damage occurs when a laser beam is used to irradiate a boundary portion between a portion having metal and a portion not having metal. Here, when the dummy metal pattern 10 is not formed in the dicing area 3, the TEG pattern 5 has a metal such as a test pad and the dicing area 3 other than the TEG pattern 5 has a metal. Since the metal is not included, when the laser is applied to the TEG pattern 5 when the laser 7 is applied to form the groove 7 in the X-axis direction, damage occurs around the TEG pattern 5.

  Therefore, in this embodiment, the dummy metal pattern 10 is formed in the dicing region 3 around the TEG pattern 5 to reduce the boundary between the portion having metal and the portion not having metal, and irradiate the laser. It is possible to reduce the damage that occurs.

  Then, even when the TEG pattern 5 is irradiated with a laser and damage occurs around the TEG pattern 5, in the manufacturing method of the semiconductor device according to this example, first, as shown in FIG. Thus, a Y-axis direction groove 8 is formed in advance between the TEG pattern 5 and the semiconductor chip region 2, and thereafter, as shown in FIG. 8B, the X-axis direction groove 7XA and the X-axis direction groove Since 7XB is formed, the TEG pattern 5 and the semiconductor chip region 2 are physically separated by the Y-axis direction groove 8YA and the Y-axis direction groove 8YB already formed in the trench areas 6YA and 6YB. Damage due to the laser is hardly transmitted to the semiconductor chip region 2.

  Finally, after forming the groove 7 in the X-axis direction and the groove 8 in the Y-axis direction in the order as described above, the dicing region 3 in the X-axis direction is formed so as to include the groove 7 in the X-axis direction by an ordinary blade device. Dicing is performed, the dicing region 3 in the Y-axis direction is diced so as to include the groove 8 in the Y-axis direction, and each semiconductor chip is cut out from the semiconductor wafer 1.

  In this dicing process, damage due to dicing occurs in the dicing area 3. Between the dicing area 3 and the semiconductor chip area 2, a groove 7 in the X-axis direction or a groove 8 in the Y-axis direction is formed in advance. Therefore, the progress of damage due to dicing is prevented by the groove 7 in the X-axis direction or the groove 8 in the Y-axis direction, and is difficult to be transmitted to the semiconductor chip region 2.

  As described above, according to the present embodiment, the dicing damage generated in the dicing region 3 is not easily transmitted to the semiconductor chip region 2 by the X-axis direction groove 7 and the Y-axis direction groove 8. Therefore, it is possible to suppress a decrease in reliability due to film peeling or the like in 2 and to manufacture a highly reliable semiconductor device.

  Further, when the X-axis direction groove 7 and the Y-axis direction groove 8 are formed in the dicing region using a laser, the Y-axis direction groove 8 which is the same direction as the direction in which the TEG pattern 5 is formed is formed. Thereafter, if the grooves are formed in the order of forming the groove 7 in the X-axis direction, which is a direction orthogonal to the TEG pattern 5, damage due to the laser is difficult to be transmitted to the semiconductor chip region 2, so that the film in the semiconductor chip region 2 is peeled off. It is possible to suppress a decrease in reliability due to the above.

1 is a schematic diagram of a semiconductor wafer according to Embodiment 1 of the present invention. FIG. 2 is a partially enlarged plan view of a semiconductor wafer before groove formation in FIG. 1. FIG. 2 is a partially enlarged plan view of the semiconductor wafer after the groove formation in FIG. 1. FIG. 4 is an A-A ′ cross-sectional view of the semiconductor wafer of FIG. 3. Process drawing which shows the formation method of the groove | channel by the laser which concerns on Example 1 of this invention. The partial enlarged plan view of the semiconductor wafer after formation of the groove | channel by the laser which concerns on Example 2 of this invention. FIG. 7 is a B-B ′ sectional view of the semiconductor wafer of FIG. 6. Process drawing which shows the formation method of the groove | channel by the laser which concerns on Example 2 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Semiconductor chip area | region 3 Dicing area | region 5 TEG pattern (metal pattern)
6XA, 6XB, 6YA, 6YB Groove region 7, 7XA, 7XB X-axis direction groove 8, 8YA, 8YB Y-axis direction groove 10 Dummy metal pattern 100 Semiconductor substrate 101 First interlayer insulating film 102 low-k film ( Interlayer insulation film)
103 Diffusion prevention film 104 Passivation film 105 Wiring layer

Claims (7)

For a semiconductor wafer having a dicing region extending in the X-axis direction and the Y-axis direction between the semiconductor chip regions,
Forming a first groove on the one axial dicing region side of the boundary between the semiconductor chip region and one axial dicing region of the X-axis or Y-axis;
Forming a second groove on the other dicing region side of the boundary between the semiconductor chip region and the other axial dicing region;
Dicing the one axial dicing region to include the first groove, and dicing the other axial dicing region to include the second groove; and
A method for manufacturing a semiconductor device, comprising: Metal having a dicing region extending in the X-axis direction and the Y-axis direction between the semiconductor chip regions, including a crossing portion of the dicing regions in the X-axis and Y-axis directions, and extending in one of the X-axis and Y-axis directions For a semiconductor wafer having a pattern in the dicing area,
In the one axial dicing region, between the metal pattern and the semiconductor chip region, on the one axial dicing region side of the boundary between the semiconductor chip region and the one axial dicing region Forming a first groove;
A step of forming a second groove on the other dicing region side of the boundary between the semiconductor chip region and the other axial dicing region after the first groove forming step;
After the second groove forming step, the one axial dicing region is diced so as to include the first groove, and the other axial dicing region is diced so as to include the second groove. Process,
A method for manufacturing a semiconductor device, comprising: Metal having a dicing region extending in the X-axis direction and the Y-axis direction between the semiconductor chip regions, including a crossing portion of the dicing regions in the X-axis and Y-axis directions, and extending in one of the X-axis and Y-axis directions For a semiconductor wafer having a pattern and a dummy metal pattern in the dicing region in the X-axis and Y-axis directions where the metal pattern is not formed,
In the one axial dicing region, between the metal pattern and the semiconductor chip region, on the one axial dicing region side of the boundary between the semiconductor chip region and the one axial dicing region Forming a first groove;
A step of forming a second groove on the other dicing region side of the boundary between the semiconductor chip region and the other axial dicing region after the first groove forming step;
After the second groove forming step, the one axial dicing region is diced so as to include the first groove, and the other axial dicing region is diced so as to include the second groove. Process,
A method for manufacturing a semiconductor device, comprising: The method of manufacturing a semiconductor device according to claim 2, wherein the metal pattern is a TEG. 5. The method of manufacturing a semiconductor device according to claim 1, wherein a plurality of interlayer insulating films including an interlayer insulating film having a low dielectric constant are stacked on the semiconductor wafer. The first groove and the second groove include an interface between the low dielectric constant interlayer insulating film and an upper layer of the low dielectric constant film, and the low dielectric constant interlayer insulating film and a lower layer of the low dielectric constant film. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the groove has a shape in which the interface is removed. The method for manufacturing a semiconductor device according to claim 1, wherein the first groove and the second groove are formed by laser irradiation.

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