JP2006099719A - Processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a processing device provided with a plurality of reconfigurable circuits. <P>SOLUTION: A processing device 100 is provided with a plurality of reconfigurable units 10 having reconfigurable circuits 12 which can change functions. The reconfigurable unit 10 has RAM 64 which memorizes data output from other reconfigurable units and control part which executes operation control of the RAM. The RAM executes writing of effective data necessary at own reconfigurable circuit among the data output from other reconfigurable units based on the directions by the control parts. The RAM writes-in output of other reconfigurable units by time sharing. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a processing apparatus including a plurality of reconfigurable circuits whose functions can be changed.

In recent years, development of a reconfigurable processor using a multi-functional element having a plurality of basic arithmetic functions called ALU (Arithmetic Logic Unit) has been advanced (for example, see Patent Document 1). In the reconfigurable processor, command data is sequentially set in the ALU circuit, so that a desired arithmetic processing circuit can be realized as a whole. Command data is created as data that compiles a source program written in a high-level programming language such as C language to create a data flow called a DFG (data flow graph) and maps the DFG to an ALU array. . Command data is stored in the command memory.
JP 2004-220377 A

  When executing arithmetic processing in real time, if the frequency of the operation clock is infinitely fast, complex arithmetic processing can be executed in real time with one ALU array, but in reality there is no infinitely fast clock. For this reason, when real-time processing is required, a single ALU array may not be able to satisfy real-time processing requirements due to limitations in the processing capability of the ALU array.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a technique capable of executing high-speed arithmetic processing by using a plurality of reconfigurable circuits.

  In order to solve the above problems, the present invention relates to a processing apparatus including a plurality of reconfigurable units having a reconfigurable circuit whose function can be changed. In this processing apparatus, each reconfigurable unit includes a first storage unit that stores data output from other reconfigurable units, and a control unit that performs operation control of the first storage unit. The first storage unit writes valid data necessary for its own reconfigurable circuit from among data output from other reconfigurable units based on an instruction from the control unit.

  According to such a feature of the present invention, high-speed arithmetic processing can be realized by using a plurality of reconfigurable units. In addition, since the first storage unit executes writing of valid data based on an instruction from the control unit, a plurality of valid data writing operations do not occur at the same time in the first storage unit. Collisions can be avoided.

  Another aspect of the present invention relates to a processing apparatus including a plurality of reconfigurable units having a reconfigurable circuit capable of changing functions. In this processing apparatus, each reconfigurable unit includes a first storage unit that stores data output from its own reconfigurable circuit. The processing device includes: a selection unit that selects data stored in the first storage unit in each reconfigurable unit; and a connection unit that supplies the data selected by the selection unit to inputs of the plurality of reconfigurable units. Is provided.

  According to another aspect of the present invention, high-speed arithmetic processing can be realized by using a plurality of reconfigurable units. In addition, by supplying the data output in each reconfigurable unit to the input of the reconfigurable unit from the connection unit, the reconfigurable unit that needs the data can receive the data, Data transfer between reconfigurable units is facilitated.

  In the above configuration, the reconfigurable circuit may include an arithmetic logic circuit that can selectively execute a plurality of types of multi-bit operations.

  Another aspect of the present invention relates to a processing apparatus including a plurality of reconfigurable units having a reconfigurable circuit capable of changing functions. In this processing apparatus, the reconfigurable unit includes a plurality of first storage units that respectively store data output from the plurality of reconfigurable units. The reconfigurable circuit reads data stored in the plurality of first storage units, respectively.

  In the above invention, the reconfigurable unit has a second storage unit that stores data output from the reconfigurable circuit of the reconfigurable unit, and the plurality of first storage units includes a plurality of reconfigurable units. You may each memorize | store the data memorize | stored in the 2nd memory | storage part of the bull unit.

  In the above invention, the plurality of first storage units may store data output from a plurality of reconfigurable units other than the reconfigurable unit including the plurality of first storage units.

  In the above invention, each of the first storage unit and the second storage unit has at least two storage units, and one storage unit and the other storage unit of the at least two storage units are defined as predetermined. It is also possible to switch between the writing operation and the reading operation at this timing.

  It should be noted that any combination of the above components and the expression of the present invention expressed as a method, apparatus, system, and computer program are also effective as an aspect of the present invention.

  ADVANTAGE OF THE INVENTION According to this invention, the technique which can perform a high-speed arithmetic process can be provided using a some reconfigurable circuit.

  The present embodiment provides a processing apparatus including a plurality of reconfigurable circuits. Below, before explaining a processing apparatus, the reconfigurable unit provided with the reconfigurable circuit which comprises a processing apparatus is demonstrated.

  FIG. 1 is a configuration diagram of a reconfigurable unit including a reconfigurable circuit. The reconfigurable unit 10 includes a reconfigurable circuit 12, a control unit 18, a memory unit 27, and path units 24 and 29. The control unit 18 includes a command memory 61 and a program counter 63 and controls the operation of the reconfigurable circuit 12. The command memory 61 is configured to output stored data based on the count value of the program counter 63. The reconfigurable circuit 12 can change the function by changing the setting. The reconfigurable unit 10 may be configured as a single chip as an integrated circuit.

  The command memory 61 functions as a setting unit that supplies setting data for configuring a desired circuit to the reconfigurable circuit 12. The path unit 24 functions as a feedback path, and connects the output of the reconfigurable circuit 12 to the input of the reconfigurable circuit 12. The data stored in the memory unit 27 is returned to the input of the reconfigurable circuit 12 via the path unit 29. The reconfigurable circuit 12 is configured as a logic circuit such as a combinational circuit or a sequential circuit.

  The memory unit 27 is configured as a RAM and has a storage area for storing a data signal output from the reconfigurable circuit 12 and / or a data signal input from the outside. The reconfigurable circuit 12 generates control data for accessing the memory unit 27. The memory control data includes a write address, a read address, and the like. The write enable signal and the read enable signal for the memory unit 27 are supplied from the command memory 61 to the memory unit 27 at a predetermined timing.

  The reconfigurable circuit 12 includes a plurality of logic circuits whose functions can be changed. Specifically, the reconfigurable circuit 12 includes a configuration in which logic circuits capable of selectively executing a plurality of arithmetic functions are arranged in a plurality of stages, and further includes an output of a preceding logic circuit string and an input of a subsequent logic circuit string. The connection part which can set the connection relationship with is provided. A plurality of logic circuits included in each stage constitutes a collection of logic circuits. This connection unit also has a function of a state holding circuit that holds the output of the preceding logic circuit row, that is, the internal state. The plurality of logic circuits are arranged in a matrix. The function of each logic circuit and the connection relationship between the logic circuits are set based on setting data supplied from the command memory 61. The setting data is generated by the following procedure.

  A program to be realized by the reconfigurable circuit 12 is held in a storage unit (not shown). The program indicates an operation description describing the operation of processing in the circuit, and describes a signal processing circuit or a signal processing algorithm in a high-level language such as C language. The compiler compiles the program, converts it into a data flow graph (DFG), and stores it in the storage unit. The data flow graph expresses the dependency of execution order between operations in a circuit, and shows the flow of operations of input variables and constants in a graph structure. In general, the data flow graph is formed so that the calculation proceeds from top to bottom.

  The data flow graph is converted into setting data. The setting data is data for mapping the data flow graph to the reconfigurable circuit 12, functions of the logic circuit in the reconfigurable circuit 12, connection relations between the logic circuits, constant data to be input to the logic circuit, and the like. Determine. The setting data is stored in the command memory 61 according to the execution order.

  The program counter 63 gives a program counter value to the command memory 61, and the command memory 61 sets the stored setting data in the reconfigurable circuit 12 as command data according to the counter value. Note that the command memory 61 may include a cache memory or another type of memory, and may be configured as a setting data supply unit that supplies setting data to the reconfigurable circuit 12.

  The command memory 61 sets the setting data in the reconfigurable circuit 12 and sequentially reconfigures the circuit of the reconfigurable circuit 12. The reconfigurable circuit 12 uses an ALU having a high-performance computing capability as a basic cell, and the reconfigurable circuit 12 and the command memory 61 are configured on one chip. It can be realized with one clock.

  FIG. 2 shows an example of the configuration of the reconfigurable circuit 12. The reconfigurable circuit 12 has a multi-stage arrangement of logic circuits each capable of selectively executing a plurality of arithmetic functions, and a connection that can arbitrarily set the connection relationship between the output of the preceding logic circuit and the input of the succeeding logic circuit. Part 52. In the reconfigurable circuit 12, the operation proceeds from the upper stage to the lower stage due to the multistage arrangement structure of the logic circuits. In the present specification, “multi-stage” means a plurality of stages. Note that the circuit configuration of the reconfigurable circuit 12 is not necessarily required to have a multi-stage arrangement. However, in order to reduce the circuit scale, it is not possible to connect all the logic circuits. It is preferable to realize the connection.

The reconfigurable circuit 12 has an ALU (Arithmetic Logic Unit) as a logic circuit. The ALU is an arithmetic logic circuit capable of selectively executing a plurality of types of multi-bit operations, and can selectively execute a plurality of types of multi-bit operations such as logical sum, logical product, and bit shift by setting. Each ALU has a selector for setting a plurality of arithmetic functions. In the illustrated example, the ALU is configured to have two input terminals and one output terminal.

  The reconfigurable circuit 12 is configured as an ALU array of X stages and Y columns in which X ALUs in the vertical direction and Y ALUs in the horizontal direction are arranged. Here, a three-stage 6-column ALU array in which three ALUs in the vertical direction and six ALUs in the horizontal direction are arranged is shown. The reconfigurable circuit 12 includes a connection unit 52 and an ALU column 53. The ALU row 53 is provided in a plurality of stages, and the connection unit 52 is provided between the front and rear ALU rows 53 to set the connection relationship between the output of the previous ALU and the input of the rear ALU.

  In the example shown in FIG. 2, a connection section 52b constituting the second stage is provided between the first-stage ALU row 53a and the second-stage ALU row 53b, and the second-stage ALU row 53b and the third-stage ALU row 53b are provided. Between the two ALU rows 53c, a connecting portion 52c constituting the third stage is provided. In addition, the connection part 52a which comprises a 1st stage is provided above the ALU row | line | column 53a of a 1st stage.

  Input variables and constants are input to the first-stage ALU 11, ALU 12,..., ALU 16, and a set predetermined calculation is performed. The calculation result output is input to the second-stage ALU 21, ALU 22,..., ALU 26 according to the connection set in the second-stage connection unit 52b. In the second-stage connection unit 52b, an arbitrary connection relationship between the output of the first-stage ALU column 53a and the input of the second-stage ALU column 53b, or a combination of predetermined connection relationships is selected. The connection connection is configured so as to realize the established connection relationship, and the desired connection is made effective by setting. Further, the connection unit 52b further includes a midway output path 54b for outputting one of the outputs of the first-stage ALU row 53a to the outside. Therefore, the connection unit 52b can supply not only the output of the ALU column 53a to the input of the ALU column 53b but also the output of one of the ALU columns 53a to the outside of the reconfigurable circuit 12.

  The second stage ALU 21, ALU 22,..., ALU 26 receives the output of the ALU column 53a and performs a predetermined calculation. The output of the calculation result is input to the third-stage ALU 31, ALU 32,..., ALU 36 according to the connection set in the connection connection of the third-stage connection section 52c. Similar to the connection unit 52b, the connection unit 52c includes an intermediate output path 54c that outputs one of the outputs of the second-stage ALU row 53b to the outside. Therefore, the connection unit 52c can not only supply the output of the ALU column 53b to the input of the ALU column 53c but also output one output of the ALU column 53b to the outside of the reconfigurable circuit 12.

  The output data from the third-stage ALU column 53 c as the final stage is output to the memory unit 27 or the path unit 24. The memory unit 27 inputs output data to the connection unit 52a via the path unit 29. The connection unit 52a sets the connection for connection and supplies data to the first-stage ALU 11, ALU 12,.

  In the present embodiment, a processing apparatus including a plurality of reconfigurable units 10 having a reconfigurable circuit 12 whose functions can be changed is provided. By cooperating and executing arithmetic processing using a plurality of reconfigurable units 10, it is possible to divide and execute one arithmetic processing by a plurality of reconfigurable units 10, thereby improving the processing speed. Can be realized.

  In order to execute the cooperative process in the plurality of reconfigurable units 10, a process of passing data between the reconfigurable units occurs. At this time, if the data transfer is not properly executed, the meaning of the parallel processing becomes meaningless, so it is necessary to take care in the data transfer. If two or more reconfigurable units 10 simultaneously output valid data required by other reconfigurable units 10, data may collide with each other, and it may not be possible to transfer valid data. If the data output timing can be grasped in advance, the timing can be adjusted. For example, in processing such as conditional branching of a loop control statement, the data output timing may change. It may be difficult to pass valid data. In particular, as the number of reconfigurable units 10 increases, it is difficult in terms of processing power to grasp the processing being executed in each reconfigurable unit 10 in real time and execute arbitration control.

  FIG. 3A shows an example of a program whose output timing differs depending on the for statement. If “a” in the conditional expression “i <a” of the for statement is a variable and the value executed by the process executed prior to the execution of the for statement can take several values of “a”, the value is output as “a”. The timing at which z is output is different.

FIG. 3B is a diagram for explaining the output timing. In accordance with the number of stages of the ALU array shown in FIG. 2, the number of stages of DFG is set to a maximum of three. For example, when “a == 1”, z is output from the first stage of the ALU array of the first mapping. On the other hand, when “a == 4”, z is output from the first stage of the ALU array of the second mapping. As described above, in the case of conditional branching, the output timing of z may not be fixed. As the number of reconfigurable units 10 increases, the output timings of all the reconfigurable units 10 are grasped and arbitration control is executed. It will be difficult to do. In consideration of this point, the processing apparatus of the present embodiment is configured so that data can be smoothly transferred between the reconfigurable units 10.

  FIG. 4 shows a configuration of a processing apparatus including a plurality of reconfigurable units. The processing apparatus 100 includes three reconfigurable units 10a, 10b, and 10c. The number of reconfigurable units 10 is an example, and may be two, or four or more. As shown in FIG. 1, the reconfigurable unit 10 has a self-loop such as path sections 24 and 29 that feed back the output of the reconfigurable circuit 12 that the reconfigurable unit 10 has, but in FIG. Those configurations are omitted. Here, a configuration for the reconfigurable unit 10 to receive data from another reconfigurable unit 10 as an input is shown.

  Each reconfigurable circuit 12 is configured as an ALU array of 3 stages × 6 columns, and has a structure capable of outputting one output from each stage. That is, six ALUs exist in each stage, but the output from one of the ALUs is used as an input to another reconfigurable unit 10. Referring to FIG. 2, one data is output from the first stage ALU column 53a from the midway output path 54b, and one data is output from the second stage ALU column 53b from the midway output path 54c. The Further, one data is output from the selection unit (not shown) from the third-stage ALU column 53c. The ALU that outputs data to the other reconfigurable unit 10 is determined by the setting data supplied from the command memory 61. Data is always output from each stage of each reconfigurable circuit 12. Whether this output is required by other reconfigurable units 10 and valid data to be passed to the other reconfigurable units 10 is used for mapping from the C description to the ALU array structure of each reconfigurable unit 10. The compiler knows when the DFG is created.

  In the processing apparatus 100, the inputs from the other reconfigurable units 10b and 10c to the reconfigurable unit 10a are three outputs from each stage of the reconfigurable unit 10b and from each stage of the reconfigurable unit 10c. It consists of a total of 6 outputs of 3 outputs. As described above, since data is always output from each stage of the reconfigurable circuit 12, the data supplied from the other reconfigurable units 10b and 10c is necessary in the own reconfigurable unit 10a. It is not necessarily valid data, and may be invalid data that is not necessary.

  In order to input six data to the reconfigurable circuit 12a, if six buses are provided, six data can be input to the reconfigurable unit 10a without time difference. However, in reality, in the reconfigurable circuit 12a, it is unlikely that the six data generated in the other reconfigurable circuits 12b and 12c are required at the same time. The reconfigurable units 10a, 10b, and 10c execute independent operations in parallel, and it is considered that the frequency of data transfer between the units is not so high. Therefore, in the processing apparatus 100 of this embodiment, in order to reduce the number of buses, each reconfigurable unit 10 has a RAM 64 that stores a plurality of data output from other reconfigurable units, An internal state holding circuit 60 for temporary storage is provided in front of the RAM 64 so that a plurality of data output from other units can be stored in the RAM 64. The internal state holding circuit 60 may be configured as a plurality of DFFs. Based on the count value supplied from the counter 70, the internal state holding circuit 60 stores a plurality of data supplied from other reconfigurable circuits in each DFF at different timings and at a predetermined cycle. . At this time, the internal state holding circuit 60 stores the data regardless of whether the data supplied from the other reconfigurable unit is valid data necessary for the reconfigurable circuit 12 of the internal state holding circuit 60.

  As shown with respect to the reconfigurable unit 10a, the internal state holding circuit 60a is supplied with outputs from the reconfigurable circuits 12b and 12c in other units. The internal state holding circuit 60a has six DFFs for holding data output from each. Each DFF is provided corresponding to the other reconfigurable circuit 12 and the output stage. The output of each DFF is supplied to the MUX 62a. The MUX 62a functions as a selection unit that selects and outputs data. Since the number of DFFs in the internal state holding circuit 60 is 6, the MUX 62a is configured as a 6: 1 multiplexer, and is stored in the six DFFs of the internal state holding circuit 60 based on the count value supplied from the counter 70. The plurality of pieces of data are selected at different timings at a predetermined cycle and supplied to the RAM 64a. The address counter 66a sets the address value of the RAM 64a.

  Although not shown, the reconfigurable units 10b and 10c other than the reconfigurable unit 10a have the same configuration. In the reconfigurable unit 10b, the output from each stage of the reconfigurable circuits 12a and 12c is supplied to the internal state holding circuit 60b. The MUX 62b selects one of the six data inputs from the internal state holding circuit 60b and outputs it to the RAM 64b. Similarly, in the reconfigurable unit 10c, the output from each stage of the reconfigurable circuits 12a and 12b is supplied to the internal state holding circuit 60c. The MUX 62c selects one of the six data inputs from the internal state holding circuit 60c and outputs it to the RAM 64c.

  In the processing apparatus 100, each reconfigurable unit 10 has a structure including one RAM 64. Therefore, the bus 68 connecting the RAM 64 and the reconfigurable circuit 12 can be realized by a single bus. As a result, the circuit scale can be greatly reduced as compared with the case where six buses are provided.

  In the embodiment, the counter 70 is configured as a hex counter, and supplies the count value to each of the internal state holding circuits 60a, 60b, 60c and the MUXs 62a, 62b, 62c. As a result, output data from each stage of the other reconfigurable unit is stored in the internal state holding circuit 60 at a cycle of once every 6 clocks, and supplied from the MUX 62 to the RAM 64 at a cycle of once every 6 clocks. Is possible.

  Specifically, the counter 70 controls the DFF EN in the internal state holding circuit 60 so that it becomes active at the timing when data is output from each output port of the reconfigurable unit, whereby each reconfigurable unit is controlled. The data output from 10 is stored in the DFF. At the next timing, the MUX 62 supplies the data stored in the DFF to the RAM 64 in a time division manner. At this time, since the data output from each output port of the other reconfigurable unit is not necessarily valid data necessary for the operation in its own reconfigurable circuit, unnecessary invalid data is written to the RAM 64. Control to not. This is controlled by the control unit 18 shown in FIG.

  The control unit 18 controls the operation of the RAM 64 by supplying the write enable signal stored in the command memory 61 to the RAM 64. Based on the instruction supplied from the control unit 18, the RAM 64 can execute writing of valid data necessary for its own reconfigurable circuit 12 from among data output from other reconfigurable units. . As a result, when the output data is valid data, the valid data is stored in the RAM 64 according to the order stored in the internal state holding circuit 60. In the case of invalid data that is not necessary, the write enable signal does not take an active value, and the RAM 64 cannot write invalid data. As a result, it is possible to avoid a situation where unnecessary data is written to the RAM 64, and the capacity of the RAM 64 can be reduced. When data is not written to the RAM 64, the operation of the address counter 66 is stopped.

  FIG. 5 shows a configuration of the RAM 64 provided in the reconfigurable unit. The RAM 64 includes two RAM0 and RAM1. The switching unit (SW) switches the RAM for writing data every predetermined cycle, and the multiplexer (MUX) switches the RAM for reading data for every predetermined cycle. Therefore, in one cycle, RAM0 is set as a data writing RAM and RAM1 is set as a data reading RAM. In the next cycle, RAM0 is set as a data reading RAM and RAM1 is set as a data writing RAM. The Thus, in the RAM 64, the RAM 0 and the RAM 1 are used by switching between the writing operation and the reading operation at a predetermined timing. Thereby, data writing and data reading can be operated independently. Therefore, the reconfigurable unit 10 can read data from the RAM 64 at a desired timing, and can solve the problem of collision between data transferred between the units. Further, according to this method, even when the order of unit output changes, it is only necessary to execute arbitration only for the write operation, and there is an advantage that the control becomes easy.

  FIG. 6 is a timing chart showing the operation of each component in the reconfigurable unit 10a. Each component of the reconfigurable unit 10 a operates in accordance with the output of the counter 70. Here, the six DFFs in the internal state holding circuit 60a are referred to as DFF1, DFF2, DFF3, DFF4, DFF5, and DFF6. DFF1 is connected to the first stage output of the reconfigurable unit 10b (reconfigurable circuit 12b), DFF2 is connected to the second stage output of the reconfigurable unit 10b, and DFF3 is the third stage of the reconfigurable unit 10b. Connect to output. DFF4 is connected to the first stage output of the reconfigurable unit 10c (reconfigurable circuit 12c), DFF5 is connected to the second stage output of the reconfigurable unit 10c, and DFF6 is the third stage of the reconfigurable unit 10c. Connect to output.

  When the counter value is 0, the first-stage output of the reconfigurable unit 10b is stored in the DFF1. Subsequently, when the counter value is 1, the second-stage output of the reconfigurable unit 10b is stored in the DFF2, and at this time, the data stored in the DFF1 is output from the MUX 62a. When the counter value is 2, the third stage output of the reconfigurable unit 10b is stored in the DFF3, and the data stored in the DFF2 is output from the MUX 62a.

  When the counter value is 3, the first stage output of the reconfigurable unit 10c is stored in the DFF 4, and the data stored in the DFF 3 is output from the MUX 62a. When the counter value is 4, the second-stage output of the reconfigurable unit 10c is stored in the DFF 5, and the data stored in the DFF 4 is output from the MUX 62a. When the counter value is 5, the third-stage output of the reconfigurable unit 10c is stored in the DFF 5, and the data stored in the DFF 4 is output from the MUX 62a. If the supplied data is valid data, the controller 18 supplies a write enable signal to the RAM 64a, and the RAM 64a writes the data to the address value specified by the address counter 66a.

  Note that the timing chart shown in FIG. 6 is an example in which data in all time zones is valid data. Therefore, the connection unit 52 in each stage of the reconfigurable unit 10 selects an ALU that outputs valid data, and connects the output line of the ALU to the internal state holding circuit 60 of another reconfigurable unit 10. As described with reference to FIG. 2, the selection of the ALU is executed by setting the connection connection by the setting data.

  When actually mapping the DFG, as shown in FIG. 6, it is rare that valid data is generated with high frequency, and in reality, invalidity that does not need to be supplied to other reconfigurable units 10 is invalid. It is often data. In the case of invalid data, the connection unit in each stage of the reconfigurable unit 10 supplies an appropriate ALU output to the internal state holding circuit 60 of another reconfigurable unit 10. This output can be anything. The invalid data is output from the MUX 62a to the RAM 64a. At this time, the write enable signal for permitting the data writing is not supplied from the control unit 18 to the RAM 64a, so that the invalid data is discarded.

  Specifically, whether the data supplied from the other reconfigurable unit 10 is valid data or invalid data is determined by mapping the setting data supplied from the command memory 61 as described above. This is determined by the compiler when the setting data is generated. Therefore, when the data supplied from the other reconfigurable units 10b and 10c to the MUX 62a is valid data, a W_EN signal that permits data writing is supplied from the command memory 61 to the RAM 64a. Thereby, the RAM 64a can write valid data. On the other hand, when the data supplied from the other reconfigurable units 10b and 10c to the MUX 62a is invalid data, the W_EN signal for permitting data writing is not supplied from the command memory 61 to the RAM 64a. Therefore, the RAM 64a does not write invalid data and can effectively use the storage area. As described above, by invalid data supplied from the other reconfigurable units 10 b and 10 c at the entrance of the RAM 64, complicated arbitration control is not required, and between the other reconfigurable units 10 b and 10 c and the RAM 64. Can be simplified and the circuit scale can be kept appropriate.

  FIG. 7 shows another example of the configuration of a processing apparatus including a plurality of reconfigurable units. The processing apparatus 200 shown in FIG. 7 includes three reconfigurable units 10d, 10e, and 10f. The number of reconfigurable units 10 is an example, and may be two, or four or more. As shown in FIG. 1, the reconfigurable unit 10 is configured to have self-loops such as path sections 24 and 29 that feed back the output of the reconfigurable circuit 12 that the reconfigurable unit 10 has. Those configurations are omitted. Here, a configuration for the reconfigurable unit 10 to receive data from another reconfigurable unit 10 as an input is shown.

  Each reconfigurable circuit 12 is configured as an ALU array of 3 stages × 6 columns, and has a structure capable of outputting one output from each stage. The output configuration of the reconfigurable circuit 12 is as described with reference to FIG.

  In the processing device 200, each reconfigurable unit 10 receives three RAMs 64 that store data output from each stage of its own reconfigurable circuit 12, and outputs from each RAM 64 and selectively outputs them. It has MUX62. Each RAM 64 has the configuration of the RAM shown in FIG. 5 and includes two RAMs 0 and 1. Specifically, the reconfigurable unit 10d includes a RAM 64d_1, a RAM 64d_2, and a RAM 64d_3 that store the output of each stage of the reconfigurable circuit 12d, and a MUX 62d that receives the output of each RAM. The reconfigurable unit 10e includes a RAM 64e_1, a RAM 64e_2, and a RAM 64e_3 that store the output of each stage of the reconfigurable circuit 12e, and a MUX 62e that receives the output of each RAM. The reconfigurable unit 10f includes a RAM 64f_1, a RAM 64f_2, and a RAM 64f_3 that store the output of each stage of the reconfigurable circuit 12f, and a MUX 62f that receives the output of each RAM.

  Data written to each RAM 64 is data to be passed to another reconfigurable unit 10. Data writing to the RAM 64 is executed regardless of the operation of the other reconfigurable unit 10. The compiler that creates the DFG for mapping the C description to the ALU array knows at which timing each reconfigurable unit 10 needs valid data from the other reconfigurable units 10. Therefore, the compiler generates a control signal for controlling the read function of the RAM 64 and the data selection function of the MUX 62 or MUX 80 in consideration of the timing at which valid data is required in another reconfigurable unit. This control signal is stored as setting data in the inter-unit command memory 84 and is output based on the count value of the program counter 86.

  In the processing device 200, the read data from the RAM 64 can be taken out at the timing to be read regardless of the write operation, and each reconfigurable unit 10 is connected to the input port via the connection unit 82. It is sufficient to use only necessary data among the data received. In the connection configuration shown in FIG. 7, when a plurality of reconfigurable units 10 require different data at the same timing, it is easy to adjust the timing by the compiler, and the DFG is used to avoid collision between data. Generate.

  The MUX 62 selects data stored in the three RAMs in each reconfigurable unit 10. The MUX 80 is selected from the RAM 64 in each reconfigurable unit 10 in the MUX 62, and the supplied data is selected between the reconfigurable units 10 and output to the connection unit 82. The connection unit 82 supplies the data selected by the MUX 80 to the inputs of the plurality of reconfigurable units 10. The connection unit 82 is configured as a common bus for the plurality of reconfigurable units 10. It is preferable that the common bus is composed of one and the circuit scale is reduced. The control unit 18 in FIG. 1 supplies the reconfigurable unit 10 with a control signal that determines whether data supplied from the connection unit 82 is received from the input port of the reconfigurable unit 10. As a result, the reconfigurable unit 10 can receive only necessary data, and can easily execute data transfer between the units.

  Hereinafter, the memory capacity of the RAM 64 in the processing device 200 will be considered. Assume that the internal clock of the processing device 200 has a speed 100 times that of one clock of external data input to the processing device 200. In this case, if one clock of the external data is set as one cycle, one cycle corresponds to 100 clocks in the processing device 200.

  In one cycle, the frequency used in another reconfigurable unit is less than the frequency in which data processed in one reconfigurable unit is used again in the same reconfigurable unit. Therefore, the capacity of the RAM 64 can be small. When 1 cycle = 100 clocks and m reconfigurable units 10 are connected, the depth of the RAM 64 with respect to one reconfigurable unit 10 is 100 / m. (100 / m) / 3. In the case of FIG. 7, since m = 3, one depth of the RAM 64 = 11. This consideration shows that the capacity of the RAM 64 can be small. Further, as described above, by reading the data stored in the RAM 64 in a time division manner, it is possible to transfer data between the reconfigurable units with a single connection unit 82. In FIG. 7, inter-unit data is input to each reconfigurable unit using a single bus. However, a structure in which connections between units are executed using a plurality of buses may be used.

  According to the processing device 100 and the processing device 200, it is possible to solve the problem that data transferred between the plurality of reconfigurable units 10 collide with each other, and parallel processing is possible, thereby improving the overall processing capability. In addition, since the buses between the units and the outside can be reduced, it is possible to reduce the circuit scale and the power consumption.

  In the above-described two embodiments, one output is provided from each stage of each unit, but a plurality of outputs may be provided.

  FIG. 8 shows another example of the configuration of a processing apparatus including a plurality of reconfigurable units. The processing apparatus 300 illustrated in FIG. 8 includes four reconfigurable units 10g, 10h, 10i, and 10j. Note that the number of reconfigurable units 10 is an example, and may be three or less, or may be five or more. As shown in FIG. 1, the reconfigurable unit 10 has a self-loop such as path portions 24 and 29 that feed back the output of the reconfigurable circuit 12 provided in the reconfigurable unit 10. However, those configurations are omitted in FIG.

  The reconfigurable unit 10g includes a reconfigurable circuit 12g, an output RAM 64g (second storage unit), a MUX 67g, and input RAMs 69g_1, 69g_2, and 69g_3 (first storage unit).

  The reconfigurable circuit 12g is configured as an ALU array of 3 stages × 6 columns, and has a structure that allows one output from each stage. In FIG. 8, for convenience of explanation, the reconfigurable circuit 12g will be described as having a structure capable of one output from the first stage shown in FIG. The basic configuration of the reconfigurable circuit 12g is as described with reference to FIGS.

  The output RAM 64g stores data output from a predetermined stage (here, the first stage) on the output side of the reconfigurable circuit 12g. The output RAM 64g is not the valid data because the data output from the first stage of the reconfigurable circuit 12g is not necessarily valid for the operation in the other reconfigurable circuits 12h, 12i, 12j. Avoid storing invalid data.

  Specifically, the control unit 94 outputs a write enable signal stored in the inter-unit command memory 95 to the output RAM 64g. When the data output from the first stage of the reconfigurable circuit 12g is valid data necessary for calculation in the other reconfigurable circuits 12h, 12i, and 12j, the output RAM 64g includes the control unit 94. Is supplied with a write enable signal. Based on the write enable signal input from the control unit 94, the output RAM 64g stores the data output from the first stage of the reconfigurable circuit 12g as valid data.

  On the other hand, when the data output from the first stage of the reconfigurable circuit 12g is not valid data, the write enable signal is not input from the control unit 94 to the output RAM 64g. In this case, the output RAM 64g does not store the data output from the first stage of the reconfigurable circuit 12g because the write enable signal is not input from the control unit 94.

  Also, the timing at which each reconfigurable unit 10 needs valid data from the output RAM 64 of another reconfigurable unit 10 is determined by the compiler that creates the DFG for mapping from the C description to the ALU array. I know.

  For this reason, the compiler converts the valid data stored in the output storage unit 64 of one reconfigurable unit 10 (for example, the reconfigurable unit 10g) to the other plurality of reconfigurable units 10 (for example, the reconfigurable unit 10g). In consideration of the timing required by the units 10h, 10i, and 10j), a control signal (including a write enable signal) is generated for controlling the function of writing valid data to the output storage unit 64.

  In other words, the other plurality of reconfigurable units 10 (for example, reconfigurable units 10h, 10i, 10j) are provided in the one reconfigurable unit 10 (for example, reconfigurable unit 10g). The compiler generates a control signal for controlling the function of writing the valid data in the output storage unit 64 at the timing of reading the valid data in the RAM 64 at the same time. This control signal is stored in the inter-unit command memory 95 and is output from the control unit 94 based on the count value of the program counter 96.

  Note that the output RAM 64 of each of the other plurality of reconfigurable units 10 (for example, reconfigurable units 10h, 10i, 10j) is provided in the one reconfigurable unit 10 (for example, reconfigurable unit 10g). The compiler generates a control signal for controlling the function of writing the valid data in the output storage unit 64 at a timing at which valid data is not simultaneously output to the MUX 67.

  The MUX 67g selects data output from the other plurality of reconfigurable units 10h, 10i, and 10j and outputs the selected data to the corresponding input RAMs 69g_1, 69g_2, and 69g_3. The MUX 67g may select data output from the other plurality of reconfigurable units 10h, 10i, and 10j based on the counter value, or may be based on the selection signal output from the inter-unit command memory 95. May be selected.

  Path portions 90a, 90b, and 90c are connected to the MUX 67g. The path unit 90a connects the MUX 67g and the output RAM 64h of the other reconfigurable unit 10h. The path unit 90b connects the MUX 67g and the output RAM 64i of the other reconfigurable unit 10i. The path unit 90c connects the MUX 67g and the output RAM 64j of the other reconfigurable unit 10j.

  Since the number of path units connected to the MUX 67g is three, the MUX 67g is configured as a 3: 1 multiplexer, and one of the path units is selected based on a counter value supplied from a counter (not shown). Are sequentially selected at a predetermined timing, and the data output from the selected path section is output to the corresponding input RAM 69g.

  The input RAMs 69g_1, 69g_2, and 69g_3 store data output from the MUX 67g. Each of the input RAMs 69g_1, 69g_2, and 69g_3 is connected to each stage on the input side of the reconfigurable circuit 12g. Specifically, the input RAM 69g_1 is connected to the connection unit 52a. The input RAM 69g_2 is connected to the connection unit 52b. The input RAM 69g_3 is connected to the connection unit 52c.

  The control unit 94 outputs a control signal that determines whether or not the reconfigurable circuit 12g reads data stored in the input RAM 69g to the reconfigurable circuit 12g. Thereby, the reconfigurable circuit 12g can read only necessary data from the corresponding input RAM 69g.

  Each of the input RAMs 69g_1, 69g_2, 69g_3, and the output RAM 64g has two RAMs 0 and 1 shown in FIG. Each of the input RAMs 69g_1, 69g_2, 69g_3, and the output RAM 64g has a write operation and a read operation at a predetermined timing (here, one cycle) between one of the two RAMs 0 and 1 and the other RAM. Switch to.

  The reconfigurable unit 10h stores the data output from the reconfigurable circuit 12h and a predetermined stage (here, the first stage) of the reconfigurable circuit 12h, similarly to the above-described reconfigurable unit 10g. RAM 64h, MUX 67h for selecting data output from other reconfigurable units 10g, 10i, 10j and outputting to corresponding input RAMs 69h_1, 69h_2, 69h_3, and data selected by MUX 67h are stored. Input RAMs 69h_1, 69h_2, and 69h_3 are included.

  The reconfigurable unit 10i includes a reconfigurable circuit 12i, an output RAM 64i that stores data output from a predetermined stage (here, the first stage) of the reconfigurable circuit 12i, and a plurality of other reconfigurable units. MUX 67i that selects data output from the units 10g, 10h, and 10j and outputs the selected data to the corresponding input RAMs 69i_1, 69i_2, and 69i_3, and input RAMs 69i_1, 69i_2, and 69i_3 that store the data selected by the MUX 67i ing.

  The reconfigurable unit 10j includes a reconfigurable circuit 12j, an output RAM 64j for storing data output from a predetermined stage (here, the first stage) of the reconfigurable circuit 12j, and a plurality of other reconfigurable units. MUX 67j that selects data output from units 10g, 10h, and 10i and outputs the selected data to corresponding input RAMs 69j_1, 69j_2, and 69j_3, and input RAMs 69j_1, 69j_2, and 69j_3 that store data selected by MUX 67j ing.

  Here, in FIG. 7, in order to prevent the ALU column 53 of each stage in the reconfigurable circuit 12 from requesting the data stored in the RAM 64 at the same timing, the compiler includes the ALU column 53 of each stage. The request from one of the ALU columns 53 is prioritized over the request from the other ALU column 53, so that the requests from the ALU columns 53 in each stage do not overlap. That is, the compiler sequentially shifts the requests in time so that the requests of the ALU columns 53 of the stages do not overlap.

  However, when the number of ALU columns 53 in each stage in the reconfigurable circuit 12 increases, the compiler sequentially shifts each request in time so that the requests in the ALU columns 53 in each stage do not overlap. A large number of DFGs must be created. For this reason, the circuit scale in the reconfigurable circuit 12 may be increased by the amount of the DFG created.

  In the connection configuration shown in FIG. 8, the ALU row 53 of each stage in the reconfigurable circuit 12 is connected to the input RAM 69 corresponding to each stage. As a result, two or more ALU columns 53 in the reconfigurable circuit 12 can directly read the data stored in the input RAM 69 corresponding to the respective stages simultaneously regardless of requests from the ALU columns of other stages. Can do.

  This eliminates the need for the compiler to create a large number of DFGs so as not to duplicate requests from the ALU columns 53 at each stage. Further, as much DFG is not created by the compiler, the reconfigurable circuit 12 can reduce the circuit scale and simplify the control operation.

  In the present embodiment, a plurality of input RAMs 69 are provided corresponding to the ALU columns 53 of each stage in the reconfigurable circuit 12, but when only one input RAM 69 is provided, Similar to the configuration shown in FIG. 7 described above, the circuit scale of the reconfigurable circuit 12 is increased.

  Specifically, the ALU columns 53 at each stage in the reconfigurable circuit 12 operate independently. For this reason, if only one input RAM 69 is provided, the ALU column 53 at each stage may simultaneously read data stored in the input RAM 69. In this case, since the request for reading data from the ALU column 53 of each stage is executed at the same time, the operation of the reconfigurable unit 10 is stopped.

  Therefore, as described above, in order to prevent requests from the ALU column 53 at each stage from being executed at the same time, the compiler adds a NOP node indicating a process for performing nothing to the DFG, and from the ALU column 53 at each stage. It is necessary to sequentially shift the requests in time. For this reason, the circuit scale is increased by the amount of the NOP node added to the DFG.

  Therefore, as shown in FIG. 8, the number of input RAMs 69 is not one, but a plurality of input RAMs 69 are provided corresponding to each of the ALU columns 53 in each stage, so that two or more ALU columns 53 can be The data stored in the input RAM 69 corresponding to each stage can be read simultaneously regardless of requests from other ALU columns. This eliminates the need for the compiler to create a DFG for avoiding duplicate requests from the ALU column 53 at each stage. In addition, the reconfigurable circuit 12 can reduce the circuit scale because the DFG is not created.

  The reconfigurable circuit 12 shown in FIG. 8 has been described as having a structure capable of outputting one output from a predetermined stage (here, the first stage). However, the present invention is not limited to this. (See FIG. 2).

  The reconfigurable unit 10 shown in FIG. 8 accepts data output from a plurality of other reconfigurable units 10, but is not limited to this, and is output from the reconfigurable unit 10 that the reconfigurable unit 10 has. The received data may be accepted.

  In the above, this invention was demonstrated based on the Example. It is to be understood by those skilled in the art that the embodiments are exemplifications, and that various modifications are possible in the combination of each component and each processing process, and such modifications are within the scope of the present invention.

It is a block diagram of a reconfigurable unit provided with a reconfigurable circuit. It is a figure which shows an example of a structure of a reconfigurable circuit. (A) is a figure which shows an example of the program from which an output timing differs with a for sentence, (b) is a figure for demonstrating an output timing. It is a figure which shows the structure of the processing apparatus provided with the several reconfigurable unit. It is a figure which shows the structure of RAM provided in a reconfigurable unit. It is a timing chart which shows operation of each composition in a reconfigurable unit. It is a figure which shows another example of a structure of the processing apparatus provided with the several reconfigurable unit. It is a figure which shows another example of a structure of the processing apparatus provided with the several reconfigurable unit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Reconfigurable unit, 12 ... Reconfigurable circuit, 18 ... Control part, 27 ... Memory part, 54 ... Halfway output path, 60 ... Internal state holding circuit, 61 ... Command memory, 62 ... MUX, 63 ... Program counter 64 ... RAM, 66 ... address counter, 67 ... MUX, 68 ... bus, 69 ... RAM, 70 ... counter, 80 ... MUX, 82 ... connector, 84 ... inter-unit command memory, 86 ... program counter, 94 ... control , 95 ... Inter-unit command memory, 96 ... Program counter, 100 ... Processing device, 200 ... Processing device

Claims (13)

A processing apparatus comprising a plurality of reconfigurable units having a reconfigurable circuit capable of changing functions,
The plurality of reconfigurable units are:
A first storage unit for storing data output from other reconfigurable units;
A control unit that performs operation control of the first storage unit,
The first storage unit executes writing of valid data required in its own reconfigurable circuit from among data output from the other reconfigurable units based on an instruction from the control unit. A processing apparatus characterized by the above.   The processing apparatus according to claim 1, wherein the first storage unit writes the output from the other reconfigurable unit in a time-sharing manner. The plurality of reconfigurable units are:
A second storage unit that stores a plurality of data output from the other reconfigurable units at different timings and in a predetermined cycle;
The processing apparatus according to claim 1, further comprising a selection unit that selects data stored in the second storage unit and supplies the data to the first storage unit. The second storage unit stores data output from the other reconfigurable unit regardless of whether the data is valid data necessary in the reconfigurable circuit of the second storage unit;
The selection unit supplies the plurality of data stored in the second storage unit to the first storage unit at different timings and at a predetermined cycle,
The processing apparatus according to claim 3, wherein the first storage unit stores only valid data based on an instruction from the control unit.   The processing apparatus according to claim 4, wherein the first storage unit stores valid data according to an order stored in the second storage unit. A processing apparatus comprising a plurality of reconfigurable units having a reconfigurable circuit capable of changing functions,
The plurality of reconfigurable units includes a first storage unit that stores data output from its own reconfigurable circuit,
The processor is
A selection unit for selecting data stored in the first storage unit in each reconfigurable unit;
And a connection unit that supplies data selected by the selection unit to inputs of the plurality of reconfigurable units.   The processing apparatus according to claim 6, wherein the connection unit is configured as a common bus for the plurality of reconfigurable units.   8. The control unit according to claim 6, wherein the plurality of reconfigurable units include a control unit that determines whether or not data supplied from the connection unit is received from an input of the reconfigurable unit. The processing apparatus in any one.   The first storage unit has at least two storage units, and one of the at least two storage units and the other storage unit are written and read at a predetermined timing. The processing apparatus according to claim 1, wherein the processing apparatus is switched to. A processing apparatus comprising a plurality of reconfigurable units having a reconfigurable circuit capable of changing functions,
The reconfigurable unit has a plurality of first storage units that respectively store data output from the plurality of reconfigurable units,
The processing device, wherein the reconfigurable circuit reads the data stored in the plurality of first storage units. The reconfigurable unit has a second storage unit that stores the data output from the reconfigurable circuit of the reconfigurable unit,
The processing apparatus according to claim 10, wherein the plurality of first storage units respectively store the data stored in the second storage unit of the plurality of reconfigurable units.   The plurality of first storage units respectively store data output from a plurality of reconfigurable units other than the reconfigurable unit including the plurality of first storage units. Item 11. The processing apparatus according to Item 10.   Each of the first storage unit and the second storage unit includes at least two storage units, and one storage unit and the other storage unit of the at least two storage units are set to a predetermined timing. The processing apparatus according to claim 10, wherein the processing is switched between a writing operation and a reading operation.

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