JP2006094541A - Apparatus and method for generation of coefficient - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To generate coefficients used for correcting quantization errors in decoding compressed image data. <P>SOLUTION: Each target pixel in a compressed image data S20 is class-sorted, based on the pixel data in a block with the target pixel set at the center. An error value δy composed of the differential between the true pixel value y of the marked pixel and the decoded value in decoding the marked pixel is found. Error value δy is expressed as a linear combination of quantization codes Q<SB>i</SB>and the coefficients wi for each class-sorted result CLASS. The coefficients w<SB>i</SB>, obtained by using the least squares method are stored in a ROM 23, in advance, corresponding with the class-sorted results CLASS. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a coefficient generation device and a coefficient generation method, and is applied to a case where a coefficient for correcting an image signal used in a compression decoder that decodes an image signal compressed and encoded for transmission or recording is obtained in advance. Can do.

  Conventionally, in a so-called image signal transmission system that transmits an image signal to a remote place, such as a video conference system, or in an apparatus that digitizes an image signal and records and reproduces it on a video tape recorder or a video disk recorder, In order to efficiently use recording media, significant information is efficiently encoded using the correlation of digitized image signals to reduce the amount of transmitted information and recorded information, thereby increasing transmission efficiency and recording efficiency. It is made like that.

  Specifically, the amount of data to be transmitted is greatly reduced by performing high-efficiency compression coding on image data. ADRC (Adaptive Dynamic Range Coding) has been proposed as one method of this high-efficiency encoding (see, for example, Japanese Patent Laid-Open No. 61-144989). ADRC divides input image data into blocks composed of a plurality of pixels, and encodes each pixel data into a number of bits smaller than the number of original quantization bits in the block unit. More specifically, a dynamic range defined by the maximum value and the minimum value of a plurality of pixels included in the two-dimensional block is obtained, and an image signal is encoded with high efficiency by performing encoding suitable for the dynamic range. Turn into.

  An ADRC encoder that realizes this ADRC is configured as shown in FIG. In FIG. 10, an ADRC encoder 1 converts an input image signal S1 into digital data of 8 bits per pixel by an analog digital conversion circuit (A / D) 2 and then supplies it to a block circuit 3. The blocking circuit 3 divides the image data into blocks of about 8 pixels × 8 lines.

  The maximum value calculation circuit 4 calculates the maximum pixel value MAX in the block, and the minimum value calculation circuit 5 calculates the minimum pixel value MIN in the block. The maximum pixel value MAX and the minimum pixel value MIN are supplied to the difference circuit 7, and the minimum pixel value MIN is further supplied to the difference circuit 8 and the framing circuit 10. As a result, the dynamic range DR in the block is output from the difference circuit 7 and sent to the framing circuit 10. Further, the difference circuit 8 performs a difference calculation between each pixel value input via the delay circuit 6 and the minimum pixel value MIN, and sends the difference value obtained as a result to the adaptive quantization circuit 9.

Adaptive quantization circuit 9, when each pixel value in the block and the L _i, the following equation

Requantization based on the operation of As a result, each pixel represented by 8 bits is represented by an n-bit quantization code Q _i smaller than this, and the amount of image information is effectively reduced. The formatting circuit 10 forms final compressed image data S2 by formatting the in-block dynamic range DR, the minimum pixel value MIN, and the quantization code Q _i in accordance with the type of transmission path and recording system.
Thus, the ADRC encoder 1 can obtain the compressed image data S2 in which the amount of information is remarkably reduced as compared with the case of transmitting 8-bit image information per pixel as it is.

The ADRC decoder that decodes the compressed image data S2 that has been compression-encoded is configured as shown in FIG. That is, when the ADRC decoder 11 inputs the compressed image data S2 to the frame decomposition circuit 12, the ADRC decoder 11 decomposes the compressed image data S2 into the minimum pixel value MIN, the in-block dynamic range DR, and the quantization code Q _i , of which the in-block dynamic range DR and The quantization code Q _i is supplied to the adaptive inverse quantization circuit 13 and the minimum pixel value MIN is supplied to the addition circuit 14.

  Here, the adaptive inverse quantization circuit 13 and the addition circuit 14 are expressed by the following equations.

As a result, the decoded value L _i ′ for each pixel is obtained, and this is sent to the block decomposition circuit 15 as decoded image data S3. The block decomposition circuit 15 converts the decoded image data S3 into a television time series by performing the reverse process of the block circuit 3 of the ADRC encoder 1 (FIG. 10). The decoded image data subjected to the block decomposition is converted into an analog signal by the digital / analog conversion circuit 16, and thus the restored image signal S4 is obtained.

  However, in conventional ADRC encoding / decoding, when performing the calculations of equations (1) and (2), a so-called approximate calculation is performed in the division part. For this reason, when the number of ADRC quantization bits is small, there is a problem that the restored image quality deteriorates.

  Conventionally, as one method for solving such a problem, the decoding target pixel is not referred to by obtaining the decoding value only with the pixel to be decoded in consideration of the correlation of the image signal, but also referring to the level of the surrounding pixels. There has been proposed a decoding device that reduces the quantization error at the time of decoding by obtaining the decoded value (Japanese Patent Laid-Open No. 1-200885).

  However, since this type of decoding device refers only to local features of pixels closest to the target decoding pixel, it has an improvement effect, but is still unsatisfactory in terms of obtaining a decoding value close to the true value. There are enough problems. For example, in the region including the surrounding pixels of the target decoding pixel, the pixel value may be offset to either one of the pixel value of the original image as a whole (so-called offset fluctuation). In such a case, even if the decoding target pixel is decoded with reference to the level of the surrounding pixels, there is an error in the entire surrounding pixels, so that an accurate decoded value cannot be obtained.

  The present invention has been made in consideration of the above points, and a coefficient used for correcting a quantization error when decoding compressed image data obtained by block unit encoding such as ADRC is generated in advance. A coefficient generation device and a coefficient generation method are proposed.

  In order to solve such a problem, in the present invention, a class classification block of a predetermined range centering on the pixel of interest is formed from encoded image data obtained by encoding the input learning image data, and the class classification block is blocked. Classify the target pixel using the inner pixel data, obtain a difference value between the true value of the target pixel from the learning image data and the decoded value when the target pixel is decoded by the decoding unit, and the difference value For each classified class is represented by a product-sum operation of the pixel data in the block used for class classification and a predetermined coefficient, the coefficient of the product-sum operation is obtained using the least square method, and the coefficient is classified. And stored in the coefficient storage means.

  As a result, depending on the classified class, for example, when the pixel values in the region including the surrounding pixels of the target decoding pixel are offset to the pixel value of the original image as a whole By effectively correcting the encoded pixel data using the correction value obtained by the product-sum operation of the coefficient read from the coefficient storage means and the pixel data in the block, the error amount including the offset amount can be effectively canceled. Can do.

  As described above, according to the present invention, a class classification block having a predetermined range centered on the pixel of interest is formed from the encoded image data obtained by encoding the input learning image data, and the class classification block contains the block. The pixel of interest is classified using the pixel data, a difference value between the true value of the pixel of interest from the learning image data and the decoded value when the pixel of interest is decoded by the decoding unit is obtained, and the difference value is obtained. For each classified class, it is represented by the product-sum operation of the pixel data in the block used for class classification and a predetermined coefficient, the coefficient of the product-sum operation is obtained using the least square method, and the coefficient is classified into the classified class. When the decompressed image is generated from the compressed image data by associating and storing in the coefficient storage means, each pixel of interest in the compressed image data is classified into a class classification block centered on the pixel of interest. Classify using the inner pixel data, obtain a correction value corresponding to the error amount between the decoded value and the true value by the product-sum operation of the coefficient corresponding to the class and the compressed image data, and use the correction value It is possible to correct the decoding error of the pixel data and obtain a restored image that is very close to the original image.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

(1) Overall Configuration In FIG. 1, in which parts corresponding to those in FIG. 11 are assigned the same reference numerals, 20 indicates an ADRC decoder to which the image data decoding method according to the present invention is applied as a whole. The ADRC decoder 20 has a class classification adaptive processing unit 21. The class classification adaptation processing unit 21 performs class classification adaptation processing on the quantization code Q _i output from the frame decomposition circuit 12, thereby changing the quantization code Q _i to a quantization code Q _i ′ closer to the true value. After the conversion, it is supplied to the adaptive inverse quantization circuit 13.

The class classification adaptive processing unit 21 inputs the quantization code Q _i to the class classification circuit 22 and classifies the pixel of interest using information around the quantization code Q _i of the pixel of interest here, and the classification result The class code CLASS that represents is output. The coefficient ROM 23 stores coefficients previously obtained for each class by learning (this coefficient is a coefficient set made up of a plurality of coefficients), and a coefficient set w corresponding to the class code CLASS is read out. .

The product-sum operation circuit 24 uses the coefficient set w read from the coefficient ROM 23 and the quantization code Q _i of the peripheral pixels of the pixel of interest to

A correction value δ _i for the target pixel is obtained by performing a linear linear combination operation represented by: Then, the addition circuit 25 adds the correction value δ _i of the target pixel and the quantization code Q _i of the target pixel, so that a new quantization code Q _i ′ (= Q _i + δ _i ) for the target pixel is obtained. can get.

The adaptive inverse quantization circuit 13 and the addition circuit 14 use the new quantization code Q _i ′ formed by the class classification adaptive processing unit 21 to

The decoded value L _i ″ is obtained by performing a decoding process based on the above and is output as decoded image data S10. The decoded image data S10 is restored by being sequentially passed through the block decomposition circuit 15 and the digital analog conversion circuit 16. The image signal is S11.

(2) Configuration Example of Class Classification Circuit Here, the class classification circuit 22 is configured as shown in FIG. 2 or FIG. 3, for example. Here, the class classification circuit 30 shown in FIG. 2 and the class classification circuit 40 shown in FIG. 3 basically encode the information of a block in a narrow range centering on the pixel of interest and the information of the block outside it. This is output as a class code CLASS.

  In the compressed image data S2 obtained by encoding in units of blocks like ADRC, the target pixel may be at the boundary of the encoding block. In such a case, the quantization code of the target pixel and its surroundings Therefore, the relationship between the quantization code of interest and the surrounding quantization codes is lost.

Therefore, in the ADRC decoder 20, a block adjustment circuit (not shown) is actually provided in the preceding stage of the class classification circuit 22, and the block adjustment circuit temporarily decodes the quantization code Q _i around the pixel of interest, and the code of the pixel of interest. Based on the dynamic range DR and minimum value MIN of the quantization block, a quantized code Q _i obtained by requantizing the decoded value is supplied to the class classification circuit 22.

(2-1) Configuration example I
First, the class classification circuit 30 shown in FIG. 2 will be described. The class classification circuit 30 inputs the quantization code Q _i input via the frame decomposition circuit 12 (FIG. 1) and a block adjustment circuit (not shown) to the first block circuit 31 and the second block circuit 32. . As shown in FIG. 4, the first blocking circuit forms a first block by the pixel of interest and its surrounding 8 pixels, and the block data is coded via a delay circuit 33 for timing adjustment. 34. Based on the input block data, the encoding circuit 34 outputs a first class code D1 in which quantization codes of 8 pixels around the target pixel are arranged in a predetermined order. In this way, the first class code D1 representing the narrow pixel range distribution pattern around the target pixel is formed.

  As shown in FIG. 4, the second blocking circuit 32 forms a second block by 8 pixels further outside the block formed by the first blocking circuit 31, and detects the maximum value of the blocked data. The data is sent to the circuit 35 and the minimum value detection circuit 36. The maximum value detection circuit 35 and the minimum value detection circuit 36 detect the maximum value and the minimum value in the eight pixels, respectively, and send the detection results to the direction encoding circuits 37 and 38.

  The direction encoding circuits 37 and 38 encode the direction of the maximum value pixel and the minimum value pixel viewed from the center (that is, viewed from the target pixel). Here, since the directions viewed from the center are divided into eight types, each of the direction encoding circuits 37 and 38 outputs a 3-bit direction code. A combination of the direction code of the direction encoding circuit 37 and the direction code of the direction encoding circuit 38 is output as the second class code D2. In this way, the second class code D2 representing the inclination direction of the image around the target pixel is formed.

  The first and second class codes D1 and D2 are synthesized by the subsequent synthesizing circuit 39. As a result, a final class code CLASS combining the first and second class codes D1 and D2 is formed. The code CLASS is output to the coefficient ROM 23.

(2-2) Configuration example II
Next, the class classification circuit 40 shown in FIG. 3 will be described. The class classification circuit 40 inputs the quantization code Q _i to the first block circuit 41 and the second block circuit 42. Similar to the first blocking circuit 31 of FIG. 2, the first blocking circuit 41 forms a first block by the pixel of interest and its surrounding eight pixels. Similarly to the second blocking circuit 32 described above, the second blocking circuit 42 also forms the second block with the outer eight pixels.

  Of the block data generated by the first block circuit 41, the quantized values of the eight pixels around the target pixel are sequentially supplied to the comparison circuit 43 and the quantized value of the target pixel is passed through the memory (D) 44. To the comparison circuit 43. As shown in FIG. 5A, the comparison circuit 43 sequentially compares the quantized value of the target pixel and the quantized values of the surrounding eight pixels. The encoding circuit 45 encodes the comparison result of the comparison circuit 43 with “1” or “0”, and outputs this as the first class code D3.

  The blocked data formed by the second blocking circuit 42 is supplied to the comparison circuit 47 via the delay circuit 46 for timing adjustment. The comparison circuit 47 is supplied with the block data formed by the first block circuit 41 via the average value calculation circuit 48. As a result, as shown in FIG. 5B, the comparison circuit 47 sequentially compares the average value of nine pixels, including the target pixel and the surrounding eight pixels, and the size of the outer eight pixels. The encoding circuit 49 encodes the comparison result of the comparison circuit 47 into “1” or “0”, and outputs this as the second class code D4.

  In this way, the second class code D4 representing the state of the pixels in a wider range compared to the first class code D3 is formed. Incidentally, when the class classification circuit 40 obtains the second class code D4, it uses the value of the target pixel as it is and does not perform comparison with the outer peripheral pixels, and uses 9 pixels including 8 neighboring pixels in advance. By calculating the average value and comparing the average value with the outer 8 pixels, for example, even when the pixel of interest is a singular point or there is noise or the like, these effects are expressed by the second class code. The second class code D4 that accurately represents the state around the target pixel can be formed without reaching D4.

  The first and second class codes D3 and D4 are synthesized by the subsequent synthesis circuit 50. As a result, a final class code CLASS is formed by combining the first and second class codes D3 and D4. The code CLASS is output to the coefficient ROM 23.

(3) Selection of Coefficient Next, a method of selecting the coefficient set w for each class stored in the coefficient ROM 23 will be described. The coefficient set w is obtained by learning using original image data with no image quality deterioration. FIG. 6 shows a configuration of a learning circuit 60 for realizing this. When the learning circuit 60 inputs not the learning image data S20 deterioration in time series conversion 61, wherein the pixel value y of the pixel of interest with respect to the learning image data S20, 8 pixels x ₁ ~x the surrounding ₈ A time series conversion process is performed so as to form one block with (not necessarily 8 pixels), and these 9 pixels y, x _{1 to} x ₈ are supplied to the ADRC encoder 62.

The ADRC encoder 62 has the same configuration as the ADRC encoder 1 described above with reference to FIG. 10, and compresses and encodes input image data, whereby a quantization code Q _i corresponding to each pixel value y, x _{1 to} x ₈ , Compressed image data S21 composed of the dynamic range DR and the minimum value MIN is generated, and the compressed image data S21 is generated by an ADRC decoder 63 having the same configuration as the conventional ADRC decoder 11 described above with reference to FIG. Decrypt.

  The decoded pixel value of the target pixel among the decoded pixel values obtained by the ADRC decoder 63 is supplied to the difference circuit 64. Further, the true pixel value y of the target pixel is supplied to the difference circuit 64 via a delay circuit 65 for timing adjustment. As a result, the difference circuit 64 calculates the difference between the pixel value of the target pixel having the compression decoding error obtained via the ADRC encoder 62 and the ADRC decoder 63 and the true pixel value y of the target pixel that has not been processed. The difference result is sent to the coefficient calculation circuit 66 as an error value δy.

The learning circuit 60 sends the quantization code Q _i output from the ADRC encoder 62 to the class classification circuit 67. The class classification circuit 67 has the same configuration as the class classification circuit 22 (FIG. 1) described above, and forms a class code CLASS representing the class of the target pixel based on a plurality of quantization codes Q _i around the target pixel. The class code CLASS is sent to the coefficient calculation circuit 66. The quantization code Q _i output from the ADRC encoder 62 is given to the coefficient calculation circuit 66 via the delay circuit 68 for timing adjustment.

In this way, the coefficient calculation circuit 66 inputs the class code CLASS, and also inputs the quantization codes Q _{1 to} Q ₈ around the pixel of interest and the error value δy from the true value of the pixel of interest, and the class represented by the class code CLASS Each time, a coefficient W representing the correlation between the error value δy and the quantization codes Q _{1 to} Q ₈ is obtained by learning using the least square method.

That coefficient calculation circuit 66, first quantization code _{Q 1,} Q 2, ......, coefficients _{w 1,} w 2 respectively _{Q 8,} ......, by multiplying _{w 8,} quantization code around the error value δy This is represented by a linear linear combination of Q _{1 to} Q ₈ and coefficients w _{1 to} w ₈ . Specifically, the coefficient calculation circuit 66 calculates the quantization code Q _{(R, S)} (where R = 1, 2,... R, S = 1, 2 ₎ for each of the error values δy _{1 to} δy _r of the same class. ,..., 8) and coefficients w _{1 to} w ₈ and a linear linear combination formula are established, and the coefficients w _{1 to} w ₈ are obtained by the least square method.

To describe this, first, the determinant Y of the error values δy _{1 to} δy _r is expressed by the following equation using the determinant X of the peripheral quantization code Q _{(R, S) and} the determinant W of the coefficients w _{1 to} w _8.

Can be expressed in the form of an observation equation. However, in the formula (5), r represents the number of target pixels of the same class.

Here, the coefficients w ₁ to w ₈ may be obtained by solving the simultaneous equations of equation (5). This is solved by the operation of the least square method. That is, first, using the residual matrix E, the equation (5)

Re-express it in the form of a residual equation like

Here from (6) in order to determine the most probable value of each coefficient _w 1 to w _8, the condition that the ^{_{e 1 2 + e 2 2 +}} ...... + e r 2 to the minimum, i.e. the formula

It is _only necessary to find the coefficients w _{1 to} w ₈ that satisfy the above _eight conditions. Here, from equation (6),

If the conditions of the equation (7) are set for i = 1, 2,..., 8, respectively,

Is obtained. Here, the following normal equation is obtained from the equations (6) and (9).

Here, since the normal equation represented by the expression (10) is a simultaneous equation having only eight unknowns, the coefficients w _{1 to} w ₈ which are the most probable values can be obtained. Exactly according to the _{w i} in equation (10) (ΣQ _jk Q _j1) (however j = 1, ......, r, k = 1, ......, 8, l = 1, ......, 8) is a matrix of If it is regular, it can be solved. Actually, simultaneous equations are solved using Gauss-Jordan elimination (sweeping method).

In practice, the coefficient calculation circuit 66 is configured as shown in FIG. That is, the coefficient calculation circuit 66 inputs the quantization codes Q _{1 to} Q _r and the error value δy to the normal equation generation circuit 70, and the normal equation generation circuit 70 performs normalization as expressed by equation (10) for each class. An equation is generated, and a coefficient set w (w _{1 to} w ₈ ) for each class is obtained by the calculation of the sweep method by the CPU arithmetic circuit 71 that follows.

  The normal equation generation circuit 70 first multiplies each pixel by the multiplier array 72. The multiplier array 72 is configured as shown in FIG. 8, and performs multiplication of pixels for each cell represented by a square, and gives each multiplication result obtained thereby to the adder memory 73.

  As shown in FIG. 9, the adder memory 73 includes an adder array 74 composed of a plurality of cells arranged in the same manner as the multiplier array 72 and a plurality of memory (or register) arrays 75A, 75B,. Has been. Memory arrays 75A, 75B,... Are provided for the number of classes represented by class code CLASS, and one memory array 75A, 75B,... Is responded to the output (class) of class code decoder 77 for decoding class code CLASS. .. Is selected, and the stored values of the selected memory arrays 75A, 75B,... Are fed back to the adder array 74. At this time, the addition result obtained by the adder array 74 is stored again in the corresponding memory arrays 75A, 75B,.

  In this way, the multiply-accumulate operation is performed by the multiplier array 72, the adder array 74, and the memory array 75, and one of the memory arrays 75A, 75B,... For each class determined by the class code CLASS. Are selected, and the contents of the memory arrays 75A, 75B,... Are updated according to the result of the product-sum operation.

The position of each array (10) ΣQ _jk Q _j1 (although according to _{w i} of the normal equation of formula, j = 1, ......, r , k = 1, ......, 8, l = 1 , ..., 8). As apparent from the normal equation (10), if the upper right term is inverted, it becomes the same as the lower left, so each array has a triangular shape.

In this way, a product-sum operation is performed during a certain period, and a normal equation for each class is generated for each pixel position. The result of each term of the normal equation for each class is stored in the memory arrays 75A, 75B,... Corresponding to the respective class, and then each term of the normal equation for each class realizes the sweep method calculation. It is calculated by the CPU arithmetic circuit 71. As a result, a coefficient set w (w _{1 to} w ₈ ) for each class is obtained, and the coefficient set w (w _{1 to} w ₈ ) is written to the address of the corresponding class in the coefficient ROM 23 (FIG. 1).

(4) Operation In the above configuration, the ADRC decoder 20 inputs the quantization code Q _i out of the compressed image data S2 formed by ADRC encoding to the class classification circuit 22, and the class classification circuit 22 pays attention. A block is formed by collecting a plurality of pixel data (quantization code) centering on a pixel (target quantization code), and a class code CLASS is generated based on the information of the block.

Next, the coefficient set w corresponding to the class code CLASS is read from the coefficient ROM 23 using the class code CLASS as a read address. Then, the product-sum operation circuit 24 performs a product-sum operation using the coefficient set w and pixel data (quantization code) around the pixel of interest, so that the adaptive inverse quantization circuit 13 continues the attention quantization code Q _i as it is. The error value δ _i is obtained from the true value generated when decoding is performed.

The ADRC decoder 20 adds in advance an error value δ _i to the quantization code Q _i in the adder circuit 25, thereby canceling in advance the decoding error that occurs during decoding in the adaptive inverse quantization circuit 13. As a result, the corrected quantized code Q _i ′ is decompressed and decoded in the adaptive inverse quantization circuit 13, so that a decoded pixel value substantially equal to a true value is output from the adaptive inverse quantization circuit 13.

Here, the coefficient set w used when calculating the error value δ _i includes the ADRC encoder 62 and the adaptive inverse quantization circuit 13 corresponding to the ADRC encoder 1 (FIG. 10) used when forming the compressed image data S2. Since it is obtained by learning using the true value y included in the original image by the learning circuit 60 constituted by the ADRC decoder 63 and the like, even if the compressed image data S2 fluctuates in offset, An error value δ _{i based} on the true value y can be obtained. Therefore, the ADRC decoder 20 can effectively cancel the offset variation and the compression error at the time of compression coding by the error value δ _i .

(5) Effect According to the above configuration, when decoding the compressed image data S2 that has been compression-encoded to a number of bits smaller than the number of original quantized bits, the compressed image data S2 is classified for each pixel of interest. obtains an error value [delta] _i using coefficient set w in accordance with the classification result cLASS from the pre-original pixel value (true value) y the use connexion the obtained coefficient set w, Yotsute to the error value [delta] _i By correcting the data, a restored image almost equal to the original image can be obtained.

(6) Other Embodiments In the above-described embodiments, the case where the present invention is applied to the ADRC decoder 20 that decodes the compressed image data S2 obtained by ADRC has been described. The present invention is not limited to this, and is widely applied when decoding image data that has been compression-coded in units of blocks such as DCT (Discrete Cosine Transform) coding, DPCM (Differential Pulse Code Modulation), BTC (Block Truncation Coding), etc. Can do.

  In the above-described embodiment, the case where the image data decoding method according to the present invention is realized by hardware as shown in FIG. 1 is described. However, the present invention is not limited to this, and compressed image data is taken into a computer. Thus, calculation processing may be performed by software.

  Further, in the above-described embodiment, the case where the coefficient ROM 22 is used as the coefficient storage means for storing the coefficient corresponding to the class has been described. However, the present invention is not limited to this, and instead of this, a RAM (Random Access Memory), An SRAM or the like may be used.

It is a block diagram which shows the structure of the ADRC decoder to which the image data decoding method by this invention is applied. It is a block diagram which shows the structural example of a class classification circuit. It is a block diagram which shows the structural example of a class classification circuit. It is a basic diagram with which it uses for description of the classification process by the class classification circuit of FIG. It is a basic diagram with which it uses for description of the classification process by the class classification circuit of FIG. It is a block diagram which shows the structure of the learning circuit for calculating | requiring a coefficient. It is a block diagram which shows the structure of a coefficient calculation circuit. It is a rough block diagram which shows the structure of the multiplier array of a coefficient calculation circuit. It is a rough block diagram which shows the structure of the adder memory of a coefficient calculation circuit. It is a block diagram which shows the structure of an ADRC encoder. It is a block diagram which shows the structure of the conventional ADRC decoder.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,62 ... ADRC encoder, 9 ... Adaptive quantization circuit, 11, 20, 63 ... ADRC decoder, 13 ... Adaptive dequantization, 21 ... Class classification adaptive processing part, 22, 30, 40, 67 …… Class classification circuit, 23 …… Coefficient ROM, 60 …… Learning circuit, S1 …… Input image signal, S2, S21 …… Compressed image data, S3, S10 …… Decoded image data, S4, S11 …… Restored image Signal, MAX: Maximum pixel value, MIN: Minimum pixel value, DR: Dynamic range, Q _i , Q _i '... Quantization code, CLASS: Class code, w ... Coefficient group, δ _i ... … Correction value, y …… true value, δy …… error data.

Claims (3)

Input means for inputting learning image data;
A class classification block having a predetermined range centered on the target pixel is formed from the encoded image data obtained by encoding the learning image data, and the target pixel is classified using the pixel data in the block of the class classification block. Classification means,
Difference value calculating means for obtaining a difference value between the true value of the target pixel from the learning image data and a decoded value when the target pixel is decoded by a decoding means;
The difference value is represented by a product-sum operation of pixel data in blocks used for the class classification and a predetermined coefficient for each class classified by the class classification means, and using the least squares method, Coefficient calculation means for obtaining a coefficient;
A coefficient generation device comprising: coefficient storage means for storing the coefficient obtained by the coefficient calculation means in a coefficient storage means in association with a class classified by the class classification means. The coefficient calculation means is
2. The coefficient generation apparatus according to claim 1, wherein the coefficient is obtained by using a sweeping method for a normal equation formed by a plurality of product-sum operations of the pixel data in the block and the coefficient. A class classification block having a predetermined range centered on the target pixel is formed from the encoded image data obtained by encoding the input learning image data, and the target pixel is classified using the pixel data in the block of the class classification block. A classification step to classify,
A difference value calculating step for obtaining a difference value between a true value of the target pixel from the learning image data and a decoded value when the target pixel is decoded by a decoding unit;
The difference value is represented by a product-sum operation of the pixel data in the block used for the class classification and a predetermined coefficient for each class classified by the class classification step, and the product-sum operation is calculated using a least square method. A coefficient calculation step for obtaining a coefficient;
A coefficient generation method comprising: a coefficient storage step for storing the coefficient obtained in the coefficient calculation step in a coefficient storage means in association with the class classified in the class classification step.

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