JP2006091982A - On-chip bus system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an on-chip bus system capable of preventing the degradation of a through-put with a small FIFO configuration. <P>SOLUTION: When a first FIFO 141A in which read data to be outputted from a first slave device 12A are stored is put in a full state, the free space of a second FIFO 141B in which read data to be outputted from a second slave device 12B are stored is confirmed, and the read data are written in the second FIFO 141B when the second FIFO 141B is not put in a full state, and the first FIFO 141A is bypassed under the control a control circuit 142A. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an on-chip bus system in which at least two or more master devices and slave devices that perform point-to-point communication are interconnected via a crossbar switch.

  In recent years, master devices and slave devices such as AXI (Advanced eXtensible Interface) and OCP (Open Core Protocol) perform point-to-point data communication in an on-chip bus system used in a system LSI (large scale integrated circuit). The bus protocol to be performed is becoming mainstream. Compared to a conventional bus protocol in which a plurality of devices are shared by a single data bus, a specific master device and slave device occupy the bus, eliminating the need for an arbitration function between a plurality of devices. High-speed data communication is possible.

  In general, the communication path between the master device and the slave device is called a channel.

  Usually, in an on-chip bus system having devices that perform data communication on these channels, a plurality of master devices and slave devices are interconnected via a crossbar switch and connected to each other in a point-to-point manner. High-speed data communication is performed in parallel between each other (for example, see Patent Document 1).

  In particular, a specific slave device such as a memory controller often concentrates access from a plurality of master devices, and is designed to process this continuously at high speed. Each channel has a FIFO for buffering data transfer for each slave device.

  This is because once the slave device starts transferring read data, if the master device cannot receive all of the read data, it continues data transfer without stopping the processing of the slave device as much as possible. It is necessary to make it.

  Furthermore, in recent years, read split transfer, in which read requests and read data replies are separated and transferred non-sequentially, has become the mainstream. In the bus protocol in this case, the channel is divided into a read request address channel and a read data return read channel. The address channel and the read channel are basically independent, and the master device can issue a plurality of requests to the slave device at a time without waiting for the return of corresponding read data.

  On the other hand, the slave device is capable of continuously processing a plurality of read requests issued in advance, and a conventional bus protocol in which the next request is intermittently issued again after returning read data. In comparison, it is possible to dramatically improve the bus utilization efficiency.

  FIG. 9 is a block diagram showing the configuration of a conventional on-chip bus system. Here, for ease of explanation, only two read devices are shown in the case where there are two master devices and two slave devices. ing.

  In FIG. 9, the on-chip bus system 10 includes master devices 11A and 11B that perform point-to-point data communication, slave devices 12A and 12B, and a crossbar switch 13 that interconnects these devices. The crossbar switch 13 reads from the write control circuits 132A and 132B and FIFOs 131A and 131B that control the writing of read data to the FIFOs 131A and 131B and FIFOs 131A and 131B that temporarily store the read data from the slave devices 12A and 12B. Read control circuits 133A and 133B for controlling data read, and switches 134A and 134B for connecting the master devices 11A and 11B to the slave devices 12A and 12B.

  FIG. 10 is a block diagram showing the configuration of a control circuit for controlling the reading and writing of the FIFOs 131A and 131B in the conventional on-chip bus system 10, in which the same parts as those in FIG. It is.

  In FIG. 10, 1001 is an AND circuit interposed between the slave device 12A (12B) and the FIFO 131A (131B), and 1002 is a NOT interposed between the slave device 12A (12B) and the FIFO 131A (131B). The circuit 1003 is an AND circuit interposed between the FIFO 131A (131B) and the master device 11A (11B), and 1004 is a NOT circuit interposed between the FIFO 131A (131B) and the master device 11A (11B). is there.

  In FIG. 10, a valid signal and a ready signal are both control signals for transferring data. If data transmission is possible on the transmission side, the valid signal is asserted. If data reception is possible on the reception side, the ready signal is asserted. That is, when both the valid signal and the ready signal are asserted, the data on the read data bus is transferred from the transmission side to the reception side. The full signal and the empty signal are signals indicating the states of the FIFOs 131A and 131B. The full signal is asserted when the FIFOs 131A and 131B are full, and the empty signal is asserted when the FIFOs 131A and 131B are empty. The we signal and the oe signal are signals indicating permission to write and output to the FIFOs 131A and 131B, respectively. When the we signal is asserted, writing to the FIFOs 131A and 131B is executed, and when the oe signal is asserted, reading from the FIFOs 131A and 131B is executed.

  Hereinafter, a case where the master device 11A issues a read request to the slave device 12A will be described.

  The slave device 12A prepares read data in response to a read request from the master device 11A, asserts a valid signal, and notifies the crossbar switch 13 that the read data can be transferred. At this time, if the full signal of the FIFO 131A is not asserted and the read data can be written, the write control circuit 132A asserts the ready signal to the slave device 12A, receives the read data, and sequentially receives the read data to the FIFO 131A. Write.

  On the other hand, if the empty signal of the FIFO 131A is not asserted and the read data can be read, the read control circuit 133A asserts the valid signal to the master device 11A via the switch 134A and the read data is transferred. Notify that it is possible. If the master device 11A can receive the read data, the master device 11A asserts the ready signal and sequentially receives the read data. Here, the switch 134A arbitrates the data transfer request from the read control circuits 133A and 133B and selects an appropriate path.

  As described above, the read data from the slave device 12A is transferred to the master device 11A via the FIFO 131A.

  Next, consider a case where the processing of the master device 11A is busy.

  In this case, since the master device 11A cannot receive the read data from the crossbar switch 13, the read control circuit 133A stops reading the read data from the FIFO 131A. That is, the ready signal from the master device 11A is not asserted, and the oe signal of the FIFO 131A is not asserted.

  On the other hand, since the slave device 12A sequentially transfers the read data regardless of the state of the master device 11A, the write control circuit 132A continues to write to the FIFO. When this state continues, the FIFO 131A becomes full, the full signal is asserted, the ready signal is not asserted to the slave device 12A, and the slave device 12A stops transferring read data.

As described above, the master device 11A and the slave device 12A transfer the read data according to the mutual processing capability.
JP 2000-148528 A

  As described above, in the prior art, when the master device processing is busy and the read data from the memory controller cannot be received immediately, the entire channel is busy, and the slave device has the buffer FIFO full. At that time, it was necessary to temporarily stop the read processing.

  In addition, a specific slave device such as a memory controller has a problem that once burst transfer is started, the penalty when interrupted is large, resulting in a decrease in throughput of the entire system. Further, this can be avoided by increasing the size of the FIFO. However, when the size of the FIFO is increased, another problem arises that the gate scale of the entire system is increased.

  The present invention has been made to solve the above-described problems of the prior art, and its purpose is to reduce the processing stop time of the slave device and to prevent the throughput from being lowered with a small FIFO configuration. Is to provide an on-chip bus system.

  In order to achieve the above object, an on-chip bus system according to the present invention comprises an on-chip bus formed by interconnecting at least two or more master devices and slave devices that perform point-to-point communication via a crossbar switch. In the bus system, first storage means for holding read data output from a first slave device, second storage means for holding read data output from a second slave device, and the first storage device When the storage means becomes full, the availability of the second storage means is confirmed. If the storage means is not full, read data is written to the second storage means and control is performed to bypass the first storage means. And a control means.

  According to the present invention, when a channel becomes busy due to concentration of read access to a specific slave device, the slave of the original channel is temporarily bypassed by using the FIFO of another channel. It is possible to reduce the processing stop time of the device and prevent a decrease in throughput with a small FIFO configuration.

  Hereinafter, embodiments of the present invention will be described with reference to FIGS.

(First embodiment)
First, a first embodiment will be described with reference to FIGS.

  FIG. 1 is a block diagram showing the configuration of the on-chip bus system according to the first embodiment. In FIG. 1, the same parts as those in FIG. 9 are denoted by the same reference numerals.

  In FIG. 1, only the read channel is illustrated in the case where there are two master devices and two slave devices for ease of explanation.

  In FIG. 1, an on-chip bus system 10 includes master devices 11A and 11B that perform point-to-point data communication, slave devices 12A and 12B, and a crossbar switch 14 that connects these devices to each other. The crossbar switch 14 temporarily stores read data from the slave devices 12A and 12B. The write control circuits 142A and 142B and FIFOs 141A and 141B that control the writing of read data to the FIFOs 141A and 141B and the FIFOs 141A and 141B. Read control circuits 143A and 143B for controlling data read, switches 144A and 144B connecting the master devices 11A and 11B to the slave devices 12A and 12B, and write to the FIFOs 141A and 141B from the write control circuits 142A and 142B are selected. It consists of a selector 145B.

  2 and 3 are block diagrams showing the configuration of a control circuit that controls the reading and writing of the FIFOs 141A and 141B in the on-chip bus system 10 according to the present embodiment. The parts are given the same reference numerals.

  In FIG. 2, 201 is an AND circuit interposed between the FIFO 141A and the switch 144A, 202 is a NOT circuit interposed between the FIFO 141A and the switch 144A, and 203 is interposed between the FIFO 141B and the switch 144A. The AND circuit 204 is a NOT circuit interposed between the FIFO 141B and the switch 144A.

  In FIG. 2, reading and writing of the FIFOs 141A and 141B perform data transfer by a two-line handshake of a valid signal and a ready signal according to the states of the FIFOs 141A and 141B, respectively. The write control circuit 142A monitors the channel state signal indicating the use status of the FIFO 141B from the other write control circuit 142B. When the FIFO 141A is full and there is a data transfer request from the slave device 12A, the FIFO 141B If the read data can be written to, the write request signal is output to the write control circuit 142B.

  On the other hand, the write control circuit 142B outputs a selection signal for selecting read data from the slave devices 12A and 12B to the selector 145B, and only when the write request signal from the write control circuit 142A is asserted. Read data from the device 12A is selected and written to the FIFO 141B. In other cases, read data from the slave device 12B is selected. A more detailed configuration of the control circuit at this time is shown in FIG.

  3, the same parts as those in FIG. 2 are denoted by the same reference numerals.

  In FIG. 3, one write control circuit 142A located between the slave device 12A and the FIFO 141A includes three AND circuits 301, 302, and 303 and one OR circuit 304. The other write control circuit 142B located between the slave device 12B and the FIFO 141B includes two AND circuits 305 and 306 and one OR circuit 307.

  In FIG. 3, the channel status signal is asserted when the FIFO 141B full signal is not asserted and the slave device 12B is not asserting the valid signal. When the full signal of the FIFO 141A is asserted and the slave device 12A asserts the valid signal, the write request signal is asserted if the channel state signal is asserted. At this time, the ready signal to the FIFO 141A and the selection signal to the selector 145B are also asserted simultaneously.

  Hereinafter, a case where the master device 11A issues a read request to the slave device 12A will be described.

  The slave device 12A prepares read data in response to a read request from the master device 11A, asserts a valid signal, and notifies the crossbar switch 14 that the read data can be transferred. At this time, if the full signal of the FIFO 141A is not asserted and the read data can be written, the write control circuit 142A asserts the ready signal to the slave device 12A, receives the read data, and sequentially receives the read data to the FIFO 141A. Write.

  On the other hand, if the empty signal of the FIFO 141A is not asserted and the read data can be read, the read control circuit 143A asserts the valid signal to the master device 11A via the switch 144A to transfer the read data. Notify that it is possible. If the master device 11A can receive the read data, the master device 11A asserts the ready signal and sequentially receives the read data. Here, the switch 144A arbitrates data transfer requests from the read control circuits 143A and 143B and selects an appropriate path.

  As described above, the read data from the slave device 12A is transferred to the master device 11A via the FIFO 141A.

  Next, consider a case where the processing of the master device 11A is busy.

  In this case, since the master device 11A cannot receive the read data from the crossbar switch 14, the read control circuit 143A stops reading the read data from the FIFO 141A. That is, the ready signal from the master device 11A is not asserted, and the oe signal of the FIFO 141A is not asserted.

  On the other hand, since the slave device 12A sequentially transfers the read data regardless of the state of the master device 11A, the write control circuit 142A continues to write to the FIFO 141A. If this state continues, the FIFO 141A becomes full and the full signal is asserted. In this state, the write control circuit 142A confirms the state of the read channel for the slave device 12B by the channel state signal. If the FIFO 141B is not full and the slave device 12B is not using it, the write control circuit 142A Issue a write request. At this time, the ready signal for the slave device 12A and the selection signal for the selector 145B are asserted, and the read data from the slave device 12A is written into the FIFO 141B. The read data written in the FIFO 141B is transferred to the master device 11A via the switch 144A after the processing of the master device 11A is recovered.

  As described above, according to the present embodiment, when the processing of the master device becomes busy, the slave device continues to transfer the read data until the FIFO becomes full, and further, Even after this, it becomes possible to use the FIFO of another read channel. For this reason, even with the same FIFO configuration, an effect equivalent to temporarily increasing the size of the FIFO can be obtained, and the slave device can continue to transfer the read data without stopping the processing. It is possible to improve the throughput of the entire system.

  In other words, when a communication channel is busy for a specific slave device that has a large penalty when interrupted once burst transfer is started, such as a memory controller, check the usage status of another channel and Otherwise, the read data can be transferred to the other channel without stopping the process.

  Also, when the original channel is detoured, information for in-order processing is added and the data communication between the channels is mutually confirmed, so that the read data can be returned to the master device in the correct order.

(Second Embodiment)
Next, a second embodiment will be described with reference to FIGS.

  FIG. 4 is a block diagram showing the configuration of the on-chip bus system according to the second embodiment. In FIG. 4, the same parts as those in FIG.

  In FIG. 4, only the read channel is illustrated in the case where there are two master devices and two slave devices for ease of explanation.

  In FIG. 4, the on-chip bus system 10 includes master devices 11A and 11B that perform point-to-point data communication, slave devices 12A and 12B, and a crossbar switch 15 that connects these devices to each other.

  The crossbar switch 15 temporarily stores the read data from the slave devices 12A and 12B. The read control circuit 152A and 152B controls the writing of the read data to the FIFOs 151A and 151B and the FIFO 151A and 151B. The read from the FIFOs 151A and 151B. Read control circuits 153A and 153B for controlling data read, switches 154A and 154B for connecting the master devices 11A and 11B to the slave devices 12A and 12B, and write to the FIFOs 151A and 151B from the write control circuits 152A and 152B are selected. And an arbitration circuit 156 that arbitrates the order of the read data.

  FIG. 5 is a diagram showing a state of the read data response field in the on-chip bus system 10 according to the present embodiment.

  Usually, the read data response field is composed of read data 501, master ID 502, and thread ID 503. The master ID 502 is the number of the master that issued the transaction, and the read data 501 is returned to the master device indicated by the master ID 502. ThreadID 503 indicates the thread number of the transaction, and different ThreadIDs may change the order of replies to the master devices 11A and 11B as different threads (out-of-order transfer), but for the same ThreadID, Changing the order of replies is prohibited (in-order transfer).

  In this embodiment, TXID 504 is added as shown in FIG. TXID 504 indicates the transfer number of the transaction in the crossbar switch 15 in the present embodiment.

  Hereinafter, the operation of the on-chip bus system 10 according to the present embodiment will be described.

  First, the basic read data transfer from the slave devices 12A and 12B to the master devices 11A and 11B is the same as that in the first embodiment described above, and the description thereof is omitted. However, when writing the read data to the FIFOs 151A and 151B, the write control circuits 152A and 152B add TXID, respectively.

  This is shown in FIG.

  As described above, TXID indicates the transfer number of the transaction in the crossbar switch 15 in the on-chip bus system 10 according to the present embodiment, and the number 0 indicates special read data from the slave device 12B. . For this reason, the write control circuit 152B always writes the number 0 in TXID. Next, the write control circuit 152A adds the transaction number for each master ID and ThreadID. FIG. 6 shows that there are three transactions of thread 0 for the master device 11A (M0) in the FIFO 151A.

  Next, consider a case where the processing of the master device 11A is busy.

  In this case, the process is the same as that in the first embodiment described above until the FIFO 151A becomes full and the full signal is asserted.

  In this state, the write control circuit 152A confirms the state of the read channel for the slave device 12B, and if the FIFO 151B is not full and does not use the slave device 12B, it issues a write request to the write control circuit 152B. . The write control circuit 152B receives the read data from the slave device 12A and writes it into the FIFO 151B together with the next TXID.

  FIG. 7 shows a state in which the FIFO 151A is full when the fourth transaction of the thread 0 is written to the master device 11A (M0), and the next transaction of the same thread is written to the FIFO 151B.

  FIG. 8 shows a state in which the FIFO 151A is full when the fourth transaction of the thread 0 is written to the master device 11A (M0), and the transaction of the next different thread is written to the FIFO 151B.

  The read data written to the FIFO 151B is transferred to the master device 11A via the switch 154A after the processing of the master device 11A is recovered. At this time, the arbitration circuit 156 monitors the values of ThreadID and TXID from the read control circuits 153A and 153B, and performs arbitration so that these values are returned to the master devices 11A and 11B in the correct order.

  That is, in FIG. 7, even if the two transactions transfer to the first master device 11B (M1) of the FIFO 151B is completed and the transaction to the master device 11A (M0) can be transferred next, the master of the FIFO 151A can be transferred. Not transferred until the fourth transaction for device 11A (M0) is completed.

  On the other hand, in FIG. 8, when the two transactions transfer to the first master device 11B (M1) of the FIFO 151B is completed and the transaction to the master device 11A (M0) can be transferred, the out of Since order transfer is possible, it is possible to transfer immediately.

  As described above, according to the present embodiment, when the processing of the master device becomes busy, the slave device continues to transfer read data until the FIFO becomes full and becomes full. After that, it becomes possible to use the FIFO of another read channel. Furthermore, by adding information for in-order processing and mutually confirming data communication between channels, it is possible to return read data to the master device in the correct order.

(Other embodiments)
The above is the description of the embodiments of the present invention. However, the present invention is not limited to these embodiments, and the functions shown in the claims or the functions of the embodiments can be achieved. Any configuration is applicable.

1 is a block diagram showing a configuration of an on-chip bus system according to a first embodiment. FIG. It is a block diagram which shows the structure of the FIFO control circuit in the on-chip bus system which concerns on 1st Embodiment. It is a block diagram which shows the structure of the FIFO control circuit in the on-chip bus system which concerns on 1st Embodiment. It is a block diagram which shows the structure of the on-chip bus system which concerns on 2nd Embodiment. It is a figure which shows the uniform state of the read data response field in the on-chip bus system which concerns on 2nd Embodiment. It is a figure which shows the uniform state of the state of FIFO and the transfer order in the on-chip bus system which concerns on 2nd Embodiment. It is a figure which shows the uniform state of the state of FIFO and the transfer order in the on-chip bus system which concerns on 2nd Embodiment. It is a figure which shows the uniform state of the state of FIFO and the transfer order in the on-chip bus system which concerns on 2nd Embodiment. It is a block diagram which shows the structure of the conventional on-chip bus system. It is a block diagram which shows the structure of the FIFO control circuit in the conventional on-chip bus system.

Explanation of symbols

10 On-chip bus system 11A Master device A
11B Master device B
12A Slave device A
12B Slave device B
13 Crossbar switch 131A FIFO
131B FIFO
132A Write control circuit 132B Write control circuit 133A Read control circuit 133B Read control circuit 134A Switch 134B Switch 14 Crossbar switch 141A FIFO
141B FIFO
142A Write control circuit 142B Write control circuit 143A Read control circuit 143B Read control circuit 144A Switch 144B Switch 145B Selector 15 Crossbar switch 151A FIFO
151B FIFO
152A Write control circuit 152B Write control circuit 153A Read control circuit 153B Read control circuit 154A Switch A
154B Switch B
155B selector 156 arbitration circuit

Claims (2)

In an on-chip bus system in which at least two or more master devices and slave devices that perform point-to-point communication are interconnected via a crossbar switch,
First storage means for holding read data output from the first slave device;
Second storage means for holding read data output from the second slave device;
When the first storage means becomes full, the availability of the second storage means is confirmed, and if it is not full, read data is written to the second storage means and bypasses the first storage means. And an on-chip bus system characterized by comprising: Information adding means for adding sequence control information when writing read data to the first storage means and the second storage means;
When it is necessary to confirm the order control information when transferring read data from the second storage means to the master device and transfer in-order, specific read data existing in the first storage means 2. The on-chip bus system according to claim 1, further comprising: a second control unit configured to wait until the data is transferred and to transfer the data immediately when the data can be transferred out of order.

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