JP2006086565A - Video signal processing apparatus and video signal recording apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a video signal processing apparatus capable of long-time recording while suppressing image deterioration as much as possible, by encoding a signal in conformity with a general rule, and to provide a video signal recording apparatus including this video signal processing apparatus. <P>SOLUTION: The video signal processing apparatus in the video signal recording apparatus has a video signal encoding circuit 1 for assigning video signal to an I frame, a P frame and a B frame, and orthogonally converting a motion compensation prediction difference value for each data of a frame or each of blocks forming the frame and encoding the value; a replacing code extraction processor 18 for extracting a code corresponding to the B frame among codes generated by the circuit 1; and a code replacing processor 19 for replacing the code, extracted by the processor 18, corresponding to the B frame by a code equivalent to a code encoded, while the extracted motion compensation prediction difference value of the block of the B frame is made to be zero. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a video signal processing apparatus that compresses and encodes a video signal into video data using motion compensation prediction, and a video signal recording apparatus including the video signal processing apparatus.

  A video signal handled in a conventional video signal recording apparatus is configured in units of frames. Since the content of the frame changes with the movement of the video over time, the video signal recording device reduces the redundancy of the video by compressing it by performing motion compensation prediction and recording. It is carried out. The data after motion compensation prediction is subjected to orthogonal transformation, and is encoded with high efficiency by using an MPEG encoding method that encodes the distribution from low frequency components to high frequency components. . At this time, a frame that is compressed using inter-frame correlation such as motion compensation and a frame that is compressed as an independent frame without using inter-frame correlation are distinguished from each other on the time axis. The P frame and the B frame are frames that use motion compensation prediction, and the I frame is a frame that does not use motion compensation prediction. The P frame is a frame obtained by performing motion compensation prediction only in one direction on the time axis, and the B frame is obtained by performing motion compensation prediction in both the positive direction and the negative direction on the time axis. Frame. These types of frame patterns are generally repeated in units of 15 frames. A group of frames in this pattern is called GOP (Group of Pictures). As shown in FIG. 1, normally, one GOP is composed of one I frame, four P frames, and ten B frames, and the frames are rearranged in the encoded state. .

  In conventional video signal recording devices, high-efficiency encoding is performed using motion-compensated prediction as described above, but since the capacity of the recording medium is limited, compression is required when recording for a long time. Increasing the rate and recording at a lower bit rate has been done. However, in this case, since the image quality is deteriorated, there is a limit to substantially reducing the bit rate.

  Conventionally, an improvement measure has been proposed in which compression coding is performed without causing memory overflow by replacing the code with dummy data (see, for example, Patent Document 1). In this method, variable-length codes of “dummy data start code” and “dummy data end code” are provided in the variable-length code table, and dummy data is inserted into the output of the image coding apparatus.

  Further, an improvement measure has been proposed in which encoding is performed with a reduced number of frames when the magnitude of the motion vector is smaller than a predetermined value (see, for example, Patent Document 2).

JP-A-7-184196 (FIG. 1, paragraphs 0086-0089) JP-A-8-111847 (FIGS. 1 and 2, paragraphs 0035-0044)

  However, in the technique disclosed in Patent Document 1, it is necessary to perform encoding lacking in versatility, for example, it is necessary to use a code other than that determined by MPEG, such as a dummy data start code. Yes (that is, the encoding becomes special), and the technique disclosed in Patent Document 1 is used for applications such as DVD (Digital Versatile Disc) players that exchange media for playback. There was a problem that I could not.

  In the technique disclosed in Patent Document 2, since the frame rate defined in MPEG is limited, in a general-purpose encoding method, the number of frames is substantially reduced for a long time. There was a problem that it could not be reduced.

  Therefore, the present invention has been made to solve the above-described problems of the prior art, and its purpose is to perform encoding for a long time while suppressing image quality deterioration by encoding according to general-purpose rules. An object of the present invention is to provide a video signal processing device that enables the video signal processing device and a video signal recording device including the video signal processing device.

  The video signal processing apparatus of the present invention allocates video signals to I frames, P frames, and B frames, and uses the I frame data or motion compensated prediction difference values for each block constituting the P frames and B frames. Video signal encoding means for performing orthogonal transform and encoding; motion compensation prediction difference value switching means for forcibly setting the motion compensation prediction difference value of at least one B frame block of the B frames to zero; It is characterized by having.

  Also, another video signal processing apparatus of the present invention allocates video signals to I frames, P frames, and B frames, and performs motion compensation for each block constituting the data of the I frames or the P frames and B frames. Video signal encoding means for encoding the prediction difference value by orthogonal transformation, replacement code extraction processing means for extracting a code corresponding to a B frame among codes generated by the video signal encoding means, and the replacement code Code replacement processing for replacing a code corresponding to at least one or more B frames extracted by the extraction processing means with a code equivalent to a code encoded with a motion compensated prediction difference value of a block of the extracted B frames as zero Means.

  Still another video signal processing apparatus according to the present invention assigns video signals to I frames, P frames, and B frames, and moves the data of the I frames or the blocks constituting the P frames and B frames. Video signal encoding means for orthogonally transforming and encoding the compensated prediction difference value, replacement code extraction processing means for extracting a code corresponding to a B frame among codes generated by the video signal encoding means, and the replacement And a code replacement processing unit that replaces a code corresponding to at least one of the B frames extracted by the code extraction processing unit with a code converted using a skipped macroblock. Yes.

  The video signal processing apparatus and the video signal recording apparatus according to the present invention comprise a motion compensation prediction difference value switching means for forcibly setting a motion compensation prediction difference value of at least one block of B frames to zero, at least one B or more. Code replacement processing means for replacing the code corresponding to the frame with a code equivalent to the code encoded with the motion compensated prediction difference value of the extracted B frame block set to zero, or corresponding to at least one B frame Code replacement processing means that replaces the code to be replaced with the code converted using the skipped macroblock, so that long-time recording can be realized, and long-time recording can be achieved simply by lowering the bit rate. There is an effect that image quality deterioration can be reduced as compared with the case where it is realized.

  In addition, since the video signal processing apparatus and the video signal recording apparatus according to the present invention perform encoding in accordance with general-purpose rules, the above-described effect that long-time recording can be realized while reducing image deterioration. In addition, there is an effect that the present invention can be applied to an apparatus using a replaceable recording medium such as a DVD.

Embodiment 1 FIG.
FIG. 2 is a block diagram showing the configuration of the video signal processing apparatus according to Embodiment 1 of the present invention. The video signal processing apparatus shown in FIG. 2 is a part of a video signal recording apparatus or a video signal recording / reproducing apparatus such as a DVD recorder or a hard disk recorder. The video signal processing apparatus shown in FIG. 2 may be, for example, a video signal processing circuit (including a case where video signal processing is performed by software) incorporated in a personal computer or the like.

As shown in FIG. 2, the video signal processing apparatus according to Embodiment 1 includes a video signal encoding circuit 1 that compresses a video signal into data and an audio signal encoding circuit 2 that compresses and converts the audio signal into data. A replacement code extraction processor 18 for detecting the B frame, a code replacement processor 19 for replacing the code of the B frame, a packetization processor 20 for packetizing the output of the code replacement processor 19, and speech signal encoding A packetization processor 21 that packetizes the output of the circuit 2 and an AV (audio / visual) multiplexer 22 that multiplexes video data and audio data are provided. As shown in FIG. 2, the video signal encoding circuit 1 includes a subtracter 3, an orthogonal transformer (DCT) 4, a quantizer (Q) 5, a scan converter 6, and an inverse quantization. Unit (Q ⁻¹ ) 7, adder 8, frame memories 9 and 10, frame memory controllers 11 and 12, positive direction motion vector extractor 13, negative direction motion vector extractor 14, and adder 15 And a statistical encoder (VLC) 16 and an elementary header processor 17.

  The video signal encoding circuit 1 converts the video signal into an I frame (Intra-Picture, an intra-frame encoded image), a P frame (Predictive-Picture, an inter-frame forward prediction encoded image), and a B frame (Bidirectionally Predictive- The motion compensated prediction difference value for each block constituting the I frame data or the P frame and the B frame is encoded by orthogonal transformation. At the time of encoding the I frame, the video signal input to the video signal encoding circuit 1 is output to the orthogonal transformer 4 as it is without being subtracted by the subtractor 3. At the time of encoding the P frame, from the video signal input to the video signal encoding circuit 1, a signal of only motion compensation prediction data in the positive direction output from the adder 5 (that is, before the encoding target frame, The video signal (I frame or P frame in FIG. 1) is subtracted. At the time of encoding the B frame, signals of motion compensation prediction data in the positive direction and the negative direction from the I frame or the P frame output from the adder 5 from the video signal input to the video signal encoding circuit 1 (that is, The motion vector is shifted by the motion vector of the frame in the positive direction (prediction from the past frame to the current frame in time) and the frame in the negative direction (prediction from the future frame to the current frame in time). The data for the added video signal) is subtracted.

  Therefore, the motion compensation prediction difference value is output from the subtracter 3 when the P frame or the B frame is encoded, and the input video signal is output as it is when the I frame is encoded. The output of the subtracter 3 is input to the orthogonal transformer 4 and frequency-converted by discrete cosine transform (DCT) or the like. The coefficients transformed by the orthogonal transformer 4 are each quantized by the quantizer 5 and converted into data so that deterioration is not noticeable visually. The data quantized by the quantizer 5 is scanned by the scan converter 6, and a variable length coding (VLC) is performed by the statistical encoder 16 in a combination of the number of consecutive zeros and the value when it is no longer zero. Is done. The data subjected to variable length encoding by the statistical encoder 16 is subjected to header processing of the video code by the elementary header processor 17 and processed into compressed data.

  On the other hand, the output of the quantizer 5 is inversely quantized by the inverse quantizer 7 and is added to the frame data subjected to motion compensation prediction by the adder 8 in order to perform motion vector extraction for motion compensation prediction. . Thereby, the original video for obtaining the motion vector is expanded, and the expanded original video is stored in the frame memories 9 and 10 by the frame memory controllers 11 and 12. The two frame memory controllers 11 and 12 and the two frame memories 9 and 10 are provided because it is necessary to perform motion compensation prediction in the positive direction and the negative direction when predicting the B frame. This is because the motion vector is obtained. If it is a frame for performing positive direction prediction, it is written into the frame memory 9 by the memory controller 11, and if it is a frame for performing negative direction prediction, it is written into the frame memory 10 by the memory controller 12. Further, in order to perform motion compensation in the positive direction, it is best that the forward motion vector extractor 13 performs subtraction by shifting the block (macroblock) for each DCT unit between the input video and the frame memory. A shift amount (i.e., a motion vector) indicating that is extracted. On the other hand, in order to perform negative direction motion compensation, a negative direction motion vector extractor 14 is used. The video shifted by the positive and negative motion vectors is averaged by the adder 15 and the output is supplied to the subtractor 3 which takes the difference of motion compensation prediction.

  The stream that has been subjected to header processing as video data by the elementary header processor 17 passes through the code replacement processor 19 as it is and is input to the packetization processor 20 in the normal mode.

  When the long-time recording mode (the mode is not the normal mode and is the “code replacement mode” by the code replacement processor 19 in the video signal processing apparatus shown in FIG. 2), the elementary header is set. The output stream from the processor 17 is supplied to a replacement code extraction processor 18 and a code replacement processor 19. In the long recording mode, the replacement code extraction processor 18 operates to extract the B frame stream in order to operate so as to replace the B frame code with a very short code.

  In MPEG, since the start of a frame (picture) is always started at '0x00000100', the first detection of each frame can be realized by extracting this code. Here, '0x' means hexadecimal notation, and '0x00000100' means hexadecimal '00000100'. Since 10 bits immediately after the 32-bit start code are allocated to the area indicating the picture number in the GOP, they are ignored. Furthermore, since the 3 bits of data subsequent to the 10 bits indicate the type of the frame, if this part is decoded, it can be determined whether the frame is an I frame, a P frame, or a B frame. Can be determined. If the frame type is '0b011', it is a B frame, and if it is other than that, it is not a B frame, so that the B frame can be uniquely identified. Here, '0b' means binary notation, and '0b011' means binary number '011'.

  In other words, the replacement code extraction processor 18 starts with “0x00000100”, the next 11th to 13th bits are “0b011”, and until just before “0x00000100” to be detected next. Is extracted as a B frame stream, and from what number bit (X address) to what number bit (Y address) of the stream is a B frame, X and Y The address is passed to the code replacement processor 19. The code replacement processor 19 operates to replace the stream from the X address to the Y address with a predetermined code. Here, the predetermined code refers to a code equivalent to a case where the output (motion compensation prediction difference value) of the difference compensation unit 3 for motion compensation prediction becomes zero. When the motion compensation prediction difference value becomes zero, the code amount of the frame becomes very small, so that the data amount is saved and recording can be performed for a longer time.

  The packetization processor 20 receives the output of the code replacement processor 19, performs processing such as time stamp addition, and performs processing to packetize the packet to a length of 1024 bytes or the like. The packetization processor 21 receives the output from the audio signal encoding circuit 2 and performs packetization processing on the audio data in the same manner as the packetization processor 20. The AV multiplexing processor 22 time-multiplexes the compressed video data from the packetizing processor 20 and the compressed audio data from the packetizing processor 21, gives an error correction code, etc. The data is transmitted to a recording unit provided with an information recording medium such as a hard disk or a magnetic tape. In the recording unit, data is recorded on the information recording medium.

  FIG. 3 is a diagram showing the experimental results of the ratio of the data amount of the I frame, P frame, and B frame in the GOP by a pie chart. In the normal mode (that is, a mode other than the long-time recording mode according to the present invention), for example, in a DVD recorder, XP (high image quality) recording mode, SP (standard image quality) recording mode, LP (double time) recording. There are a plurality of recording modes depending on the bit rate such as a mode and an EP (three times time) recording mode. FIG. 3 shows the ratio of the data amount in the EP recording mode.

  As a result of the experiment, the average code amount of GOP was 76629 bytes. Among these, the B frame is 23530 bytes, which is 31% of the whole, and the minimum code amount when the motion compensation prediction difference value is set to zero is 1380 bytes. Therefore, when the long-time recording mode of the present invention is set, a free space of 22150 bytes (= 23530 bytes-1380 bytes) can be obtained. That is, a recording time of about 1.4 times (≈76629 / (76629-22150)) can be achieved. In addition, at this time, by setting the recording time to 1.4 times, there is no excessive image quality degradation of the I frame or P frame. For example, when 6 hours can be recorded in the EP mode in the normal mode, the normal mode is switched to the long-time recording mode (code replacement mode) in the first embodiment, so that 8.4 hours (= 1.4 times × 6 hours). ) Can be recorded. By using the long-time recording mode in the first embodiment, the motion image of the B frame is visually impaired, so that the motion of the image becomes slightly unnatural compared to the case of using the normal mode. However, image quality degradation within one frame is completely the same as that in the EP mode in the normal mode, and there is an advantage that a recording time of more than 8 hours can be achieved.

  FIG. 4 is a diagram showing a procedure for setting the long-time recording mode in the video signal recording apparatus in which the video signal processing apparatus according to the first embodiment is incorporated. As shown in FIG. 4, to set the long-time recording mode, the mode is set on the user interface. According to the present invention, an infrared light receiving unit 25 is provided in the video signal recording device (recorder) 23 having a long-time recording mode according to the first embodiment, and the remote control 24 is used on the television screen connected to the video signal recording device 23. A button operation is performed to select the long-time recording mode (UP) display 26. By such a simple operation, it is possible to set recording in the long-time recording mode. Although FIG. 4 has been described as the first embodiment, the same setting can be made in the second and third embodiments described later. Note that the method for setting the long-time recording mode is not limited to the procedure shown in FIG.

  In the above description, the operation of replacing the code of the B frame when the long-time recording mode according to the present invention is selected has been described. However, in the case of the B frame, a method of fixing the output of the differentiator 3 to zero. May be adopted. FIG. 5 is a block diagram showing a configuration of a modification of the video signal processing apparatus according to Embodiment 1 of the present invention. In FIG. 5, the same reference numerals are given to the same or corresponding components as those shown in FIG. The video signal processing apparatus shown in FIG. 5 is a motion for forcibly setting the motion compensated prediction difference value (that is, the output of the difference unit 3 of the video signal encoder 1a) of at least one B frame block to zero. 2 is different from the video signal processing apparatus shown in FIG. 2 in that the compensated prediction difference value switching unit 40 is provided and the rewritten code extraction processing unit 18 and the code replacement processing unit 19 are not provided. According to the video signal processing device shown in FIG. 5, as with the video signal processing device shown in FIG. 2, long-time recording can be realized while suppressing deterioration in image quality as much as possible.

  FIG. 6 is a diagram showing a concept of a replacement code for realizing the long-time recording mode in the video signal processing apparatus according to the first embodiment. FIG. 6 explains the replacement operation of the code replacement processor according to the first embodiment in another form. In the B frame and the P frame, macroblocks are encoded in order, but video signals such as NTSC and PAL have 720 pixels in the horizontal direction of the screen, and therefore, 45 macroblocks (= 720 ÷ 16). Exists. A group of these 45 macroblocks (first to 45th macroblocks) is called a slice. In the slice, as shown in FIG. 6, it is allowed to skip the encoding of the macroblock, and such a code is called a skipped macroblock. Normally, one macroblock must be encoded, but skipped macroblocks can be encoded together.

  FIG. 7 is a diagram for specifically explaining data for one slice in the video signal processing apparatus according to the first embodiment. FIG. 7 shows a case where data for one slice is encoded with 5 bytes. It is coded that 1 is assigned as a variable length code representing zero which is the shortest code as a motion vector, a macro block escape code is placed next to the motion vector, and the macro block address is advanced 33 at a stroke. Furthermore, the code arrangement is such that the macroblock address increment value is set to 10, so that the addresses of a total of 43 macroblocks are incremented at once, and the codes representing the types of the first macroblock and the 45th macroblock are as follows: A minimum code is obtained by assigning a code representing non-encoding. Although FIG. 7 has been described as the first embodiment, similar settings can be made in the second and third embodiments described later.

When encoding is performed as described above, the field motion appears as jerkiness (a phenomenon in which the operation appears jerky) after performing a decoding process that performs decompression during reproduction. Thin field decimation processing may be added. FIG. 9 is a block diagram showing a configuration for performing a thinning process in the video signal processing apparatus according to Embodiment 1 of the present invention. In FIG. 9, the same or corresponding components as those shown in FIG. In FIG. 9, the thinning processor 41 converts the input video signal into a progressive video signal by thinning out the fields, and inputs it to the video signal encoding circuit 1b. In the case of performing field thinning processing in the DVD, it is determined that thinning is also performed in the horizontal direction. Therefore, in the case of NTSC, thinning processing is performed so as to obtain horizontal 352 pixels and vertical 240 pixels. Before performing this thinning process, an anti-aliasing measure is taken with a low-pass filter (LPF). Moreover, since the number of macroblocks included in one slice is 22 (= 352 ÷ 16) by thinning out to be horizontal 352 pixels, the macroblock address increment is set to '0b00010100 without using the macroblock escape. If ', only the first macroblock and the 22nd macroblock need be assigned to the non-coding type. At this time, the code amount allocated to one slice is 4 bytes. Since the slice start code is 4 bytes and the picture header and the picture extension header are 18 bytes,
The shortest code length of the B frame in the case of 720 pixels × 480 pixels is
18 + 30 × (5 + 4) = 288 bytes, and the shortest code length of the B frame in the case of 352 pixels × 240 pixels is
18 + 15 × (4 + 4) = 138 bytes.

  Depending on the encoding circuit form, even if the motion compensated prediction difference value is forcibly set to zero, the skipped macroblock as described above is not used. The most efficient encoding result can be obtained in the case of adopting. Although FIG. 8 has been described as the first embodiment, the same setting can be made in the second and third embodiments described later.

Embodiment 2. FIG.
FIG. 10 is a block diagram showing a configuration of a video signal processing apparatus according to Embodiment 2 of the present invention. 10, the same or corresponding components as those shown in FIG. 2 are denoted by the same reference numerals. The video signal processing device shown in FIG. 10 replaces the packetization processor 20a that packetizes the output of the elementary header processor 17 in the video signal encoding circuit 1c, and depacketizes the output of the packetization processor 20a. It has a depacketization processor 27 that outputs the depacketized code to the code extraction processor 18 and the code replacement processor 19, and a repacketization processor 28 that packetizes the output of the code replacement processor 19. This is different from the video signal processing apparatus shown in FIG. According to the video signal processing device shown in FIG. 10, as with the video signal processing device shown in FIG. 2, long-time recording can be realized while suppressing deterioration in image quality as much as possible.

  The elementary header processor 17 outputs compressed video data with a header. The packetization processor 20 adds a time stamp or the like to the output data from the elementary header processor 17 to form a fixed-length packet. Depending on the configuration of the LSI or the like, a packetized signal may be output, and the second embodiment corresponds to such a case. When the data packetized by the packetization processor 20 is output from the LSI, the depacketization processor 27 performs depacketization processing for removing the packet in order to replace the B frame with a short code. The output data is not processed by the depacket processor 27, the code replacement processor 19, and the repacketizer 28 in the normal mode (a mode other than the long time mode according to the present invention), and the signal is Pass as it is.

  When the long-time recording mode is set, the output stream of the depacket processor 27 is supplied to the replacement code extraction processor 18 and the code replacement processor 19. In the long recording mode, the replacement code extraction processor 18 operates to extract the B frame stream in order to operate so as to replace the B frame code with a very short code.

  In MPEG, since the start of a frame (picture) is always started at “0x00000100”, the first detection of each frame can be realized by extracting this code. Since 10 bits immediately after the 32-bit start code are allocated to the area indicating the picture number in the GOP, they are ignored. Further, since the data type 3 bits following the 10 bits represents the frame type, if this part is decoded, it can be determined whether the frame is an I frame, a P frame, or a B frame. Can be determined. If the frame type is '0b011', it is a B frame, and if it is not, it is not a B frame, so that the B frame can be uniquely identified.

  In other words, the replacement code extraction processor 18 starts with “0x00000100”, the next 11th to 13th bits are “0b011”, and the code immediately before the next code “0x00000100” is B It is extracted that the stream is a frame, and what number bit (X address) to what number bit (Y address) of the stream is a B frame, and the X and Y addresses are It is passed to the code replacement processor 19. The code replacement processor 19 operates to replace the stream from the X address to the Y address with a predetermined code. Here, the predetermined code refers to a code equivalent to a case where the output (motion compensation prediction difference value) of the difference compensation unit 3 for motion compensation prediction becomes zero. When the motion compensation prediction difference value becomes zero, the code amount of the frame becomes very small, so that the data amount is saved and recording can be performed for a longer time. In this long recording mode, the repacketization processor 28 receives the output of the code replacement processor 19, performs processing such as time stamping, and packetizes the packet to a length of 1024 bytes or the like.

  The repacketization processor 28 receives the output of the code replacement processor 19, performs processing such as time stamp addition, and performs processing of packetizing to a length of 1024 bytes or the like. The packetization processor 21 receives the output from the audio signal encoding circuit 2 and performs packetization processing on the audio data in the same manner as the packetization processor 20. The AV multiplexing processor 22 time-multiplexes the compressed video data from the repacketizing processor 28 and the compressed audio data from the packetizing processor 21, and adds an error correction code or the like. The data is transmitted to a recording unit equipped with an information recording medium such as a DVD, hard disk, or magnetic tape. In the recording unit, data is recorded on the information recording medium.

  In the second embodiment, since the signal is processed as described above, the circuit configuration in which the LSI or the like performs up to the packetization process is an optimal form in which recording can be performed for a long time. Such an LSI has a cost-effective configuration.

  In the second embodiment, points other than those described above are the same as in the first embodiment.

Embodiment 3 FIG.
FIG. 11 is a block diagram showing a configuration of a video signal processing apparatus according to Embodiment 3 of the present invention. In FIG. 11, the same or corresponding components as those shown in FIG. In the video signal processing apparatus shown in FIG. 11, the encoding circuit 29 includes a packetization processor 20 that performs packetization processing of the video data output from the elementary header processor 29, and the audio signal encoding circuit 2. A packetizing means 21 for packetizing the audio data output from the audio signal encoding circuit 2, and an AV multiplexing processor 22 for multiplexing the packetized video signal and the audio signal, and , An AV separation processor 30 that separates a video signal and an audio signal from an output signal of the AV multiplexing processor 22, a depacketization processor 27, a repacketization processor 28, and an AV multiplexing processor 31. This is different from the video signal processing apparatus of the first embodiment shown in FIG. According to the video signal processing apparatus shown in FIG. 11, as with the video signal processing apparatus shown in FIG. 2, it is possible to realize long-time recording while suppressing deterioration of image quality as much as possible.

  In the third embodiment, data obtained by multiplexing compressed video and audio is output from the AV multiplexing processor 22 and separated by the AV separation processor 30. In the long recording mode, the AV separation processor 30 extracts video packets from the output data of the encoding circuit 29. The packet packet extracted is subjected to depacket processing for removing the packet in order to replace the B frame with a short code by the depacket processor 27. For this output data, the output stream of the depacket processor 27 is supplied to the replacement code extraction processor 18 and the code replacement processor 19. In the long recording mode, the replacement code extraction processor 18 operates to extract the B frame stream in order to operate to replace the B frame code with a very short code.

  In MPEG, since the start of a frame (picture) is always started at “0x00000100”, the first detection of each frame can be realized by extracting this code. Since 10 bits immediately after the 32-bit start code are allocated to the area indicating the picture number in the GOP, they are ignored. Further, since the data type 3 bits following the 10 bits represents the frame type, if this part is decoded, it can be determined whether the frame is an I frame, a P frame, or a B frame. Can be determined. If the frame type is '0b011', it is a B frame, and if it is not, it is not a B frame, so that the B frame can be uniquely identified.

  In other words, the replacement code extraction processor 18 starts with “0x00000100”, the next 11th to 13th bits are “0b011”, and the code immediately before the next code “0x00000100” is B It is extracted that the stream is a frame, and what number bit (X address) to what number bit (Y address) of the stream is a B frame, and the X and Y addresses are It is passed to the code replacement processor 19. The code replacement processor 19 operates to replace the stream from the X address to the Y address with a predetermined code. Here, the predetermined code refers to a code equivalent to a case where the output (motion compensation prediction difference value) of the difference compensation unit 3 for motion compensation prediction becomes zero. When the motion compensation prediction difference value becomes zero, the code amount of the frame becomes very small, so that the data amount is saved and recording can be performed for a longer time.

  In this long recording mode, the repacketization processor 28 receives the output of the code replacement processor 19, performs processing such as time stamping, and packetizes the packet to a length of 1024 bytes or the like. On the other hand, since the audio data packet which is audio is output from the AV separation processor 30, the repacketized video data is time-multiplexed with the AV remultiplexing processor 31 for error correction. A recording process is performed by assigning a code or the like. In the normal mode, the data operates so as to pass through the AV separation processor 30, the depacket processor 27, the code replacement processor 19, the repacketization processor 28, and the AV remultiplex processor 31 as they are.

  In the third embodiment, since the signal is processed as described above, the circuit configuration in which the LSI or the like performs up to the packetization process is an optimal form that can perform recording for a long time. Such an LSI has a cost-effective configuration.

  Next, a method for deriving a VBV (Video Buffering Verifier) delay value when performing code replacement processing in the long-time recording mode will be described. The VBV delay value represents the processing timing for the compressed data to be able to be decoded without buffer failure during reproduction / decompression, and is a value that determines the transition of the VBV buffer.

FIG. 12A is a diagram showing the transition of the VBV buffer of the virtual decoder during recording in the normal mode, and FIG. 12B is the transition of the VBV buffer of the virtual decoder during recording in the long-time recording mode. FIG. 12A and 12B, the horizontal axis indicates time, the vertical axis indicates the VBV buffer occupation amount, and the solid line indicates the transition of the VBV buffer. 12 by a solid line in the VBV buffer in (a) the slope a _N represents the transfer rate of the play stream in the recording of the normal mode. The head of the I picture is carried out filling the VBV buffer at a transfer rate a _N, decoding is started tau _N0 hours after represented by VBV delay value. At that time, d _N0 which is the data amount of the I picture is extracted from the VBV buffer. Filling of the next picture is started as soon as the filling of the first picture is completed. Similarly, after τ _N1 hours, the data amount d _N1 is extracted from the VBV buffer.

At this time, the difference X _N0 between the filling start times of adjacent pictures is X _N0 = τ _N0 + Δf−τ _N1
It is represented by Here, Δf is a display frame interval, which is 1 / 29.97 in NTSC. Also, d _N0 = a _N · X _N1 between the transfer rate a _N and the code amount d _N0
There is a relationship.

On the other hand, the long-time recording stream shown in FIG. 12B has the same relationship as the normal stream. That means
X _T0 = τ _T0 + Δf−τ _T1
d _T0 = a _T · X _T1
It is. Here, X _T0 is the difference in filling start time between the first I picture and the next picture in the long-time recording stream, X _T1 is the difference in filling start time between the second picture and the third picture in the long-time recording stream, τ _T0 is the VBV delay value of the first I picture of the long-time recording stream, τ _T1 is the VBV delay value of the second picture of the long-time recording stream, d _T0 is the data amount of the first I picture of the long-time recording stream, and a _T is This is the transfer rate of the long recording stream. Further, assuming that the filling amount of the leading VBV buffer is the same between the normal stream and the long-time recording stream, a _N · τ ₀ = a _T · τ _T0
The relationship is guided.

This is the content indicated by the broken lines in FIGS. 12 (a) and 12 (b). From the above, the VBV delay value of the long-time recording stream is τ _T0 = a _N / a _T · τ ₀
τ _T1 = τ _T0 -d _T0 / a _T + Δf
τ _T2 = τ _T1 −d _T1 / a _T + Δf
The relationship is guided. That is, the VBV delay value of the long-time recording stream can be obtained from the transfer rate a _N of the normal stream, the transfer rate a _{T of} the long-time recording stream, and the VBV delay value τ _{0 of the first} picture in the long-time recording stream. As described above, in general, the VBV delay value is not obtained by simulating the transition of the VBV buffer as in the case of obtaining the VBV delay value, but the VBV delay value of the long-time recording stream is obtained by the above simple arithmetic calculation. be able to.

  In the above description, the method of deriving the VBV delay value of the long-time recording stream by calculation has been described. However, the long-time recording stream can also be configured by replacing all the VBV delay values with the fixed value '0xFFFF'. The VBV delay value of “0xFFFF” is a value indicating that the stream is a VBR (Variable Bit Rate). On the other hand, when a value other than '0xFFFF' is entered as the VBV delay value, CBR (Constant Bit Rate) is indicated. In MPEG-2, since CBR is defined as a special form of VBR, there is no problem with setting the generated special reproduction stream to VBR. In this case, calculation processing related to the VBV delay value is not required at all, and only data replacement is required, so that higher speed processing is possible.

  12A and 12B has been described as the third embodiment, the same setting can be made in the first and second embodiments.

  In the third embodiment, points other than the above are the same as those in the first or second embodiment.

It is a figure which shows the structure of GOP in MPEG. It is a block diagram which shows the structure of the video signal processing apparatus which concerns on Embodiment 1 of this invention. It is a figure which shows the experimental result of the ratio of the data amount of I frame, P frame, and B frame which occupies in GOP by a pie chart. 6 is a diagram showing a procedure for setting a long-time recording mode in the video signal processing apparatus according to Embodiments 1 to 3. FIG. It is a block diagram which shows the structure of the modification of the video signal processing apparatus which concerns on Embodiment 1 of this invention. 6 is a diagram showing a concept of a replacement code for realizing a long-time recording mode in the video signal processing device according to Embodiments 1 to 3. FIG. 6 is a diagram for specifically explaining data for one slice in the video signal processing device according to Embodiments 1 to 3. FIG. 6 is a diagram for explaining field thinning processing in the video signal processing device according to Embodiments 1 to 3. FIG. It is a block diagram which shows the structure of the other modification of the video signal processing apparatus which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structure of the video signal processing apparatus which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structure of the video signal processing apparatus which concerns on Embodiment 3 of this invention. 6 is a diagram for explaining a method of calculating a VBV delay value in the video signal processing device according to Embodiments 1 to 3. FIG.

Explanation of symbols

1, 1a, 1b, 1c Video signal encoding circuit, 2 Audio signal encoding circuit, 3 Subtractor, 4 Orthogonal transformer (DCT), 5 Quantizer (Q), 6 Scan converter, 7 Inverse quantizer (Q ⁻¹ ), 8 adder, 9,10 frame memory, 11, 12 frame memory controller, 13 positive direction motion vector extractor, 14 negative direction motion vector extractor, 15 adder, 16 statistical encoder (VLC) ), 17 elementary header processor, 18 replacement code extraction processor, 19 code replacement processor, 20, 21 packetization processor, 22 AV multiplexing processor, 23 video signal recording device (recorder), 24 remote control, 25 Light receiving unit of video signal recording device, 26 button display indicating long-time recording mode, 27 depacketizing processor, 28 repacketizing processor, 29 Encoding circuit, 30 AV separation processor, 31 AV remultiplexing processor, 40 motion compensation prediction difference value switch, 41 decimation processor.

Claims (11)

Video in which video signals are allocated to I frame, P frame, and B frame, and the data of the I frame or the motion compensated prediction difference value for each block constituting the P frame and B frame is orthogonally transformed and encoded. Signal encoding means;
A video signal processing apparatus comprising: motion compensation prediction difference value switching means for forcibly setting a motion compensation prediction difference value of at least one B frame block of the B frames to zero.   A first mode in which the motion-compensated prediction difference value switching unit directly applies the motion-compensated prediction difference value of a block of a B frame to the video signal encoding unit; and the motion-compensated prediction difference value switching unit has at least one B frame 2. The apparatus according to claim 1, further comprising mode setting means for forcibly setting a motion compensation prediction difference value of each block to zero and selecting one of the second modes given to the video signal encoding means. Video signal processing device. Video in which video signals are allocated to I frame, P frame, and B frame, and the data of the I frame or the motion compensated prediction difference value for each block constituting the P frame and B frame is orthogonally transformed and encoded. Signal encoding means;
Replacement code extraction processing means for extracting a code corresponding to a B frame among the codes generated by the video signal encoding means;
A code equivalent to a code obtained by encoding a code corresponding to at least one B frame among the B frames extracted by the replacement code extraction processing unit with a motion compensation prediction difference value of a block of the B frame as zero. A video signal processing apparatus comprising: a code replacement processing unit that replaces Video in which video signals are allocated to I frame, P frame, and B frame, and the data of the I frame or the motion compensated prediction difference value for each block constituting the P frame and B frame is orthogonally transformed and encoded. Signal encoding means;
Replacement code extraction processing means for extracting a code corresponding to a B frame among the codes generated by the video signal encoding means;
Code replacement processing means for replacing a code corresponding to at least one of the B frames extracted by the replacement code extraction processing means with a code converted using a skipped macroblock. A characteristic video signal processing apparatus.   A first mode in which the code corresponding to the B frame extracted by the replacement code extraction processing means passes through the code replacement processing means as it is, and the B frame extracted by the replacement code extraction processing means in the code replacement processing means 5. The method according to claim 3, further comprising mode setting means for selecting any one of a second mode for replacing a code corresponding to at least one of the B frames. Video signal processing device.   6. The video signal processing according to claim 3, further comprising: a thinning unit that converts the video signal input to the video signal encoding unit into a progressive video signal by thinning a field. apparatus.   7. The video signal processing apparatus according to claim 3, further comprising packetization processing means for packetizing the output of the code replacement processing means. First packetization processing means for packetizing the output of the video signal encoding means;
Depacketization processing means for depacketizing the output of the first packetization processing means and outputting the depacketized code to the replacement code extraction processing means and the code replacement processing means;
The video signal processing apparatus according to claim 3, further comprising: a second packetization processing unit configured to packetize an output of the code replacement processing unit. First packetization processing means for packetizing video data obtained by the video signal encoding means;
Second packetization processing means for packetizing audio data;
Multiplexing processing means for multiplexing the output from the first packetization processing means and the output from the second packetization processing means;
Separation processing means for separating video data and audio data from the output from the multiplexing processing means;
The video signal processing apparatus according to any one of claims 3 to 6, wherein the video data separated by the separation processing means is input to the replacement code extraction processing means and the code replacement processing means. .   10. The video signal processing apparatus according to claim 9, wherein the code replacement processing unit recalculates a VBV delay value and performs code replacement using the recalculated VBV delay value. A video signal processing device according to any one of claims 1 to 10,
A video signal recording apparatus comprising: recording means for recording the compressed data output from the video signal processing apparatus.

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