JP2006085363A - Test bench system, program and storage medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve accuracy of verification of a circuit when simultaneously operating a plurality of test scenarios in parallel. <P>SOLUTION: A start order selection part of each of the test scenarios G1, G2 is inputted with random designation information outputted by a random designation part, determines start order of a plurality of tests constituting a test group included inside the respective test scenarios G1, G2 corresponding to the random designation information, and decides the start order of the tests of the test group. The determination and the decision are randomly performed by the random designation information. Each test inside the test group is sequentially started in the set order, and simulation is executed. The simulation is executed in simultaneous operation in parallel with the test scenarios G1, G2. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a test bench system that verifies the operation of a circuit, a program that realizes the test bench system, and a storage medium that stores the program.

  For a test bench system for verifying a circuit such as an LSI (Large Scale Integrated Circuit) constituting an ASIC (Application Specified IC), for example, a technique disclosed in Patent Document 1 is known.

JP 2002-230073 A

  In recent years, the operation speed of LSIs has been increased, and many functions are integrated in one LSI due to improvements in microfabrication technology. Therefore, technical improvement, accuracy improvement, productivity improvement, etc. of the test bench for verifying the ASIC constituting such an LSI are important issues.

  In order to improve the test bench technology, accuracy, and productivity, first, the test model that performs bus settings connected to the ASIC and the test scenarios that perform various settings are handled separately, so that the test bench productivity and reuse can be improved. It may be possible to improve the performance and to verify the simultaneous operation in the ASIC in which a plurality of data paths exist.

  However, in such a test bench system, when a plurality of test scenarios are operated in parallel, a plurality of tests in each test scenario operate sequentially (serially).

  Therefore, in a large-scale, high-function LSI in recent years, there is a problem that a failure may occur due to an unexpected combination of corner case timings.

  It is an object of the present invention to improve the accuracy of circuit verification by allowing a test included in each test scenario executed in parallel to be changed at random when a plurality of test scenarios are operated in parallel. It is to improve.

  The present invention operates a bus model connected to a circuit to be verified and a plurality of test scenarios used for verifying the operation of the circuit using the bus model in parallel, and operates in parallel. Means for randomly selecting a test in each of the test scenarios.

  From another aspect, the present invention operates a bus model connected to a circuit to be verified by bus and a plurality of test scenarios used for verifying the operation of the circuit using the bus model in parallel. A computer-readable program for causing a computer to execute means for randomly selecting a test in each of the test scenarios operating in parallel.

  According to the present invention, when a plurality of test scenarios are operated simultaneously in parallel, the test included in each test scenario being executed in parallel can be randomly changed, so that the accuracy of circuit verification is improved. be able to.

  The best mode for carrying out the present invention will be described.

  FIG. 1 is a functional block diagram of a test bench system 1 according to the present embodiment. The test bench system 1 is a device that verifies the operation of the circuit 2 to be verified. Circuit 2 is an ASIC in this example. The test bench system 1 is a bus model that is bus-connected to the circuit 2, that is, a CPU bus model 3 that is a bus function model corresponding to the CPU interface of the circuit 2, and a bus function model that corresponds to the interface of the circuit 2. Interface (I / F) bus models 4 and 5. In this example, the I / F bus models 4 and 5 can function as a bus function model corresponding to a circuit data input interface and a circuit data output interface.

  Test scenarios G1 and G2 are test scenarios corresponding to the I / F bus models 4 and 5, respectively. In the test scenarios G1 and G2, the CPU bus model 3 is activated to set the circuit 2 and activate the operation. Also, the corresponding test scenarios G1 and G2 activate the operations of the I / F bus models 4 and 5, respectively. When the operation activation of each I / F bus model 4, 5 is set, each I / F bus model 4, 5 starts operation with respect to the circuit 2. In this embodiment, an example in which two I / F bus models and two test scenarios are prepared is shown, but the present invention does not limit the number of these.

  The error control unit 6 is activated when an error occurs due to simulation execution from the test scenarios G1 and G2 and the I / F bus models 4 and 5, and executes control to interrupt or end the simulation.

  The random designation unit 7 individually gives random designation information to each of the test scenarios G1 and G2 at the start of simulation (described later).

  FIG. 2 is a functional block diagram showing the configuration of each of the test scenarios G1 and G2. Since the test scenarios G1 and G2 have the same configuration and operation, the common configuration and operation will be described with reference to FIG. The activation order selection unit 11 of each test scenario G1, G2 receives random designation information output from the random designation unit 7, and a plurality of tests are included in each test scenario G1, G2 corresponding to this random designation information. The starting order of the group 12 (test 1 to test N) is determined, and the starting order of the test group 12 (test 1 to test N) is determined. This determination and determination is performed randomly based on random designation information. Tests 1 to N in the test group 12 are sequentially activated in the set order, and simulation is performed. Further, the test scenarios G1 and G2 can operate simultaneously and execute a simulation.

  As a result, the activation of the test group 12 of each test scenario G1, G2 varies, and when the test scenarios G1, G2 are operated simultaneously, the tests 1 to N of the test scenario G1, and the test A plurality of operation combinations can be realized for the combinations of the test 1 to the test N in the scenario G2, and many operation timings generated by combinations of operation states of the respective I / F bus models 4 and 5 can be verified. The verification accuracy of the circuit 2 can be improved.

  In addition, when the activation order of the test groups 12 of the test scenarios G1 and G2 is determined, the activation order selection unit 11 outputs the activation order information, which is information on the activation order, to the outside and displays the log.

  As a result, it is possible to know the test schedule that is currently being simulated, to present valuable information as information to be analyzed when a failure occurs, and to improve analysis efficiency. In addition, even when the test bench is completed normally, it functions as the test bench functional coverage, and it is possible to know in what combination the simulation was performed.

  That is, in the above-described case, since a plurality of tests in each test scenario G1, G2 are activated at random, a person in charge (scenario designer, circuit designer, etc.) is required when a failure is discovered and analyzed. Since it is not possible to recognize in which order the tests are executed, it may take time to narrow down the conditions. In particular, a failure recognized for the first time by simultaneous operation of the test scenarios G1 and G2 is likely to be caused by a combination of a plurality of factors, and analysis of the factors becomes difficult.

  Therefore, when the simulation is executed and the test startup order of each test scenario G1, G2 is determined, the test startup order of each test scenario G1, G2 is displayed in the log, thereby clarifying the current conditions and improving the analysis efficiency. Can be improved. It also functions as a function coverage for confirming in what combination the test bench is verified.

  The test progress confirmation unit 13 recognizes which test is currently being performed among the tests 1 to N, and every time the test on which the simulation is performed is changed, which test is currently being performed. Test information that is information on whether or not This test information is output to the error control unit 6. The error control unit 6 is activated when the above-described error occurs, and based on the test information given from the test scenario, determines whether the test being executed is the test 1 to the test N when an error is found, Error information, which is information indicating which error occurred during execution of which test, is output to the outside.

  Thereby, the operation status of each I / F bus model 4 and 5 at the time of simultaneous operation of the test scenarios G1 and G2 is clarified, and the efficiency of failure analysis can be improved.

  That is, in the above case, when the error control unit 6 finds an error, it can display an error message specific to the test included in each test scenario G1, G2, but the error only appears as a result. The cause of the error is not necessarily in the I / F bus model 4 or 5 corresponding to the test scenario G1 or G2 displaying the error message. The other I / F bus model 5 or 4 does not affect the self, but there may be a behavior that affects the other I / F bus model 4 or 5. Then, after displaying an error message for a test of a certain test scenario G1 or G2, by displaying error information indicating a test operating at that time in another test scenario G2 or G1, test scenarios G1 and G2 are displayed. It becomes possible to clarify the specific factor in the simultaneous operation of the two, and the analysis efficiency can be improved.

  Next, a specific hardware configuration example of the test bench system 1 will be described. FIG. 3 is a block diagram of the electrical connection of the test bench system 1. As shown in FIG. 3, the test bench system 1 is realized by a computer such as a workstation. The computer performs various operations and centrally controls each unit, and a memory 212 including various ROMs and RAMs. Are connected by a bus 213.

  The bus 213 is connected to a magnetic storage device 214 such as a hard disk, an input device 215 such as a keyboard and a mouse, and a display device 216 via a predetermined interface, and a predetermined communication for communicating with the network 201. An interface 219 is connected. As the storage medium 217, various media such as an optical disk such as a CD and a DVD, a magneto-optical disk, and a flexible disk can be used. As the storage medium reading device 218, specifically, an optical disk device, a magneto-optical disk device, a flexible disk device, or the like is used according to the type of the storage medium 217.

  The test bench system 1 becomes operable by reading the program 220 for executing the program of the present invention from the storage medium 217 for implementing the storage medium of the present invention and installing it in the magnetic storage device 214. These programs 20 may be downloaded and installed via a network 201 such as the Internet. Note that the program 220 may operate on a predetermined OS.

  The bus 213 is connected to the circuit 2 via a predetermined interface 221. The CPU 211 executes processing based on the program 220, and the CPU bus model 3, the I / F bus models 4 and 5, the error control unit 6, the random designation unit 7, the activation order selection unit 11, and the test progress confirmation unit 13 are A test process is performed to check whether the operation of the circuit 2 is normally performed using the test group 12 of the test scenarios G1 and G2. The display of the log is performed by the display device 216.

It is a functional block diagram of the test bench system which is one embodiment of the present invention. It is a functional block diagram of a test scenario. It is a block diagram of the electrical connection of a test bench system.

Explanation of symbols

1 Test bench system 2 Circuit 3, 4, 5 Bus model 12 Test group 217 Storage medium 220 Program G1, G2 Test scenario

Claims (7)

A bus model that is bus-connected to the circuit to be verified;
Means for simultaneously operating a plurality of test scenarios used for verifying the operation of the circuit using the bus model, and randomly selecting a test in each of the test scenarios operating in parallel;
Equipped with a test bench system.   2. The test bench system according to claim 1, wherein when the random selection order is determined, the selecting means outputs information on the order to the outside.   When a predetermined error occurs due to the execution of the verification, it further comprises means for outputting information on which test is operating in each test scenario to the outside when the error occurs. Item 3. A test bench system according to item 1 or 2. A bus model that is bus-connected to the circuit to be verified; and
Means for simultaneously operating a plurality of test scenarios used for verifying the operation of the circuit using the bus model, and randomly selecting a test in each of the test scenarios operating in parallel;
A computer-readable program that causes a computer to execute.   The program according to claim 4, wherein the selecting means outputs information of the order when the order of the random selection is determined.   When a predetermined error occurs due to the execution of the verification, it further comprises means for outputting information on which test is operating in each test scenario to the outside when the error occurs. Item 6. The program according to item 4 or 5. A storage medium storing the program according to any one of claims 4 to 6.

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