JP2006080399A - Semiconductor device and method for manufacturing it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device with an insulating resin layer having a good adhesion formed in a through-hole and with a via (a through-hole conductive part) formed through it. <P>SOLUTION: The semiconductor device has a semiconductor substrate 1 with an element integrated and formed on its surface, a through-hole 2 penetrating through the semiconductor substrate, a first insulating resin layer 5 formed on the sidewall surface of the through-hole, a second insulating resin layer 6 formed on the front-back both surfaces of the semiconductor substrate, a first conductive layer formed on the first insulating layer in the through-hole, and a second conductive layer 7 formed on the second insulating resin layer and conducted with the first conductive layer. The method for manufacturing the semiconductor device comprises the steps of forming the through-hole by irradiating laser to the semiconductor substrate, filling the insulating resin in the through-hole, forming a resin through-hole in the filled insulating resin in a concentricity fashon, and forming a via for conducting the surface and the rear surface of the semiconductor substrate by forming the conductive layer on the sidewall surface of the resin through-hole. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device for a multichip package on which a plurality of semiconductor chips are mounted, and a manufacturing method thereof.

  In recent years, electronic devices, particularly computers and communication devices, have been used with semiconductor chips having small and large-scale integrated circuits as functions have increased. As a method for increasing the degree of circuit integration in a small size, there are proposed an SOC (System On Chip) in which circuits are integrated on one chip and an SIP (System In Package) in which a plurality of chips are integrated in one package. Among these systems, in particular, SIP can be used in combination with existing chips, so that the cost for designing and processing a semiconductor substrate (wafer) can be suppressed.

  A multi-chip package having a structure in which a plurality of chips are stacked and mounted is being put into practical use. As a package that can be most compact and highly integrated, a structure in which a through via hole is conventionally formed in a chip and stacked. Packages have been proposed

For example, a hole that does not penetrate the substrate is formed in the semiconductor substrate by a method such as RIE (reactive ion etching), photoetching, or wet etching, and an insulating film such as Si ₃ N ₄ or SiO ₂ is formed in the hole by LPCVD or the like. A semiconductor device having a structure in which a conductive material is exposed by embedding a conductive material in a hole and then retreating (thinning) the semiconductor substrate from the back surface by a method such as grinding has been proposed.
(For example, see Patent Document 1)

  However, in such a method for forming a semiconductor device, a hole is formed in the semiconductor substrate by using a method such as RIE or wet etching, and a mask exposure process is required. There was a drawback of becoming.

In addition, an insulating layer is required between the silicon on the wall surface of the through hole and the conductor layer for forming the via hole. However, in the case of drilling by the RIE method, when the insulating layer is formed using an insulating resin, adhesion There is a problem that the reliability is low and the reliability is low. Therefore, in the method described in Patent Document 1, a method of forming an insulating film in the hole by a CVD method or the like is employed, but it takes time to deposit the insulating film, and the cost is high. In the case of increasing the thickness of the insulating film in order to reduce the parasitic capacitance, there is a problem that it takes more time and costs are increased.
JP-A-10-223833

  The present invention has been made to solve such a problem. An insulating resin layer having good adhesion is formed in a through hole, and a via (through-hole conducting portion) is formed through the reliability. It is an object to provide a highly reliable semiconductor device and a manufacturing method for obtaining such a semiconductor device.

  A semiconductor device according to one embodiment of the present invention includes a semiconductor substrate, a through hole penetrating the semiconductor substrate, a first insulating resin layer formed on a side wall surface of the through hole, and a front surface and a back surface of the semiconductor substrate. A second insulating resin layer formed in a predetermined region of at least one surface of the first insulating layer; a first conductor layer formed on the first insulating resin layer in the through hole; and the second insulating layer. A second conductor layer formed in a predetermined region on the resin layer and electrically connected to the first conductor layer is provided.

  A method of manufacturing a semiconductor device according to one aspect of the present invention includes a step of irradiating a semiconductor substrate with elements integrated and formed on a surface thereof to form a through hole, and a step of filling the through hole with an insulating resin. And forming a conductive layer on the side wall surface of the resin through hole formed in the insulating resin, concentrically forming a resin through hole having a smaller diameter than the through hole in the insulating resin filled in the step, And a step of forming a via (through hole conducting portion) for conducting the front surface and the back surface of the semiconductor substrate.

  According to the semiconductor device of one embodiment of the present invention, an insulating resin layer having a favorable thickness and insulating property is formed on the side wall surface of the through hole, and is suitable for stacking a plurality of chips (through hole conducting portion). Can be obtained in a short process time without incurring an increase in cost.

  In addition, according to the method for manufacturing a semiconductor device of one embodiment of the present invention, a highly reliable semiconductor device can be obtained in which the insulating resin layer formed on the side wall surface of the through hole has good adhesion.

  Hereinafter, modes for carrying out the present invention will be described. Although the embodiments will be described with reference to the drawings, the drawings are provided for illustration, and the present invention is not limited to the drawings.

  FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to the first embodiment of the present invention. In this figure, reference numeral 1 denotes a silicon substrate on which elements (active elements or passive elements, for example, active elements) are integrated and formed on the surface, and the silicon substrate 1 has through holes 2 penetrating the front and back. ing. The through holes 2 are formed by laser irradiation, and the side wall surfaces thereof are made of amorphous silicon. A silicon wiring layer 3 and an Al electrode (pad) 4 are formed on the surface (element surface) of the silicon substrate 1.

  A layer 5 made of a first insulating resin is formed on the side wall surface of the through hole 2 made of amorphous silicon. Here, as the first insulating resin, polyimide resin, benzodicyclobutene resin, epoxy resin, phenol resin, cyanate ester resin, bismaleimide resin, bismaleimide-triazine resin, polybenzoxazole, butadiene resin, silicone resin, Polycarboxylic diimide, polyurethane resin or the like is used.

  In addition, second insulating resin layers 6 are formed in predetermined regions on the front surface and the back surface of the silicon substrate 1, respectively. The second insulating resin and the first insulating resin may be the same type or different types.

  Further, there are Ti, Ni, Cu, V, Cr, Pt, and the like on the first insulating resin layer 5 in the through hole 2 and the bottom of the through hole 2 and around the through hole 2 on the surface side of the silicon substrate 1. A conductor layer 7 such as Pd, Au, or Sn is formed. An electrode 8 is formed at the end of the through hole 2 on the back side of the silicon substrate 1.

  A via (through-hole conducting portion) is formed by the conductor layer 7 formed in the through hole 2, and the Al electrode 4 portion on the surface (element surface) of the silicon substrate 1 and the electrode 8 on the back surface through the via. Is connected. It should be noted that Ti, Ni, Cu, V, Cr, Pt, Pd, Au, Sn, etc. can be used as the conductor constituting the electrode 8.

  In 1st Embodiment comprised in this way, since insulating resin (1st insulating resin) is used as an insulating material which covers the side wall surface of the through-hole 2, in addition to being low-cost, insulating The thickness can be increased stably and good insulation and reliability are ensured.

  Further, since the side wall surface of the through hole 2 is made of amorphous silicon and the insulating resin layer 5 is formed thereon, the adhesion of the insulating resin layer 5 to the base material is good. That is, since silicon and the resin material as a base material generally have poor adhesion, when an insulating resin layer is formed in the through-hole 2 formed in the silicon substrate 1 by the RIE method or the like, the insulating resin layer and its resin The thermal stress caused by the difference in thermal expansion coefficient between the conductor layer formed on the silicon and silicon tends to cause peeling / cracking of the insulating resin layer. In the semiconductor device of the first embodiment, the through hole 2 Is formed by laser irradiation, and the side wall surface of the through hole 2 has an amorphous structure, so that the insulating resin layer 5 has high adhesion and a highly reliable via hole is formed.

  Next, a second embodiment of the present invention will be described. 2 to 4 are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to the second embodiment.

  In the second embodiment, first, as shown in FIG. 2A, a silicon wafer 10 having elements integrated and formed on a surface is prepared, and a holding tape (BSG tape) 11 is pasted on the surface (element surface). Then, backside polishing is performed. At this time, in order to increase the bending strength, a process such as dry polishing, RIE, or CMP may be performed last. In the figure, reference numeral 12 denotes a silicon wiring layer formed on the surface (element surface) of the silicon wafer 10, and 13 denotes an Al electrode (pad) connected to the circuit.

  Next, the BSG tape 11 is peeled off and, as shown in FIG. 2B, the holding tape 14 is pasted on the back surface, and then the silicon wafer 10 is irradiated with laser to form the through holes 15. A YAG laser having a wavelength of 355 nm can be used, but the wavelength of the laser is not limited to this. A hole may be formed in the holding tape 14 simultaneously with the opening of the silicon wafer 10.

  In addition, after drilling with a laser, cleaning (cleaning) may be performed as necessary, and a protective film is formed in advance on the surface of the silicon wafer 10 in preparation for scattered matter at the time of drilling, This protective film may be removed after drilling.

  Next, as shown in FIG. 2C, an insulating resin 16 such as polyimide is printed from the element surface side of the silicon wafer 10, and the insulating resin 16 is filled in the through holes 15. As the insulating resin 16, polyimide resin, benzodicyclobutene resin, epoxy resin, phenol resin, cyanate ester resin, bismaleimide resin, bismaleimide-triazine resin, polybenzoxazole, butadiene resin, silicone resin, polycarboxylic diimide, polyurethane Resins selected from resins and the like can be used.

  The filling of the insulating resin 16 by printing may be performed in a vacuum. In printing in vacuum, voids in the insulating resin 16 can be eliminated. The filling of the insulating resin 16 into the through hole 15 can also be performed by a roll coat method. Since the holding tape 14 is also perforated and the through hole 15 is opened on the holding tape 14 side, the filling of the insulating resin 16 into the through hole 15 is easy and reliable.

  Next, as shown in FIG. 2D, the insulating resin 16 formed on the element surface of the silicon wafer 10 is removed by polishing. This step is performed as necessary. Thereafter, if necessary, the insulating resin 16 protruding from the rear surface after polishing the holding tape is polished to flatten the rear surface of the silicon wafer 10. This polishing may not be performed if the amount of the insulating resin 16 protruding from the back surface is small.

  Next, as shown in FIG. 2 (e), after holding the holding tape 14 on the element surface of the silicon wafer 10, an insulating resin film 17 is formed on the back surface. As this insulating resin, for example, a polyimide resin can be used, and it can be formed by spin coating or printing. Further, it may be formed by a roll coat method or a curtain coat method. Although the insulating resin film 17 can be formed at a low cost by adopting a method of applying a liquid insulating resin, a method of attaching a dry film may be adopted.

Next, as shown in FIG. 3 (f), the back surface of the silicon wafer 10 is bonded to the glass support 19 through an adhesive (for example, an ultraviolet curable adhesive) 18, and then into the through hole 15. The filled insulating resin 16 is irradiated with a laser to form small diameter through holes concentrically. The laser to be used at this time may be a CO ₂ gas laser or a YAG laser because the object of drilling is a resin.

  In addition, when a photosensitive insulating resin is used as the insulating resin 16 filled in the through hole 15, the through hole can be formed by exposure and development. Whichever method is employed, it is possible to easily form the insulating resin 16 layer having a sufficient thickness in the through hole 15 as compared with the formation of the insulating layer by the CVD method. The insulating resin 16 existing on the Al electrode 13 on the element surface of the silicon wafer 10 is also removed when forming the through-hole or separately as necessary.

  Next, as shown in FIG. 3G, a conductive metal layer (seeding layer metal) 20 is formed by electroless plating on the element surface of the silicon wafer 10 and the side wall surface and bottom of the through hole 15. By using a vapor deposition method or a sputtering method instead of the electroless plating method, an even better conductor metal layer 20 can be formed. As the conductive metal, for example, Ti, Ni, Cu, V, Cr, Pt, Pd, Au, Sn, etc. can be used, and can be selected from these according to the purpose.

  Thereafter, as shown in FIG. 3H, a resist layer 21 is formed on the conductive metal layer 20 formed on the element surface, and is exposed and developed. The resist may be liquid or film. Then, using the conductive metal layer 20 formed in the previous step as an electrode, an electrolytic plating layer 22 of Ni / Cu, Cu, Cu / Ni / Au or the like is formed.

  Next, as shown in FIG. 3I, after the resist layer 21 is peeled off, the conductive metal layer 20 used as an electrode is removed by etching. Thus, a conductive layer is formed on a predetermined region of the element surface and on the side wall surface and bottom of the through hole 15.

  Thereafter, as shown in FIG. 4 (j), a protective film (wiring protective resin film) 23 is formed on the element surface by coating or pasting as required for reliability, and an opening is formed by exposure and development. Form. The protective film 23 may be formed by a liquid coating method or a film pasting method. When flatness is required when forming the protective film 23, the through hole 15 may be filled with the resin itself for forming the protective film 23 or with another resin in advance.

  When the conductive metal layer is a Ni / Cu or Cu layer, a conductive layer 24 such as Au or Ni / Au is formed in the opening of the protective film 23 by electroless plating. Since this conductor layer 24 can be used as a connection electrode at the time of chip lamination, it may be on the through hole 15 but may be formed at a place other than the through hole.

  When solder is used as the connection method, the protective film 23 functions as a solder resist. In place of the protective film 23, a resist is applied or pasted, exposed and developed to form a pattern, and when the conductive metal layer is Ni / Cu or Cu layer, Au, Ni / Au, etc. are obtained by electroless plating. It is also possible to take a method of forming a conductive layer and stripping the resist. In this case, a solder resist is unnecessary.

  As shown in FIG. 4 (k), after the glass support 19 is attached to the element surface of the silicon wafer 10 and bonded via the adhesive 18, the conductive metal layer is Ni / Cu, Cu layer, Electroless plating of Au or Ni / Au is performed on the through-hole portion on the back surface to form a back electrode 25 such as Au or Ni / Au.

  Thereafter, the glass support 19 is peeled off, and as shown in FIG. 4L, a dicing tape 26 is attached to the back surface as necessary, and then a process such as dicing is performed. Thus, a semiconductor device having a structure in which a rewiring layer is formed only on the element surface of the silicon wafer 10 and a connection electrode with another chip is provided on the through hole 15 is obtained.

  According to the second embodiment configured as described above, a highly reliable semiconductor device suitable for a structure in which a plurality of chips are stacked can be manufactured. Further, it is not necessary to use an expensive apparatus such as RIE, and since there are few mask exposure / development steps, a semiconductor device can be obtained at low cost.

  Further, since the through hole 15 is formed in the silicon wafer 10 by laser irradiation, and the side wall surface of the through hole 15 is made of amorphous silicon, the insulating resin 16 filled in the through hole 15 is formed. Adhesion with is high. Furthermore, since the side wall surface of the through hole 15 is reliably covered with the insulating resin 16 layer reaching the back surface of the silicon wafer 10, the insulation between the base material (silicon) on the side wall surface of the through hole 15 and the conductor layer is ensured. And a highly reliable via (through-hole conduction part) is formed.

  The third embodiment shows a method of manufacturing a semiconductor device in which a junction (connection electrode) with another semiconductor chip is formed on a wiring drawn from a via on the back surface of a silicon wafer. This embodiment is different from the second embodiment in that rewiring is formed not only on the element surface of the silicon wafer but also on the back surface.

  In the third embodiment, similarly to the second embodiment, after sequentially performing the steps shown in FIGS. 2A to 4J, the glass support is attached to the element surface of the silicon wafer. . Then, a conductive metal layer (seeding layer metal) is formed on the entire back surface of the silicon wafer including the through hole by electroless plating, vapor deposition, or sputtering.

  Next, a resist is formed on the conductive metal layer, and is exposed and developed. The resist may be liquid or film. Then, an electroplating layer of Ni / Cu, Cu, Cu / Ni / Au or the like is formed using the conductive metal layer as an electrode, and after removing the resist, the conductive metal layer used as the electrode is removed by etching.

  Thereafter, as required for reliability, a protective film (wiring protective resin film) is formed on the back surface by coating or pasting, and an opening is formed by exposure and development. The protective film may be formed by applying a liquid material or applying a film. When the conductive metal layer is Ni / Cu or Cu layer, an electrode such as Au or Ni / Au is formed by electroless plating in the opening of the protective film.

  Since this electrode can be used as a connection electrode at the time of chip lamination, it may be on the through hole, but can also be formed at a place other than the through hole. When solder is used as the connection method, the protective film functions as a solder resist. In place of the protective film, a resist is applied or pasted, exposed and developed to form a pattern, and when the conductive metal layer is Ni / Cu, Cu layer, the electroless plating can be used such as Au, Ni / Au, etc. A method of forming an electrode and stripping the resist can also be employed. In this case, a solder resist is unnecessary.

  Thereafter, the glass support is peeled off and, if necessary, a dicing tape is attached to the back surface, and then processing such as dicing is performed. In this way, a semiconductor device having a structure in which rewiring is formed not only on the element surface of the silicon wafer but also on the back surface and a connection electrode with another semiconductor chip is formed on the wiring drawn out from the via (through-hole conducting portion). Can be obtained.

  In the second and third embodiments described above, an example in which wiring is formed by the semi-additive method on the element surface and the back surface of the silicon wafer has been described, but wiring is performed by a full additive method or a subtractive method instead of the semi-additive method. Layers can also be formed.

  In the third embodiment, a glass support is attached to one surface of the silicon wafer to form a conductive metal layer (seeding layer metal), as shown in FIGS. 3 (h) and 3 (i). In the same manner as shown, a resist is formed to form a wiring pattern, and then a glass support is pasted on the other surface of the silicon wafer to form a wiring pattern in the same manner, but the glass support is not used. It is also possible. In that case, after the through hole is formed, the conductive metal layer can be formed by plating sequentially or simultaneously on both sides of the silicon wafer and the side wall surface of the through hole. Then, resist formation may be performed sequentially or simultaneously on both sides, and a wiring pattern may be simultaneously formed on both sides of the silicon wafer by plating. At this time, it is also possible to form a conductor layer by plating on the side wall surface of the through hole simultaneously with the formation of the wiring pattern. This method has an advantage that the conductor layer and the wiring pattern of the via (through hole conducting portion) can be formed with fewer steps (plating step).

1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing which shows the process of the first half of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the intermediate | middle process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the process of the latter half of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2,15 ... Through-hole, 3 ... Silicon wiring layer, 4, 13 ... Al electrode (pad), 5 ... 1st insulating resin layer, 6 ... 2nd insulating resin layer, 7 ... Conductor layer DESCRIPTION OF SYMBOLS 10 ... Silicon wafer, 14 ... Holding tape, 16 ... Insulating resin, 17 ... Insulating resin film, 18 ... Adhesive, 19 ... Glass support, 20 ... Conductive metal layer (seeding layer metal), 21 ... Resist layer, 22 ... Electroplating layer such as Ni / Cu, 23 ... Protective film, 24 ... Conductor layer such as Au, Ni / Au, 25 ... Back electrode.

Claims (7)

A semiconductor substrate;
A through hole penetrating the semiconductor substrate;
A first insulating resin layer formed on the side wall surface of the through hole;
A second insulating resin layer formed in a predetermined region of at least one of the front surface and the back surface of the semiconductor substrate;
A first conductor layer formed on the first insulating resin layer in the through hole;
A semiconductor device comprising a second conductor layer formed in a predetermined region on the second insulating resin layer and electrically connected to the first conductor layer.   2. The semiconductor device according to claim 1, wherein the semiconductor substrate has an element (active element or passive element) formed on a surface thereof.   3. The semiconductor according to claim 1, wherein a base material region having an amorphous structure is formed on a side wall surface of the through hole of the semiconductor substrate, and the first resin insulating layer is formed thereon. apparatus. Irradiating a semiconductor substrate on which elements are integrated and formed with a laser to form a through hole;
Filling the through hole with an insulating resin;
Forming a resin through hole concentrically smaller in diameter than the through hole in the insulating resin filled in the step; and
Forming a conductor layer on a side wall surface of a resin through-hole formed in the insulating resin, and forming a via (through-hole conducting portion) for conducting the surface and the back surface of the semiconductor substrate. Device manufacturing method.   5. The method of manufacturing a semiconductor device according to claim 4, wherein a resin through hole is formed by irradiating the insulating resin with a laser.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the conductor layer is formed on the side wall surface of the resin through hole by plating.   7. The method for manufacturing a semiconductor device according to claim 4, further comprising a step of forming a desired wiring on at least one of the front surface and the back surface of the semiconductor substrate.

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