JP2006050200A - Reader/writer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reader/writer for a non-contact IC card which achieves a circuit configuration using a microcomputer chip without using an exclusive IC. <P>SOLUTION: The microcomputer chip is used for the circuit configuration of the reader/writer, so as to output a transmission signal to a data carrier and to read or decode a reception signal from the data carrier. When a receiving operation is performed, a sub-carrier wave component signal is extracted from the reception signal from the data carrier and an encoding signal is taken out after performing binarization. Then, the microcomputer successively reads the encoding signal by the same frequency as that of the sub-carrier wave. In this case, reading is performed by the microcomputer using a redundant algorithm to recognize each kind of logic even when a part of plurality of pulses is lost by utilizing that the logic "1" and "0", which are expressed by the encoding signal, respectively include the plurality of pulses. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a reader / writer that performs non-contact communication with a data carrier such as an integrated circuit (hereinafter referred to as IC) card.

  A conventional reader / writer will be described below with reference to FIGS.

  FIG. 5 is a waveform diagram showing reading means for reading a received signal of a conventional reader / writer, and FIG. 6 is a circuit configuration diagram of the conventional reader / writer.

  Each of the reader / writer 16 and the data carrier 20 performs communication based on the encoding method and the modulation method defined in the ISO15693 standard.

  First, the configuration and operation of the data carrier 20 will be described.

  The data carrier 20 includes a data carrier antenna 22 and an IC chip 21, and the data carrier antenna 22 is connected to the antenna terminal of the IC chip 21. The data carrier 20 receives a carrier wave component signal from the reader / writer antenna 11 of the reader / writer 16 as a power supply receiving operation, and receives it from the data carrier antenna 22. The received carrier wave component signal is used as an operation clock signal for the IC chip 21 circuit.

  Further, in order to receive a command from the reader / writer 16 as a command receiving operation, the data carrier 20 receives a command signal based on the encoding method and the modulation method defined by the ISO15693 standard transmitted from the reader / writer antenna 11. The command signal is received by the carrier antenna 22, and the command signal is demodulated and decoded by the internal circuit of the IC chip 21 to recognize the command content.

  In addition, as an internal processing operation, the data carrier 20 performs processing according to the recognized command content and prepares the processing result as response data.

  Further, the data carrier 20 transmits a response signal including the response data to the reader / writer 16 as a response transmission operation, in order to transmit a response signal based on the encoding method defined in the ISO standard, a modulation method, That is, an impedance modulation method is used in which the impedance of the data carrier antenna 22 is changed to change the voltage between the terminals of the reader / writer antenna 11.

  Next, the configuration and operation of the reader / writer 16 will be described.

  The circuit of the reader / writer 16 creates and outputs command data, and inputs and determines response data. The dedicated IC 17, the modulation circuit 8, the final amplifier 9, the matching circuit 10, and the reader / writer antenna 11 The oscillation circuit 12, the crystal resonator 13, the filter circuit 14, the detection circuit 18, and the binarization circuit 15 are included.

  The oscillation circuit 12 oscillates the crystal resonator 13 having an oscillation frequency of 13.56 MHz and outputs a carrier signal C of 13.56 MHz.

  First, an operation in which the reader / writer 16 transmits a command signal to the data carrier 20 will be described. The dedicated IC 17 generates command data encoded by an encoding method defined by the ISO15693 standard, and a modulation signal B including the command data is output to the modulation circuit 8. The modulation circuit 8 amplitude-modulates the carrier signal C with the modulation signal B by a modulation method defined by the ISO15693 standard, and outputs a modulation output signal D to the final amplifier 9. The final stage amplifier 9 amplifies the modulation output signal D and outputs the transmission signal E to the matching circuit 10. In the command transmission operation to the data carrier 20, the matching circuit 10 transmits the transmission signal E from the reader / writer antenna 11 with an appropriate antenna power defined by the Domestic Radio Law and a modulation degree defined by the ISO15693 standard. Thus, in the reception operation of the response signal from the data carrier 20, matching is performed so that the reception signal F is obtained from the reader / writer antenna 11 with an appropriate amplitude in terms of circuit operation.

  FIG. 5 shows the waveform of each signal in the operation in which the reader / writer 16 receives the response signal from the data carrier 20.

  The response signal received by the reader / writer antenna 11 extracts the received signal F from the matching circuit 10 and outputs it to the filter circuit 14 as described above. The filter circuit 14 is a bandpass filter having a center frequency of 423.75 kHz, extracts the demodulated signal G, which is a 423.75 kHz subcarrier component including the response signal, from the received signal F, and outputs the demodulated signal G to the detection circuit 18. The detection circuit 18 further detects an envelope of the demodulated signal G and outputs a detection signal L having a communication speed of 26.48 kbit / sec (hereinafter referred to as kbps) to the binarization circuit 15. Finally, the binarization circuit 15 binarizes the detection signal L, converts it to a 26.48 kbps binarization signal M, and outputs it to the dedicated IC 17.

  The dedicated IC 17 creates a timing for the binarized signal M with the carrier signal C inputted as a clock signal, samples it at a sampling timing of 26.48 kbps indicated by an upward arrow in FIG. Get data. This sampling operation is performed at a sampling timing of 26.48 kHz, which is a carrier component of the transmission signal E, and is obtained by dividing the 13.56 MHz carrier signal C.

  The dedicated IC 17 further recognizes the response signal from the data carrier 20 by recognizing the encoded data in the response signal from the sampling data.

Through the above series of operations, communication between the reader / writer 16 and the data carrier 20 defined by the ISO15693 standard is realized.
JP 2001-175826 A

  As described above, the reader / writer having the conventional circuit configuration requires the dedicated IC 17 as is apparent from the circuit configuration diagram of the conventional reader / writer of FIG. 6, and this is an application specific integrated circuit (hereinafter referred to as ASIC). Need to be developed in. For this reason, the development cost and development period for ASIC development are needed.

  The present invention solves this problem, and an object of the present invention is to provide a reader / writer that enables reader / writer development without extra development cost and development time.

  The reader / writer according to the present invention includes a non-contact communication unit that performs non-contact communication with a data carrier by electromagnetic inductive coupling, a modulation unit that modulates a command signal transmitted to the data carrier, and a command modulated by the modulation unit. In the receiving operation of the response signal from the data carrier to the command signal via the non-contact communication means, the transmission signal created based on the signal is transmitted from the non-contact communication means with a prescribed modulation degree. And a matching circuit that performs matching so that a received signal can be obtained, and a demodulated signal obtained by demodulating a subcarrier component including a response signal in the received signal is binarized to obtain logic “1” and “0”. Encoding means for outputting an encoded signal in which each corresponding waveform is composed of a plurality of pulses; In the recognition operation of the pulse, without recognize some of the plurality of pulses, it is determined from the recognition result of the other pulse redundantly characterized in that a logical recognition means for performing logical recognition.

  The reader / writer of the present invention realizes a reader / writer function using a microcomputer chip without developing a dedicated IC, and does not require an extra development cost and development period for developing a dedicated IC. is there.

  Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1, 2, 3, and 4.

  FIG. 1 is a waveform diagram showing redundant reading means for a reader / writer reception signal in one embodiment of the present invention, and FIG. 2 is an algorithm for performing redundant reading of the reader / writer reception signal in this embodiment. FIG. 3 is a waveform diagram showing a reading signal reading means of the reader / writer in the present embodiment, and FIG. 4 is a circuit configuration diagram of the reader / writer in the present embodiment.

  Each of the reader / writer 1 and the data carrier 20 performs communication based on an encoding method and a modulation method defined in the ISO15693 standard.

  The configuration and operation of the data carrier 20 are the same as those of the prior art shown in FIGS.

  Next, the operation of the reader / writer 1 of the present embodiment will be described.

  The circuit of the reader / writer 1 generates and outputs command data, and inputs and determines response data, a microcomputer 2, a modulation circuit 8, a final stage amplifier 9, a matching circuit 10, and a reader / writer antenna 11. And an oscillation circuit 12, a crystal resonator 13, a filter circuit 14, and a binarization circuit 15. In addition, about the member same as the member in the prior art shown in FIG. 4, or the member of the same function, the same code | symbol was attached | subjected and detailed description was abbreviate | omitted.

  The oscillation circuit 12 oscillates the crystal resonator 13 having an oscillation frequency of 13.56 MHz and outputs a carrier signal C of 13.56 MHz.

  The microcomputer 2 includes at least a micro processor unit (hereinafter referred to as MPU) 3, a memory 4, a transmission serial input / output (hereinafter referred to as I / O) circuit 5, and a timer / counter circuit 6. The reception serial I / O circuit 7 is incorporated.

  An operation in which the reader / writer 1 transmits a command to the data carrier 20 will be described. The memory 4 is provided with a memory space for recording transmission data, and command data encoded by an encoding method defined in the ISO15693 standard is recorded in advance in this memory space. The command data is sequentially output as a transmission command signal A byte by byte from the memory 4 and sent to the transmission serial I / O circuit 5.

  The transmission serial I / O circuit 5 converts the received data for each byte into a data signal having a continuous serial arrangement, and outputs the data signal to the modulation circuit 8 as a modulation signal B. The modulation circuit 8 amplitude-modulates the carrier signal C with the modulation signal B by a modulation method defined by the ISO15693 standard, and outputs a modulation output signal D to the final amplifier 9. The final stage amplifier 9 amplifies the modulation output signal D and outputs the transmission signal E to the matching circuit 10. In the command transmission operation to the data carrier 20, the matching circuit 10 transmits the transmission signal E from the reader / writer antenna 11 with an appropriate antenna power defined by the Domestic Radio Law and a modulation degree defined by the ISO15693 standard. Thus, in the reception operation of the response signal from the data carrier 20, matching is performed so that the reception signal F is obtained from the reader / writer antenna 11 with an appropriate amplitude in terms of circuit operation.

  Next, an operation in which the reader / writer 1 receives a response signal from the reader / writer 20 will be described. The waveform of each signal in the receiving operation is shown in FIG.

  The response signal received by the reader / writer antenna 11 is extracted as the received signal F from the matching circuit 10 as described above and output to the filter circuit 14. The filter circuit 14 is a bandpass filter having a center frequency of 423.75 kHz, extracts a demodulated signal G that is a 423.75 kHz subcarrier component including a response signal from the received signal F, and outputs the demodulated signal G to the binarization circuit 15. To do. The binarization circuit 15 binarizes the demodulated signal G and converts it into a binarized signal H of 423.75 kbps.

  The receiving serial I / O circuit 7 built in the microcomputer 2 samples the binarized signal H of 423.75 kbps at the sampling timing of 423.75 kbps shown by the upward arrow in FIG. A reception response signal K having sampling data is obtained. This sampling operation is performed by a sampling timing signal J of 423.75 kHz obtained by frequency-dividing a 13.56 MHz carrier signal C that is a carrier component of the transmission signal E.

  The sampling operation is faster than the operation of sampling 26.48 kbps sampling data performed by a conventional reader / writer. In order to cope with this, the reader / writer 1 of the present embodiment records the data read by the receiving serial I / O circuit 7 in a memory space for recording the received data provided in the memory 4 sequentially for each byte. Go. In the reader / writer 1 of the present embodiment, the maximum data length according to the standard of the response from the data carrier is recorded, and when the response data having the maximum data length is received, the sampling operation is stopped, and the memory 4 The reception data recorded in the received data recording memory space is started to be recognized.

  Next, a reception data recognition algorithm in the reader / writer according to the present embodiment will be described with reference to FIGS.

  As described above, the reader / writer 1 does not perform envelope detection of the demodulated signal G as in the conventional reader / writer, and binarizes the demodulated signal G of 423.75 kHz directly by the binarizing circuit 15 so that the signal is 423.75 kbps. A binary signal H is obtained. For this reason, by causing the binarization circuit 15 to perform a binarization operation at a speed higher than that of the conventional reader / writer, the operation reliability of the binarization circuit 15 is lowered.

  That is, when the binarization circuit 15 is operating normally, a binarized signal H having a normal waveform shown in FIG. On the other hand, if the reception operation is affected by factors such as a change in the positional relationship between the reader / writer and the data carrier and noise mixing in the reader / writer antenna, the binarization circuit 15 can follow the transient operation. First, the binarization circuit 15 generates a binary signal H having a waveform with one missing pulse as shown in FIG. 1 (b) or two missing pulses as shown in FIG. 1 (c). End up.

  In order to solve such a problem of missing pulses, the reader / writer of this embodiment generates a data recognition error due to the missing one or two pulses in the sampling operation of the binary signal H of the microcomputer 2. However, as defined in the ISO15693 standard, logic “1” and “0” are each composed of a plurality of pulses, and even if some of these pulses cannot be recognized, other pulses The MPU 3 built in the microcomputer 2 has a function of performing logical recognition in a redundant manner by utilizing the property that the logical recognition can be performed by making a redundant determination from the read result of the.

  Next, a logic recognition algorithm in the MPU 3 will be described.

  As shown in Figs. 1 (b) and 1 (c), this recognition algorithm consists of six consecutive pulses, excluding the first and last pulses that are most likely to be lost due to the effects of the above transient operation. If all the pulses are recognized, the logic can be recognized.

  A flowchart of the recognition algorithm is shown in FIG. 1-bit encoded data is represented by a 2-byte data encoding method from D0 to D15 defined by the ISO15693 standard. By receiving D0 to D15 at 423.75 kbps, a 1-bit encoded signal is represented. It can be received at 26.48 kbps.

  Here, 2-byte data is received in order from D0 to D15.

  FIG. 2 (a) shows a bit arrangement of normal data, and the above-described encoding method uses a logical value of a 1-bit encoded signal as eight continuous pulses as shown in FIG. 2 (a). In other words, when the data sampled with the logic “1” is only D0 to D7, the logic is “0”, and when the data is only D8 to D15, the logic is “1”.

  Due to the characteristics of the binarization circuit 15, the eight continuous pulses are most likely to be missing in the middle two pulses due to the transient operation. For this reason, as shown in FIG. 2B, in the logic recognition algorithm, as the first stage, D3 and D4 which are the center data of D0 to D7 and D11 and D12 which are the center pulses of D8 to D15 are used. Simultaneous logic recognition is performed. That is, as is clear from FIG. 2 (a), if the logics of D3 and D4 are both “1” and the logics of D11 and D12 are both “0”, the encoding logic is “1”. Otherwise, it is determined as “0”. Further, in the logic recognition algorithm in the present embodiment, the second-stage logic recognition is further performed in order to increase the reliability of the logic recognition. That is, in order to support the first-stage logic recognition result, if the first-stage logic recognition determines that the encoding logic is “1”, are all D1, D2, D5, and D6 all “1”? If so, since it was confirmed that the six data D1, D2, D3, D4, D5 and D6 in the center of D0 to D7 are all “1”, the encoding logic is “1”. If it is not, it is concluded that there is an error because the logical recognition of the first stage and the second stage contradicts each other. Similarly, when the encoding logic is determined to be “0” in the first stage logic recognition, it is further confirmed whether D9, D10, D13 and D14 are all “1”, and if so, from D8 Since it was confirmed that the six data D9, D10, D11, D12, D13 and D14 in the center of D15 are all “1”, it is concluded that the encoding logic is “0”. Since the logic recognition in the first stage and the second stage contradict each other, it is concluded that there is an error.

  As described above, this recognition algorithm ends logical recognition for one encoded data by two-step data recognition and determination, and therefore can perform logical recognition continuously at a practical speed.

  Furthermore, the redundant logic recognition means of this recognition algorithm can improve the reliability of the receiving operation of the response from the data carrier in the reader / writer 1, and there is no practical problem in communication with the data carrier. A bit error rate is realized.

  With such a series of contents, the reader / writer 1 can realize the function of the reader / writer using a microcomputer without using a dedicated IC.

  According to the above description, an application example to the communication system defined by the ISO15693 standard has been shown as an embodiment of the present invention. However, the encoding method of response data from the data carrier is logical “1”. And “0” are each composed of a plurality of pulses, and even if some of the plurality of pulses cannot be recognized, the above coding is performed by redundantly judging from the reading results of other pulses. The redundant logic recognition may be performed in the same manner for the communication method defined in the ISO14443 standard by utilizing the property that the logic recognition can be performed.

  The present invention transmits a command signal to the data carrier, receives a response signal to the command of the data carrier, and makes a redundant determination from the recognition result of other pulses even if some of the plurality of pulses cannot be recognized. Therefore, a reader / writer function can be realized by using a microcomputer chip, which is useful for a reader / writer that does not require a dedicated IC.

The wave form diagram which shows the redundant reading means of the received signal of the reader / writer in one embodiment of this invention The flowchart figure which shows the algorithm which performs the redundant reading of the received signal of the reader / writer in one embodiment of this invention The wave form diagram which shows the reading means of the received signal of the reader / writer in one embodiment of this invention 1 is a circuit configuration diagram of a reader / writer according to an embodiment of the present invention. Waveform diagram showing a means for reading a received signal of a conventional reader / writer Circuit diagram of conventional reader / writer

Explanation of symbols

1 Reader / Writer (invention) 2 Microcomputer 3 Micro Processor Unit (MPU)
4 Memory 5 Transmission Serial I / O Circuit 6 Timer / Counter Circuit 7 Reception Serial I / O Circuit 8 Modulation Circuit 9 Final-stage Amplifier 10 Matching Circuit 11 Reader / Writer Antenna 12 Oscillation Circuit 13 Crystal Oscillator 14 Filter Circuit 15 Binary Circuit 16 (conventional) reader / writer 17 dedicated IC
18 Detection Circuit 20 Data Carrier 21 IC Chip 22 Data Carrier Antenna A Transmission Command Signal B Modulation Signal C Carrier Signal D Modulation Output Signal E Transmission Signal F Reception Signal G Demodulation Signal H (in the Reader / Writer of the Present Invention) Binary Signal J Sampling timing signal K Reception response signal L Detection signal M Binary signal (in conventional reader / writer)

Claims (1)

Non-contact communication means for performing non-contact communication with a data carrier by electromagnetic inductive coupling;
Modulation means for amplitude modulating a command signal to be transmitted to the data carrier;
A transmission signal created based on the command signal modulated by the modulation means is transmitted from the non-contact communication means with a prescribed modulation degree, and a response signal from the data carrier to the command signal via the non-contact communication means A matching circuit that performs matching so as to obtain a reception signal having a predetermined amplitude in the reception operation of
By binarizing the demodulated signal obtained by demodulating the subcarrier component including the response signal in the received signal, each waveform corresponding to logic “1” and “0” is composed of a plurality of pulses. Encoding means for outputting an encoded signal;
In the operation of recognizing the plurality of pulses, even if some of the plurality of pulses cannot be recognized, logic recognition means is provided that performs logic recognition by redundantly judging from the recognition results of other pulses. Reader / writer.

Images