JP2006047006A - Disconnection detection circuit - Google Patents

Disconnection detection circuit Download PDF

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JP2006047006A
JP2006047006A JP2004225780A JP2004225780A JP2006047006A JP 2006047006 A JP2006047006 A JP 2006047006A JP 2004225780 A JP2004225780 A JP 2004225780A JP 2004225780 A JP2004225780 A JP 2004225780A JP 2006047006 A JP2006047006 A JP 2006047006A
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pads
disconnection
voltage
detection circuit
circuit
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Junichi Nagata
淳一 永田
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Denso Corp
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Denso Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a disconnection detection circuit capable of more surely detecting the disconnection of connection members between a plurality of pads arranged on the terminals of a semiconductor device and circuit wiring. <P>SOLUTION: The voltages of the plurality of pads 2a-2d, 3a-3d respectively connected with drains and sources of a power MOSFET 1 are detected by a plurality of voltage detection circuits 11a-11d, and 12a-12d respectively. A determination circuit 13 detects the disconnections of the bonding wires 6a-6d, and 7a-7d connecting between the pads 2a-2d, 3a-3d and lead frames 4, and 5 on the basis of changes of each detected voltage. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体素子の１つの端子について複数配置されるパッドと回路配線との間を接続する接続部材の断線を検出するための断線検出回路に関する。   The present invention relates to a disconnection detection circuit for detecting disconnection of a connection member that connects between a plurality of pads arranged for one terminal of a semiconductor element and circuit wiring.

図４には、半導体集積回路内に形成されているパワーＭＯＳＦＥＴ及びその周辺の構成を示す。パワーＭＯＳＦＥＴ１は、半導体基板上の形成領域として示しており、その両側には、ドレイン，ソースに夫々接続されている４つのパッド２ａ〜２ｄ，３ａ〜３ｄが配置されている。そして、夫々のパッド２ａ〜２ｄ，３ａ〜３ｄは、図示しない保護膜の対応する部位に接続用の穴があけられており、リードフレーム（回路配線）４，５に対し複数のボンディングワイヤ６ａ〜６ｄ，７ａ〜７ｄを介して接続されている。   FIG. 4 shows the configuration of a power MOSFET formed in a semiconductor integrated circuit and its periphery. The power MOSFET 1 is shown as a formation region on a semiconductor substrate, and on both sides thereof, four pads 2a to 2d and 3a to 3d connected to a drain and a source are arranged. Each of the pads 2a to 2d and 3a to 3d has a hole for connection at a corresponding portion of a protective film (not shown), and a plurality of bonding wires 6a to 6 are connected to the lead frames (circuit wiring) 4 and 5. 6d and 7a-7d are connected.

このように、ＦＥＴ１のドレイン，ソースとリードフレーム４，５との間を複数のボンディングワイヤ６，７を介して接続するのは、ＦＥＴ１を介して大電流を低抵抗で効率よく流すためである。例えば、ボンディングワイヤ６，７の１本の抵抗値をＲbｗとし、ＦＥＴ１に流れる電流をＩＬとすると、ボンディングワイヤ１本だけで接続すれば電力損失はＲbｗ×ＩＬとなるが、ボンディングワイヤを４本並列に接続すれば電力損失はＲbｗ／４×ＩＬに低減される。   The reason why the drains and sources of the FET 1 and the lead frames 4 and 5 are connected via the plurality of bonding wires 6 and 7 is to allow a large current to flow efficiently through the FET 1 with low resistance. . For example, if the resistance value of one of the bonding wires 6 and 7 is Rbw and the current flowing through the FET 1 is IL, the power loss is Rbw × IL if only one bonding wire is connected, but four bonding wires are used. If connected in parallel, the power loss is reduced to Rbw / 4 × IL.

電力損失が少なくなるということは、ＦＥＴ１の許容電流をより大きく取ることができることでもある。しかし、そのように許容電流をより大きく設定した場合にボンディングワイヤ６，７の何れかが断線すると、その部分で発生する電力損失がより大きくなり、場合によっては残りのワイヤが溶断することも考えられる。ワイヤが溶断すれば、前記電力損失は更に大きくなってワイヤの溶断が更に進み、場合によっては全てのボンディングワイヤ６，７が溶断し、ＦＥＴ１が機能しなくなるおそれもある。   The fact that the power loss is reduced also means that the allowable current of the FET 1 can be increased. However, if either of the bonding wires 6 and 7 is disconnected when the allowable current is set to be larger in this way, the power loss generated in that portion becomes larger, and in some cases, the remaining wires may be fused. It is done. If the wire is blown, the power loss is further increased, and the wire is further blown. In some cases, all the bonding wires 6 and 7 are blown, and the FET 1 may not function.

斯様な問題を解決するために、特許文献１に開示されている技術を適用した場合を図５に示す。上記技術は、車両用方向指示器の点滅回路（フラッシャ）においてランプの断線を検出することを目的としたものであり、その技術をボンディングワイヤ６，７の断線検出に適用した場合を想定する。
２つのＦＥＴ１Ａ，１Ｂのソースは共通に接続されており、それらのドレインは、オペアンプ８の非反転入力端子、反転入力端子に夫々接続されている。尚、図５では、ＦＥＴ１（Ａ，Ｂ）を回路シンボルで示している。斯様に断線検出回路を構成した場合、リードフレーム５から、ＦＥＴ１Ａのソース，ドレインを介してリードフレーム６に流れる電流経路において、ＦＥＴ１のオン抵抗並びにボンディングワイヤ７の抵抗でドロップした電圧をオペアンプ８が増幅して出力する構成となる。この場合、ドレイン側におけるボンディングワイヤ６の何れかが断線したことを、オペアンプ８の非反転入力端子側の電位上昇によって検出することができる。
特開平６−４８２４６号公報 FIG. 5 shows a case where the technique disclosed in Patent Document 1 is applied to solve such a problem. The above technique is intended to detect the disconnection of the lamp in the flashing circuit (flasher) of the vehicular direction indicator, and it is assumed that the technique is applied to the detection of the disconnection of the bonding wires 6 and 7.
The sources of the two FETs 1A and 1B are connected in common, and their drains are connected to the non-inverting input terminal and the inverting input terminal of the operational amplifier 8, respectively. In FIG. 5, FET1 (A, B) is indicated by a circuit symbol. When the disconnection detection circuit is configured in this way, in the current path flowing from the lead frame 5 to the lead frame 6 through the source and drain of the FET 1A, the voltage dropped by the ON resistance of the FET 1 and the resistance of the bonding wire 7 is used as the operational amplifier 8. Is amplified and output. In this case, the disconnection of any of the bonding wires 6 on the drain side can be detected by the potential increase on the non-inverting input terminal side of the operational amplifier 8.
JP-A-6-48246

しかしながら、図５に示す構成では、ＦＥＴ１のオン抵抗のばらつきが大きいため、ボンディングワイヤ６の断線による電流の僅かな変化を検出するのは困難である。例えば、ＦＥＴ１のオン抵抗を１００ｍΩ、ボンディングワイヤ６の抵抗を同じく１００ｍΩ／本とすると、オン抵抗が一般に２０％〜３０％ばらつくことを考えれば、ボンディングワイヤが１本断線した場合の抵抗値の変化は上記ばらつきの範囲内となってしまう。   However, in the configuration shown in FIG. 5, since the variation in the on-resistance of the FET 1 is large, it is difficult to detect a slight change in current due to the disconnection of the bonding wire 6. For example, assuming that the ON resistance of FET 1 is 100 mΩ and the resistance of the bonding wire 6 is also 100 mΩ / piece, the change in resistance value when one bonding wire is broken considering that the ON resistance generally varies from 20% to 30%. Falls within the above range of variation.

本発明は上記事情に鑑みてなされたものであり、その目的は、半導体素子の１つの端子に複数配置されるパッドと回路配線との間を接続する接続部材の断線を、より確実に検出することができる断線検出回路を提供することにある。   The present invention has been made in view of the above circumstances, and an object of the present invention is to more reliably detect disconnection of a connection member that connects between a plurality of pads arranged on one terminal of a semiconductor element and circuit wiring. An object of the present invention is to provide a disconnection detection circuit capable of performing the above.

請求項１記載の断線検出回路によれば、複数の電圧検出手段によって複数のパッドの電圧を夫々検出し、断線検出手段は、検出された各電圧の変化に基づいて接続部材の断線を検出する。斯様に構成すれば、半導体素子に通電が行われた場合のオン抵抗の影響を受けることなく各パッドの電圧を直接検出することができ、それらの電圧変化によって接続部材の断線を確実に検出することが可能となる。   According to the disconnection detection circuit of the first aspect, the voltages of the plurality of pads are detected by the plurality of voltage detection units, respectively, and the disconnection detection unit detects the disconnection of the connection member based on the detected change in each voltage. . With this configuration, the voltage of each pad can be directly detected without being affected by the on-resistance when the semiconductor element is energized, and disconnection of the connecting member is reliably detected by the change in voltage. It becomes possible to do.

請求項２記載の断線検出回路によれば、１つ以上の電圧差検出手段によって、複数のパッドの内２つのパッドの電圧差を検出し、断線検出手段は、電圧差検出手段によって検出された電圧差に基づき接続部材の断線を検出する。即ち、接続部材の断線が発生すると、当該接続部材が接続されていたパッドの電位は、他のパッドとの間を接続している配線の抵抗分の影響を受けて、他のパッドの電位と相対的に大きく異なる状態になる。従って、２つのパッドの電圧差に基づくことで接続部材の断線を確実に検出することができる。   According to the disconnection detection circuit of the second aspect, the voltage difference between two pads of the plurality of pads is detected by one or more voltage difference detection means, and the disconnection detection means is detected by the voltage difference detection means. The disconnection of the connecting member is detected based on the voltage difference. That is, when the disconnection of the connection member occurs, the potential of the pad to which the connection member is connected is affected by the resistance of the wiring connected to the other pad, and the potential of the other pad A relatively different state. Therefore, the disconnection of the connection member can be reliably detected based on the voltage difference between the two pads.

請求項３記載の断線検出回路によれば、電圧差検出手段を、２つのパッドの内、互いに一方のパッドの電圧を基準電圧とするように接続されるウインドウコンパレータで構成する。即ち、夫々に接続部材が接続されている場合、各パッドの電位は略等しい、若しくは２つのパッド間の電位は一定の電位差を維持していると見ることができる。その状態から、１つのパッドの接続部材が断線すると当該パッドの電位が変動するため、ウインドウコンパレータの出力信号も変化する。従って、接続部材の断線を確実に、且つ簡単な構成で検出することができる。   According to the disconnection detecting circuit of the third aspect, the voltage difference detecting means is constituted by a window comparator connected so that the voltage of one of the two pads is set as a reference voltage. That is, when connecting members are connected to each other, it can be considered that the potentials of the pads are substantially equal, or the potential between the two pads maintains a constant potential difference. From this state, when the connection member of one pad is disconnected, the potential of the pad changes, so that the output signal of the window comparator also changes. Therefore, the disconnection of the connection member can be reliably detected with a simple configuration.

請求項４記載の断線検出回路によれば、半導体素子をパワーＭＯＳＦＥＴとする。即ち、パワーＭＯＳＦＥＴは、導通状態となった場合に比較的大きな電流を流す用途に用いられる。そのため、接続部材の一部が断線した場合の影響は大きく、断線が連鎖的に発生する可能性も高い。従って、本発明を適用すれば、パワーＭＯＳＦＥＴを使用する場合のフェイルセーフとして有効である。   According to the disconnection detection circuit of the fourth aspect, the semiconductor element is a power MOSFET. That is, the power MOSFET is used for an application in which a relatively large current flows when the power MOSFET is in a conductive state. Therefore, the influence when a part of the connection member is disconnected is large, and there is a high possibility that the disconnection occurs in a chain. Therefore, if the present invention is applied, it is effective as a fail-safe when a power MOSFET is used.

（第１実施例）
以下、本発明の第１実施例について図１を参照して説明する。尚、図４と同一部分には同一符号を付して説明を省略し、以下異なる部分についてのみ説明する。第１実施例では、パワーＭＯＳＦＥＴ（半導体素子）１のドレイン，ソース（端子）に夫々４個ずつ配置されているパッド２ａ〜２ｄ，３ａ〜３ｄに対して、夫々電圧検出回路（電圧検出手段）１１ａ〜１１ｄ，１２ａ〜１２ｄを接続する。そして、それらの電圧検出回路１１ａ〜１１ｄ，１２ａ〜１２ｄの出力端子は、判定回路（断線検出手段）１３の入力端子に夫々接続されている。 (First embodiment)
A first embodiment of the present invention will be described below with reference to FIG. 4 that are the same as those in FIG. 4 are denoted by the same reference numerals and description thereof is omitted. In the first embodiment, a voltage detection circuit (voltage detection means) is provided for each of the pads 2a to 2d and 3a to 3d arranged at the drain and source (terminal) of the power MOSFET (semiconductor element) 1, respectively. 11a-11d and 12a-12d are connected. The output terminals of the voltage detection circuits 11a to 11d and 12a to 12d are connected to the input terminal of the determination circuit (disconnection detection means) 13, respectively.

電圧検出回路１１ａ〜１１ｄ，１２ａ〜１２ｄは、例えば、各パッド２ａ〜２ｄ，３ａ〜３ｄの電圧を、夫々の基準電圧と比較するコンパレータで構成される。ドレイン側のパッド２ａ〜２ｄは、夫々に対応するボンディングワイヤ（接続部材）６ａ〜６ｄが断線すると電位が上昇するように変化し、ソース側のパッド３ａ〜３ｄは、夫々に対応するボンディングワイヤ（接続部材）７ａ〜７ｄが断線すると電位が下降するように変化する。   The voltage detection circuits 11a to 11d and 12a to 12d are composed of, for example, comparators that compare the voltages of the pads 2a to 2d and 3a to 3d with respective reference voltages. The drain-side pads 2a to 2d change so that the potential increases when the corresponding bonding wires (connection members) 6a to 6d are disconnected, and the source-side pads 3a to 3d correspond to the corresponding bonding wires ( When the connecting members 7a to 7d are disconnected, the potential changes.

即ち、実態的な配線としては図５に示すものと同様であり、例えば、ソース側のボンディングワイヤ７ｄが断線したとすると、パッド３ｄの電位，即ちパッド３ｃ及び３ｄの共通接続点の電位は、パッド３ｃから前記共通接続点までの配線ｌｓによる電圧降下分だけ下降する。一方、ドレイン側のボンディングワイヤ６ｄが断線したとすると、パッド２ｄの電位，即ちパッド２ｃ及び２ｄの共通接続点の電位は、パッド２ｃから前記共通接続点までの配線ｌｄによりパッド２ｃに対して生じている電圧降下分だけ上昇することになる。   That is, the actual wiring is the same as that shown in FIG. 5. For example, if the source-side bonding wire 7d is disconnected, the potential of the pad 3d, that is, the potential of the common connection point of the pads 3c and 3d is The voltage drops by the voltage drop due to the wiring ls from the pad 3c to the common connection point. On the other hand, if the drain-side bonding wire 6d is disconnected, the potential of the pad 2d, that is, the potential of the common connection point of the pads 2c and 2d is generated with respect to the pad 2c by the wiring ld from the pad 2c to the common connection point. It will rise by the voltage drop.

この時の電位変化は流れる電流量によっても異なるが、例えば、数ｍＶ〜数１０ｍＶ程度である。従って、夫々の電位変化の状態に応じて、電圧検出回路１１，１２を構成するコンパレータの出力信号レベルがロウからハイに変化するように設定しておく。また、各コンパレータの基準電圧は、夫々のパッド２ａ〜２ｄ，３ａ〜３ｄの実際の電位に応じて独立に設定する。   The potential change at this time varies depending on the amount of current flowing, but is, for example, about several mV to several tens of mV. Therefore, the output signal level of the comparator constituting the voltage detection circuits 11 and 12 is set so as to change from low to high in accordance with the state of potential change. Further, the reference voltage of each comparator is set independently according to the actual potential of each of the pads 2a to 2d and 3a to 3d.

また、判定回路１３はＯＲゲートで構成し、何れかの電圧検出回路１１，１２の出力信号がハイレベルになると、その出力端子１４のレベルをロウからハイに変化させるようにする。そして、出力端子１４は、半導体集積回路の外部端子としておき、そのレベル変化を外部よりモニタできるようにしておく。従って、ユーザは、出力端子１４のレベルをモニタすることで、ボンディングワイヤ６ａ〜６ｄ，７ａ〜７ｄの断線を検出することが可能となる。   The determination circuit 13 is composed of an OR gate, and when the output signal of any of the voltage detection circuits 11 and 12 becomes high level, the level of the output terminal 14 is changed from low to high. The output terminal 14 is set as an external terminal of the semiconductor integrated circuit so that the level change can be monitored from the outside. Therefore, the user can detect the disconnection of the bonding wires 6a to 6d and 7a to 7d by monitoring the level of the output terminal 14.

以上のように本実施例によれば、パワーＭＯＳＦＥＴ１のドレイン，ソースに夫々接続される複数のパッド２ａ〜２ｄ，３ａ〜３ｄの電圧を複数の電圧検出回路１１ａ〜１１ｄ，１２ａ〜１２ｄによって夫々検出し、判定回路１３は、検出された各電圧の変化に基づいてパッド２ａ〜２ｄ，３ａ〜３ｄとリードフレーム４，５との間を接続するボンディングワイヤ６ａ〜６ｄ，７ａ〜７ｄの断線を検出するようにした。従って、ＦＥＴ１に通電が行われた場合のオン抵抗の影響を受けることなく各パッド２，３の電圧を直接検出することができ、それらの電圧変化によってボンディングワイヤ６ａ〜６ｄ，７ａ〜７ｄの断線を確実に検出することが可能となる。   As described above, according to this embodiment, the voltages of the pads 2a to 2d and 3a to 3d connected to the drain and source of the power MOSFET 1 are detected by the voltage detection circuits 11a to 11d and 12a to 12d, respectively. The determination circuit 13 detects the disconnection of the bonding wires 6a to 6d and 7a to 7d connecting the pads 2a to 2d and 3a to 3d and the lead frames 4 and 5 based on the detected changes in the voltages. I tried to do it. Therefore, it is possible to directly detect the voltages of the pads 2 and 3 without being affected by the on-resistance when the FET 1 is energized, and the bonding wires 6a to 6d and 7a to 7d are disconnected due to the voltage change. Can be reliably detected.

また、パワーＭＯＳＦＥＴ１は、導通状態となった場合に比較的大きな電流を流す用途に用いられるので、ボンディングワイヤ６ａ〜６ｄ，７ａ〜７ｄの一部が断線した場合の影響は大きく、断線が連鎖的に発生する可能性も高い。従って、本発明を適用すれば、パワーＭＯＳＦＥＴ１を使用する場合のフェイルセーフとして有効である。   In addition, since the power MOSFET 1 is used for an application in which a relatively large current flows when it is in a conductive state, the influence when a part of the bonding wires 6a to 6d and 7a to 7d is disconnected is large, and the disconnection is chained. There is a high possibility that it will occur. Therefore, if the present invention is applied, it is effective as a fail safe when the power MOSFET 1 is used.

（第２実施例）
図２は、本発明の第２実施例を示すものであり、第１実施例と同一部分には同一符号を付して説明を省略し、以下異なる部分についてのみ説明する。第２実施例は、第１実施例における電圧検出回路１１ａ〜１１ｄ，１２ａ〜１２ｄに代えて、４つの差電圧検出回路（電圧差検出手段）１５ａ，１５ｂ，１６ａ，１６ｂを用いている。差電圧検出回路１５ａはパッド２ａ，２ｂ間の差電圧，差電圧検出回路１５ｂはパッド２ｃ，２ｄ間の差電圧，差電圧検出回路１６ａはパッド３ａ，３ｂ間の差電圧，差電圧検出回路１６ｂはパッド３ｃ，３ｄ間の差電圧を検出するように配置されている。 (Second embodiment)
FIG. 2 shows a second embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals and the description thereof is omitted. Only the different parts will be described below. The second embodiment uses four differential voltage detection circuits (voltage difference detection means) 15a, 15b, 16a, 16b instead of the voltage detection circuits 11a-11d, 12a-12d in the first embodiment. The difference voltage detection circuit 15a is the difference voltage between the pads 2a and 2b, the difference voltage detection circuit 15b is the difference voltage between the pads 2c and 2d, the difference voltage detection circuit 16a is the difference voltage between the pads 3a and 3b, and the difference voltage detection circuit 16b. Are arranged to detect the voltage difference between the pads 3c and 3d.

差電圧検出回路１５，１６は、例えば、差動増幅回路とコンパレータとの組み合わせで構成されており、例えば差電圧検出回路１５ａは、パッド２ａ，２ｂ間の差電圧を増幅してコンパレータに出力し、そのコンパレータは、差動増幅回路が出力した電圧信号レベルが基準電圧を超えた場合にハイレベルの信号を出力する。そして、その信号変化に基づき、第１実施例と同様の判定回路１３によって断線判定を行う。   The differential voltage detection circuits 15 and 16 are composed of, for example, a combination of a differential amplifier circuit and a comparator. For example, the differential voltage detection circuit 15a amplifies the differential voltage between the pads 2a and 2b and outputs it to the comparator. The comparator outputs a high level signal when the voltage signal level output from the differential amplifier circuit exceeds the reference voltage. Based on the signal change, the disconnection determination is performed by the same determination circuit 13 as in the first embodiment.

以上のように第２実施例によれば、差電圧検出回路１５ａ，１５ｂ，１６ａ，１６ｂによって、複数のパッド２ａ〜２ｄ，３ａ〜３ｄの内２つのパッドの電圧差を検出し、判定回路１３は、差電圧検出回路１５，１６によって検出された電圧差に基づきボンディングワイヤ６ａ〜６ｄ，７ａ〜７ｄの断線を検出するようにした。
即ち、第１実施例で説明したように、ボンディングワイヤ６，７の断線が発生すると、当該ボンディングワイヤ６，７が接続されていたパッド２，３の電位は、他のパッドとの間を接続している配線の抵抗分の影響を受けて、他のパッドの電位と相対的に大きく異なる。従って、２つのパッドの電圧差に基づくことでボンディングワイヤ６，７の断線を確実に検出することができる。 As described above, according to the second embodiment, the difference voltage detection circuits 15a, 15b, 16a, and 16b detect the voltage difference between two of the pads 2a to 2d and 3a to 3d, and the determination circuit 13 Detects the disconnection of the bonding wires 6a to 6d and 7a to 7d based on the voltage difference detected by the differential voltage detection circuits 15 and 16.
That is, as described in the first embodiment, when the bonding wires 6 and 7 are disconnected, the potentials of the pads 2 and 3 to which the bonding wires 6 and 7 are connected are connected to other pads. Under the influence of the resistance of the wiring, the potential of other pads is relatively different. Therefore, the disconnection of the bonding wires 6 and 7 can be reliably detected based on the voltage difference between the two pads.

（第３実施例）
図３は本発明の第３実施例を示すものである。第３実施例では、第２実施例と同様に２つのパッド間の電圧差を検出する構成であるが、その電圧差をウインドウコンパレータを用いて検出するようにしたものである。コンパレータ１７ａの反転入力端子，非反転入力端子はパッド２ａ，２ｂに夫々接続され、対を成すコンパレータ１７ｂの反転入力端子，非反転入力端子はパッド２ｂ，２ａに夫々接続されている。そして、夫々対を成すコンパレータ１７ｃ及び１７ｄ，１８ａ及び１８ｂ，１８ｃ及び１８ｄは、夫々パッド２ｃ及び２ｄ，３ａ及び３ｂ，３ｃ及び３ｄに同様の関係で接続されており、夫々の対がウインドウコンパレータ１９，２０，２１，２２を構成している。 (Third embodiment)
FIG. 3 shows a third embodiment of the present invention. In the third embodiment, the voltage difference between the two pads is detected as in the second embodiment, but the voltage difference is detected using a window comparator. The inverting input terminal and the non-inverting input terminal of the comparator 17a are connected to the pads 2a and 2b, respectively, and the inverting input terminal and the non-inverting input terminal of the paired comparator 17b are connected to the pads 2b and 2a, respectively. The paired comparators 17c and 17d, 18a and 18b, 18c and 18d are connected to the pads 2c and 2d, 3a and 3b, 3c and 3d, respectively, in the same relationship. , 20, 21 and 22 are configured.

そして、コンパレータ１７ａ〜１７ｄの出力端子は４入力ＯＲゲート２３の入力端子に夫々接続されており、コンパレータ１８ａ〜１８ｄの出力端子は４入力ＯＲゲート２４の入力端子に夫々接続されている。また、それらのＯＲゲート２３，２４の出力端子はＯＲゲート２５の入力端子に夫々接続されている。これらのＯＲゲート２３〜２５は、判定回路（断線検出手段）２６を構成している。   The output terminals of the comparators 17a to 17d are connected to the input terminal of the 4-input OR gate 23, respectively, and the output terminals of the comparators 18a to 18d are connected to the input terminal of the 4-input OR gate 24, respectively. The output terminals of the OR gates 23 and 24 are connected to the input terminal of the OR gate 25, respectively. These OR gates 23 to 25 constitute a determination circuit (disconnection detection means) 26.

次に、第３実施例の作用について説明する。例えば、ウインドウコンパレータ１９は、パッド２ａの電位がパッド２ｂの電位よりも高くなった場合にコンパレータ１７ｂがハイレベル信号を出力し、逆に、パッド２ｂの電位がパッド２ａの電位よりも高くなった場合にコンパレータ１７ａがハイレベル信号を出力する。尚、コンパレータ１７の内部構成によって、両電圧の差が所定電圧以上となった場合に、出力信号レベルを変化させても良い。その他のウインドウコンパレータ２０，２１，２２についても、夫々に接続されているパッド２，３の電位関係について同様の作用を成す。そして、判定回路２６は、何れかのコンパレータ１７ａ〜１７ｄ，１８ａ〜１８ｄがハイレベル信号を出力すれば、出力端子２７のレベルをハイレベルに変化させる。   Next, the operation of the third embodiment will be described. For example, in the window comparator 19, when the potential of the pad 2a becomes higher than the potential of the pad 2b, the comparator 17b outputs a high level signal, and conversely, the potential of the pad 2b becomes higher than the potential of the pad 2a. In this case, the comparator 17a outputs a high level signal. Note that, depending on the internal configuration of the comparator 17, the output signal level may be changed when the difference between the two voltages exceeds a predetermined voltage. The other window comparators 20, 21, 22 also have the same action with respect to the potential relationship between the pads 2, 3 connected thereto. The determination circuit 26 changes the level of the output terminal 27 to a high level when any of the comparators 17a to 17d and 18a to 18d outputs a high level signal.

即ち、各パッド２，３にボンディングワイヤ６，７が接続されている場合、各パッドの電位は略等しいか又は２つのパッド間の電位は一定の電位差を維持していると見ることができる。その状態から、１つのパッドの接続部材が断線すると当該パッドの電位が変動するため、ウインドウコンパレータ１９〜２２の出力信号が変化する。
以上のように第３実施例によれば、２つのパッドの内、互いに一方のパッドの電圧を基準電圧とするように接続されるウインドウコンパレータ１９〜２２によって、夫々が接続されている２つのパッドの差電圧を検出することで、ボンディングワイヤ６，７の断線を検出するようにした。従って、断線を確実に、且つ簡単な構成で検出することができる。 That is, when the bonding wires 6 and 7 are connected to the pads 2 and 3, it can be considered that the potentials of the pads are substantially equal or the potential between the two pads maintains a constant potential difference. From this state, when the connection member of one pad is disconnected, the potential of the pad fluctuates, so that the output signals of the window comparators 19 to 22 change.
As described above, according to the third embodiment, of the two pads, the two pads connected to each other by the window comparators 19 to 22 connected so that the voltage of one of the pads is used as the reference voltage. The disconnection of the bonding wires 6 and 7 is detected by detecting the difference voltage of. Accordingly, the disconnection can be reliably detected with a simple configuration.

本発明は上記し且つ図面に記載した実施例に限ることなく、次のような変形が可能である。
第２実施例において、差電圧検出回路１５，１６側にコンパレータを設ける代わりに、判定回路１３をＡ／Ｄ変換器とＣＰＵとで構成し、ＣＰＵが差動増幅回路の出力電圧をＡ／Ｄ変換して読み込むようにしても良い。 The present invention is not limited to the embodiment described above and illustrated in the drawings, and the following modifications are possible.
In the second embodiment, instead of providing a comparator on the differential voltage detection circuits 15 and 16, the determination circuit 13 is composed of an A / D converter and a CPU, and the CPU outputs the output voltage of the differential amplifier circuit to the A / D. It may be converted and read.

第２，第３実施例において、電圧差を検出する２つのパッドは、隣り合うものに限らず、ＦＥＴ１の同じ端子に接続されているものであればどのような組み合わせであっても良い。
同じ端子に接続されるパッドの数は「４」に限らず、「３」以下でも「５」以上であっても良い。 In the second and third embodiments, the two pads for detecting the voltage difference are not limited to adjacent pads, and any combination may be used as long as they are connected to the same terminal of the FET 1.
The number of pads connected to the same terminal is not limited to “4”, and may be “3” or less or “5” or more.

接続部材はボンディングワイヤ６，７に限ることなく、例えば、パッドとセラミック基板上の配線パターンとを接続するはんだバンプなどでも良い。
半導体素子はパワーＭＯＳＦＥＴ１に限ることなく、パワートランジスタやＩＧＢＴなどであっても良い。 The connecting member is not limited to the bonding wires 6 and 7, and may be, for example, a solder bump that connects the pad and the wiring pattern on the ceramic substrate.
The semiconductor element is not limited to the power MOSFET 1 but may be a power transistor, an IGBT, or the like.

本発明の第１実施例であり、断線検出回路の電気的構成を示す図FIG. 1 is a diagram illustrating an electrical configuration of a disconnection detection circuit according to a first embodiment of the present invention. 本発明の第２実施例を示す図１相当図FIG. 1 equivalent view showing a second embodiment of the present invention. 本発明の第３実施例を示す図１相当図FIG. 1 equivalent view showing a third embodiment of the present invention. パワーＭＯＳＦＥＴのソース，ドレインとリードフレームとの間を、ボンディングワイヤにより接続した状態を示す図The figure which shows the state which connected between the source and drain of power MOSFET and the lead frame with the bonding wire 従来技術の一例を示す図１相当図FIG. 1 equivalent diagram showing an example of the prior art

符号の説明Explanation of symbols

図面中、１はパワーＭＯＳＦＥＴ（半導体素子）、２，３はパッド、４，５はリードフレーム（回路配線）６，７はボンディングワイヤ（接続部材）、１１，１２は電圧検出回路（電圧検出手段）、１３は判定回路（断線検出手段）、１５，１６は差電圧検出回路（電圧差検出手段）、１９〜２２はウインドウコンパレータ、２６は判定回路（断線検出手段）を示す。

In the drawings, 1 is a power MOSFET (semiconductor element), 2 and 3 are pads, 4 and 5 are lead frames (circuit wiring) 6 and 7 are bonding wires (connection members), and 11 and 12 are voltage detection circuits (voltage detection means). , 13 is a determination circuit (disconnection detection means), 15 and 16 are differential voltage detection circuits (voltage difference detection means), 19 to 22 are window comparators, and 26 is a determination circuit (disconnection detection means).

Claims (4)

半導体素子の１つの端子について複数配置されるパッドと、それらのパッドと回路配線との間を接続する接続部材の断線を検出するための断線検出回路であって、
前記複数のパッドの電圧を夫々検出する複数の電圧検出手段と、
これら複数の電圧検出手段によって検出された各電圧の変化に基づいて、前記接続部材の断線を検出する断線検出手段とを備えたことを特徴とする断線検出回路。 A disconnection detection circuit for detecting a disconnection of a plurality of pads arranged for one terminal of a semiconductor element, and a connection member connecting between the pads and circuit wiring,
A plurality of voltage detecting means for respectively detecting voltages of the plurality of pads;
A disconnection detection circuit comprising: disconnection detection means for detecting disconnection of the connection member based on a change in each voltage detected by the plurality of voltage detection means. 半導体素子の端子に複数配置されるパッドと、それらのパッドと回路配線との間を接続する接続部材の断線を検出するための断線検出回路であって、
前記複数のパッドの内、２つのパッドの電圧差を検出する１つ以上の電圧差検出手段と、
この電圧差検出手段によって検出された電圧差に基づいて、前記接続部材の断線を検出する断線検出手段とを備えたことを特徴とする断線検出回路。 A disconnection detection circuit for detecting disconnection of a plurality of pads arranged on terminals of a semiconductor element and a connection member connecting between the pads and circuit wiring,
One or more voltage difference detecting means for detecting a voltage difference between two pads of the plurality of pads;
A disconnection detection circuit comprising: disconnection detection means for detecting disconnection of the connection member based on the voltage difference detected by the voltage difference detection means. 前記電圧差検出手段は、前記２つのパッドの内、互いに一方のパッドの電圧を基準電圧とするように接続されるウインドウコンパレータで構成されていることを特徴とする請求項２記載の断線検出回路。   3. The disconnection detection circuit according to claim 2, wherein the voltage difference detection means is constituted by a window comparator connected so that the voltage of one of the two pads is a reference voltage. . 前記半導体素子は、パワーＭＯＳＦＥＴであることを特徴とする請求項１乃至３の何れかに記載の断線検出回路。

The disconnection detection circuit according to claim 1, wherein the semiconductor element is a power MOSFET.

JP2004225780A 2004-08-02 2004-08-02 Disconnection detection circuit Pending JP2006047006A (en)

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JP2008528979A (en) * 2005-02-01 2008-07-31 シーメンス アクチエンゲゼルシヤフト Method and circuit for testing an electrical contact connection between a first output pin of a first power switch of a power switch device, an external node, a second output pin of a second power switch of the power switch device, and the node apparatus
JP2008187066A (en) * 2007-01-31 2008-08-14 Oki Electric Ind Co Ltd Power transistor
US8156804B2 (en) 2006-10-18 2012-04-17 Denso Corporation Capacitive semiconductor sensor
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008528979A (en) * 2005-02-01 2008-07-31 シーメンス アクチエンゲゼルシヤフト Method and circuit for testing an electrical contact connection between a first output pin of a first power switch of a power switch device, an external node, a second output pin of a second power switch of the power switch device, and the node apparatus
US8156804B2 (en) 2006-10-18 2012-04-17 Denso Corporation Capacitive semiconductor sensor
JP2008187066A (en) * 2007-01-31 2008-08-14 Oki Electric Ind Co Ltd Power transistor
CN103000601A (en) * 2011-09-12 2013-03-27 瑞萨电子株式会社 Semiconductor chip
WO2018211735A1 (en) * 2017-05-19 2018-11-22 三菱電機株式会社 Semiconductor device
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