JP2006041241A - Ceramic wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the occurrence of irregularities at a via conductor part of a ceramic wiring board which is sintered by suppressing contraction characteristics in X-Y axis direction, allowing formation of a flat surface, resulting in suppressed occurrence of defective IC which is mounted. <P>SOLUTION: The ceramic wiring board comprises an insulating substrate 2 where a plurality of insulating layers 2a-2e are laminated, a flat conductor pattern 3 formed on the surface and backside as well as inside the insulating substrate 2, a via conductor 4 in which a paste containing metal powder is so filled and sintered as to penetrate the insulating layers 2a-2e, and a plurality of electrode pads 6 that are flip chip mounted, surface mounted using a solder, or wire bonded to an electric element 5 on the surface of the insulating substrate 2. The via conductor 4 directly connected to the electrode pad 6a is connected to a flat conductor pattern 3b on the backside of the insulating substrate 2, with a part of the connection path being partially deviated from the vertical direction of the center of the connection pad 6a. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention comprises a high-frequency module substrate for communication equipment, a power amplifier substrate, a wiring substrate on which a semiconductor element is mounted, and a package, in which a wiring layer is formed on an insulating substrate made of ceramics and used in a mobile phone, a wireless LAN, or the like. The present invention relates to a ceramic wiring board suitable for such as.

  Conventionally, as a wiring board, for example, a wiring board on which a semiconductor element is mounted and mounted, a high-density wiring layer can be formed, and various circuits can be easily formed by the wiring layer. A multilayer ceramic wiring board in which a plurality of wiring layers are laminated is often used.

  This multilayer ceramic wiring board is composed of a wiring layer composed of an insulating substrate such as alumina, aluminum nitride, or glass ceramic and a conductor such as W, Mo, Cu, or Ag formed on the surface thereof. In addition, there are provided ones in which a lid is bonded to the surface of the wiring board and a semiconductor element or the like mounted on the surface of the wiring board is hermetically sealed or sealed with an organic resin.

  In recent years, high output has progressed, and wiring boards applied to hybrid integrated circuit devices on which semiconductor elements such as MMIC and various electronic components are mounted have become higher in size due to the incorporation of active circuit elements and the miniaturization of wiring. An accurate wiring board is required.

  For such high dimensional accuracy, through-holes are formed in a conventional green sheet of alumina or glass ceramics, and a via paste is filled with a conductive paste made of metal such as W, Mo, Cu, or Ag. In the method of forming, further printing the conductor paste on the sheet surface, laminating and firing, fine dimensional control cannot be performed due to the shrinkage action peculiar to ceramics in the XY axis direction, and high integration and high pin count are achieved. It could not be applied to a wiring board on which the IC of No. 1 was mounted.

As a technique for solving such a problem, the ceramic green sheet laminate is fired while being pressed, or a layer of an inorganic composition that does not sinter at the firing temperature is formed on the surface of the ceramic green sheet and fired simultaneously. Accordingly, it has been proposed to manufacture a wiring board with high dimensional accuracy that maintains the dimensions during molding by shrinking only in the Z-axis direction and suppressing shrinkage in the XY-axis direction. (For example, Patent Documents 1 and 2)
JP-A-7-86743 JP 2001-339166 A

  However, the multilayer wiring board using the manufacturing method for controlling the shrinkage characteristics in the XY axis direction has a large substrate shrinkage in the Z axis direction. Therefore, as shown in FIG. 5, when the via conductor 23 is formed directly below the electrode pad 22 connected to the IC or the like on the surface of the insulating substrate 21, the electrode pad 22a on which the via conductor 23 is formed; In the electrode pad 22b that is not connected to the via conductor 22, the sintering temperature and the shrinkage behavior of the via conductor formation region and the region where the via conductor is not formed are different. As a result, between the electrode pads 22a and 22b. The unevenness difference 23 is likely to occur in the thickness direction, and the electrode pad 22a immediately above the via conductor 23 tended to rise extremely. Therefore, when mounting an ultra-multi pin IC or a thin high-power IC, mounting defects, chipping of the IC, and the like have occurred due to unevenness between the electrode pads 22a and 22b.

  Therefore, the present invention suppresses the occurrence of unevenness of the electrode pad connected to the via conductor in the fired ceramic wiring board by suppressing the shrinkage characteristic in the XY direction, and forms a flat surface. Therefore, it is an object of the present invention to provide a wiring board capable of suppressing the occurrence of a mounting defect m with an IC or the like.

  The ceramic wiring board of the present invention includes an insulating substrate formed by laminating a plurality of insulating layers, a planar conductor pattern formed on the front surface, the back surface, and the inside of the insulating substrate, and a metal layer so as to penetrate the dielectric layer. A via conductor filled and fired with a paste containing powder; and a plurality of electrode pads to be mounted on an insulating substrate surface with an electric element and flip chip, surface mounting using a brazing material, or wire bonding, A via conductor directly connected to the electrode pad is connected to the planar conductor pattern on the back surface of the insulating substrate, and a part of the connection path is partially deviated from a vertical direction of the center of the connection pad. It is what.

  Thus, in the connection path connecting the via conductor connected to the electrode pad formed on the surface side of the insulating substrate and the planar conductor pattern on the back surface of the insulating substrate, a portion partially deviated from the vertical direction of the center of the connection pad By providing, the protrusion of the via conductor on the lower surface side from the step generated in this shifted portion is reduced, and even if there is a protrusion, the connection pad is not directly affected, so that the electrode The flatness on the pad forming surface can be increased.

  In particular, it is appropriate that the longest length in the vertical direction from the electrode pad of the via conductor directly connected to the electrode pad that exhibits such an effect is 60% or less of the total thickness of the insulating substrate.

  Further, it is appropriate that the displacement amount of the connection path is not less than the diameter of the via hole conductor from the center of the electrode pad.

  The diameter of the via conductor varies depending on the circuit configuration and the like, and the thickness of the electrode pad and the insulating layer, the number of layers, etc. Generally, the diameter of the via conductor is 100 to 300 μm, the thickness of the insulating layer is 150 μm or less, The number of the insulating layers is suitably 5 or more.

  Furthermore, the electrode pad portion is further formed by the connection path from the insulating substrate to the planar conductor pattern on the back surface of the insulating substrate comprising a combination of three or more via-hole conductors and two or more planar conductor patterns formed inside. The flatness of can be increased.

  The present invention is most suitably applied when the wiring substrate is fired so that the amount of firing shrinkage in the XY direction is smaller than the amount of firing shrinkage in the Z direction.

  According to the ceramic wiring board of the present invention, in the connection path connecting the via conductor connected to the electrode pad formed on the insulating substrate surface side and the planar conductor pattern on the back surface of the insulating substrate, from the vertical direction of the center of the connection pad. Even in a high-dimensional accuracy ceramic wiring board that is fired so that the amount of firing shrinkage in the XY direction is smaller than the amount of firing shrinkage in the Z direction by providing a part that is partially displaced, the electrode on the surface of the insulating substrate Protrusion due to via conductors connected to the pads can be reduced, thereby improving the flatness of the surface of the insulating substrate and suppressing occurrence of defects when an IC is mounted on this surface. A highly reliable wiring board can be provided with a high yield.

  Hereinafter, the ceramic wiring board of the present invention will be described with reference to the drawings. FIG. 1 is a schematic sectional view showing an example of the ceramic wiring board of the present invention. According to the ceramic wiring substrate 1 of FIG. 1, the insulating substrate 2 is constituted by a laminated body obtained by laminating a plurality of ceramic insulating layers 2 a to 2 e, and a thickness of 5 to A wiring circuit layer 3 of 20 μm is deposited. In order to connect two or more wiring circuit layers 3 formed in different layers, via conductors 4 having a diameter of 50 to 150 μm are formed through the insulating layers 2a to 2e.

  A high-frequency semiconductor element 5 is mounted on the surface of the wiring substrate 1, and an electrode pad 6 for flip-chip mounting the semiconductor element 5 is formed on the mounting portion. A via conductor 4 having a diameter of 50 to 200 μm is connected to the electrode pad 6 a and is electrically connected to the wiring circuit layer 3 b on the lower surface of the insulating substrate 2. The electrode pad 6b is connected to the wiring circuit layer 3 formed on the substrate surface.

  In the present invention, it is important that a part of the connection path from the via conductor 4 directly connected to the electrode pad 6 to the wiring circuit layer 3b on the back surface of the insulating substrate is partially shifted from the vertical direction of the center of the connection pad 6a. It is. Specifically, as shown in FIG. 2, the electrode pad 6a is connected to the wiring circuit layer 3b on the back surface via the via conductor 4a, the planar conductor 7, and the via conductor 4b.

  In this way, the entire ceramic wiring board 1 is moved in the Z direction by partially shifting the connection path through the plane conductor 7 without being linearly connected by the via conductor from the electrode pad 6a to the wiring circuit layer 3b on the back surface. Even when the via conductor 4 formed in the vertical direction does not sufficiently contract in the Z direction, the via conductor 4 becomes a via conductor 4a and 4b at a partially shifted step portion. Since it is divided, the via conductor is prevented from projecting to the surface side of the insulating substrate 2 as compared with the case where it is formed linearly, and the flatness of the entire electrode pad group including the electrode pad 6a is increased. Can do.

  Further, the ceramic wiring board has a longest length in the vertical direction from the center of the electrode pad 6a of the via conductor 4 directly connected to the electrode pad 6a, that is, a length L1 from the electrode pad 6a to the flat conductor 7 at the shifted portion. The total thickness L2 of the insulating substrate 2 is desirably 75% or less, and particularly desirably 60% or less, and further desirably 50% or less of the total thickness. Thereby, the protrusion of the substrate surface to the electrode pad 6a by the via conductors 4a and 4b can be effectively reduced.

  In addition, since the via conductors 4a and 4b are for forming an electric circuit, the diameter of the via conductor 4 is preferably 50 to 200 μm in order to reduce resistance.

  Further, the amount of deviation of the path in the via conductor 4, that is, the amount of deviation M between the center of the via conductor 4a and the via conductor 4b is equal to or larger than the diameter d of the via conductors 4a and 4b, and the via conductors 4a and 4b are particularly desirable. The diameter is preferably 2d or more.

  Further, in order to further reduce the protrusion due to the via conductor 4, the connection path from the electrode pad 6 a to the wiring circuit layer 3 b on the back surface of the insulating substrate is provided with three or more via hole conductors and two or more planar conductors formed inside. It is desirable to form with two or more stages depending on the combination with the pattern. Specifically, the schematic cross-sectional view of FIG. 3 is a diagram formed in two steps, and is formed from the electrode pad 6a via the via conductor 9a, the planar conductor 10a, the via conductor 9b, the planar conductor 10b, and the via conductor 9c. Connected to the wiring circuit layer 3b. Also in this case, the via conductors 9a, 9b, 9c are formed at positions shifted from each other, and the shift amounts M1, M2 between the via conductors 9a, 9b, between the via conductors 9b, 9c, and between the via conductors 9a, 9c are as follows. In any case, it is desirable that the via conductors 4a and 4b have a diameter d or more, particularly preferably the via conductors 4a and 4b have a diameter 2d or more.

  According to such a structure, the via conductor 9 connecting the electrode pad 6a and the wiring circuit layer 3b can be divided into a plurality of via conductors 9a, 9b, 9c, and the planar conductors 10a, 10b project the via conductors. As a whole, the flatness of the substrate surface by the via conductor can be increased. As the number of stages increases, the length of the connection path becomes longer and a predetermined area is required for routing. Therefore, the number of stages is preferably 5 or less.

  Furthermore, the thickness of the insulating layers 2a to 2e in the wiring board 1 is 150 μm or less and the total number of the insulating layers is 5 or more in order to incorporate various circuits such as inductors and capacitors and reduce the size and height. It is desirable that it be formed.

  The electrode pad 6a in the wiring substrate of FIGS. 1, 2, and 3 has been described as the one in which the semiconductor element 5 is flip-chip mounted. However, the electrode pad 6a is not limited to the flip-chip mounting but is wire-bonded. It may be an electrode pad. Moreover, it is not restricted to the semiconductor element 5, It may be an electrode pad for mounting various electronic components, such as a capacitor | condenser, a filter, and an inductor, with a brazing material.

  The insulating substrate in the ceramic wiring board of the present invention is composed of a glass ceramic sintered body obtained by firing glass powder or a mixture of glass powder and ceramic filler powder, thereby providing a wiring circuit layer, a thermal via conductor, and a via. Cu, Ag, Au, Ni, Pt, Pd, or a mixture thereof can be used for the conductor, the planar conductor layer, and the like.

  The wiring circuit layer 3 and the thermal via conductor 4 are filled with a conductor made of the same component as the wiring circuit layer 3 described above.

The glass component used includes at least SiO ₂ and contains at least one of Al ₂ O ₃ , B ₂ O ₃ , ZnO, PbO, alkaline earth metal oxide, and alkali metal oxide. Te, for _example, SiO 2 _-B 2 _{O 3 system, SiO2-B 2 O 3 -Al} 2 O 3 system -MO series (where, M is Ca, Sr, Mg, indicating the Ba or Zn) borosilicate glass, such as , Alkali silicate glass, Ba glass, Pb glass, Bi glass and the like. These glasses are desirably crystallized glass in which crystals are precipitated by firing in order to increase the substrate strength.

As the ceramic filler, SiO ₂ such as quartz and cristobalite, Al ₂ O ₃ , ZrO ₂ , mullite, forsterite, enstatite, spinel, magnesia and the like are preferably used.

  The glass component and the filler component are preferably 10% to 70% by weight of the glass component and 30% to 90% by weight of the ceramic filler component in order to increase the substrate strength.

  The ceramic wiring board of the present invention is usually prepared by adding an organic binder organic solvent or the like to the glass powder or a mixture of glass powder and ceramic filler powder to prepare a slurry, and then using a doctor blade method or a calender roll method. A ceramic green sheet having a predetermined thickness is produced.

  Thereafter, a through hole for forming a via conductor is formed in the ceramic green sheet by micro drilling, punching, laser processing or the like, and then Cu, Ag, Au, Ni, Pt, Pd, or a mixture thereof is formed in the through hole. The conductor paste is filled by screen printing or the like, and printed on various wiring circuit patterns.

  And after laminating and pressure-bonding the ceramic green sheet on which the via conductor and the wiring circuit layer are formed, the ceramic wiring substrate having the wiring circuit layer and the via conductor can be manufactured by firing at a temperature of 850 to 1000 ° C. .

  The ceramic wiring board of the present invention is particularly suitably applied to those fired so that the amount of firing shrinkage in the XY direction is smaller than the amount of firing shrinkage in the Z direction. In the case of a normal firing method, firing shrinks at the same level with respect to the X, Y, and Z directions, but firing so that the amount of firing shrinkage in the XY direction is smaller than the amount of firing shrinkage in the Z direction. In this case, the shrinkage amount of the via conductor is less likely to sufficiently shrink following the shrinkage amount of the ceramic in the Z direction. In such a case, by adopting the structure of the ceramic wiring board of the present invention, the protrusion due to the via conductor can be reduced and the flatness of the substrate surface can be increased.

  As a method of firing so that the amount of firing shrinkage in the XY direction is smaller than the amount of firing shrinkage in the Z direction, for example, according to the method described in JP-A No. 2001-158670, as shown in FIG. After laminating a sheet 12 mainly composed of a hardly sinterable ceramic material, which is difficult to sinter at the firing temperature of the ceramic green sheet, on the upper and lower surfaces of the laminate 11 of the ceramic green sheet, the laminate is fired. Therefore, the ceramic green sheet laminate 11 is restrained from shrinking in the XY direction by the frictional force with the sheet, and is forcedly shrunk in the Z direction. -The shrinkage in the Y direction can be reduced, and a wiring board with high dimensional accuracy can be produced.

  The hard-to-sinter ceramic sheet is mainly made of a ceramic material that does not sinter at the firing temperature, such as alumina and silica, and is appropriately molded into a sheet with an appropriate amount of glass added as an adhesive. The In addition, by applying pressure in the Z direction upon firing, firing shrinkage in the Z direction can be further promoted, and a wiring board with high dimensional accuracy in the XY direction can be manufactured.

  Next, an example in which the ceramic wiring board according to the present invention was produced will be described.

SiO ₂ —Al ₂ O ₃ —MgO—B ₂ O ₃ —ZnO-based glass 60% by mass, alumina powder having an average particle diameter of 1 μm as a ceramic filler, 40% by weight, organic binder, acrylic resin, solvent Toluene was added and mixed to prepare a slurry, which was then formed into a sheet on a carrier film by a doctor blade method to prepare a green sheet having a thickness of 50 to 150 μm.

  Next, a through hole was formed in the green sheet by punching, and a Cu conductor paste was filled therein to form a via conductor having a diameter of 100 μm. The conductor paste is prepared by adding acrylic resin and toluene to Cu powder and mixing them uniformly. And the said copper paste was printed on the surface of this green sheet with the screen printing method, and the electrode pad, wiring circuit layer, and planar conductor with a diameter of 200 micrometers were formed.

  Thereafter, 5 to 12 green sheets obtained in the same manner were laminated and pressed to form a green sheet laminate.

On the other hand, 97% by mass of alumina powder having an average particle size of 1 μm and ₃ % by mass of SiO ₂ —Al ₂ O ₃ —MgO—B ₂ O ₃ —ZnO-based glass are added and mixed. Two sinterable sheets were produced. Then, the hardly sinterable sheet was laminated and pressure-bonded to the upper and lower surfaces of the green sheet laminate.

  And this laminated body was heat-processed in 400-750 degreeC nitrogen atmosphere, the organic component in a green sheet or a conductor paste was decomposed and removed, and it baked in 900 degreeC nitrogen atmosphere for 1 hour. And the hard-to-sinter sheet | seat adhering to the surface was removed by the sandblasting method. The XY shrinkage ratio obtained from the dimensions before and after firing was 0.5%, which was high in dimensional accuracy.

  In this example, the electrode pads to be flip-chip mounted were arranged in a matrix with 15 vertical and 15 horizontal electrode pads with a pitch of 0.5 mm. As shown in Table 1, the connection path between the electrode pad on the front surface of the substrate and the wiring circuit layer on the back surface of the substrate is the via diameter, the shift amount between the via conductors, and the electrode of the via conductor directly connected to the electrode pad. Various changes were made to the maximum vertical length from the pad.

With respect to the manufactured evaluation sample, the flatness of the substrate surface of the semiconductor element mounting portion is measured by a surface shape measuring microscope, and the semiconductor chip including the electrode pad having a flatness of 20 μm or more in the flip chip mounting portion is regarded as a defective product. did.

  From Table 1, sample No. 1 in which the electrode pad and the wiring circuit layer on the back surface of the substrate are formed with only one vertical via conductor. 1 and 10, the flatness exceeded 20 μm, and it was not suitable for flip chip mounting. On the other hand, the product of the present invention formed by two or more via conductors formed at a shifted position between the electrode pad and the wiring circuit layer on the back surface of the substrate and the planar conductor connecting them has a flatness of 20 μm or less. Thus, it was possible to provide a wiring board having almost no XY shrinkage and excellent flatness.

  In particular, the longest vertical length of the via conductor directly connected to the electrode pad from the electrode pad is 60% or less of the total thickness of the insulating substrate, and the displacement of the connection path is from the center of the electrode pad. The flatness was further improved by being equal to or larger than the diameter of the via-hole conductor, and the flatness was reduced as the number of via conductors was increased by increasing the number of steps of deviation.

It is a schematic sectional drawing for demonstrating the ceramic wiring board of this invention. It is a schematic sectional drawing for demonstrating another ceramic wiring board of this invention. It is a schematic sectional drawing for demonstrating another ceramic wiring board of this invention. It is a schematic sectional drawing for demonstrating an example of the manufacturing method of the ceramic wiring board of this invention. It is a principal part expanded sectional view of the conventional ceramic wiring board.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Ceramic wiring board 2 Insulating board 2a-2d Ceramic insulating layer 3 Wiring circuit layers 4, 9 Via conductor 5 High frequency semiconductor element 6 Electrode pad 7, 10 Planar conductor

Claims (7)

Filled and fired with an insulating substrate formed by laminating a plurality of insulating layers, a planar conductor pattern formed on the front, back and inside of the insulating substrate, and a paste containing metal powder so as to penetrate the dielectric layer In a ceramic wiring board comprising a plurality of electrode pads that are made via conductors, and electrical elements and flip-chip mounting on the insulating substrate surface, surface mounting using a brazing material, or wire bonding,
The via conductor directly connected to the electrode pad is connected to the planar conductor pattern on the back surface of the insulating substrate, and a part of the connection path is partially displaced from the vertical direction of the center of the connection pad. Characteristic ceramic wiring board. 2. The ceramic wiring board according to claim 1, wherein the longest vertical length of the via conductor directly connected to the electrode pad is 60% or less of the total thickness of the insulating substrate. 3. The ceramic wiring board according to claim 1, wherein a displacement amount of the connection path is equal to or larger than a diameter of the via-hole conductor from the center of the electrode pad. 4. The ceramic wiring board according to claim 1, wherein the via conductor has a diameter of 50 to 200 [mu] m. 2. The insulating substrate, wherein the connection path from the electrode pad to the planar conductor pattern on the back surface of the insulating substrate comprises a combination of three or more via-hole conductors and two or more planar conductor patterns formed inside. The ceramic wiring board according to claim 4. 6. The ceramic wiring board according to claim 1, wherein the insulating layer has a thickness of 150 [mu] m or less, and the total number of the insulating layers is 5 or more. The ceramic wiring board according to any one of claims 1 to 6, wherein the wiring board is fired so that a firing shrinkage amount in the XY direction is smaller than a firing shrinkage amount in the Z direction.

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