JP2006031155A - Semiconductor device and bus system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent fluctuation of terminal voltage V<SB>T</SB>due to an increased current of a terminal resistance 1 resulting from continuous output of a signal having a logic pattern of approximation to a bus of T-LVTTL transmission system. <P>SOLUTION: When an address is matched to a given address, an address comparator 7 transmits a matching signal 73. An inverting circuit 6 inverses, on receipt of the matching signal 73, a signal transferred between a bus 1D and an internal circuit 101. Since a series of data having continuous addresses are inversely inputted and outputted only when a predetermined address is designated, the logic pattern of approximation is inverted there and interrupted, so that continuous output of the logic of approximation can be prevented. When the terminal voltage V<SB>T</SB>exceeds a predetermined range, a dummy signal of logic "1" or "0" is outputted to an invalid bus to correct the terminal voltage. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device that drives a bus composed of a transmission line terminated with a termination resistor using a complementary signal, and more particularly to a semiconductor device that accesses a semiconductor memory device, and such a bus and a bus including the semiconductor device. About the system.

  A bus system for driving a bus composed of a transmission line terminated with a termination resistor by using a complementary signal, for example, a T-LVTTL (Terminated Low Voltage Transistor Transistor Logic) type or CTT (Center Tapped Termination) type bus system is a semiconductor. Since it is excellent in high-speed signal transmission capability between devices, it is widely used for signal transmission requiring high speed, for example, signal transmission between a CPU and a semiconductor memory device.

  FIG. 18 is a block diagram of a conventional resistance-terminated bus system, showing a T-LVTTL type bus system. FIG. 19 is a T-LVTTL circuit diagram showing a set of transmission line, output circuit, and receiving circuit constituting the T-LVTTL bus system.

Referring to FIG. 18, a bus system for connecting a semiconductor device 100 and the semiconductor memory device 200 including a CPU, a data bus 1D consisting transmission line 1 of N _D present, consisting of the transmission line 1 of N _A present An address bus 1A and a control bus 1C composed of N _C transmission lines 1 to which control signals are transmitted are provided. The bus system further includes a reference voltage source 5 that generates a reference voltage V _REF and a termination voltage source 3 that generates a termination voltage V _T. The output of the reference voltage source V _REF is applied to the reference voltage input terminal 20 of the semiconductor device 100 and the semiconductor memory device 200 via a wiring. On the other hand, the output of the termination voltage source 3 is connected to one end of the termination resistor 4 via a wiring, and supplies a common termination voltage V _T to all the termination resistors 4.

  The output circuit 11 converts a signal transmitted from the internal circuit 101 of the semiconductor device 100 or the memory circuit 201 in the semiconductor memory device 200 into a complementary signal and outputs it to the transmission line 1. The input circuit 12 receives a complementary signal on the transmission line 1, converts it to the logic level of the internal circuit 101 or the memory circuit 201, and inputs the signal to these circuits 101 and 201.

Referring to FIG. 19, the transmission line 1 is terminated to a termination voltage V _T by, for example, a 75Ω termination resistor 4. This termination voltage V _T is set to an intermediate potential between the top line and the base line of the complementary signal transmitted through the transmission line 1, for example, ½ of the power supply voltage VCC of the output circuit 11. The output circuit 11, the two transistors T _R 1, T _R 2 consists CMOS push-pull circuit connected in series, from the high-voltage high level signal and low level signal of the low voltage from the terminal voltage V _T than the terminal voltage V _T The complementary signal is output to the transmission line 1. Note that the output can be in a high impedance state. The input circuit 12 is composed of a differential amplifier circuit having the reference voltage V _REF applied to the reference voltage input terminal 20 as one input, and a complementary signal on the transmission line 1 is connected to the other input terminal of the differential circuit. _Is input and compared with the reference voltage V _REF to determine the logic level. Note that the termination voltage V _T can also be used as the reference voltage V _REF . (See Patent Document 1 for T-LVTTL.)

Such a bus system is suitable for transmitting a high-speed signal because the amplitude of the signal to be transmitted is small and the signal level can be symmetric with respect to the termination voltage V _T (or the reference voltage V _REF ). However, in this bus system, the power consumption increases depending on the signal pattern of the complementary signal, and it is necessary to secure a power supply having a sufficient current capacity to cope with this. Next, this power consumption will be described. In this specification, “signal pattern” refers to a logical pattern of signals simultaneously existing on a plurality of lines, and is distinguished from a sequence of signal patterns including time changes.

In this bus system, when a high level signal is output from the output circuit 11, the transistor T _R2 connected to the power supply voltage VCC is turned on, and the transistor T _R1 connected to the ground is turned off. At this time, the signal current output from the output circuit (hereinafter referred to as "source current" Ic.) Sequentially transistor T _R 2 from the power supply voltage VCC of the output circuit 11, the transmission line 1 and through the terminating terminal resistor 4 voltage V _T Flows into. Conversely, when a low level signal is output from the output circuit 11, the transistor T _R2 connected to the power supply voltage VCC is turned off, and the transistor T _R1 connected to the ground is turned on. At this time, the signal current absorbed into the output circuit (hereinafter referred to as “sink current” I _S ) passes from the termination voltage V _T to the ground voltage of the output circuit 11 through the termination resistor 4, the transmission line 1, and the transistor T _R 1. Inflow.

The sum I _{TT of} the source current I _C and sink current I _S flowing into or out of the termination voltage V _T through the termination resistor 4 (ie, the current flowing in the termination voltage V _T ) is the number of high level signals output to the bus. When M _H and the number of low level signals are M _L ,
I _TT = M _H × i _C −M _L × i _S
It is expressed. Here, i _C and i _S are a source current I _C and a sink current I _S flowing through one termination resistor 4, respectively.

Therefore, when i _C = i _S where the complementary signal is a complete complementary type, if the number of high level signals and low level signals simultaneously output to the bus is the same (ie, M _H = M _L ), the termination voltage current does not flow through the V _T. On the other hand, even if i _C = i _S , if the number of high level signals and low level signals is greatly biased to either one, the absolute value of the current I _TT flowing in the termination voltage V _T is the difference between the numbers (M It increases in proportion to ( _H − _ML ). Increasing or decreasing the current I _TT causes fluctuations in the termination voltage V _T and increases the error rate of the bus system. For this reason, the termination voltage source 3 is required to have a sufficient current capacity so that the termination voltage V _T can be held in a specified voltage range even when the absolute value of the current I _TT flowing in the termination voltage V _T is maximum.

If the period during which the current I _TT is maximized is short, a small-capacity termination voltage source 3 can be used by connecting a smoothing capacitor in parallel to the termination voltage source 3 and absorbing the peak current of the current I _TT . However, the method of smoothing the current I _TT using a smoothing capacitor is not practical in applications where one of the high level signal and the low level signal continues for a long period of time because the capacity of the smoothing capacitor becomes too large.

Such a large difference between the number of high-level signals and the number of low-level signals continuously occurs for a long period of time, especially when accessing a semiconductor memory device, in particular, an approximate signal pattern is frequently generated continuously. This is likely to occur frequently when accessing semiconductor memory devices related to For example, in image processing, data signals that are all composed of high level signals or all composed of low level signals or data signals having a pattern close to this are frequently input and output to successive memory addresses. In this case, the smoothing capacitor cannot prevent the termination voltage V _T from shifting due to the deviation of the signal pattern over a long period of time. For this reason, the image processing has a problem that the terminal voltage source 3 having a sufficient capacity corresponding to the signal pattern in which the maximum current I _TT flows is necessary.

A similar problem occurs with the termination voltage source 3 that supplies the power supply voltage VCC and the termination voltage V _T of the output circuit 11. That is, since the source current I _C flowing out from the power supply voltage VCC increases in proportion to the number of high level signals, if a signal pattern with a large number of high level signals continues, a large power supply current (the power supply voltage VCC power supply voltage VCC) Current) flows. Similarly, a large sink current flows in the termination voltage V _T for a long time when a signal pattern having a large number of low level signals continues. Therefore, the output circuit 11 and the termination voltage source 3 require a large current capacity power source.
Japanese Unexamined Patent Publication No. 7-95220 (paragraphs (0002) to (0014) and FIG. 25)

  As described above, in a conventional bus system in which a bus composed of a transmission line terminated with a termination resistor is driven using a complementary signal, a signal pattern unevenly distributed in a high level signal or a low level signal is continuously transmitted over a long period of time. In some applications, a large-capacity termination voltage source is required. Also, a large current capacity is required for the power supply of the semiconductor device. As a result, the bus system becomes expensive and power consumption increases.

  The present invention drives a bus system capable of reducing the current capacity of a termination voltage source for supplying a termination voltage and a power source for supplying a power supply voltage of a semiconductor device, even in an application where unevenly distributed signal patterns are continuous, and the bus. An object is to provide a semiconductor device.

  A semiconductor device having a first configuration according to the present invention for solving the above-described problem is a semiconductor including a data input / output circuit for inputting / outputting complementary signals to / from a plurality of transmission lines terminated to a termination voltage via a termination resistor. Regarding the device, an address comparison circuit that sends a match signal when the transmission destination or transmission source address matches a predetermined address, and data that is transmitted between the internal circuit and the data input / output circuit when the match signal is received And an inverting circuit for inverting the signal.

  According to the first configuration, when accessing a predetermined address, the data on the transmission line (the logic indicated by the complementary signal) and the data input to and output from the internal circuit (the logic indicated by the data signal) are inverted. To do. Hereinafter, this configuration will be described separately when data is output and when it is input.

  In this configuration, when storing a series of data output from the internal circuit to the transmission destination, when sequentially accessing a plurality of addresses specifying the data transmission destination and sequentially outputting the series of data to the transmission line, Inverted data is output at a predetermined address, and non-inverted data is output at other addresses. As a result, the data signal output to the transmission line is mixed with the inverted data signal and the non-inverted data signal with the progress of access, in other words, with the passage of time. For this reason, even if a series of data signals output from the internal circuit is a data signal containing one logical value (for example, a high level signal), the complementary signal output from the data input / output circuit to the transmission line is Both logical values (high level signal and low level signal) are mixed on the time axis. Therefore, both logical values are interchanged in a short period, and as a result, the time averages of the numbers of both logical values are almost equal in a short period.

  For example, when a 4-bit data signal pattern (0001) is continuous, if an address and a predetermined address are accessed so as to alternately match and mismatch every two clocks, (0001) (0001) (1110) (1110) When four signal patterns are repeatedly output to the data bus (in this example, a bus including four transmission lines corresponding to 4 bits), a time average of logic 1 and 0 is obtained when a time interval of 4 clocks or more is taken. Are equal (in this example, the number of logic 1s and 0s per time averaged clock is equal to 2 each). This is an example of the same data signal pattern, but even if the data signal pattern changes, the time average of logic 1 and 0 can be regarded as practically equal if the signal pattern is similar. .

  As described above, according to this configuration, the high level signal and the low level signal output to the bus alternate in a short period of time, so that the termination voltage and the power supply of the output circuit of the semiconductor device can be easily used with a small-capacity smoothing capacitor. The flowing peak current can be absorbed. Further, since the time average values of the high level signal and the low level signal output to the bus are substantially equal, even if the smoothing capacitor and the termination voltage source have a small capacity, a shift of the termination voltage in one direction is avoided. For this reason, the power supply of the termination voltage source and the output circuit of the semiconductor device can be reduced.

  Furthermore, in this configuration, when data is input from the transmission source to the internal circuit, the input data signal of the data input / output circuit is inverted and input to the internal circuit when the address specifying the data transmission destination matches the predetermined address. The As described above, since transmission data to a predetermined address is inverted and transmitted, it is necessary to receive data returned from the predetermined address as inverted data. For example, when the address designates a memory device (for example, a semiconductor memory device), inverted data is written to the predetermined address, and this inverted data is read and returned. In this configuration, since data at a predetermined address is inverted at the time of reception, normal logical value data can be input to the internal circuit.

  In the first configuration, a plurality of predetermined addresses can be designated. This designation may be an address in which one or more specific bits in the bits constituting the address take a logical value 0 or 1. Address match can also be determined for a portion from which a part of the address is extracted. In this case, the address comparison circuit can be made small.

  According to a second configuration of the present invention, the first configuration is applied to a system for accessing a semiconductor memory device divided into a plurality of regions. In the second configuration, the address includes an area designation address that designates the area and an in-area address that designates an address in the area. Further, an address storage device for storing a predetermined address for each area is provided. When the in-area address matches a predetermined address stored in the address storage device in the designated area, the address comparison circuit sends a match signal to invert the transmission data between the data input / output circuit and the internal circuit. .

  In this configuration, a predetermined address can be set for each of a plurality of areas. Therefore, by assigning an area for each program or for each data having different characteristics, it is possible to designate a predetermined address suitable for the characteristics of the program and data. For example, in a program that uses a series of image data, two different intervals can be designated by two predetermined addresses in an application in which image data stored at two different intervals is processed. Further, the present invention can be applied to a program that alternately accesses data having a small bias in the logical pattern or data having different patterns in a short time. In these cases, it is possible to select the designated address so that the switching operation of the inverting circuit between the inversion and non-inversion is reduced, and to reduce the power consumption associated with this switching.

  In the semiconductor device having the third configuration according to the present invention, the accumulated number of differences between the number of high-level signals and the number of low-level signals output to the bus are respectively determined by predetermined values (first and second accumulated numbers). Difference accumulating means for sending a correction signal indicating that it is within or less than or greater than that range. Here, “becomes” less than or more than that range includes the case where the predetermined value when exiting and entering the range have different hysteresis characteristics from the predetermined value when entering. By providing the hysteresis characteristic in this way, the pull-back operation (that is, sending of the correction signal) once the cumulative number is out of the range can be stably continued, so that the circuit operation caused by sending the correction signal An increase in power consumption associated with can be suppressed. Of course, it does not have to have hysteresis characteristics. If the first and second cumulative numbers match, information indicating that the number is within the range can be omitted.

  Furthermore, it comprises validity determination means for detecting an invalid transmission line (a transmission line in which a valid signal is not transmitted) and sending a determination signal for specifying the invalid transmission line. When an invalid transmission line is detected, a dummy signal is output to the invalid transmission line. As the dummy signal, the high level signal is selected when the cumulative number of differences between the number of high level signals and the number of low level signals indicated by the correction signal is less than a predetermined range, and the low level signal is selected when the cumulative number is large. For this reason, the difference in the number of high-level and low-level signals output to the bus is corrected by adding a dummy signal and stays within a predetermined range for a long period. Therefore, even if a signal pattern biased to one level is continuously transmitted as an effective signal, it is corrected in the same number of directions by the dummy signal. In addition, even when a signal whose difference in the number of high-level and low-level signals is slightly biased to one side is transmitted over a long period of time, such a slight deviation is accumulated because the accumulated number of signals is corrected to be the same. Never do.

  The termination voltage provided with the smoothing capacitor shifts depending on the cumulative number of differences between the number of high-level signals and the number of low-level signals previously output to the transmission line. For this reason, if a signal pattern biased to one level continues for a long period of time, if the current capacity of the termination voltage source is small, the termination voltage shifts in one direction and the error rate of the bus increases. According to this configuration, since the difference in the number of high level and low level signals over a long period is corrected and reduced by the dummy signal, the long-term termination voltage in one direction that occurs when a smoothing capacitor is used as the termination voltage source. Shift can be suppressed. For this reason, the peak current flowing in the termination voltage can be absorbed using the smoothing capacitor, and the capacitance of the termination potential source can be reduced.

  In the fourth configuration of the present invention, the termination voltage applied to the termination resistor is within a range determined by predetermined voltages (first and second voltages) instead of the difference accumulation means of the third configuration. Or a termination voltage monitoring circuit for sending a correction signal indicating that the signal is lower or higher than the range. Again, “lower” or “higher” means including a case having hysteresis characteristics. When the termination voltage exceeds a predetermined range, a dummy signal is output to the invalid transmission line, and the termination voltage is brought close to the predetermined range. Therefore, similarly to the third configuration, a smoothing capacitor can be used to reduce the current capacity of the termination voltage source, and further can be omitted.

  The third or fourth configuration described above can also be applied to the semiconductor device having the first or second configuration. In the bus system using the semiconductor devices having the first to fourth configurations described above, the termination voltage can also serve as the reference voltage of the differential amplifier circuit that constitutes the input circuit. Moreover, it can also comprise only a smoothing capacitor as a termination voltage source of a 1st-4th structure. As a result, the number of voltage sources can be reduced or omitted, and the device cost can be reduced. Furthermore, the inversion operation of the inversion circuit described above can be stopped by a stop signal input from the outside or generated by a program. By this stop, the data bus returns to the same operation as that of a normal conventional system. By applying this stop signal to the initial operation after power-on, the smoothing capacitor can be charged more quickly and the rising period can be shortened.

  According to the present invention, a complementary signal is output to a bus having a transmission line terminated to a termination voltage via a termination resistor so that the number of high-level signals and low-level signals is equal. The power source of the power source and the semiconductor device can be reduced, and a low-cost semiconductor device and bus system with low power consumption can be provided.

(1) First Embodiment A first embodiment of the present invention relates to a circuit for driving a bus system including an image processing semiconductor device and a semiconductor memory device therefor. FIG. 1 is a block diagram of a first embodiment of the present invention, showing a semiconductor device, a semiconductor memory device, and a bus system connecting between the semiconductor device according to the first embodiment of the present invention.

Referring to FIG. 1, the bus, N _D present (e.g. 32) data bus 1D consisting transmission line 1, N _A present (e.g. 12) transmission line address bus 1A and N _C present consisting of 1 ( For example, a control bus 1C including nine transmission lines 1 is included. Each transmission line 1 is terminated to a common termination voltage V _T by a termination resistor 4. One end of these transmission lines 1 is connected to the input circuit 12, the output circuit 11 or the input / output circuit 2 of the semiconductor device 100, and the other end is connected to a similar circuit of the semiconductor memory device 200. Further, a termination voltage source 3 and a reference voltage source 5 for generating a termination voltage V _T and a reference voltage V _REF are provided. A part or all of the input / output circuit 2 of the semiconductor device 100 connected to the control bus 1C can be replaced with the output circuit 11 depending on the application. These are the same as the conventional bus system. Further, since the input circuit 12 and the output circuit 11 are the same as the conventional T-LVTTL circuit shown in FIG. 19, the following description will be given with reference to FIG.

Referring to FIGS. 1 and 19, the termination voltage V _T, the top line of the complementary signal output to the transmission line 1 from the output circuit 11 (the voltage level during a high-level signal) to the baseline (at a low level signal The intermediate voltage of the voltage level), for example, 1/2 of the power supply voltage VCC of the output circuit 11 is selected. The reference voltage V _REF is normally set equal to the termination voltage V _T. In this case, the termination voltage V _T and the reference voltage V _REF can be shared by one power source, for example, the termination voltage source 3.

The reference voltage V _REF is applied to the reference voltage input terminal of the input circuit 12 through the reference voltage input terminal 20 of the semiconductor device 100 and the semiconductor memory device 200. The input circuit 12 has a differential amplifier circuit, and differentially amplifies the complementary signal of the transmission line 1 input to the other end and the reference voltage V _REF applied to the reference input end, and outputs a logic signal. . In FIG. 1, the input circuit and the output circuit of the semiconductor memory device 200 are omitted.

The output circuit 11 has a CMOS push-pull circuit, and outputs the input logic signal to the transmission line 1 as a complementary signal. The voltage level of the complementary signal output from the output circuit 11 is, for example, the top when the power supply voltage VCC of the output circuit 11 is 2.5 V, the ground potential is 0 V, the termination voltage V _T and the reference voltage V _REF are 1.25 V. The line is 2.5V and the base line is 0V. Therefore, for example, a 16.6 mA source or sink current I _C or I _S flows through the termination resistor 4 of 75Ω. If necessary, some or all of the output circuits 11 may be three-state output circuits including a high impedance state.

  The internal circuit 101 of the semiconductor device 100 includes a control circuit 22 that controls the bus system. The control circuit 22 inputs and outputs control signals to and from the control bus IC via the control register 24. The internal circuit 101 further includes an address calculation circuit 21 that calculates a transfer destination or transfer source address. The address calculated by the address calculation circuit 21 is output to the address bus 1A via the address register 23.

  Further, the address calculation circuit 21 transmits the calculated address 71 to the address comparison circuit 7. As described above, the address 71 to be transmitted to the address comparison circuit 7 is directly acquired from the address calculation circuit 21 instead of the address register 23. As a result, the address output to the address bus IA can be acquired early. This is because the address calculation circuit 12 normally has means such as address prefetching, and can acquire an address to be executed considerably later than the address currently being executed.

FIG. 2 is a block diagram of an address comparison circuit according to the first embodiment of the present invention. The address of N _A bits (for example, 12 bits) input to the address comparison circuit 7 is stored in the register 71A, and any n _A bits are selected as the selection bits 72 from among them. The number and position of the selected bits may be fixed in advance or may be changed by a program.

  A predetermined address 74 having the same bit length as the selected bit 72 is stored in a register memory 75 including a plurality of (for example, four) registers before or during execution of the program by the program to be executed.

  The comparison circuit 76 is provided for each register constituting the register memory 75, and outputs a coincidence signal 73 when a predetermined address 74 stored in the register coincides with the selection bit 72. The output of each comparison circuit 76 is input to an OR gate, and the output is sent from the address comparison circuit 7 as a match signal 73. Therefore, if the predetermined address 74 stored in any one register constituting the register memory 75 matches the selection bit 72, the address comparison circuit 7 outputs a match signal 73. In the storage location of the predetermined address 74, a bit string obtained by extracting only the bit at the position corresponding to the selection bit 72 from all the bits of the predetermined address 74 is stored.

  Referring again to FIG. 1, the coincidence signal 73 output from the address comparison circuit 7 is input as a control signal for the inverting circuit 6 inserted between the internal circuit 101 and the data input / output circuit 2. When the coincidence signal 73 is input, the inverting circuit 6 inverts the data signal output from the internal circuit 101 and transmits it to the output circuit 11 of the data input / output circuit 2, and from the input circuit 12 of the data input / output circuit 2. The output data signal is inverted and transmitted to the internal circuit 101. Therefore, when the coincidence signal 73 is active, the input / output data signal of the internal circuit 101 and the complementary signal on the data bus 1D are in a mutually inverted relationship. On the other hand, when there is no coincidence signal 73, that is, when it is inactive, the inverting circuit passes the data signal as it is. Accordingly, at this time, the input / output data signal of the internal circuit 101 and the complementary signal on the data bus 1D are in phase with each other. The inverting circuit 6 can be realized by an exclusive OR circuit as is well known.

FIG. 3 shows a modification of the address comparison circuit of the first embodiment, and shows a modification of the address comparison circuit shown in FIG. Referring to FIG. 3, the address comparison circuit 7 according to the modified example receives n _A selection bits 72 (for example, 3 of the second, third, and fifth bits) from the output of the register 71A that stores the N _A bit address. Selected) and input to the AND circuit. Therefore, when all the selection bits 72 are logic 1, a coincidence signal 73 is output. In this variation, the circuit is simple and fast. It is also possible to provide a plurality of AND circuits for inputting different sets of selection bits and to use the logical sum of the outputs as the coincidence signal 73. Thereby, a plurality of predetermined addresses 74 can be designated by a simple circuit.
(Write operation of the first embodiment)
First, the write operation of the first embodiment will be described in comparison with the above-described conventional bus system. The write cycle to the semiconductor memory device 200 was performed with a burst length of 4, a data mask bit of L, a CS bit of L, and a CKE bit of H. In the present embodiment, the input terminals of these data mask bit, CS bit, and CKE bit can be directly connected to a high-level or low-level potential, and no transmission line is connected to these input terminals. Of course, if necessary, the transmission line 1 constituting the control bus 1C can be connected to these input terminals. The selection bit 72 selects the second bit of the write address (which is a logical address), and a match signal 73 is output when this bit of the address is logic “1”. That is, a series of addresses, for example, a series of write addresses (−−0), (−−1), (−−2), (−−3), (−−4) represented by a three-digit hexadecimal number, When (--5), (--6), and (--7) are successively accessed, the inverted data is output to the data bus 1D every two addresses, that is, every two clocks. Specifically, non-inverted data at addresses (--0), (--1), (--4), and (--5) are converted into addresses (--2), (--3), and (- The data inverted in −−6) and (−−7) is output. Hereinafter, the address and data contents are displayed in hexadecimal and the control signal is displayed in octal. In addition,-in () represents arbitrary logic values.

  FIG. 12 is an explanatory diagram of a write operation according to the first embodiment of the present invention, and FIG. 13 is an explanatory diagram of a write operation of a comparative example, showing the operation of a conventional bus system. Here, the control signal, address bus signal and data bus signal are complementary signals output to the control bus 1C, address bus 1A and data bus 1D, the write address is the logical address of the system, and the write data is the semiconductor memory. Data to be written to the device 200 is shown.

  In order to simplify the description, a case will be described here in which write data composed of 32-bit data per word is stored in write addresses (logical addresses) that are continuous every 8 words.

  Referring to FIG. 13, first, control signal ACTV (logic “3” indicating bank active) is output to control bus 1C, and row (RAW) address (000) of semiconductor memory device 200 is output to address bus 1A. To do. Next, following the control signal NOP (logic “7” indicating that there is no valid command), the control signal WRT (logic “4” indicating write) and the column (COLUMN) address (000) serving as the head address to the address bus 1A are displayed. ) Is output.

  Next, together with the WRT signal, the first word of write data is output to the data bus 1D, and the remaining three words are sequentially output to the data bus 1D during the subsequent three clocks. Then, the four words in the first half of the write data are written into four consecutive addresses (addresses in the semiconductor memory device 200) following the column address (000). Thereafter, the column address (404) is again output to the address bus IA together with the WRT signal, and the remaining four words of the write data are sequentially output to the data bus 1D, and the “0th bank ( 04) ”is written to four consecutive addresses. Thus, 8-word write data is stored in the addresses (addresses) designated by the eight column addresses of the row address (000) block of the semiconductor memory device 200, that is, (000) to (007) of the 0th bank. Is done. Here, the first digit of the column address (404) includes the designation of the bank and the precharge operation, and the first digit displayed in a 4-digit binary number designates the bank and the second digit designates the precharge operation. For example, the first digit “4” of the column address (404) is (0100) in binary notation, designates the bank 0 and instructs the precharge operation, and the following two digits “04” The (04) address in hexadecimal notation is shown. Similarly, the first digits “8” and “C” of the column address are (1000) and (1100), respectively, in binary notation, each designates the first bank, does not perform the precharge operation, and designates the first bank. This indicates that the precharge operation is performed by designating.

  Similarly, another 8-word write data is written in the logical addresses (80000) to (80007) following the above write operation, that is, the eight column addresses (800) to (803) of the row address (800) block. ), (804) to (807).

  The address calculation circuit 21 calculates an address 71 of the transmission destination (write destination) and transmits it to the address comparison circuit 7. The address 71 does not need to match the address output to the address bus 1A, that is, the address designated by the address bus signal, and for example, a write address that is a logical address can be used. When the second bit of the write address is logic “1”, the address comparison circuit 7 has, for example, the write address (−−−− 2), (−−−− 3), (−−−− 6), (− ---- 7),..., The match signal 73 is sent, so that the data on the data bus 1D and the write data are inverted from each other while these write addresses are accessed.

  In the address comparison circuit 7 described above, the match or mismatch of the write address, which is a logical address, is determined. Instead, the address to be output to the address bus 1A, that is, the address specified by the address bus signal is determined. You can also. At this time, in the present embodiment having a burst length of 4 words, since the address of 3 words following the head address is not output, it is necessary to calculate in the address calculation circuit 21.

  As described above, in the present embodiment, when eight consecutive write addresses are continuously accessed, the coincidence signal 73 is output every two accesses, that is, every two clocks. Therefore, the data bus signal appearing on the data bus 1D is a signal that appears by alternately alternating inverted data and non-inverted data every two clocks.

  Referring to FIG. 12, the write data consisting of the first 8 words is composed of small numerical values and has many logic “0”. However, the write data is inverted every two clocks, and the logic of the inverted data bus signal is “1”. Further, write data consisting of another 8 words to be subsequently written has a large numerical value, and has a lot of logic “1”. Similarly, this write data is inverted every two clocks and becomes a data bus signal containing a lot of logic “0”. In this way, even when write data containing a lot of logic “1” or “0” is written, a data bus signal string in which both logics are mixed on the time axis is output to the data bus 1D. .

All source currents and all sink currents flowing through the buses 1D, 1A, 1C (hereinafter referred to as “total source currents” and “total sink currents” are sums and sinks of source currents flowing through the data bus 1D, address bus 1A, and control bus 1C, respectively. Is the sum of currents 1), source current and sink current I _C , I _S are both 16.6 mA, and there are 53 transmission lines 1 constituting buses 1D, 1A, 1C. Of these, the number of data buses 1D is as large as 32, and the influence of the logic pattern of the write data output to this bus is the largest.In this embodiment, both logics are mixed in the data bus signal on the time axis. Therefore, the time average of all source currents and all sink currents (for example, the average of 4 clocks), and also the termination voltage source current (the termination voltage V _T ) which is the difference between these currents. The time average of the flowing current is small.

  The total source current (the sum of the total sink current and the total sink current is constant) is large mainly when a signal having a lot of logic “1” is output as a data bus signal, and between signals having a lot of logic “0”. small. Referring to FIG. 12, a period in which a pattern with a lot of logic “1” is output, for example, two clocks in which (FFFFFFFD) (FFFFFFFC) is output, then two clocks later (FFFFFFF9) (FFFFFFF8) (FFFFFFFF) A large total source current flows between four clocks when (FFFFFFFE) is output and between two clocks when (FFFFFFFB) and (FFFFFFFA) are output with a delay of two clocks. However, before and after the period during which the large current flows, a two-clock period in which a pattern with many small logic “0s” is output is inserted. Thus, the total source current varies between a large current and a small current in units of 2 clocks or 4 clocks, and the same or approximate level of the total source current does not continue for a longer period. The total source current that fluctuates in 2 to 4 clocks is easily smoothed by a small-capacity smoothing capacitor (a stray capacitance may be used if possible). Therefore, the power supply capacity of the output circuit 11 of the semiconductor device that is the source of the source current is sufficiently smaller than the peak current of 0.88A and closer to the average current (practically, it may be 0.44A). It becomes possible to do.

  Note that during the period when no valid signal is output for the address bus signal and data bus signal (indicated by-in the figure), a signal having the same number of logic "1" and "0" (55..5) is output. To do. Thereby, the difference between the total source current and the total sink current can be reduced. This method can also be applied to control signals if possible.

The termination voltage source current flowing in the termination voltage source 3 is a value obtained by subtracting all sink currents from all source currents. When the absolute values of both currents are equal, that is, the logic “1” of the complementary signal output to the bus. When the number of “0” is equal, it is 0 (indicated by a dotted line in the figure). Since a valid data bus signal is not output in the first two clocks (output period of ACTV and NOP) and the last two clocks (output period of two NOPs) shown in FIG. 12, (55..5) is output. The numbers of logic “1” and “0” are almost equal. Therefore, the total source current and the total sink current in this period are antagonized, and the termination voltage source current becomes a value close to zero. After the data bus signal is output, as described above, a period in which the total source current is large (that is, a period in which the total sink current is small) and a period in which the total source current is small (that is, a period in which the total sink current is large) are 2 to 4 clocks. Appears alternately every time. Accordingly, the termination voltage source current vibrates positively and negatively around zero. This vibration is easily smoothed using a small smoothing capacitor 16 because of its short period. Therefore, similarly to the power supply capacity of the semiconductor device 100, it is sufficient that the capacity of the termination voltage source 3 can supply an average current (which is practically close to zero) smaller than the peak current. For example, the termination voltage source 3 can be a small-capacity power source used only for correcting the shift of the termination voltage V _T that cannot be compensated for by the smoothing capacitor 16.

The consumption current consumed for driving the bus system of the present embodiment is represented by the sum of the total source current and the current flowing out from the termination voltage source 3. FIG. 12 shows the current consumption of this embodiment in comparison with a comparative example which is a prior art described in detail below. The consumption current is oscillating in the same manner as the fluctuation of the total source current. On the other hand, the current consumption of the comparative example is substantially constant at a value close to the maximum current consumption of the present embodiment. Therefore, in the present embodiment, a reduction in consumption current corresponding to the low current period of the vibration is saved compared with the comparative example.
(Write operation of comparative example)
As a comparative example, the operation of the conventional bus system described above with reference to FIGS. 1 and 2 will be described. Referring to FIG. 13, the control signal, write address, and write data (not shown) are the same as those in the first embodiment. However, in the comparative example, there is no coincidence signal, and the data bus signal and the write data always coincide. As a result, the temporal changes of the total source current, total sink current, and termination voltage source current are different.

  In the comparative example, the write data is output to the data bus 1D as it is (without being inverted) as a data bus signal. Therefore, referring to FIG. 13, the total source current is very small while 8-word write data having a large first logic “0” is output continuously for 8 clocks. While the subsequent 8-word write data with many logic “1” s are output continuously for 8 clocks, the total source current becomes a large value close to the maximum. The total sink current is the opposite of the total source current. When an invalid transmission line is generated in the address bus 1A or the data bus 1D, a low level signal (logic “0”) is supplied to the address bus 1A and a high level signal (logic “1” is applied to the data bus 1D, as is normally done. )).

The termination voltage source current is the difference between the total source current and the total sink current, and vibrates positively or negatively around 0 along the total source current. As long as the write data of a pattern with a lot of logic “0” continues, all source currents have a value close to zero, and conversely, a value with a lot of logic “1” has a value close to the maximum. As described above, the fluctuation cycle of the total source current depends on the pattern of the write data, and an extremely long cycle often appears in an application in which approximate write data continues, such as image processing. The same applies to the termination voltage source current. This makes it difficult for the smoothing capacitor 16 to absorb the peak current, and these power supplies are always required to have a sufficient capacity corresponding to the maximum current. For example, since a source current i _{C of} 16.6 mA per line flows in the transmission line 1, a total source current of 0.88 A at the maximum flows in a bus composed of 53 transmission lines 1. Therefore, the power supply for the output circuit 11 is required to have a capacity for supplying the entire source current. Further, the termination voltage source 3 is required to have a current supply capability of ± 0.88 A.

  FIG. 13 shows the current consumption of the comparative example. In the comparative example, the write data is output to the data bus 1D without being inverted. Therefore, depending on the data, all source currents or all sink currents that are always near the maximum flow continuously for a long period of time. For this reason, current consumption close to the maximum flows continuously for a long time.

Comparing the first embodiment of the present invention with the comparative example, in the first embodiment, the capacitance of the termination voltage source 3 can be practically close to 0, whereas in the comparative example, the total source current and the total power A capacity for flowing a maximum sink current ± 0.88 A is required. In addition, the power supply of the output circuit is sufficient in this embodiment with a capacity of an average value of all source currents of 0.44 A, but in the comparative example, a capacity of a maximum value of all source currents of 0.88 A is required. Furthermore, the time average value of current consumption is also small in this embodiment.
(Read operation of the first embodiment)
Next, the read operation of the first embodiment will be described in comparison with the conventional bus system described above. FIG. 14 is a diagram for explaining the read operation of the first embodiment of the present invention, and FIG. 15 is a diagram for explaining the read operation of a comparative example, showing the read operation of the conventional bus system.

  In the following description of the read operation of the first embodiment, the write data (in the read operation, “read data”) stored in the semiconductor memory device 200 by the write of the first embodiment described above will be described. A case of reading into the internal circuit 101 will be described.

  The control signal for the read operation is the same as the write operation except that the WRT signal at the time of the write operation is replaced with an RD (write) signal. The read address is a logical address and designates a reading source (address designated by the write address during the write operation). The corresponding address bus signal is the same as the write operation.

  In order to simplify the description, an operation of successively reading 8 words of read data (1 word 32 bits) from 8 consecutive read addresses will be described.

  As the read address, the first read data is read from the continuous logical addresses (00000) to (00007), and then the second read data is read from the continuous logical addresses (80000) to (80007). The first read data includes many logic “0”, and the second read data includes many logic “1”. The read data is data (write data) to be stored in the semiconductor memory device 200 by the write operation, and is not actually data (data bus signal) stored in the semiconductor memory device 200. That is, since a part of the data is inverted and stored in the semiconductor memory device 200, the read data is obtained by correcting the inverted part.

  In the read operation, as in the write operation, an address corresponding to the read address is output as an address bus signal. In response to this, the data stored in the semiconductor memory device 200 is sequentially output to the data bus 1D as a data bus signal. This data bus signal is partially inverted (every two clocks) as described above. In the present embodiment, when the read address matches a predetermined address (address where the second bit is logic “1”), a match signal is output in synchronization with the corresponding address bus signal, and the data bus signal is inverted. Read into the internal circuit 101. Since this predetermined address is common to the write operation and the read operation, it may be the same address (logical address or address specified by the address bus signal) as the address where the data is inverted during the write operation. ) Also reverses the data during the read operation. For this reason, data in which a part stored in the semiconductor memory device 200 is inverted can be correctly read.

  The total source current of the semiconductor device (total source current of the semiconductor device) flows only slightly because the data bus 1D is not driven during the read operation. Since (55... 5) is sent to the ineffective transmission line in the same manner as in the conventional example, the entire source current of about 1/2 of the maximum value flows before and after the read operation with many ineffective transmission lines.

  The total source current of the memory device (the total source current flowing through the output circuit of the semiconductor memory device 200) is consumed to output the data stored in the semiconductor memory device 200 to the data bus 1D as a data bus signal. This total source current of the memory device depends on the logic pattern of the data bus signal (the difference in the number between “0” and “1”). On the other hand, data stored in the semiconductor memory device 200 and output as a data bus signal during a read operation is inverted every two clock cycles during a write operation, so that the data bus signal is also inverted every 2 to 4 clocks, Alternate. For this reason, the total source current of the memory device is a current that oscillates at a cycle of 2 to 4 clocks. For this reason, the power supply capacity of the output circuit 11 can be reduced by using the smoothing capacitor 16. Note that the sink current changes opposite to the increase and decrease of the source current in both the semiconductor device 100 and the semiconductor memory device 200.

The termination voltage source current varies in accordance with the sum of the total source current of the semiconductor device 100 and the total source current of the semiconductor memory device 200, and oscillates positively and negatively with a period of 2 to 4 clocks around the voltage 0. Therefore, the termination voltage source 3 can be reduced in capacity for the same reason as the write operation.
(Read operation of comparative example)
The comparative example is the same conventional bus system as the comparative example of the write operation. The read operation will be described below.

  In the comparative example, like the known read operation of the semiconductor memory device 200, the data bus signal always coincides with the read data (data read into the internal circuit 101 of the semiconductor device 100). The logical pattern of the read data is a biased pattern in which the first 8 words have a lot of logic “0” and the following 8 words have a lot of logic “1”. This bias pattern is directly applied to the data bus 1D as a data bus signal. Is output. As a result, the total source current of the semiconductor memory device 200 that outputs the data bus signal continues to a value close to 0 during the 8 clocks in which the first 8 words are output, and reaches a maximum value during the subsequent 8 clocks. The total source current of the semiconductor device is a small value corresponding to the control signal and the address bus signal. As for the termination voltage source current, a positive current (current consumed by flowing out from the power supply) flows during the first 8 clocks, and a negative current (current flowing into the power supply) flows during the subsequent 8 clocks. As described above, the terminal voltage source current continues to be positive or negative over a long period of time when read data having a biased pattern continues. For this reason, the power supply capacity cannot be reduced.

In addition, the current consumption, which is the sum of the current flowing out from the termination voltage source 3 and all the source currents of the semiconductor device 100 and the semiconductor memory device 200, keeps a value close to the maximum that can flow while the data bus signal is output. is doing. Referring to the consumption current of FIG. 15, compared to the comparative example described here, the consumption current of the first embodiment is reduced by the amount corresponding to the low current period of 2 clocks.
(2) Second Embodiment A semiconductor device according to the second embodiment relates to a mode in which the semiconductor memory device 200 according to the first embodiment is divided into a plurality of regions. 4 and 5 are a circuit diagram of an address comparison circuit according to the second embodiment of the present invention and a modification of the address comparison circuit according to the second embodiment of the present invention, respectively.

  Referring to FIG. 4, in the second embodiment, an address 71 (which may be a logical address or an address output to the address bus 1A) input to the address comparison circuit 7 is an area designation address 71a and an in-area address 71b. Separated. The area designation address 71a is composed of data for specifying a plurality of areas, for example, 2-bit data for specifying four areas.

  The register memory 75 includes two registers as one set, and four sets of register memories 75 are provided. The four sets of register memories 75 are provided corresponding to four areas, respectively. Therefore, these register memories 75 store two predetermined addresses 74 for each area for four areas.

The two selectors 77 are controlled by the area designation address 71a, select one set of register memories 75 designated by the area designation address 71a from the four sets of register memories 75, and store the two stored therein. The predetermined address 74 is output to the comparison circuit 76. The comparison circuit 76 (including the OR circuit in the figure) compares the n _A bit selection bits extracted from the in-region address 71b with two predetermined addresses 74, and when either of them matches, a logic “1” is obtained. Is output. A logical sum with the output stop signal 78 is output from the address comparison circuit 7 as the coincidence signal 73. The stop signal 78 is generated from an external terminal or by a program. The stop signal 78 is generated in the initial operation, for example, immediately after the power is turned on, so that the inversion operation of the inversion circuit 6 is stopped, and the logic pattern of (FF... F) is set on all the transmission lines 1 of the data bus 1D. The rise time of the initial operation can be shortened by outputting and charging the smoothing capacitor 16 at an early stage.

  According to the second embodiment, a plurality of different predetermined addresses can be set for each region into which the semiconductor memory device 200 is divided. Therefore, by setting a predetermined address in accordance with the characteristics of the program or data, the operation frequency of the inverting circuit 6 can be appropriately set even when a different program or data is used.

  Referring to FIG. 5, in the modified example of the address comparison circuit according to the second embodiment, a register memory 75 including eight registers is provided for each page. In one register memory 75, eight predetermined addresses 74 are stored. Further, each register is provided with a 1-bit valid flag 79.

  Eight predetermined addresses 74 stored in the register memory 75 corresponding to the page designated by the area designation address 71a are read and output to the eight comparison circuits 76 provided in pairs therewith. At this time, reading of a register whose valid flag 79 is negative (“0”) is prohibited. The eight comparison circuits 76 send out a coincidence signal 73 when the selection bit 72 and one of the eight predetermined addresses 74 coincide. Others are the same as the address comparison circuit of the second embodiment.

In the present modification, the specific predetermined address 74 can be set to be used or not used simply by dynamically changing the valid flag 79, so that a plurality of sets of two or more predetermined addresses 74 are partially overlapped. It can be used simultaneously in programs. For this reason, the use efficiency of the register is good, and the required address 74 to be changed by a program or the like can be reduced.
(3) Third Embodiment In the third embodiment of the present invention, the semiconductor device and the bus system according to the first embodiment are improved so that the termination voltage shift is corrected.

FIG. 6 is a block diagram of a third embodiment of the present invention. Referring to FIG. 6, in the bus system according to the third embodiment, there is no termination voltage source 3, and a smoothing capacitor 16 is simply connected instead. Other bus structures are the same as in the first embodiment. In a system in which the termination voltage source 3 is omitted, when a complementary signal biased to one logic is output to the bus for a long time, the voltage shift of the smoothing capacitor 16 is absorbed by the termination voltage source 3 and corrected. Therefore, the termination voltage V _T shifts. In this embodiment, the accumulated number of logic “1” and “0” output to the buses 1D, 1A, and 1C is monitored, and the bus output is controlled so that the accumulated number approaches zero, and the termination voltage V _T Suppress the shift.

  FIG. 7 is a block diagram of a switching circuit according to the third embodiment of the present invention, and shows the data switching circuit 26 and its peripheral circuits shown in FIG. In the third embodiment, referring to FIG. 6, switching circuits 26A, 27, and 28 that are controlled to be switched by dummy signal control circuit 13 are provided in data bus 1D, address bus 1A, and control bus 1C, respectively. Referring to FIG. 7, switching circuit 26 </ b> A switches between the data signal output from data register 25 and dummy signal 61 by switching signal 64 and outputs it to output circuit 11. Therefore, a data signal or dummy signal 61 is output to the data bus 1D according to the switching signal. The address bus 1A and the control bus 1C are the same except that the data register 25 is replaced with the address register 26 and the control register 27, respectively.

The dummy signal 61 is generated by the difference accumulating means 8 together with the correction signal. The difference accumulating means 8 subtracts the number of logic “0” from the number of logic “1” output from the switching circuits 26A, 27, 28, and accumulates the subtracted value. This cumulative value is compared with a preset lower limit value and upper limit value (corresponding to the first cumulative number and the second cumulative number, respectively). When the cumulative value is smaller than the lower limit value (the logic “0 indicating active”) The dummy signal 61 (with a logic “1” indicating that it is smaller than the lower limit value) is output simultaneously with the output of the correction signal 62, and when it is greater than the lower limit value (with a logic “0” indicating that it is active) Simultaneously with the output of the correction signal 62, the dummy signal 61 (with a logic “0” indicating that it is greater than the lower limit value) is output. When the cumulative number is within the range between the lower limit value and the upper limit value, the correction signal 62 becomes logic “1” indicating inactivity. That is, a dead zone is within the range between the lower limit value and the upper limit value. The width of this dead zone can be zero. The dummy signal 61 may be output based on a target accumulated value, for example, zero, and when it is smaller than this, the logic “1” is output when it is larger. The difference accumulating means 8 can be constituted by a circuit. Further, modification of the terminal voltage V _T gradually from being made as a result of normal hundreds to thousands of side affects accumulation period of the clock can also be performed by a program part of the function of the differential accumulation means 8.

  In 3rd embodiment, it has the validity determination means 10 which detects the transmission line 1 from which the further effective signal is not output. The validity determination means 10 monitors the operations of the bus control circuit 22 and the address calculation circuit 21 and identifies the transmission line 1 that does not output a valid signal as an invalid transmission line. This specification is performed in units of the data bus 1D, the address bus 1A, and the control bus 1C. Control is facilitated by specifying the bus unit. Of course, it can be performed in smaller units if necessary. As such a specifying method, for example, when the bus control command does not require an address or a data signal, or when an address is transmitted only for a specified period and an address is not required before or after such as burst transfer, the data bus 1D And the address bus 1A can be specified as an invalid transmission line. It is also possible to monitor chip enable or chip select, detect a period when a part of the control bus 1C is not used, and specify a part of the control bus 1C as an invalid transmission path.

  The validity determination means 10 has a logic "1" indicating that the bus is an invalid transmission line for a bus identified as an invalid transmission path to a dummy signal control circuit 13 provided corresponding to the bus. A determination signal 63 is sent out. As described above, the dummy signal control circuit 13 is provided for each specific unit of the invalid transmission line, and the determination signal 63 is transmitted from the validity determination unit 10 for each specific unit.

  Referring to FIG. 7, dummy signal control circuit 13 uses switching circuit 26 </ b> A as a switching signal 64 with the logical sum of determination signal 63 transmitted from validity determination means 10 and correction signal 62 transmitted from difference accumulation means 8. , 27, 28. FIG. 8 is a diagram for explaining the operation of the dummy signal control circuit according to the third embodiment of the present invention. Referring to FIG. 8, dummy signal 61 is output from switching circuit 26A only when the determination signal is “0” and the correction signal is “0”. In other cases, the contents of the registers 25, 23, and 24, that is, the data signal, the address, and the control signal are output as in the normal operation.

That is, the dummy signal 61 is output when the bus is an invalid transmission line and the accumulated value of the difference between the logic “1” and “0” output to all the buses exceeds the predetermined range. In other cases, a normal signal is output to the bus. The dummy signal 61 becomes logic “0” when a signal pattern with many high level signals continues and the cumulative number exceeds the upper limit, and a low level signal is output to the bus. Conversely, when the low level signal continues and the cumulative number becomes smaller than the lower limit, the dummy signal becomes logic “1” and the high level signal is output to the bus. Accordingly, the number of high-level and low-level signals is always corrected to fall within a predetermined range by the output of the dummy signal to the bus. For this reason, the shift of the termination voltage V _T is suppressed.

  In the third embodiment, a part or all of the transmission lines 1 constituting the control bus 1C are subject to calculation of the difference between the cumulative numbers of logic “1” and “0” or to output dummy signals ( Therefore, it can be excluded from the determination target of the invalid transmission line) or both. As a result, the circuit scale can be reduced and the power consumption can be further reduced.

  For example, clock distribution lines and data strobe signal lines can be excluded from such objects. Since these signals output “1” and “0” alternately and continuously during the operation period, they hardly affect the cumulative number. For this reason, even if these signal lines are excluded, the operation of this embodiment is hardly adversely affected. Therefore, it is preferable to reduce power consumption by excluding such transmission lines from the cumulative number calculation target.

These lines are held at high impedance or low or high level during periods of non-operation. A transmission line held at a high impedance during a non-operation period, for example, a normal strobe signal line, can output a dummy signal. On the other hand, a transmission line that outputs a low or high level signal during a non-operation period, for example, a clock distribution line, needs to be excluded from a dummy signal output target. The operation of the clock distribution line may be set in advance or may be determined as an invalid transmission line determination target.
(Write operation of the third embodiment)
FIG. 16 is an explanatory diagram of the write operation of the third embodiment of the present invention. Referring to FIG. 16, at the fourth and fifth clocks of the address bus signal before correction (corresponding to the address bus signal in the first embodiment described above), logic “1” in which all bits are high level signals. (FFF) is output to the address bus 1A. The control signal, write address, pre-correction address signal, write data, and data bus signal are the same as in the first embodiment. Similarly, the data bus signal and the write data are inverted while the coincidence signal 73 is active.

  The accumulated numbers shown in FIG. 16 are the logic “1” and “0” of signals output from the semiconductor device 100 on all the transmission lines 1 constituting the bus of the present embodiment accumulated by the difference accumulating unit 8. And the cumulative number difference. This cumulative number falls below a predetermined lower limit at the third, fourth and eighth clocks. However, since a valid pre-correction address bus signal is output at the third clock, the address bus 1A is not an invalid transmission line and does not output a switching signal. On the other hand, the valid address bus signal before correction is not output at the fourth clock and the subsequent fifth clock, and the address bus 1A is an invalid transmission line. As in the fourth and fifth clocks, when the accumulated number falls below a predetermined lower limit (or exceeds the upper limit), and when the address bus 1A becomes an invalid transmission line at the same time and subsequent clocks, switching to instruct a dummy signal output A signal 64 is transmitted. On the other hand, at the eighth clock, the cumulative number falls below a predetermined lower limit, and at the same time, the address bus 1A also becomes an invalid transmission line, but a valid pre-correction address bus signal is output at the subsequent ninth clock. Therefore, the invalid transmission line of 2 clocks cannot be used continuously. For this reason, the switching signal 64 is not transmitted at the eighth clock. In this way, the dummy signal is output only when the address bus 1A is in an invalid transmission line for two clock cycles or more, because the interval of the switching operation of the switching circuits 26A, 27, 28 is shortened and the consumption accompanying the switching operation. This is to prevent the power from increasing. Of course, the switching signal 64 can be sent during a period when the cumulative number exceeds the upper and lower limits and at the same time the address bus 1A becomes an invalid transmission line.

Referring to FIG. 16, normally, (55... 5) is sent to the ineffective transmission line as in the first embodiment. Therefore, for example, the change in the cumulative number is small in the first and second clocks. As a result of a large output of logic “0” in the third to fourth clocks, the cumulative number falls below the lower limit, but a dummy signal (FFF) is output to the address bus 1A at the fourth and fifth clocks, Furthermore, since the data bus signal in which the write data is inverted at the fifth and sixth clocks is output to the data bus 1D, the time average numbers of the logic “0” and “1” output to the bus compete with each other. At the sixth clock, the cumulative number approaches zero. At this time, the termination voltage V _T varies along the cumulative number and falls within the voltage range determined by the upper and lower limits of the cumulative number. Therefore, the termination voltage source 3 can be constituted by only the smoothing capacitor 16 and the termination voltage source 3 for charging and discharging the smoothing capacitor 16 can be omitted.

In this embodiment, since the smoothing capacitor 16 is not charged at the initial stage of operation of the bus system, the termination voltage V _T is a value close to 0V. Thus, as an initial operation, it must charge smoothing capacitor 16 to the terminal voltage V _T to boost a predetermined voltage. This charging can be executed by a program that outputs a dummy signal for a certain period (FF ·· F) as an initial operation. Alternatively, it can be executed by connecting a small-capacity termination voltage source 3 for initial charging in parallel with a smoothing capacitor.
(4) Fourth Embodiment The fourth embodiment of the present invention relates to a bus system that outputs a dummy signal to the bus so that the termination voltage V _T falls within a predetermined voltage range.

  FIG. 9 is a block diagram of a fourth embodiment of the present invention. The termination voltage source 3 and the smoothing capacitor 16 of the fourth embodiment are the same as those of the third embodiment, and the termination voltage source 3 can be omitted as in the third embodiment. The semiconductor device 100 according to the fourth embodiment includes a validity determination unit 10 for detecting an invalid transmission line in a bus control circuit 22. The switching circuit 27 receives the switching signal 64 and outputs a dummy signal 61 to the transmission line 1. The dummy signal control circuit 13 selects an invalid transmission line based on the determination signal 63 output from the validity determination means 10 and generates a switching signal 64 for the transmission line selected according to the correction signal 62 and the determination signal 63. To do. As in the third embodiment, the dummy signal control circuit 13 is provided for each of the data bus 1D, the address 1A, and a part of the control bus 1C.

In the fourth embodiment, a termination voltage monitoring circuit 9 that monitors the termination voltage V _T is provided in the semiconductor device 100. The termination voltage monitoring circuit 9 transmits a correction signal 62 to the dummy signal control circuit 13 when the termination voltage V _T exceeds a predetermined voltage range, and at the same time, a dummy signal 61 (logic “1” or “0” that corrects the termination voltage V _T. Is output to the switching circuit 27. Therefore, as in the third embodiment, the shift of the termination voltage V _T can be corrected and the termination voltage V _T can be held near the predetermined voltage. It is desirable to avoid frequent switching operations by providing hysteresis characteristics to the upper and lower terminal voltages V _{T at} which the correction signal 62 is transmitted.

The clock distribution line and the data strobe signal line can be handled as dummy signal control similar to the third embodiment.
(4) Fifth Embodiment The fifth embodiment of the present invention relates to a form in which the termination voltage monitoring circuit of the fourth embodiment is applied instead of the difference accumulating means of the third embodiment.

  FIG. 10 is a block diagram of a fifth embodiment of the present invention. The buses 1D, 1A, 1C reference voltage source 5, smoothing capacitor 16, and termination voltage source 3 of this embodiment are the same as those of the third embodiment. The address comparison circuit 7 and the inverting circuit 6, the dummy signal control circuit 13, and the switching circuits 26A, 27, and 28 are the same as in the third embodiment. For the clock distribution line and the data strobe signal line, dummy signal control similar to that of the third embodiment can be performed.

The fifth embodiment includes a termination voltage monitoring circuit 9 that monitors the termination voltage V _T and sends a correction signal 62 when the voltage becomes higher or lower than a predetermined voltage range. That is, the generation of the correction signal 62 for the termination voltage V _T has a hysteresis characteristic. Thereby, it is avoided that the generation and disappearance of the correction signal are frequently repeated. When the termination voltage V _T is higher or lower than a predetermined voltage range, the termination voltage monitoring circuit 9 outputs a dummy signal of logic “0” or “1” accordingly.

The dummy signal control circuit 13 and the switching circuits 26A, 27, and 28 are provided for each of the buses 1D, 1A, and 1C. The validity determining means 10 for detecting the invalid transmission line is provided as a part of the control circuit 22, and the determination signal 63 for identifying the bus composed of the invalid transmission line is sent to the dummy signal control circuit 13 corresponding to each bus. Send it out. Other operations are the same as in the third embodiment. (Write operation of the fifth embodiment)
FIG. 17 is an explanatory diagram of the write operation of the fifth embodiment of the present invention. The meanings of the control signal to the data bus signal shown in FIG. 17 are the same as the write operation of the third embodiment shown in FIG. Although the coincidence signal is not shown here, the coincidence signal operates in the same manner as in FIG. 16, and a data bus signal obtained by inverting a part of the write data is output to the data bus 1D as in FIG. Yes.

Referring to FIG. 17, the termination voltage monitoring circuit 9 is, for example, separated by several tens mV, for example, above and below the voltage V _T0 = 1.25 V which is ½ of the power supply voltage VCC = 2.5 V of the output circuit, for example. Upper and lower voltage limits are set. In the first clock cycle - a second clock cycle, the termination voltage V _T will modify the signal is in the voltage range defined by the upper and lower limits are not output. When a data bus signal and an address bus signal containing a lot of logic “0” are output at the third to fourth clocks, a current (flowing into the smoothing capacitor is set to be positive) in response to these signals. And the terminal voltage V _T is changed. The termination voltage V _T changes after the fourth clock and falls below the lower limit at the fifth clock. The termination voltage monitoring circuit 9 detects this and outputs a correction signal 62. At the same time, a dummy signal of logic “1” is generated.

At the fifth clock, since there is no valid address bus signal (pre-correction address bus signal), a determination signal 63 indicating that the address bus 1A is an invalid transmission line is sent from the validity determination means 10 to the address bus 1A. It is transmitted to the corresponding dummy signal control circuit 13. The dummy signal control circuit 13 that has received the determination signal 63 and the active correction signal 62 transmits the switching signal 64 together with the dummy signal 61 to the switching circuit 27 corresponding to the address bus 1A. As a result, a corrected address bus signal consisting of (FFF) is sent to the address bus 1A. Since the fifth clock includes many outputs of logic “1” to the bus, the termination voltage V _T starts to rise beyond the lower limit.

At the sixth clock, the termination voltage V _T is already within the voltage range defined beyond the lower limit. However, since the voltage at which the correction signal 62 disappears is set higher than the generated voltage (the above lower limit), the correction signal 62 continues to be generated after the sixth clock. Therefore, after the sixth clock, when there is no valid pre-correction address bus signal, that is, after the eighth, tenth, twelfth to fourteenth and sixteenth clocks, the address bus 1A has a post-correction consisting of (FFF). An address bus signal is output. Further, since there is no valid data bus signal at the 19th and 20th clocks, an active determination signal and a logic “1” dummy signal 61 are also sent to the dummy signal control circuit 13 corresponding to the data bus 1D. A data bus signal composed of (FF ·· F) is also output to the bus 1D. As a result, the termination voltage V _T is pulled back into the defined voltage range. Here, the case where the termination voltage V _T is lower than the lower limit has been described, but the same applies to the case where the terminal voltage V _T exceeds the upper limit.
(6) Modified example of the termination voltage source of the present invention In the above-described embodiment of the present invention, the termination voltage V _T and the reference voltage V _REF can be used in common to supply a voltage from one voltage source. This eliminates the need for one of the power supplies, thereby further reducing power consumption. Also, the power supply cost is reduced. Hereinafter, a modification of the embodiment of the present invention will be described.

FIG. 11 is an explanatory diagram of the termination voltage source according to the embodiment of the present invention, and shows a modification in which the termination voltage V _T and the reference voltage V _REF are made common.

Fig.11 (a) represents the modification which concerns on 1st embodiment and 2nd embodiment. In this modification, referring to FIG. 11A, the reference voltage V _REF and the termination voltage V _T are supplied from one termination voltage source 3. Thus, the reference voltage source 5 can be omitted, which contributes to a reduction in manufacturing cost. Further, a smoothing capacitor 16 is connected in parallel with the termination voltage source 3 to absorb the peak current flowing through the termination voltage source 3. Therefore, the termination voltage source 3 only needs to supply an average current close to zero, and power consumption can be reduced.

  The smoothing capacitor 16 needs a capacity sufficient to smooth the fluctuation synchronized with the cycle in which the output signal on the data bus 1D is switched by the inverting circuit 6. On the other hand, if the capacity is too large, it takes time to charge during the initial operation and the startup time is delayed. Accordingly, a time constant that smoothes fluctuations between several tens of clocks to several thousand clocks, for example, several hundred clocks is preferable. The capacity required for the smoothing capacitor 16 depends on the current capacity of the termination power supply 3.

FIG. 11B shows a modification according to the third embodiment. In this modification, referring to FIG. 11 (b), the reference voltage V _REF and the termination voltage V _T are supplied from one smoothing capacitor 16. In the third embodiment, since the numbers of logic “1” and “0” output to the bus compete for a long period of time, for example, several thousand clocks, the average current flowing through the termination voltage V _T is almost zero. The termination voltage source 3 for charging the smoothing capacitor 16 can be reduced. Therefore, not only the reference voltage source 5 can be omitted, but also the termination voltage source 3 can be replaced with the smoothing capacitor 16. For this reason, it greatly contributes to cost reduction and power saving. In order to suppress the shift of the long-period termination voltage V _T that cannot be smoothed by the smoothing capacitor 16 or to shorten the start-up time, a small-capacity termination voltage source 3 can be used together for charging. .

FIG. 11C shows a modification according to the fourth and fifth embodiments. This modification, with reference to FIG. 11 (c), the same as modification of the third embodiment shown in FIG. 11 (b), and supplies the termination voltage V _T from the smoothing capacitor 16. In the fourth and fifth embodiments, since the termination voltage V _T is constantly monitored and corrected, the fluctuation of the long period of the termination voltage V _T is remarkably small, and a dummy signal is generated until the smoothing capacitor 16 is charged at the beginning of startup. In this case, the terminal voltage source 3 for charging is rarely required. Therefore, the termination voltage source 3 can be replaced with the smoothing capacitor 16. Of course, similar to the modification according to the third embodiment, the termination voltage source 3 can be used together to achieve the same effect.

  The present invention relates to a semiconductor device that drives a bus composed of a transmission line terminated with a termination resistor using a complementary signal, in particular, a semiconductor device that accesses the semiconductor memory device 200, and a bus system including such a bus and the semiconductor device. Used.

In the above description of the embodiment of the present invention, the invention described in the following supplementary notes is disclosed.
(Supplementary note 1) Data input for inputting / outputting the complementary signal to / from a data bus including a plurality of transmission lines terminated via a termination resistor at a termination voltage set between the top line and the base line of the complementary signal In a semiconductor device provided with an output circuit,
An address comparison circuit for sending a coincidence signal when the transmission destination or transmission source address of the complementary signal matches a predetermined address;
An internal circuit of the semiconductor device for inputting / outputting a data signal converted into or converted from the complementary signal by the data input / output circuit to / from the data input / output circuit;
And an inverting circuit that is inserted between the internal circuit and the data input / output circuit and inverts and transmits the data signal transmitted between the internal circuit and the data input / output circuit when the coincidence signal is received. A semiconductor device.
(Appendix 2) In the semiconductor device according to Appendix 1,
The transmission destination or transmission source address includes an area designation address for designating one area in a plurality of areas of the semiconductor memory device, and an area address for designating an address in the area,
The predetermined address is stored in an address storage device provided for each area,
The coincidence signal is transmitted when one of the predetermined addresses stored in the address storage device provided corresponding to an area designated by the area designation address coincides with an address in the area. Semiconductor device.
(Supplementary Note 3) An output circuit is provided for outputting the complementary signal to a bus including a plurality of transmission lines that are terminated via a terminating resistor at a termination voltage set between the top line and the base line of the complementary signal. In semiconductor devices,
The difference between the number of high-level signals and low-level signals of the complementary signals output from the output circuit to the bus is counted and accumulated, and the accumulated number of the differences is less than a predetermined first accumulated number or a predetermined first number Difference accumulation means for sending a correction signal when the accumulated number exceeds 2,
Validity determination means for monitoring bus control of the semiconductor device, detecting an invalid transmission line from which the effective complementary signal is not transmitted among the plurality of transmission lines, and sending a determination signal for identifying the invalid transmission line And
The output circuit, when receiving the correction signal, outputs a high-level or low-level dummy signal to the invalid transmission line specified by the determination signal according to the correction signal.
(Supplementary Note 4) An output circuit is provided for outputting the complementary signal to a bus including a plurality of transmission lines that are terminated via a termination resistor at a termination voltage set between the top line and the base line of the complementary signal. In semiconductor devices,
A termination voltage monitoring circuit that monitors the termination voltage and sends a correction signal when the termination voltage is lower than a predetermined first voltage or higher than a predetermined second voltage;
Validity determination means for monitoring bus control of the semiconductor device, detecting an invalid transmission line from which the effective complementary signal is not transmitted among the plurality of transmission lines, and sending a determination signal for identifying the invalid transmission line And
The output circuit, when receiving the correction signal, outputs a high-level or low-level dummy signal to the invalid transmission line specified by the determination signal according to the correction signal.
(Supplementary Note 5) The semiconductor device according to any one of Supplementary Notes 1 and 2, wherein the inversion operation of the inversion circuit is stopped by inputting a stop signal.
(Supplementary note 6) In a bus system that performs signal transmission with another semiconductor device using the semiconductor device according to any one of Supplementary notes 1 to 4, via the transmission line,
The semiconductor device and the other semiconductor device include: a differential circuit that differentially amplifies the complementary signal input from the transmission line by comparing with a reference voltage; and a reference voltage input terminal to which the reference voltage is input Have
The power supply of the termination voltage consists of a smoothing capacitor with one end being the termination voltage and the other end grounded,
The bus system, wherein the termination voltage is connected to the reference voltage.

Block diagram of the first embodiment of the present invention Block diagram of address comparison circuit of first embodiment of the present invention First Embodiment of the Present Invention Address Comparison Circuit Modification Second Embodiment Address Comparison Circuit Circuit Diagram of the Present Invention Second embodiment of the present invention Address modification circuit modification Block diagram of a third embodiment of the present invention Switching circuit block diagram of a third embodiment of the present invention Operation explanatory diagram of the dummy signal control circuit of the third embodiment of the present invention Block diagram of the fourth embodiment of the present invention Block diagram of fifth embodiment of the present invention Embodiment of the present invention Termination voltage source explanatory diagram 1st embodiment write operation explanatory drawing of this invention Comparative example write operation explanatory diagram First embodiment of the present invention read operation explanatory diagram Comparison example Explanatory diagram of write operation of the third embodiment of the present invention Fifth embodiment of the present invention write operation explanatory diagram Conventional termination resistor bus system block diagram T-LVTTL circuit diagram

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Transmission line 1D Data bus 1A Address bus 1C Control bus 2 Data input / output circuit 3 Termination voltage source 4 Termination resistance 5 Reference voltage source 6 Inversion circuit 7 Address comparison circuit 8 Difference accumulation means 9 Termination voltage monitoring circuit 10 Effectiveness judgment means 11 Output circuit 12 Input circuit 13 Dummy signal control circuit 16 Smoothing capacitor 20 Reference voltage input terminal 21 Address calculation circuit 22 Control circuit 23 Address register 24 Control register 25 Data register 26 Data switching circuit 26A, 27, 28 Switching circuit 61 Dummy signal 62 Modification Signal 63 Determination signal 64 Switching signal 71 Address 71a Area designation address 71b In-area address 72 Selection bit 73 Match signal 74 Predetermined address 75 Register memory (address storage device)
76 Comparison Circuit 77 Selector 78 Stop Signal 79 Valid Flag 100 Semiconductor Device 101 Internal Circuit 200 Semiconductor Memory Device 201 Memory Circuit V _T Termination Voltage V _REF Reference Voltage I _C Source Current I _S Sink Current

Claims (5)

A data input / output circuit for inputting / outputting the complementary signal to / from a data bus including a plurality of transmission lines terminated via a terminating resistor at a termination voltage set between the top line and the baseline of the complementary signal In semiconductor devices
An address comparison circuit for sending a coincidence signal when the transmission destination or transmission source address of the complementary signal matches a predetermined address;
An internal circuit of the semiconductor device for inputting / outputting a data signal converted into or converted from the complementary signal by the data input / output circuit to / from the data input / output circuit;
And an inverting circuit that is inserted between the internal circuit and the data input / output circuit and inverts and transmits the data signal transmitted between the internal circuit and the data input / output circuit when the coincidence signal is received. A semiconductor device. The semiconductor device according to claim 1,
The transmission destination or transmission source address includes an area designation address for designating one area in a plurality of areas of the semiconductor memory device, and an area address for designating an address in the area,
The predetermined address is stored in an address storage device provided for each area,
The coincidence signal is transmitted when one of the predetermined addresses stored in the address storage device provided corresponding to an area designated by the area designation address coincides with an address in the area. Semiconductor device. In a semiconductor device including an output circuit that outputs a complementary signal to a bus including a plurality of transmission lines that are terminated via a termination resistor at a termination voltage that is set between the top line and the baseline of the complementary signal.
The difference between the number of high-level signals and low-level signals of the complementary signals output from the output circuit to the bus is counted and accumulated, and the accumulated number of the differences is less than a predetermined first accumulated number or a predetermined first number Difference accumulation means for sending a correction signal when the accumulated number exceeds 2,
Validity determination means for monitoring bus control of the semiconductor device, detecting an invalid transmission line from which the effective complementary signal is not transmitted among the plurality of transmission lines, and sending a determination signal for identifying the invalid transmission line And
The output circuit, when receiving the correction signal, outputs a high-level or low-level dummy signal to the invalid transmission line specified by the determination signal according to the correction signal. In a semiconductor device including an output circuit that outputs a complementary signal to a bus including a plurality of transmission lines that are terminated via a termination resistor at a termination voltage that is set between the top line and the baseline of the complementary signal.
A termination voltage monitoring circuit that monitors the termination voltage and sends a correction signal when the termination voltage is lower than a predetermined first voltage or higher than a predetermined second voltage;
Validity determination means for monitoring bus control of the semiconductor device, detecting an invalid transmission line from which the effective complementary signal is not transmitted among the plurality of transmission lines, and sending a determination signal for identifying the invalid transmission line And
The output circuit, when receiving the correction signal, outputs a high-level or low-level dummy signal to the invalid transmission line specified by the determination signal according to the correction signal. In a bus system that performs signal transmission via the transmission line with another semiconductor device using the semiconductor device according to claim 1,
The semiconductor device and the other semiconductor device include: a differential circuit that differentially amplifies the complementary signal input from the transmission line by comparing with a reference voltage; and a reference voltage input terminal to which the reference voltage is input Have
The power supply of the termination voltage consists of a smoothing capacitor with one end being the termination voltage and the other end grounded,
The bus system, wherein the termination voltage is connected to the reference voltage.

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