JP2006024610A - Thin-film transistor and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin-film transistor wherein a channel length can be easily shortened as compared with the resolution of a pattern and the quantity of handling current can be increased at low cost as a result. <P>SOLUTION: A gate electrode 5, a gate insulating film 7 covering the gate electrode 5, and a channel layer (semiconductor thin film of a channel part) 11 covering the gate electrode 5 with the gate insulating film 7 in between are stacked on a substrate 3 in this order or in reverse order, and a source electrode 9 and a drain electrode 15 are separately placed on the surface and backsides of the channel layer 11, respectively. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a thin film transistor suitable for driving a display device using a current driven element such as an organic electroluminescent element, and a display device using the thin film transistor.

  A thin film transistor (TFT) using a thin film semiconductor layer is used for a driving element such as an active matrix liquid crystal display device or an organic EL display device. FIG. 7 shows a schematic cross-sectional view of a thin film transistor having an inverted stagger structure (so-called bottom gate type) as one of thin film transistors used in these display devices.

  As shown in this figure, in a thin film transistor 100 having an inverted stagger structure, a gate electrode 102 is formed on an insulating substrate 101 such as glass, and a gate insulating film 103 and a channel portion semiconductor thin film 104 are provided in this order so as to cover the gate electrode 102. It has been. An insulating channel protective film 105 is provided on the central portion of the channel portion semiconductor thin film 104 above the gate electrode 102. The source electrode 106 s / drain electrode made of an n-type semiconductor thin film is formed on the channel protective film 105 and extends from the channel protective film 105 to the channel portion semiconductor thin film 104 exposed from the channel protective film 105. 106d is provided. The tips of the source wiring 107s / drain wiring 107d wired on the gate insulating film 103 are laminated on the source electrode 106s / drain electrode 106d.

  Note that a structure in which the stacking order of each member on the insulating substrate 101 is reversed is a staggered (so-called top gate type) thin film transistor.

  Here, in the thin film transistor having the above-described configuration, it is known that parasitic capacitance is formed between the gate electrode 102 and the source electrode 106s and between the gate electrode 102 and the drain electrode 106d, using the gate insulating film 103 as a dielectric. ing. Since these parasitic capacitances vary greatly due to the pattern shift of the gate electrode 102 with respect to the source electrode 106s / drain electrode 106d, it is difficult to make the circuit constant constant within or between the substrates. Such variations in parasitic capacitance cause variations in display quality of display devices using such thin film transistors as drive elements.

  Therefore, by adopting a configuration in which the source electrode is sandwiched between the two drain electrodes in the same layer, the parasitic capacitance between the gate electrode and the source electrode and the gap between the gate electrode and the drain electrode can be obtained regardless of the positional deviation of the gate electrode. A configuration in which the parasitic capacitance is constant has been proposed (see Patent Document 1 below).

JP-A-2-79476

  By the way, among the display devices using the thin film transistors having the above-described configurations as driving elements, a display device in which organic electroluminescent elements are arranged as light emitting elements has color reproducibility, wide viewing angle, high speed response, high contrast, etc. It has many excellent features. In such a display device, since the organic electroluminescent element is a current-driven element, an increase in the amount of handling current is required in order to improve the luminance of the thin film transistor that drives the organic electroluminescent element.

  In order to increase the amount of current handled, it is effective to widen the channel width of the thin film transistor or shorten the channel length. However, when the channel width is simply increased, the area occupied by the thin film transistor increases. For this reason, the adhesion of dust during the manufacturing process causes a decrease in yield.

  On the other hand, when the channel length is shortened, in the thin film transistor 100 having the configuration described with reference to FIG. 7, for example, the channel length L is determined by the pattern width of the channel protective film 105. Narrow it. However, the channel protective film 105 is patterned by etching using a resist pattern formed by lithography as a mask. For this reason, in order to form the channel protective film 105 having a narrower pattern width, it is necessary to use an exposure apparatus having a high (small) resolution limit at the time of pattern exposure in lithography. However, an exposure apparatus with a high (small) resolution limit is expensive, which increases the cost of the display device.

  The same applies to a thin film transistor (described in Patent Document 1) in which a source electrode is sandwiched between two drain electrodes in the same layer. That is, in such a configuration, the distance between the source electrode and the drain electrode provided in the same layer on the insulating substrate is the channel length. Therefore, in order to obtain a thin film transistor having a shorter channel length, it is necessary to use an exposure apparatus having a high (small) resolution limit when patterning the source electrode and the drain electrode.

  Therefore, the present invention provides a thin film transistor that can easily shorten the channel length without being affected by the resolution of the pattern, and can thereby increase the amount of current to be handled, and by using this thin film transistor. An object is to provide a display device having high luminance and excellent display characteristics.

  In order to achieve the above-described object, the thin film transistor of the present invention includes a gate electrode, a gate insulating film covering the gate electrode, and a channel portion semiconductor thin film covering the gate electrode via the gate insulating film in this order or vice versa. Are stacked in this order. A source electrode and a drain electrode are separately placed on the front surface side and the back surface side of the channel portion semiconductor thin film.

  In the thin film transistor having such a configuration, the source electrode and the drain electrode are separately provided on the front surface side and the back surface side of the channel portion semiconductor thin film. For this reason, the channel length between the source electrode and the drain electrode does not depend on the resolution of the pattern, and the other of the channel part semiconductor thin film with respect to the source electrode provided on one surface of the channel part semiconductor thin film It is set only by alignment of the drain electrode provided on the surface. Therefore, the channel length can be shortened beyond the resolution of the pattern.

  The present invention is also a display device using the thin film transistor having the above structure, and includes the thin film transistor having the above structure and a display element connected to the thin film transistor on an insulating substrate. Examples of the display element include a current-driven light emitting element such as an organic electroluminescent element.

  In the display device having such a structure, the above-described thin film transistor is connected to the display element, so that the display element is driven by the thin film transistor whose channel length is shortened without depending on the resolution of the pattern.

  As described above, according to the thin film transistor of the present invention, the channel length can be set only by the alignment of the drain electrode with respect to the source electrode. Therefore, the exposure without depending on the pattern resolution, that is, the high resolution exposure. The channel length can be shortened without using a device. As a result, it is possible to provide a thin film transistor with an increased handling current amount at a low cost without increasing the occupied area.

  According to the display device of the present invention, the thin film transistor having an increased handling current amount is connected to the display element in this way, so that display characteristics can be improved at low cost (specifically, in terms of luminance). It becomes possible to plan.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, the thin film transistor embodiment and the display device embodiment will be described in this order.

<First Embodiment>
FIG. 1 shows the configuration of the thin film transistor in the first embodiment. 1A is a plan view of the thin film transistor viewed from above, and FIG. 1B is a cross-sectional view taken along line AA ′ in FIG. Further, in the plan view, a part of the member is cut out for illustration.

  The thin film transistor 1 shown in these drawings is a thin film transistor 1 having an inverted stagger (so-called bottom gate type) structure, and is formed on an insulating substrate 3 in order from the lower layer side to a gate electrode 5 and a gate insulating film 7 (only a cross-sectional view). ), Source wiring 8, source electrode 9, channel semiconductor thin film (hereinafter referred to as channel layer) 11, channel protective film 13, drain electrode 15 and drain wiring 17 are laminated.

  Of these, the substrate 3 is made of an insulating material such as glass, quartz, sapphire, or plastic.

  The gate electrode 5 patterned on the upper portion of the substrate 3 is formed by shaping a tip portion extended from the gate wiring portion 5a (see a plan view) to a predetermined width, and is composed of molybdenum (Mo) and aluminum (Al). And made of a metal material such as chromium (Cr). The gate electrode 5 is formed by patterning a metal material film deposited using a sputtering apparatus or the like by dry etching or wet etching using a resist pattern formed by lithography as a mask.

  The gate insulating film 7 covering the gate electrode 5 is made of, for example, a silicon nitride film, a silicon oxide film, or the like, and is provided so as to cover the entire surface of the substrate 3.

  The source wiring 8 provided on the gate insulating film 7 is made of a transparent conductive material such as a metal material or indium tin oxide (ITO), and the deposited material film is masked with a resist pattern. A pattern is formed by dry etching or wet etching.

  The source electrode 9 provided on the source wiring 8 is made of, for example, a semiconductor layer such as amorphous silicon into which an n-type impurity is introduced. The source electrode 9 is formed in a pattern so that the tip end portion extended from the source wiring 8 is laminated on the edge of the gate electrode 5, and is provided so as to cover the upper part and the side wall of the source wiring 8. It is important to separate the channel layer 11 provided on the upper portion from the source wiring 8 so that they do not contact each other.

  Such a source electrode 9 is formed by patterning a semiconductor film doped with n-type impurities by dry etching or wet etching using a resist pattern as a mask. The n-type impurity may be introduced when the semiconductor film is formed, or the n-type impurity introduced into the source wiring 8 by ion implantation may be diffused into the semiconductor film constituting the source electrode 9 by thermal diffusion. .

  The channel layer 11 provided on the source electrode 9 is made of a semiconductor layer such as amorphous silicon that does not contain impurities. The channel layer 11 is patterned so as to cover the top of the gate electrode 5 including the tip edge portion of the source electrode 9 superimposed on the gate electrode 5. In the plan view, a part of the channel layer 11 is notched in order to show the lower layer of the channel layer 11, but the channel layer 11 has a rectangular shape covering the tip edge portion of the source electrode 9. To do.

  The channel protective film 13 provided on the upper layer of the channel layer 11 is made of, for example, a silicon nitride film or a silicon oxide film, and extends from the tip of the source electrode 9 superimposed on the gate electrode 5 to the central portion of the gate electrode 5. It is assumed that the pattern is formed so as to cover the top. The channel protective film 13 is provided in a state of being aligned with the source electrode 9 so as to be in a predetermined state. That is, the opposite side S2 (see the plan view) of the channel protective film 13 located on the channel layer 11 with respect to the side S1 (see the plan view) at the tip of the source electrode 9 superimposed on the gate electrode 5 is They are aligned so that they are parallel and maintained at a predetermined distance L. In the plan view, a part of the channel protective film 13 is notched to show the lower layer of the channel protective film 13, but the channel protective film 13 has a rectangular shape covering the tip edge portion of the source electrode 9. .

  Further, the drain electrode 15 provided on the upper layer of the channel protective film 13 is made of a semiconductor layer such as amorphous silicon into which an n-type impurity is introduced in the same manner as the source electrode 9. It is disposed at a position facing the electrode 9. That is, the drain electrode 15 is patterned in a shape covering the channel layer 11 exposed from the channel protective film 13 in a state where the tip is laminated on the edge including the opposite side S2 in the channel protective film 13. Suppose that it is formed.

  Such a drain electrode 15 is patterned by dry etching or wet etching of a semiconductor film doped with n-type impurities using a resist pattern as a mask.

  The drain wiring 17 provided in the upper layer of the drain electrode 15 is formed in a pattern so as to widely overlap the upper part of the drain electrode 15, and is routed and wired under the gate electrode 5. The drain wiring 17 is patterned by dry etching or wet etching of a metal material film or a transparent conductive material film deposited using a sputtering apparatus or the like using a resist pattern formed by a lithography method as a mask. ing.

  In the thin film transistor 1 configured as described above, the source electrode 9 and the drain electrode 15 are placed separately on the front surface side and the back surface side with the channel layer 11 and the channel protective film 13 therebetween. In the thin film transistor 1 having such a configuration, the distance between the source electrode 9 and the portion of the drain electrode 15 in contact with the channel layer 11, that is, the distance between the side S 1 of the source electrode 9 and the opposite side S 2 of the channel protective film 13. L is the channel length L.

  For this reason, the channel length L in the thin film transistor 1 is not dependent on the resolution of the pattern when forming the source electrode 9, the channel protective film 13, and the drain electrode 15. The value is set according to the arrangement state.

  Accordingly, the channel length L can be shortened by setting the arrangement position of the channel protective film 13 with respect to the source electrode 9 without depending on the resolution of the pattern. As a result, it is possible to increase the amount of current handled by the thin film transistor 1 at low cost without increasing the exclusive area and without performing lithography processing with high resolution.

Second Embodiment
FIG. 2 shows the configuration of the thin film transistor according to the second embodiment. 2A is a plan view of the thin film transistor viewed from above, and FIG. 2B is a cross-sectional view taken along line AA ′ in FIG. 2A. The thin film transistor 20 of the second embodiment shown in these drawings differs from the thin film transistor of the first embodiment described with reference to FIG. 1 in that the source electrode 9 and the drain electrodes 15a and 15b on the gate electrode 5 are planar. It is in the arrangement state, and it is assumed that other configurations including the stacking order and the material of the members are the same as those in the first embodiment.

  That is, in the thin film transistor 20 of the second embodiment, the source electrode 9 is disposed above the gate electrode 5 at a planar position sandwiched between the two drain electrodes 15a and 15b.

  In such a configuration, the tip of the source electrode 9 covering the source wiring 8 is laminated on the central portion of the gate electrode 5 via the gate insulating film 7 (shown only in the sectional view).

  In this case, the channel protective film 13 provided on the upper layer of the channel layer 11 is patterned in a shape covering the central portion of the gate electrode 5 including the tip of the source electrode 9 superimposed on the gate electrode 5. Suppose that The channel protective film 13 is provided in a state of being aligned with the source electrode 9 so as to be in a predetermined state. That is, in the source electrode 9 superimposed on the gate electrode 5, two sides S1 and S1 (see a plan view) arranged opposite to the drain electrodes 15a and 15b, and a channel arranged opposite to these sides S1 and S1 The two opposing sides S2 and S2 (see the plan view) of the channel protective film 13 on the layer 11 are aligned so as to be parallel and maintained at a predetermined distance L1 and L2. In the plan view, a part of the channel protective film 13 is notched to show the lower layer of the channel protective film 13, but the channel protective film 13 has a rectangular shape covering the tip edge portion of the source electrode 9. .

  The two drain electrodes 15a and 15b are arranged at positions facing each other with the source electrode 9 and the channel protective film 13 interposed therebetween. That is, the drain electrodes 15a and 15b are formed on the channel layer 11 exposed from the channel protective film 13 in a state where the tip is laminated on the edge including the opposite sides S2 and S2 in the channel protective film 13. It is assumed that the pattern is formed in a shape covering the surface.

  Similarly to the thin film transistor of the first embodiment described with reference to FIG. 1, the thin film transistor 20 of the second embodiment as described above includes the channel layer 11 and the channel protective film 13 formed by the source electrode 9 and the drain electrodes 15a and 15b. It is placed separately on the front side and the back side. Also in the thin film transistor 20 having such a configuration, the distance between the source electrode 9 and the portion of the drain electrodes 15a and 15b in contact with the channel layer 11, that is, the side S1 of the source electrode 9 and the opposite side S2 of the channel protective film 13 Distances L1 and L2 are channel lengths L1 and L2.

  Therefore, the channel lengths L1 and L2 in the thin film transistor 20 are smaller than the pattern resolution when the source electrode 9 and the drain electrode 15 are formed by narrowing the protruding width of the channel protective film 13 with respect to the source electrode 9. Can be set to a value. Therefore, since the channel lengths L1 and L2 can be shortened regardless of the pattern resolution, the amount of current handled by the thin film transistor 20 can be increased at a low cost without performing a high-resolution lithography process, as in the first embodiment. It becomes possible

  Further, in the thin film transistor 20 having such a configuration, by setting the two drain electrodes 15a and 15b to the same potential, a transistor having a channel length L1 and a channel width W1 and a transistor having a channel length L2 and a channel width W2 are arranged in parallel. Equivalent to the connected one.

  In this case, if the width between the sides S <b> 1-S <b> 1 of the source electrode 9 and the width between the opposite sides S <b> 2-S <b> 2 of the channel protective film 13 are maintained, the positional displacement of the channel protective film 13 with respect to the source electrode 9 occurs. Even when the channel lengths L1 and L2 vary, the total handling current amount of the two transistors described above can be kept substantially constant. In addition, the amount of current handled increases as the channel width increases as compared with the thin film transistor of the first embodiment. However, when the amount of current handled is constant, the current density decreases as the channel width increases. Accordingly, an effect of suppressing the threshold shift of the thin film transistor 20 can be obtained.

<Third Embodiment>
FIG. 3 shows a cross-sectional view of the thin film transistor of the third embodiment. The thin film transistor 21 of the third embodiment shown in this figure is different from the thin film transistor of the first embodiment described with reference to FIG. 1 in that the drain electrode 15a, The other configuration is the same as that of the first embodiment. That is, the thin film transistor 21 of the third embodiment is configured as a channel etch type.

  In the thin film transistor 21 having such a configuration, the distance between the source electrode 9 and the portion of the drain electrodes 15a and 15b in contact with the channel layer 11 is the channel length L1 and L2.

  In the thin film transistor 21 having such a configuration, the source electrode 9 and the drain electrodes 15a and 15b are separately provided on the front surface side and the back surface side with the channel layer 11 therebetween. Therefore, the channel lengths L1 and L2 in the thin film transistor 21 are smaller than the pattern resolution when forming the source electrode 9 and the drain electrodes 1515a and 15b by narrowing the distance between the drain electrodes 15a and 15b with respect to the source electrode 9. Can also be set to a small value. Therefore, similarly to the second embodiment described above, the channel lengths L1 and L2 can be shortened regardless of the pattern resolution, and the thin film transistor 21 with an increased amount of current to be handled can be obtained at low cost.

  Similarly to the thin film transistor of the second embodiment, by setting the two drain electrodes 15a and 15b to the same potential, a transistor having a channel length L1 and a channel width W1 and a transistor having a channel length L2 and a channel width W2 are arranged in parallel. Therefore, it is possible to reduce the threshold shift.

<Fourth embodiment>
FIG. 4 shows a plan view of the thin film transistor of the fourth embodiment. The thin film transistor 22 of the fourth embodiment shown in this figure is different from the thin film transistor of the second embodiment described with reference to FIG. 2 in that the drain electrode 15 arranged with the source electrode 9 in between is continuous. The other configurations are the same. In FIG. 4, a part of the channel protective film 13 is notched to show the lower layer of the channel protective film 13, but the channel protective film 13 has a rectangular shape that covers the tip edge portion of the source electrode 9. .

  Even in the thin film transistor 22 having such a configuration, similarly to the thin film transistor of the second embodiment, the source electrode 9 and the drain electrode 15 are arranged on the front surface side and the back surface side with the channel layer 11 and the channel protective film 13 therebetween. Therefore, the channel length can be set to a value smaller than the pattern resolution when forming the source electrode 9 and the drain electrode 15 by narrowing the protruding width of the channel protective film 13 with respect to the source electrode 9. . Therefore, the channel length can be shortened regardless of the pattern resolution, and the thin film transistor 22 with an increased amount of current to be handled can be obtained at a low cost. It is also possible to reduce the threshold shift by an amount corresponding to the increase in channel width.

  In the thin film transistor 22 having such a configuration, a channel is formed on a portion of the channel layer 11 where the drain electrode 15 is disposed so as to surround the source electrode 9. For example, in the figure, a channel is formed in a portion where the source electrode 9 and the drain electrode 15 are surrounded by a “U” shape. In this case, since the channel length becomes longer at the corner portion of the “U” shape, the source electrode 9 is formed in a circular plane, and the source electrode 9 is surrounded by the drain electrode 15 having a planar shape along the circle. Thus, the channel length can be made substantially constant around the source electrode 9.

<Fifth Embodiment>
FIG. 5 is a plan view of the thin film transistor of the fifth embodiment. The thin film transistor 23 of the fifth embodiment shown in this figure is a further development of the thin film transistor of the fourth embodiment shown in FIG. 4, and a plurality of protrusions are provided on the source electrode 9, and these protrusions are sandwiched. In this way, the drain electrode 15 is provided with a plurality of protrusions.

  With such a structure, a thin film transistor structure having a smaller channel and a longer channel width, a large amount of current to be handled, and a threshold shift can be suppressed.

  In the first to fifth embodiments described above, each embodiment in which the present invention is applied to a thin film transistor having an inverted stagger structure has been described. However, the present invention can also be applied to a thin film transistor having a staggered structure. In this case, the stacking order on the substrate 3 in the above-described embodiment may be reversed. Even with the thin film transistor having such a configuration, the same effects as those of the respective embodiments can be obtained.

  In the first to fifth embodiments described above, the source electrode and the drain electrode may be interchanged, and which one is used as the source electrode depends on the circuit using the thin film transistor of each embodiment. It will be selected.

  Furthermore, the first embodiment described with reference to FIG. 1 and the fourth embodiment described with reference to FIG. 4 can be combined with the third embodiment, and each has a configuration in which the channel protective film 13 is not used. There may be. Furthermore, the channel protective film 13 may be provided in the thin film transistor 23 of the fifth embodiment described with reference to FIG.

<Sixth Embodiment>
Next, as a sixth embodiment, an embodiment of a display device using the above-described thin film transistor of the present invention will be described with reference to FIG.

  The display device 30 shown in FIG. 6 is configured using, as the thin film transistor described in each embodiment, for example, a substrate 3 on which the thin film transistors 20 of the second embodiment described using FIG. 2 are arranged. In such a substrate 3, the formation surface side of the thin film transistor 20 is covered with an interlayer insulating film 31, and a plurality of organic electroluminescent elements (so-called organic EL elements) connected to the thin film transistors 20 on the interlayer insulating film 31. 32 is provided. FIG. 6 shows only one pixel of the display device.

  The organic electroluminescent element 32 provided in the display device 30 includes a lower electrode 33 connected to the drain electrode of the thin film transistor 20 through a connection hole 31 a provided in the interlayer insulating film 31. The lower electrode 33 is patterned for each pixel, and the periphery thereof is covered with the insulating film pattern 34 so that only the central portion is widely exposed. Further, an organic layer 35 including at least a light emitting layer is laminated on the exposed portion of each lower electrode 33 in a patterned state. The light emitting layer provided in the organic layer 35 is made of an organic material that emits light by recombination of holes and electrons injected into the light emitting layer. An upper electrode 36 is disposed and formed above each organic layer 35 and the insulating film pattern 34 thus patterned in a state where insulation is maintained between the lower electrode 35. The upper electrode 36 may be formed as an electrode common to each organic electroluminescent element 32.

  In this display device 30, the lower electrode 33 is used as an anode (or cathode), and the upper electrode 36 is used as a cathode (or anode). Then, by injecting holes and electrons from the lower electrode 33 and the upper electrode 36 into the organic layer 35 sandwiched between the lower electrode 33 and the upper electrode 36, in the light emitting layer portion of the organic layer 35. It has a configuration in which light emission occurs. In the case where the display device 30 is a top emission type in which emitted light is extracted from the upper electrode 36 side, the upper electrode 36 is configured using a material having high light transmittance. On the other hand, when the display device 30 is a transmissive type that extracts emitted light from the substrate 3 side, the substrate 3 and the lower electrode 33 are configured using a material having high light transmittance.

  In the display device 30 having such a configuration, the thin film transistor 20 having the configuration of the above-described embodiment, that is, the thin film transistor 20 with an increased amount of handling current is connected to the organic electroluminescent element 32. Thereby, the display characteristic (luminance) in the display device 30 can be improved.

It is a figure which shows the structure of the thin-film transistor of 1st Embodiment. It is a figure which shows the structure of the thin-film transistor of 2nd Embodiment. It is a figure which shows the structure of the thin-film transistor of 3rd Embodiment. It is a figure which shows the structure of the thin-film transistor of 4th Embodiment. It is a figure which shows the structure of the thin-film transistor of 5th Embodiment. It is a figure which shows the structure of the display apparatus of 6th Embodiment. It is a figure which shows the structure of the conventional thin-film transistor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,20,21,22,23 ... Thin-film transistor, 3 ... Substrate, 5 ... Gate electrode, 7 ... Gate insulating film, 9 ... Source electrode, 11 ... Channel part semiconductor thin film, 15, 15a, 15b ... Drain electrode, 30 ... Display device, 32... Organic electroluminescent element (display element)

Claims (5)

On the substrate, a gate electrode, a gate insulating film covering the gate electrode, and a channel part semiconductor thin film covering the gate electrode through the gate insulating film are stacked in this order or in the reverse order,
A thin film transistor, wherein a source electrode and a drain electrode are separately placed on the front surface side and the back surface side of the channel part semiconductor thin film. The thin film transistor according to claim 1, wherein
The thin film transistor, wherein the source electrode and the drain electrode are disposed above the gate electrode with a predetermined interval. The thin film transistor according to claim 1, wherein
The thin film transistor, wherein the other of the source electrode and the drain electrode is disposed at a position between the source electrode and the drain electrode on the gate electrode. In a display device in which a thin film transistor and a display element connected to the thin film transistor are provided over a substrate,
The thin film transistor
On the substrate, a gate electrode, a gate insulating film covering the gate electrode, and a channel part semiconductor thin film covering the gate electrode via the gate insulating film are stacked in this order or in the reverse order, and the channel part semiconductor A display device, wherein a source electrode and a drain electrode are separately placed on a front surface side and a back surface side of a thin film. The display device according to claim 4, wherein
The display device is an organic electroluminescent device.

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