JP2006018712A - Digital/analog consolidation semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital/analog consolidation semiconductor integrated circuit which is highly reliable and capable of suppressing inconveniences by noise occurred in a digital circuit sufficiently. <P>SOLUTION: A digital/analog consolidation semiconductor integrated circuit 10 for consolidating an analog circuit 5 and a digital circuit 6 is provided with: a noise generating means 9 for generating noises of the digital circuit 6; a clock phase regulating means 7 for regulating phases of a clock to be inputted to the digital circuit 6; and an analysis means 8 for analyzing characteristics of the analog circuit 5. On the basis of the analysis results of an analysis tool 8 at the time generating the noises by the noise generating means 9, phase adjustment is performed by a clock phase adjustment means 7. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a digital / analog mixed semiconductor integrated circuit in which an analog circuit and a digital circuit for controlling the analog circuit are mixed, and more particularly to a digital / analog mixed semiconductor integrated circuit including a plurality of digital / analog mixed units. It is.

  Conventionally, in a digital / analog mixed type semiconductor integrated circuit in which an analog circuit and a digital circuit are mixedly mounted on the same substrate, it is known that a noise generated when the digital circuit operates adversely affects the operation of the analog circuit. (For example, refer to Patent Document 1).

Patent Document 1 and the like disclose a technique aimed at suppressing the influence on the analog circuit due to noise in such a digital circuit.
Specifically, first, the clock for the digital circuit generated by the clock generation circuit is advanced by the phase advance circuit. Then, a reference clock for an analog circuit mounted on the same integrated circuit as the digital circuit is generated.

JP-A-10-97342

  The conventional digital / analog mixed type semiconductor integrated circuit described above cannot sufficiently suppress a problem caused by noise generated in the digital circuit. Such a problem has been particularly manifested in a digital / analog mixed type semiconductor integrated circuit mounted on a storage device that has been increased in capacity and speed in recent years.

Details are as follows.
In recent years, a new high-speed serial transfer protocol standard has been formulated to meet the demand for larger capacity and higher speed for storage devices such as hard disks and optical disks. These standards enable serial data to be transferred at a high speed of 1.5 to 2.5 Gbps, as represented by serial ATA, PCI express, and the like.

  In these standards, a low-amplitude differential signal is often used as a serial data transmission / reception signal in order to perform high-speed data transfer. Therefore, as the semiconductor integrated circuit, a digital / analog mixed type semiconductor integrated circuit in which analog circuits such as a receiver and a driver are provided in the front end (FEP) is used. The analog circuit in such a digital / analog mixed type semiconductor integrated circuit has a very high required characteristic because the transfer rate becomes very fast.

  Also, for digital circuits that control analog circuits of a mixed digital / analog semiconductor integrated circuit, the operating frequency inside the digital circuit has increased to the gigahertz order. Therefore, the noise generated in the digital circuit is increased, and the noise is spread over a high frequency band. For this reason, in the mixed digital / analog semiconductor integrated circuit, the noise generated in the digital circuit has an increasing influence on the analog circuit.

Furthermore, in standards such as serial ATA and PCI express, the number of channels of devices has been increased, and the degree to which analog circuits of digital / analog mixed semiconductor integrated circuits are subject to noise is increasing. In other words, the analog circuit is configured to be affected by the mutual interference of noise between channels having multiple channels and the influence of noise in peripheral digital circuits.
Here, it is conceivable that the multi-channel mutual interference can be reduced by arranging the multi-channeled channels at positions sufficiently distant from each other. However, in that case, a space for sufficiently separating the respective channels is required, which causes a problem that the digital / analog mixed semiconductor integrated circuit becomes large.

  On the other hand, the technique disclosed in Patent Document 1 described above aims to reduce the influence of noise generated by a digital circuit synchronized with an analog circuit by adjusting the phase of a clock input to the analog circuit. However, in the above-described large-capacity and high-speed digital / analog mixed semiconductor integrated circuit, it is not possible to expect the effect of reducing the influence of noise in each analog circuit. That is, there is a possibility that a malfunction in the operation of the analog circuit may occur with respect to noise that has been increased due to high speed, mutual interference of noise between channels, noise generated by peripheral digital circuits, and the like.

  The present invention has been made to solve the above-described problems, and provides a highly reliable digital / analog mixed semiconductor integrated circuit capable of sufficiently suppressing problems caused by noise generated in a digital circuit. There is.

  A digital / analog mixed type semiconductor integrated circuit according to a first aspect of the present invention is a digital / analog mixed type semiconductor integrated circuit in which an analog circuit and a digital circuit are mixed and generates noise of the digital circuit. Noise generating means, clock phase adjusting means for adjusting the phase of the clock input to the digital circuit, and analyzing means for analyzing the characteristics of the analog circuit, and when noise is generated by the noise generating means The phase adjustment by the clock phase adjusting means is performed based on the analysis result of the analyzing means.

  According to a second aspect of the present invention, in the digital / analog mixed semiconductor integrated circuit according to the first aspect of the invention, the phase is fixed after the phase adjustment by the clock phase adjusting means is completed. The generation of noise by the noise generating means is stopped.

  According to a third aspect of the present invention, there is provided the digital / analog mixed semiconductor integrated circuit according to the first or second aspect, wherein the noise generating means is provided between the analog circuit and the digital circuit. This is a noise generating circuit provided in FIG.

  According to a fourth aspect of the present invention, there is provided a digital / analog mixed type semiconductor integrated circuit according to the first aspect of the present invention, wherein the analyzing means is configured to detect the analog circuit depending on the presence or absence of ALIGN detection. This is a means for judging the noise state at.

  According to a fifth aspect of the present invention, there is provided a digital / analog mixed type semiconductor integrated circuit according to any one of the first to fourth aspects, wherein the digital / analog has the analog circuit and the digital circuit. A plurality of mixed loading units are provided.

  According to a sixth aspect of the present invention, there is provided a digital / analog mixed semiconductor integrated circuit according to the fifth aspect of the present invention, wherein the noise generating means, the clock phase adjusting means, and the analyzing means include a plurality of the plurality of the analyzing means. It is provided for each digital / analog mixed unit.

  The present invention adjusts the phase of the clock input to the digital circuit based on the analysis result obtained by analyzing the characteristics of the analog circuit when noise is generated in the digital circuit by the noise generating means. Accordingly, it is possible to provide a highly reliable digital / analog mixed type semiconductor integrated circuit capable of sufficiently suppressing problems caused by noise generated in the digital circuit.

Embodiment.
Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. In addition, in each figure, the same code | symbol is attached | subjected to the part which is the same or it corresponds, The duplication description is simplified or abbreviate | omitted suitably.

FIG. 1 is a block diagram showing a digital / analog mixed semiconductor integrated circuit 10 according to an embodiment.
The digital / analog mixed semiconductor integrated circuit 10 according to the present embodiment includes a first generation PHY layer 19 corresponding to the serial ATA standard.

  As shown in FIG. 1, in the PHY layer 19 (physical layer), a receiver 5A and a driver 5B are formed as analog circuits, and a receiver circuit 6A, a transmitter circuit 6B, a control circuit 6C, and a link layer I / F circuit are formed as digital circuits. 6D is formed. The receiver 5A and the driver 5B are connected to the I / O 2A and 2B, respectively, and function as an analog front end. The reception circuit 6A that receives data from the receiver 5A and the transmission circuit 6B that transmits serial data to the driver 5B operate at 1.5 GHz. The PHY layer 19 is connected to the link layer (data link layer) via the link layer I / F circuit 6D.

The digital / analog mixed semiconductor integrated circuit 10 of the present embodiment is a multi-channel semiconductor integrated circuit, and includes a plurality of digital / analog mixed units 1A to 1D as shown in FIG. Yes.
Each of the four digital / analog mixed units 1A to 1D in the digital / analog mixed semiconductor integrated circuit 10 includes the digital circuit 6 (6A to 6D) and the analog circuit 5 (5A, 5B) described in FIG. A PHY layer 19 is formed.

  As shown in FIG. 2, the four digital / analog mixed units 1A to 1D each include a noise generation circuit 9 as noise generation means, a clock phase adjustment circuit 7 as clock phase adjustment means, and an analog circuit. And an analyzing means 8 for analyzing the characteristics of 5.

FIG. 3 is a block diagram showing the configuration of the noise generation circuit 9 and the clock phase adjustment circuit 7.
As shown in FIG. 3, the clock phase adjustment circuit 7 is configured to be able to select one clock from a plurality of clocks having different phases based on the clock selection signal. The clock phase adjustment circuit 7 configured as described above adjusts the phase of the clock input to the digital circuit 6. In this embodiment, the clock phase adjustment circuit 7 is provided in the digital circuit 6, but the position of the clock phase adjustment circuit 7 is not limited to this.

  The noise generation circuit 9 is a shift register including a plurality of flip-flops (F / F). The noise generation circuit 9 configured in this way can arbitrarily generate noise synchronized with the noise generated by the digital circuit 6. Here, the noise generation circuit 9 is provided between the analog circuit 5 and the digital circuit 6 with reference to FIG. Thereby, the noise resistance during normal communication can be improved. This will be described in detail later.

  The analysis means 8 provided in the digital circuit 6 is a means for judging the noise state in the analog circuit 5 based on the presence or absence of ALIGN detection. This will be described in detail later. In the present embodiment, the analyzing means 8 is provided in the digital circuit 6, but the position of the analyzing means 8 is not limited to this.

The operation of each of the digital / analog mixed units 1A to 1D configured as described above will be described below with reference to FIG.
The PHY layer of the serial ATA standard in this embodiment starts an operation called an OOB sequence when power is turned on. Here, the OOB sequence is a negotiation sequence from immediately after resetting or immediately after returning to the power management mode defined by the serial ATA standard to transition to the communication state.

  First, when the power is turned on and the control of the digital / analog mixed type semiconductor integrated circuit 10 is started (step S1), the noise generating circuit 9 is operated before entering the above-described OOB sequence to be equivalent to the internal digital circuit 6. Noise is generated (step S2).

Here, the noise of the digital circuit 6 generated by the noise generating circuit 9 affects the operation of the analog circuit 5. In addition to the noise of the digital circuit 6 in the same digital / analog mixed unit, the noise affected by the analog circuit 5 is set in the vicinity of the noise generated from the digital circuit 6 of the adjacent digital / analog mixed unit. There is also noise generated from the digital circuits of other devices.
When these noises are synchronized, the influence on the analog circuit 5 is maximized, causing distortion in the transmitted / received signal. Such distortion of the transmission / reception signal causes an error in transmission / reception with the host.

After step S2, the above-described OOB sequence is started (step S3).
FIG. 5 is a timing chart showing an OOB sequence performed between the host and the device (in which the digital / analog mixed semiconductor integrated circuit 10 is mounted).
As shown in FIG. 5, signaling (communication of COMRESET, COMINIT, and COMWAKE in the figure) is performed between the host and the device in a power-on state (power ON).

During signaling, the data transmission / reception period is recognized, but the data content is not recognized. It is data called ALIGN in the latter half of the sequence that recognizes the contents of the data. As shown in FIG. 5, ALIGN data is transmitted from both the host and the device. Then, by confirming that both sides can correctly receive ALIGN data (ALIGN detection), it is determined whether or not communication is possible.
Therefore, when the peripheral noise or the noise generated from the digital circuit 6 of the adjacent unit and the digital circuit 6 of its own unit affects the operation of the analog circuit 5, the above-described ALIGN detection cannot be performed.

In the present embodiment, ALIGN detection of the OOB sequence in the PHY layer of the serial ATA standard is used as analysis means (analysis means 8 in FIG. 2) for analyzing the characteristics of the analog circuit 5.
Specifically, after the OOB sequence is started in step S3, the presence / absence of ALIGN detection is determined (step S4). As a result, if ALIGN detection cannot be performed, the clock phase is adjusted by the clock phase adjusting circuit 7 because the noise state in the analog circuit 5 is poor (step S5).

  Specifically, if ALIGN detection cannot be performed, it is determined that the peripheral noise or the noise generated by the digital circuit 6 of the adjacent unit is synchronized with the noise generated by the digital circuit 6 of the own unit. The clock selection signal of the clock phase adjustment circuit 7 is controlled. Thereby, the phase of the clock for the digital circuit 6 in its own unit is changed, and ALIGN detection is performed again (step S4).

If ALIGN is detected in step S4, the noise generation by the noise generation circuit 9 is stopped assuming that the noise state in the analog circuit 5 is good (step S6). At this time, the clock phase adjusted by the clock phase adjusting circuit 7 is also fixed.
That is, when ALIGN detection is possible, it is possible to adjust the phase so that ambient noise, adjacent unit noise, and noise generated from the digital circuit 6 of the own unit are not synchronized.

Thereafter, the OOB sequence is completed in a state where ALIGN detection is possible (a state where the contents of the data can be recognized) (step S7), and this flow is ended (step S8).
That is, the influence of noise on the analog circuit 5 is reduced, and the characteristics necessary for transmission and reception that enable ALIGN detection are ensured. Then, in this state, the operation of the noise generation circuit 9 is stopped and a transition is made to the normal communication state.

Here, in the present embodiment, the noise generation circuit 9 is disposed at the boundary position between the digital circuit 6 and the analog circuit 5. As a result, a noise source is brought close to the analog circuit 5, and the influence of noise at the time of the above-described characteristic analysis of the analog circuit 5 can be maximized. That is, the accuracy of the characteristic analysis of the analog circuit 5 can be improved.
On the other hand, during normal communication, the noise generation circuit 9 is stopped, so that the stopped noise generation circuit 9 functions as a capacitance component. That is, the noise component generated from the digital circuit 6 is reduced. Therefore, the noise resistance of the digital / analog mixed semiconductor integrated circuit 10 during normal communication is improved, and the operation of the analog circuit 5 is further stabilized.

  As described above, according to the configuration of the digital / analog mixed semiconductor integrated circuit 10 in the present embodiment, the characteristics of the analog circuit 5 when the noise is generated in the digital circuit 6 by the noise generating circuit 9 are analyzed. Based on the analysis result, the phase of the clock input to the digital circuit 6 is adjusted. As a result, it is possible to sufficiently suppress problems caused by noise generated in the digital circuit 6.

  In the present embodiment, the digital / analog mixed type semiconductor integrated circuit 10 is constituted by a plurality of digital / analog mixed units 1A to 1D. However, the present invention is naturally applied to a single digital / analog mixed unit. Can be applied. In this case, the analog circuit 5 in the single digital / analog mixed unit is not affected by the noise from the adjacent digital / analog mixed unit, but from the influence of the noise in its own unit or the devices installed in the vicinity. It will be affected by the noise that occurs. Therefore, even in the case of a single digital / analog mixed unit, the clock input to the digital circuit 6 based on the analysis result obtained by analyzing the characteristics of the analog circuit 5 when the noise is generated in the digital circuit 6 by the noise generation circuit 9. By performing the phase adjustment, it is possible to obtain the same effect as in the present embodiment.

  It should be noted that the present invention is not limited to the present embodiment, and it is obvious that the present embodiment can be modified as appropriate within the scope of the technical idea of the present invention, other than suggested in the present embodiment. is there. Further, the number, position, shape, and the like of the above-described constituent members are not limited to the present embodiment, and the number, position, shape, and the like that are suitable for implementing the present invention can be used.

1 is a block diagram showing a digital / analog mixed semiconductor integrated circuit according to an embodiment of the present invention; FIG. It is a schematic diagram showing a digital / analog mixed type semiconductor integrated circuit equipped with a plurality of digital / analog mixed units. It is a circuit diagram which shows a noise generation circuit and a clock phase adjustment circuit. It is a flowchart which shows the control performed with a digital / analog mixed type semiconductor integrated circuit. It is a timing chart which shows the sequence between a host device.

Explanation of symbols

1A to 1D digital / analog mixed unit,
2, 2A, 2B I / O,
5, 5A, 5B analog circuit,
6, 6A-6D digital circuit,
7 Clock phase adjustment circuit (clock phase adjustment means),
8 analysis means,
9 Noise generation circuit (noise generation means),
10 Digital / analog mixed type semiconductor integrated circuit,
19 PHY layer, 20 link layer.

Claims (6)

A digital / analog mixed type semiconductor integrated circuit in which an analog circuit and a digital circuit are mixed,
Noise generating means for generating noise of the digital circuit;
Clock phase adjusting means for adjusting the phase of the clock input to the digital circuit;
Analyzing means for analyzing the characteristics of the analog circuit,
A digital / analog mixed semiconductor integrated circuit, wherein the phase adjustment by the clock phase adjustment means is performed based on an analysis result of the analysis means when noise is generated by the noise generation means. 2. The digital / analog mixed semiconductor integrated circuit according to claim 1, wherein after the phase adjustment by the clock phase adjusting means is completed, the phase is fixed and the generation of noise by the noise generating means is stopped. . 3. The digital / analog mixed semiconductor integrated circuit according to claim 1, wherein the noise generating means is a noise generating circuit provided between the analog circuit and the digital circuit. 4. The digital / analog mixed semiconductor integrated circuit according to claim 1, wherein the analyzing means is means for determining a noise state in the analog circuit based on presence / absence of ALIGN detection. 5. The digital / analog mixed type semiconductor integrated circuit according to claim 1, comprising a plurality of digital / analog mixed units each having the analog circuit and the digital circuit. 6. The digital / analog mixed semiconductor integrated circuit according to claim 5, wherein the noise generating means, the clock phase adjusting means, and the analyzing means are provided for each of the plurality of digital / analog mixed units.

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