JP2005538562A - Reduced chip test method at wafer level - Google Patents

Abstract

The present invention relates to production testing of semiconductor devices, and more particularly to production testing of such devices at the wafer level. The method according to the present invention includes the step (20) of generating quality test data with a limited number of semiconductor devices on a wafer, and testing other semiconductor devices on the wafer based on the generated quality test data. Determining (24) what to do and testing (28) or not (26) other semiconductor devices on the wafer based on the result of the determining step. A corresponding wafer prober is also described.

Description

  The present invention relates to the testing of semiconductor devices, particularly active devices such as chips, and more particularly to production testing of these devices at the wafer level, i.e. before cutting or dicing the wafer into individual chips and Concerning chip assembly.

  The manufacturing stage of the integrated circuit can be divided into two processes. The first step, wafer manufacturing, is a sophisticated and complex process for manufacturing silicon chips, also called dies. The second step, assembly, is a very precise and automated process of packaging the die. These two stages are commonly known as “front end” and “back end”, respectively. A production test is a test during the manufacture of a semiconductor device, which is distinguished from a chip test performed during design or supporting manufacturing, and is often referred to as a technical test.

  The silicon chips are grouped on the silicon wafer before being separated from each other at the beginning of the assembly stage. These are created on each wafer in a multi-step process, with each step adding a new layer to the wafer or modifying an existing one. These layers form the elements of the individual electronic circuit. These process steps may be, for example, etching, diffusion, photomasking, ion implantation, metal deposition, doping and passivation.

  A wafer probe process, also called a preliminary test, is performed between wafer manufacture and assembly. Next, the functionality of the semiconductor device is verified by performing a plurality of generally electrical tests with a special microprobe. The wafer probe consists of two different tests: a process parametric test that checks the wafer manufacturing process itself and a full wafer probe test that verifies the functionality of the finished product. Bad dies are marked, for example, with black dots, and after cutting the wafer they can be separated from good dies. The percentage of good dice on an individual wafer is called its yield.

  Pre-test failure patterns are used by chip manufacturers to detect process errors in the early stages and adjust those processes before certain errors can generate more rejects. Wafer manufacturing suffers from two types of yield losses:

  -Foreseeable yield loss caused by defect density in chip making processes such as diffusion processes. The defect density may include spot defects caused by the particles. These types of rejects are randomly distributed on the wafer. For this type of reject, you can calculate how cost-effective it is if you omit the preliminary test, i.e. remove the preliminary test cost, while the low yield and final test yield The additional cost of a defective package increases the final test cost.

  -Unpredictable yield loss caused by errors during the manufacturing process. These are errors due to malfunction of the chip making device, for example a diffusion device, manual errors, or parameters that vary slowly during manufacturing over a long period of time.

  For mature products and mature designs in the mature process, a high pre-test yield is expected due to low predictable yield loss. Thus, preliminary testing may not be required. Until now, however, unpredictable yield loss has been a justification for pre-testing all wafers.

  Next, the first step in assembly after the preliminary test is to separate the silicon chip, and this step is called die cutting. The die is then placed on a lead frame, the “lead” being a chip leg that is soldered or placed into a socket on the printed circuit board. At this stage the device is fully functional but it is not possible to use it without some kind of support system. Any scratch can change its behavior or affect its reliability, and any impact can cause a failure. Thus, the die is placed in a ceramic or plastic package to protect it from the outside world. In the case of a microcontroller, a thin wire, typically 33 microns, connects the chip to the outside world and allows electronic signals to be supplied to the chip. The process of connecting these thin wires from the chip bond pads to the package leads is called wire bonding. The package not only protects the chip from external influences but also facilitates handling of the entire device.

  At the end of the assembly process, the integrated circuit is tested again by automated test equipment. This is called the final test. Only integrated circuits that pass these tests are shipped to their final destination. A high rate of defective products in the final test can cause serious delivery problems on the customer side. Furthermore, if a failure is detected in the final test rather than the preliminary test, the failure is detected at a very late point. In this case, the feedback loop back to the proper manufacturing process can be very long, i.e. all wafers manufactured during the corresponding time interval can be worthless.

  Another reason for the preliminary test is that after assembly, the location of the wafer failure is not known. Information about the shape and location of the failure is important for the chip maker to determine the root cause of the error.

  To reduce their test time, manufacturers are increasing the number of pins required on a probe card by testing multiple devices simultaneously.

  To reduce the test time as much as possible, each parameter can be reduced by either omitting the preliminary or final test altogether or by dividing these tests, which are referred to as simultaneous tests, into preliminary and final tests. Test only once. Although omitting the final test may be done, it is dangerous for some manufacturing steps after pre-tests such as inking, polishing and cutting, which may damage the integrated circuit. Also related to this is that mechanical stress in the silicon chip itself, which is generated by assembly, for example by the pressure of the plastic, causes further failure. Due to this stress, there may be partial vacancy or shortage. Products that fail due to this mechanism may pass through after removing the package from the chip.

According to one prior art method, which chips are tested in N times of at least one test T ₁ of the such tests. The better results Test T _1, the test T ₂ takes place in the chip. If the results of the test T ₂ bad, mark is attached to a defective product to the chip, the test of the next chip is performed. If a chip passes all of the N tests given, it is marked as good and the next chip is tested.

  In JP-08-274139, a sampling position is specified in a wafer, and all test item measurements are performed at the sampling positions of all wafers. Next, the sampling measurement result is examined to determine whether the quality of each wafer is good, intermediate or bad. Bad wafers are removed. Next, the result of the wafer determination process is examined, and the lot determination is processed based on the number of good wafers in the lot. Similarly, depending on the number of good wafers that the lot contains, the lot quality can be good, intermediate, or bad. If the lot is considered good, the peripheral area of the good and intermediate wafers is removed and the remaining is considered good. If the lot is considered intermediate, then the good wafer peripheral area is removed and the intermediate quality wafer is fully tested. If the lot is considered bad, the quality and intermediate wafers are fully tested. The determination of a complete wafer test is not based on wafer sampling measurements, but is based on the entire lot result.

  With respect to wafer mask and wafer stepper errors, it is possible to fully test a single wafer at a time. On this fully tested wafer, all stepper and mask errors are visible and can be corrected by the chip maker. Although the yield loss due to these errors is small, since it is repeated on each wafer, a lot of rejected products are finally generated.

  General methods for testing semiconductor wafers and equipment by their users during their manufacture are described in 1999, “Integrated Circuit Manufacturability” by IEEE, Gyvez, and Pradham, and 1999, Springer Press, Bajescu and Libuit It is described in the book “Components”.

An object of the present invention is to provide a reduction in test costs and a reduction in test time during wafer testing of ICs, diodes and transistors of any equipment typically manufactured on a semiconductor wafer.
It is a further object of the present invention to increase the test capacity for wafer level testing of semiconductor devices.

The above objective is accomplished by a method and device according to the present invention.
The basic idea of the preliminary test method and apparatus according to the present invention is to identify unpredictable yield loss by testing only a sample of the product on each wafer. If the sample yield meets the defect density of the process, and if the sample contains enough area to detect a particular pattern, the remaining wafers need not be tested. If not, the entire wafer must be tested.

The present invention provides a method for testing the quality of a semiconductor device on a wafer. The method
Generating quality test data for a limited number of semiconductor devices on the wafer;
Determining whether to test other semiconductor devices on the wafer based on the generated quality test data;
Testing or not testing other semiconductor devices on the wafer based on the result of the determining step;
If some semiconductor devices have not been tested, selecting at least one untested semiconductor device on the wafer for further processing. “Limited number” means less than the total number, especially less than half, for example 25% or less, 10% or less or 5% or less.

  The determination step is performed according to a predetermined determination parameter such as, for example, a comparison between a preset value and a yield calculated from the generated quality test data. The preset value is 80% or more, preferably 90% or more, more preferably 95% or more, and even more preferably 97% or more. The preset value of acceptable yield depends on the die size.

  The determination step may be a step of automatically determining, but may not be so.

  In the method according to the invention, the quality test data may indicate the quality of the manufacturing process used to manufacture the semiconductor device. Alternatively, the quality test data may indicate the functionality of the semiconductor device.

  A limited number of semiconductor devices that are initially tested may be placed on the wafer as determined by the spatial pattern. Such spatial patterns may include a circular pattern and / or an X intersection pattern and / or a pattern in the form of a plus sign. Alternatively, the spatial pattern may include a spiral pattern. According to yet another embodiment, the pattern is a render pattern, ie, a pattern that scans wafer lines line by line, testing every xth, eg, but not limited to, every fourth, tenth or twentieth device. It may be.

All semiconductor devices on the wafer may be the same, or some of them may be different.
The semiconductor device may be an active or passive semiconductor device.
The step of generating quality test data preferably includes only non-destructive testing.

The present invention also provides a method for testing the quality of semiconductor devices on a plurality of wafers. This method
Generating quality test data for a limited number of semiconductor devices on some of the plurality of wafers;
Determining, for each wafer tested, whether to test other semiconductor devices on the tested wafer based on the generated quality test data;
Testing or not testing the other semiconductor device on the tested wafer based on the result of the determining step;
If some semiconductor devices have not been tested, selecting at least one untested semiconductor device on the wafer for further processing. In this case too, the “limited number” means less than the total number, in particular less than half, for example 25% or less, 10% or less or 5% or less. A limited number of semiconductor devices on each wafer are placed on the wafer as determined by the spatial pattern. This spatial pattern allows one to obtain a substantially complete wafer map by moving it between wafers, for example by rotating it, ie by stacking different wafer maps. It is.

  The present invention also provides a method of manufacturing a plurality of semiconductor devices on a wafer, wherein one of the method steps includes performing a quality test according to the test method of the present invention.

The present invention further provides a wafer prober for testing a plurality of semiconductor devices on a wafer. Wafer prober
Selecting means for selecting a limited number of semiconductor devices on the wafer to be tested;
At least one probe that measures whether the selected semiconductor device meets at least one preset quality specification and generates a quality test result;
Determining means for deciding whether to test another semiconductor device on the wafer based on the quality test result;

The wafer prober may include a plurality of probes that establish temporary electrical contacts between the wafer prober and individual semiconductor devices on the wafer. The wafer prober may include at least one optical measurement device that performs optical measurements.
The wafer prober may further include storage means for storing the generated test results.

The at least one preset specification may be a design and / or performance specification.
The quality test result may be a non-destructive test result.

  These and other features, features and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. This description is given for the sake of example only, without limiting the scope of the invention. The reference figures quoted below refer to the attached drawings.

Definition Wafer: An array of microcircuits or thin slices of semiconductor material with parallel surfaces on which individual semiconductors are formed.

  Yield: The ratio of available parts selected after a screening test to the number of parts presented after the test.

  Active semiconductor devices on wafer: semiconductor devices with active transistor components, especially multi-component semiconductor devices such as integrated circuits, application specific integrated circuits (ASIC), other custom circuits including multiple transistors such as liquid crystal display active matrix, Includes gate arrays such as hybrid circuits, memories, microprocessors, and field programmable gate arrays (FPGAs) residing on the wafer.

  Integrated circuit: A monolithic microcircuit that consists of interconnected active and passive elements that are inseparably associated with each other and formed in situ or within a single substrate to perform electronic circuit functions.

  Passive semiconductor device: Passive components such as resistors, capacitors, inductors, and antennas.

  Screening test: A test or combination of tests aimed at measuring specific parameters during production operations to monitor, control and improve the process. It is not used to select individual pass or fail devices or wafers. It is also a test that monitors a process or package. Some products in a specific chip making process, such as a diffusion process, or a specific package are subjected to a life test. These represent all other products or wafers in the same chip making process or in the same package.

  Burn-in: A task that is applied to semiconductor devices prior to their final use to stabilize those properties and identify devices that cause premature failure. Usually includes electrical and / or temperature stress on the device causing failure of the device near the edge.

  Dynamic test: A circuit test that evaluates the response to alternating current.

  Chip: A single substrate on which all active and passive components are manufactured. The chip is not normally ready for use until it is packaged and external connections are provided. Die and chip are synonymous.

  Package: A container for electronic components with a terminal that provides electrical and / or optical access to the interior of the container.

  Quality test: A test that confirms whether an item meets specified requirements. This test is usually a non-destructive test. However, there is a case where a “voltage selection test” is performed on each device during operation manufacturing. In this test, X percent, eg 10%, than the normal operating voltage. A high voltage 20% or 200% higher is applied to the device under operating conditions. In particular, the supply current is measured before and after this test. If the currents before and after the “stress test” are not the same, the product is damaged by the stress test and is regarded as a rejected product. This test captures early failures and prevents them from reaching the customer. Mainly it tests the quality of the gate oxide. In this case, the device that “works well” has been destroyed by the quality test. Another exception to non-destructive testing is trimming / zener zapping. During the preliminary or final test, the parameters are measured. If the parameter is not within the device specifications, only in special design circuits, but a small percentage may be added to or subtracted from this parameter by trimming, eg poly trimming, OTP, etc., or by zener zapping. It may be possible. This trimming or zapping process destroys certain parts in the chip. The same trimming / zener zapping process may be used to add or lock specific IC functions for specific customers.

  Reliability test: A test or analysis that is performed in addition to other types of tests to assess the level of product reliability, and the reliability or stability of this level of time and optionally under different environmental conditions. Test specific parameters for lifetime.

  Wafer probe test: Quality test for wafers. Also called preliminary test or e-sort. All tests are performed at the product level to assess whether the equipment meets the expected quality.

Description of Embodiments for Illustrative Embodiments While the present invention will be described with reference to particular drawings based on specific embodiments, the present invention is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. For example, the sizes of the tip 4 and the probe tip 8 in FIG. 1 are exaggerated.

  Where the term “comprising” is used in the present description and claims, it does not exclude other elements and steps. Where an indefinite or definite article is used when referring to a singular noun, such as “a” or “an”, “the”, this is the plural of that noun unless something else is specifically stated. including.

  In the following, reference will be made primarily to chips on the wafer, but the invention relates to testing any semiconductor device manufactured at the wafer level including, but not limited to, ICs, diodes, transistors. The component may be an active semiconductor device, in particular a multi-component monolithic device manufactured on a wafer.

  A typical semiconductor wafer is 200 mm (8 inches) in diameter and typically contains 500 to 10,000 chips. Recently, there has been a trend towards 300 mm (12 inch) wafers containing more chips. The wafer size limiting the present invention is not taken into account.

  In the wafer probe according to the present invention, temporary electrical contacts are established between the test equipment and a limited number of individual chips on the wafer to determine whether each of these chips meets the design and performance specifications. You may do it. Alternatively, optical measurement may be performed. The test device transmits a signal, such as an electrical signal or an optical signal, to the chip and analyzes the returning signal. The test is nondestructive in most cases. The test is an unreliable test and does not determine the expected lifetime of the part. A wafer probe test system according to the invention is shown in the very schematic embodiment of FIG.

This comprises:
Selection means 2: This selects a limited number of chips 4 on the wafer 6 to be tested, and this limited number of chips 4 is only tested in the first step.

  Probe tip 8: A conventional probe or probe tip 8 is a single, usually tapered, metal needle whose tip touches down to a metallized bond pad on the tip 4 to be tested. Or positioned to make electrical contact therewith. Typical bond pads have a width in the range of 40 to 150 microns and a length in the range of 60 to 150 microns. The bond pad dimensions depend on the thickness of the bond wire and the current through the wire. Each chip 4 includes a number of bond pads that can be connected to a chip circuit to transmit electrical signals to and from the chip 4.

  Probe card 10: The probe card 10 is a composite printed circuit board that includes a custom ordered array of probe needles or probe tips 8 that simultaneously contact all bond pads on one or more chips 4. The probe card 10 is mainly used in production tests.

  Probe station 12: The probe station 12 manually or automatically aligns the wafer 6 to the probe card 10 or vice versa, allowing the probe 8 to contact the bond pad of the chip 4 or to the chip accurately. To do. The probe station 12 may be provided with a motor 14 for driving it. The selection means 2 may be connected to a motor 14, and in selecting a particular chip 4 to be tested, the motor 14 of the probe station 12 allows the probe tip 8 suitable for testing that particular chip 4 to be tested. The probe station 12 is automatically moved to the next position.

  Test device 16: The test device 16 transmits an electrical signal to the chip 4 or a plurality of chips via the probe 8 and the probe card 10, and evaluates the returned signal. Test equipment 16 used in production tests is often referred to as automatic test equipment or ATE and is specifically designed for high volume testing. The test device 16 comprises a decision unit 18 for determining on the basis of the returned signal whether other chips on the wafer 6 that were not originally selected by the selection means 2 should also be tested. In that case, a suitable signal is sent from the decision unit 18 to the selection means 2 and then controls the motor 14 of the probe station 12 so that each chip 4 that has not been tested before can be tested.

  Optionally, all chips can be tested in this second step.

  A schematic block diagram of an embodiment of the method according to the invention is shown in FIG. The method begins at block 19. In a first step 20, sampling measurements are taken, thereby generating quality test data for a limited number of chips 4 on the wafer 6. In a second step 22 the result of the sampling measurement 20 is considered / analyzed and in a third step 24 it is determined on the basis of the generated quality test data whether other chips 4 on the wafer 6 should also be tested. . This determination may be based on the calculation of the yield from the generated test data and a comparison between this yield and a preset value. For example, the calculated yield is 95% or more, preferably 97% or more. In some cases, the other chip 4 is not tested. If the result of the decision step is that the yield is sufficiently high compared to the preset value, further testing on the previously untested chip is omitted (step 26). However, if the calculated yield is lower than a preset value, all of the other chips 4 on the wafer 6 are tested in step 28, and each chip is marked as good or bad depending on the result of the test. Attached. Thereafter, the measurement ends (block 29).

  According to an embodiment of the invention, the sample of product to be tested on the wafer 6 is preferably tested according to a predetermined pattern, for example a wheel pattern as shown in FIG. This wheel pattern includes "annular patterns" 30, 32 near the edge of the wafer. This pattern covers the perimeter. The wheel pattern covers the “X pattern” 34 as well as the “+ pattern” 36. Both of these patterns 30, 32, 34, 36 cover area failures.

  Test data is generated from the chip 4 on the patterns 30 to 36. The test data generated is a reflection of reliable quality in all areas of the wafer.

  These tested sample yield targets are required to determine whether to perform 100% testing of the same wafer. Wafers called ugly dies because the chip that belongs to a particular area of the wafer is discarded to yield a clear decision level that determines whether the entire wafer should be tested, for example the yield near the edge is not very predictable Chips close to the edge of the need not be tested in the pattern. For example, 5 to 10 mm may be excluded from the wafer edge. It is preferred that ugly dies are always removed from the test. These devices tend to be at high risk of early failure and are known to cause customer complaints, so ugly dice always reject even in conventional tests, even if they pass the test program. Has been.

  In order to check for wafer stepper errors, it is preferable to combine the method of testing based on the above samples with a full test of every Nth wafer. For example, one out of 25 wafers is always 100% tested, and the remaining 24 wafers are tested for a limited number of dies. According to the present invention, each of these 24 wafers is 100% tested or not, depending on the results obtained for these 24 wafers.

  When using a “wheel pattern” as described above, a complete wafer map pattern can be reconstructed, for example, by stacking individual wafer maps. That is, if the “wheel pattern” occupies 10% of the chip and consists of another group of devices on each wafer and the pattern is shifted by rotating or moving the pattern, a stack of 10 rotated patterns Can be a mapping to a complete wafer map. This eliminates the need to test an entire wafer to check for wafer mask and wafer stepper errors.

  In addition, if more than X wafers are fully tested at once, for example, if more than 20% of wafers are fully tested for determination according to the present invention, all wafers may be fully tested. preferable. This may be controlled manually.

  As an experiment, 10% of the chips on the wafer were tested according to the present invention in a wheel pattern as shown in FIG. The pre-set yield value that determines whether the wafer should be fully tested was set to 97%. 20% of the wafers tested had a yield <97% and were therefore fully tested. This resulted in 80% of the wafers and only 10% of the chips being tested. Only 20% of the wafer tested all the chips on the wafer. As a result, the test time during the preliminary test was reduced by 66%. Therefore, the total throughput time was reduced to approximately 33% of the original throughput time.

  In addition to reducing test time, this method is very useful because it increases the pre-test capacity, and thus can increase production by 66% during periods of insufficient tester capacity.

  The above method is easy to implement in an existing test environment. This can be done within a 2 hour time frame for a new product.

  Although preferred embodiments, specific structures and configurations have been described herein for an apparatus according to the present invention, it is understood that various changes and modifications can be made in form and detail without departing from the scope and spirit of the invention. I want to be. For example, although the wheel pattern has been described as the sampling measurement pattern, any pattern suitable for obtaining representative quality test data, such as a spiral pattern or a random pattern, can be used.

1 is a schematic elevation view of a wafer probe test system according to an embodiment of the present invention. 3 is a flowchart of a method for testing the quality of a semiconductor device on a wafer according to an embodiment of the present invention. FIG. 4 is an illustration of a wheel test pattern that can be used with the present invention.

Claims (10)

A method for testing the quality of a semiconductor device on a wafer,
Generating quality test data for a limited number of semiconductor devices on the wafer;
Determining whether to test other semiconductor devices on the wafer based on the generated quality test data;
Testing or not testing other semiconductor devices on the wafer based on the result of the determining step;
If some semiconductor devices have not been tested, selecting at least one untested semiconductor device on the wafer for further processing;
A method comprising:   The method according to claim 1, wherein the determining step is a step of automatically determining based on a comparison between a preset value and a yield calculated from the generated quality test data.   The method of claim 1, wherein the limited number of semiconductor devices are disposed on the wafer as determined by a spatial pattern.   The method of claim 3, wherein the pattern comprises a pattern selected from one or more of a circular pattern, an X-intersection pattern, a plus sign shape pattern, and a spiral pattern. A method for testing the quality of a semiconductor device on a plurality of wafers,
Generating quality test data for a limited number of semiconductor devices on some of the plurality of wafers;
Determining, for each wafer tested, whether to test other semiconductor devices on the tested wafer based on the generated quality test data;
Testing or not testing the other semiconductor device on the tested wafer based on the result of the determining step;
If some semiconductor devices have not been tested, selecting at least one untested semiconductor device on the wafer for further processing; and
The limited number of semiconductor devices on each wafer is placed on the wafer as determined by the spatial pattern, and the spatial pattern is substantially complete by moving it between the wafers. A method that is capable of obtaining a wafer map.   The method of claim 5, wherein moving the spatial pattern includes rotating the spatial pattern.   6. A method of manufacturing a plurality of semiconductor devices on a wafer, wherein one of the method steps includes the step of performing a quality test according to any of claims 1 or 5. A wafer prober for testing the quality of a plurality of semiconductor devices on a wafer,
Selecting means for selecting a limited number of semiconductor devices on the wafer to be tested;
At least one probe that measures whether the selected semiconductor device meets at least one preset quality specification and generates a quality test result;
Determining means for determining whether to test another semiconductor device on the wafer based on the quality test result;
A wafer prober with   9. The wafer prober according to claim 8, wherein the at least one preset specification is a design and / or performance specification.   9. The wafer prober according to claim 8, further comprising storage means for storing the generated test result.

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