JP2005522035A - Method for forming an improved metal silicide contact to a conductive silicon-containing region - Google Patents

Abstract

A stack layer (220) comprising at least three material layers (221) (222) and (223) is provided to form a silicide portion (208) in and on the conductive silicon-containing region. A layer (221) adjacent to silicon supplies metal atoms for the silicide reaction. The intermediate layer (222) is a metal nitrogen compound formed by supplying a gas containing nitrogen during the deposition. This gas supply is stopped to form the upper layer (223). This method can be carried out as an in situ method. This can significantly improve throughput and deposition tool performance as compared to typical prior art processes that require the use of at least two deposition chambers.

Description

  The present invention relates generally to the field of integrated circuit manufacturing, and more particularly to semiconductor devices having metal silicide portions in these regions to reduce the sheet resistance of conductive silicon-containing regions.

In current ultra-high density integrated circuits, device features are shrinking to increase device performance and functionality.
However, shrinking the feature size entails certain problems that can partially offset the benefits gained by the reduced feature size.
In general, reducing the processing size of a transistor element, for example, lowers the channel resistance in the transistor element, thereby facilitating current flow and increasing the switching speed of the transistor.
However, when the processing dimensions of these transistor elements are reduced, the cross-sectional areas of the electric wiring and the contact region are reduced as the processing dimensions are reduced. The main problem is that the electrical resistance of the region providing electrical contact to the substrate increases.
However, the cross-sectional area determines the resistance of each wiring or contact area, as well as the properties of the electrical wiring and the material contained in the contact area.

The problem described above is a typical process in this respect, also called critical dimension (CD), like the channel extension of a field effect transistor formed under the gate electrode between the source and drain regions of the transistor. Possible for critical feature size.
Shrinking this extension of the channel, commonly referred to as the channel length, reduces the falling edge of the transistor element by reducing the capacitance between the gate electrode and the channel and by reducing the resistance of the shorter channel. And device performance with respect to rise time can be significantly improved.
However, shrinking the channel length is generally the size of any electrical wiring, such as polysilicon and the gate electrode of a field effect transistor made from contact regions that allow electrical contact to the drain and source regions of the transistor. Is further reduced, thus reducing the cross-sectional area available for charge carrier transportation.
As a result, if the reduced cross-sectional area is not compensated for by improving the electrical properties of the material forming the wiring and contact regions, electrical wiring and contact regions such as gate electrodes, drains and source contact regions are more High resistance.

Therefore, it is particularly important to improve the properties of conductive regions that are basically composed of a semiconductor material such as silicon.
For example, in current integrated circuits, individual semiconductor devices, such as field effect transistors, capacitors, and the like, are primarily based on silicon, and the individual devices are connected by silicon wiring and metal wiring.
The resistivity of metal interconnects can be improved by replacing commonly used aluminum with, for example, copper, but if the electrical characteristics of semiconductor interconnects and semiconductor contact regions containing silicon are needed, process engineers Face difficult challenges.

  Generally, processing is performed so that metal silicide portions are formed on these silicon-containing regions. This metal silicide portion exhibits a much lower sheet resistance than silicon, even in the deeply doped state.

In FIGS. 1a-1c, a typical prior art process flow for forming a metal silicide portion on a conductive silicon-containing region is described.
FIG. 1 a shows a schematic cross-sectional view of an FET (Field Effect Transistor) 100 formed in a substrate 101. The substrate 101 may be a silicon substrate or another substrate suitable for carrying the FET 100.
The dimensions of the FET 100 are defined by a shallow trench isolation region 103 that can be formed by an insulating material such as silicon dioxide.
For example, the gate insulating layer 106 including silicon dioxide separates the gate electrode 109 basically composed of polysilicon from the well region 102. The well region 102 may include N-type dopant atoms and / or P-type dopant atoms depending on the characteristics of the FET 100 required.
Further, a source region and a drain region, both indicated by reference numeral 105, are provided in the well region 102. Conversely, these regions are doped into the well region 102.
The region on the surface of the well region 102 under the gate insulating layer 106 is also called a channel region.
The lateral distance in FIG. 1 a that separates the drain region 105 and the source region 105 is called the channel length.
For example, the sidewall spacer 107 containing silicon dioxide or silicon nitride is formed so as to be in contact with the sidewall of the gate electrode 109.
Metal silicide portions 108 are formed on the surfaces of the drain region / source region 105 and the gate electrode 109. This metal silicide portion 108 is generally cobalt in a low-resistance ohmic state to reduce the resistance of the respective conductive silicon-containing regions such as the gate electrode 109 and the source / drain regions 105.・ Contains silicide (CoSi ₂ ).

The structure shown in FIG. 1a is typically formed by subsequent process steps.
First, after forming the trench isolation region 103 by etching the trench and refilling with silicon dioxide, the gate insulating layer 106 is formed by, for example, an oxidation process.
Next, a polysilicon layer is deposited and patterned to form the gate electrode 109 by a sophisticated photolithography technique.
Thereafter, a first implantation step is performed to define a lightly doped region in the source region / drain region 105, and then an implantation mask is used in an implantation step after the source region / drain region 105 is defined. Sidewall spacers 107 are formed.
Next, a layer of refractory metal including, for example, titanium, tantalum, zirconium, cobalt, nickel and the like is deposited over the structure shown in FIG. 1a.
Typically this metal is deposited by sputtering in a sputtering tool containing the corresponding target to provide the required metal.

FIG. 1 b schematically shows a partially enlarged cross-sectional view of the drain region 105 including the refractory metal layer 110 deposited on the drain region 105.
On the upper surface of the refractory metal layer 110, if the refractory metal layer 110 is formed essentially of cobalt, a cap layer 111, which can typically comprise titanium or titanium nitride, is disposed.
The cap layer 111 is generally formed by sputtering deposition. In this sputtering deposition, the substrate 101 is processed in a separate deposition chamber to form a cap layer 111.

Thereafter, a first annealing step performed at a first average temperature (generally in the range of 440 ° C. to 600 ° C. when using cobalt as the refractory metal) is performed in the refractory metal and drain regions in layer 110. This is performed to initiate a chemical reaction between the silicon in 105.
Of course, it should be noted that corresponding reactions also occur in the gate electrode 109 and the source region 105.
During this first annealing step, the metal of layer 110, such as cobalt, and the silicon in region 105 are exposed to diffusion to form cobalt monosilicide.
As this reaction occurs, the cap layer 111, which essentially contains titanium, acts as a so-called gettering layer, which reacts well with oxygen atoms present in the annealing environment to form titanium oxide.
Thus, the titanium cap layer 111 can significantly reduce oxidation of cobalt in the underlying layer 110 or otherwise form cobalt oxide, increasing the resistance of the resulting silicide layer. be able to.
However, upon diffusion during the first anneal step, titanium and cobalt tend to form a composite that is essentially non-reactive with silicon, and thus not useful for low ohmic silicide portions.

On the other hand, if the cap layer 111 essentially comprises titanium nitride, the cap layer 111 essentially serves as an inert layer during the first annealing step. However, this cap layer 111 provides only some ability to protect the underlying cobalt from being oxidized by the remaining oxygen in the annealing environment.
Furthermore, during annealing and formation of cobalt monosilicide, the grain boundaries increase and titanium can accumulate if the titanium cap layer 111 is used.

Thereafter, unreacted cobalt in cap layer 111 and layer 110 is removed by a selective wet etch process.
Next, in order to transform the cobalt monosilicide into a more stable cobalt disilicide, the second annealing step is performed at a higher average temperature than in the first annealing step (if cobalt is used in layer 110, Typically in the range of 650 ° C. to 700 ° C.). This cobalt disilicide exhibits significantly lower sheet resistance than cobalt monosilicide.
As described above, in the case of the titanium cap layer 111, titanium can accumulate at the grain boundary of cobalt monosilicide. Thus, the primary diffusion route for chemical reactions during the second annealing step can be significantly hindered by accumulated titanium.

Further, as shown in FIG. 1c, a cobalt titanium layer 112 may be formed during the first annealing step. Accordingly, the thickness of the silicide portion 108 is reduced.
Furthermore, due to the titanium accumulated at the grain boundaries, the final silicide portion 108 and the underlying interface 113 of the silicon-containing region 105 may be relatively rough, and thus are attributed to increased charge carrier dispersion. The increased electrical resistance.
If a titanium nitride layer is used as the cap layer 111, substantially no cobalt titanium layer 112 can be produced, but instead the resulting silicide portion 108 will contain a substantial amount of cobalt oxide. May be included. Thereby, the electrical resistance of the silicide portion 108 further increases.

  As a result, according to prior art processing, the overall resistance of the conductive silicon-containing region can be significantly improved by forming silicide portions in these regions, but with respect to the quality of the silicided portions and processes There is still room for improvement in consideration of optimization.

The present invention generally relates to a method of forming a silicided portion in a conductive silicon-containing region. In the present invention, a stack layer is provided. One or more metal layers in the stack provide the metal to form a metal silicide portion, while the other layers in the stack are down while the chemical reaction between the metal and silicon begins. Provided to protect the metal layer.
Furthermore, according to one aspect, complex deposition techniques requiring two separate deposition chambers are significantly simplified by providing a method that can be performed in situ to form a stack layer. be able to. Thereby, the metal layer and the protective layer can be deposited in one deposition chamber.

According to one embodiment of the present invention, a method for forming a region having a reduced resistance value in a conductive silicon-containing region includes a substrate having a conductive silicon-containing region formed thereon. Providing and depositing a stack layer including a first metal layer, a second metal layer, and a metal nitrogen compound layer located therebetween on the conductive silicon-containing region.
The method further includes heat treating the substrate to form a metal silicide portion in the conductive silicon-containing region.

According to one further embodiment of the present invention, a method for forming a silicide portion in a conductive silicon-containing region formed on a substrate includes depositing a metal on the conductive silicon-containing region in a plasma environment. Including the steps of:
In addition, a nitrogen-containing gas is supplied to the reactive plasma environment for subsequent deposition of metal nitrogen compounds.
Thereafter, the supply of the gas containing nitrogen is stopped in order to deposit the metal again.
In addition, heat treatment is performed to form a metal silicide portion that is substantially formed from a metal located between the conductive silicon-containing region and the metal nitrogen compound.

The invention may be understood by reference to the detailed description taken in conjunction with the accompanying drawings. In the drawings, like reference numerals indicate like elements.
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will be described in detail.
However, the drawings and detailed description are not intended to limit the invention to the particular form disclosed. On the contrary, the invention extends to the spirit and scope of the invention as defined by the appended claims, modifications, equivalents and alternatives.

BEST MODE FOR CARRYING OUT THE INVENTION

An exemplary embodiment of the present invention is described below.
For clarity, not all features of an actual product are described in this specification.
In developing such real products, a number of implementation-specific decisions are made, subject to system and business-related restrictions that change from implementation to implementation, to achieve the developer's special purpose. There must be.
Moreover, such development efforts can be complex and time consuming, but nonetheless are routine for those skilled in the art who would benefit from this disclosure.

In the following description, an example of an embodiment of the present invention will be described by taking an FET including a conductive silicon-containing region as an example.
However, it should be understood that the present invention is applicable to any conductive silicon-containing region provided in an integrated circuit.
For example, a certain die region or each semiconductor element may be connected by polysilicon wiring. The polysilicon wiring may have a relatively small cross-sectional area according to design requirements so that any improvement in the conductivity of these wirings significantly enhances the overall performance of the integrated circuit.

FIG. 2a schematically shows a cross section of a semiconductor device 200 in the form of a FET having essentially the same components and parts as already described in FIG. 1a.
Except for the difference between the 200th generation and the 100th generation, the corresponding part is displayed by the same sign in the last two digits.
Accordingly, the semiconductor device 200 includes a shallow trench isolation region 203 formed in the substrate 201. The substrate 201 may be any suitable substrate including, for example, a silicon substrate, a silicon-on-insulator substrate, and the like.
The drain and source regions 205 are separated by a well region 202 having a central portion. A gate insulating layer 206 that electrically isolates the gate electrode 209 from the well 02 is formed on the central portion of the well region 202.
Further, the sidewall spacer 207 is located on the sidewall of the gate electrode 202.

The process flow for forming the semiconductor device 200 may include substantially the same process steps as already described with respect to FIG. 1a.
Therefore, the description corresponding to this is omitted.
In addition, the semiconductor device 200 shown in FIG. 2a includes a layer stack 220 that is deposited to later form silicided portions of the drain and source regions 205 and the gate electrode 209 (for this purpose). , Detailed below).

FIG. 2B is a diagram schematically showing a partially enlarged cross section of the semiconductor element 200 including a part of the stack layer 220 and the underlying silicon-containing region (for example, the region 205).
According to certain embodiments, the stack layer 220 includes three layers: a first metal layer 221, a second layer 222 that includes a metal nitrogen compound, and a third layer 223 that takes the form of a metal layer.
The first metal layer 221 may include a refractory metal or a suitable alloy including, for example, cobalt, titanium, zirconium, tantalum, tungsten, nickel, and the like.
The second layer 222 may include a metal nitrogen compound such as a metal nitride formed from one of the refractory metals described above.
The third layer 223 may include, for example, a metal or metal alloy containing any of the metals described above.
The thickness of each layer 221, 222, and 223 is selected to meet specific needs.
That is, the first layer 221 is a material source for the metal silicide portion to be formed in or on the conductive silicon-containing region 205.
As described above, the thickness of the first layer 221 is selected so that the silicide portion to be formed has a required thickness.
After forming a metal silicide portion, which becomes an inactive layer, ie, a diffusion barrier layer that substantially prevents diffusion from the first layer 221 to the second layer 222 and / or the third layer 223 The thickness of the second layer 222, which aids in the chemical reaction between the first layer 221 and the second layer 222 during this process step, will sufficiently protect the underlying first layer 221 during the subsequent annealing step. Selected.
For example, when the metal nitride in the second layer 222 is titanium nitride, the typical layer thickness is in the range of about 10 to 100 nm.
The thickness of the third layer 223, which serves as a getter layer that reacts with oxygen atoms or other reactive byproducts to form a metal oxide or other composite in a later annealing step, is preferably substantially Is selected to consume all of the oxygen atoms or to strike the surface of this third layer.
In general, a thickness in the range of about 10 nm to 30 nm is sufficient to maintain an undesired degree of oxidation in the first layer 221 within an acceptable range.

In one embodiment, the first layer 221 and the third layer 223 include substantially the same metal. The second layer 222 substantially includes a metal nitride formed of the same metal as that forming the first layer and the third layer.
Using the same metal for the first layer 221, the second layer 222, and the third layer 223 has the following advantages.

Preferably, in high density integrated circuit superfabrication on a substrate with a large diameter, the metal layer is deposited by physical vapor deposition methods such as sputtering for a fairly high uniformity that can reach the entire surface of the substrate. .
During sputtering deposition, a substrate, such as substrate 201, includes a reaction chamber (illustrated) that includes a target (ie, a disk-shaped material that is typically to be deposited on the substrate and a means for creating a plasma environment). Not inserted).
In general, plasma is generated using a noble gas such as argon to direct ions and electrons to cause target atoms to act on the target material.
Thereafter, some of the free atoms move to the substrate and condense on it to form a metal layer such as the first layer 221.
Sputtering process parameters such as chamber pressure, power supplied to the plasma generating means, DC or AC bias voltage supplied to the substrate, distance between target and substrate, deposition process time and the like Can be controlled to adjust the thickness of the first layer 221 according to design requirements.
Since sputtering tools and processes are already well established in the prior art, a detailed description thereof will be omitted.

After the first layer 221 is deposited to the required thickness, a nitrogen containing gas (eg, nitrogen (N ₂ )) is added to the plasma environment.
Many refractory metals, such as titanium, zirconium, tantalum, tungsten and the like, form nitrogen compounds during sputtering in the presence of nitrogen so that the second layer 222 can be formed as a metal nitride layer. It is known.
Further, deposition process parameters, including the parameters described above, and particularly the flow rate of nitrogen supplied to the reactive plasma environment may be controlled to adjust the thickness and characteristics of the second layer 222.
After the desired thickness is obtained, the supply of nitrogen is stopped. This plasma environment is further maintained over time, such that more metal is deposited on the substrate than metal nitride.
Eventually, the process proceeds until substantially all of the remaining nitrogen gas is consumed so that a substantially “pure” metal layer 223 is produced.

In addition, any trapped nitrogen in the target material, or any metal nitride deposited on the target and on the chamber walls, is nitrogen-free so that contamination of the metal nitride in subsequent sputtering deposition processes is minimized. Can be removed during the unprocessed deposition process.
The deposition process of the third layer 223 is stopped when the required thickness is reached, or when the degree of “clean” in the deposition chamber has been required.
Since the third layer 223 functions as a mere sacrificial layer, the thickness is not important as long as the minimum effect required when removing oxygen atoms with a getter is guaranteed.
Thus, according to this particular embodiment, the stack layer 220 comprising the three layers 221, 222 and 223 can be formed by an in situ sputtering process. This significantly improves throughput and tool performance.

According to an example of a further embodiment, the first layer 221 can be deposited in a first plasma environment, for example to form a cobalt layer. Thereafter, the substrate 201 is exposed to a second plasma environment including a second target material (for example, titanium) and a gas component including nitrogen.
After the titanium nitride layer is deposited, the supply of gas containing nitrogen is stopped. Also, as described in the above embodiment, the titanium layer 223 is gradually deposited at the same time as the sputtering target is removed.
Thus, the first layer 221 is selected to produce an optimized silicide portion, and the second layer 222 and the third layer 223 are selected to properly protect the first layer 221 during subsequent thermal processing. The material composition can be selected.

As the next process step, a heat treatment is performed to initiate a chemical reaction between the silicon in the conductive silicon-containing region 205 and the first metal layer 221.
For this purpose, according to one embodiment, the type of metal contained in the first layer 221 initiates a chemical reaction between the metal in the first layer 221 and the underlying silicon, and metal silicon. A first annealing step at a first average temperature may be performed to form a composite.
During this annealing step, the second layer 222 substantially prevents vertical diffusion of the materials of the first layer 221 and the third layer 223. This is particularly effective when the first layer and the third layer contain different metals.
Furthermore, the second layer 222 does not substantially react with the metal of the first layer 221.
Moreover, reactive elements, particularly oxygen that may be present in this environment, are substantially consumed by the third layer 223 by forming oxide-like composites with these reactive elements. Is done.

Thereafter, the second layer 222 and the third layer 223 are selectively removed. Also, excess material in the first layer 221 that has not reacted with the underlying silicon is removed.
Such removal can be done by performing various known wet etch processes.

FIG. 2c schematically illustrates the metal silicon composite 225 formed in and on the conductive silicon-containing region 205 after removing excess material.
Thereafter, a further heat treatment, such as a second annealing step, causes the metal silicon composite to have a much lower resistance than the silicon in region 205 or metal silicon composite 225 at an average temperature higher than the average temperature in the first heat treatment. Performed to deform to the metal silicide shown.

FIG. 2d schematically shows the semiconductor device 200 after the completion of the second heat treatment, in which a metal silicide portion 208 is formed in and on the source / drain regions 205 and the gate electrode 209. ing.
By providing the second layer 222 during the first heat treatment, diffusion activity between these two layers is substantially avoided even if the metal of the first layer 221 is different from the metal of the third layer 223. Thus, the interface between the silicon and metal silicide regions 208 is significantly improved.

In the embodiments described above, the stack layer 220 has been described as having three different layers, but the stack layer 220 is suitable for obtaining the required diffusion barrier function and the required gettering function. Any number of layers may be included.
In particular, the transition between the second layer 222 and the third layer 223 exhibits anti-diffusion properties that require a portion of the first metal layer 221 while the top surface of the stack layer 220 has a better getter. It can be a gradual movement where the ratio of metal and metal nitride can be stepwise different to indicate ring efficiency.
This is true for embodiments using an in situ deposition process. In this in situ deposition process, the supply of nitrogen gas can be controlled to obtain the metal nitride and metal configuration required for the second and third layers.
Further, in some embodiments, the first layer 221 and the second layer 222 can be deposited in an in situ process to form the metal layer 221 and the corresponding nitride layer 222 while the third layer 223 is a separate layer. It can be formed from different materials in the deposition process.

It should be noted that in other embodiments, more than four layers may be used in the stack layer to obtain the protective cap required for the silicide forming metal. is there.
In other embodiments, particularly when in situ deposition is used for two or three of the layers, the term layer refers to its function rather than to the underlying layer or the boundary to the overlying layer. The layer substantially defined by is described.
For example, a metal nitride layer that is supplied by nitrogen and deposited by sputtering, and a layer that is formed by stopping the supply of nitrogen after the metal nitride has reached a certain thickness, is a finally formed layer. It is difficult to define a clear physical boundary between them due to the gettering function and the inert effect of the previous layer, but can be understood as at least two layers.

It will be apparent to those skilled in the art having the benefit of the teachings described herein that the particular embodiments described above can be practiced with modification in a different but equivalent manner. is there. For example, the process steps described above may be performed in a different order.
Furthermore, nothing else described in the appended claims is intended to limit the invention to the details of construction or design shown herein.
Accordingly, the specific embodiments described above may be substituted or modified and all such variations are considered within the spirit and scope of the invention.
Accordingly, the protection sought in this application is set forth in the appended claims.

1 is a cross-sectional view schematically illustrating a semiconductor device including a silicide portion formed according to a typical prior art process. 1 is a cross-sectional view schematically illustrating a semiconductor device including a silicide portion formed according to a typical prior art process. 1 is a cross-sectional view schematically illustrating a semiconductor device including a silicide portion formed according to a typical prior art process. 1 is a cross-sectional view schematically illustrating a semiconductor device in a plurality of manufacturing stages according to one embodiment of the present invention. 1 is a cross-sectional view schematically illustrating a semiconductor device in a plurality of manufacturing stages according to one embodiment of the present invention. 1 is a cross-sectional view schematically illustrating a semiconductor device in a plurality of manufacturing stages according to one embodiment of the present invention. 1 is a cross-sectional view schematically illustrating a semiconductor device in a plurality of manufacturing stages according to one embodiment of the present invention.

Claims (13)

Providing a substrate (201) having conductive silicon-containing regions formed thereon;
A stack layer (220) including a first metal layer (221), a second metal layer (223), and a metal nitrogen compound layer (222) positioned therebetween is deposited on the conductive silicon-containing region. Steps,
Heat treating the substrate (201) to form a metal silicide portion (208) in the conductive silicon-containing region;
Forming a region having a reduced resistance value in a conductive silicon-containing region.   The method of any preceding claim, wherein the first metal layer (221), the second metal layer (223), and the metal nitrogen compound layer (222) comprise the same metal.   The method of any preceding claim, wherein depositing the stack layer (220) is performed in situ. Depositing the stack layer (220) comprises:
Sputter depositing the first metal layer (221) in a plasma environment;
Supplying a nitrogen-containing gas to the plasma environment to deposit the metal nitrogen compound layer (222);
Stopping the supply of the nitrogen-containing gas to deposit the second metal layer (223);
The method of claim 1 comprising: Depositing the stack layer (220) comprises:
Exposing the substrate (201) to a first plasma environment to deposit the first metal layer (221);
Supplying a nitrogen-containing gas to a second plasma environment to deposit the metal nitrogen compound layer (222), and exposing the substrate (201) to the second plasma environment;
Stopping the supply of the nitrogen-containing gas to the second plasma environment to deposit the second metal layer (223);
The method of claim 1 comprising: Depositing the stack layer (220) comprises:
Exposing the substrate (201) to a first plasma environment to deposit the first metal layer (221);
Supplying a nitrogen-containing gas to the first plasma environment to deposit the metal nitrogen compound layer (222);
Exposing the substrate (201) to a second plasma environment to deposit the second metal layer (223);
The method of claim 1 comprising: The step of heat-treating the substrate (301) includes:
A first annealing process at a first average temperature;
A second annealing process at a second average temperature that is higher than the first average temperature;
The method of claim 1 comprising:   Removing unreacted metal of the second metal layer (223), the metal nitrogen compound layer (222), and the first metal layer (221) prior to the second annealing process; The method of claim 7.   The method of any preceding claim, wherein the first metal layer (221) comprises at least one of cobalt, titanium, zirconium, tantalum, nickel, and tungsten.   The method of any preceding claim, wherein the second metal layer (223) comprises at least one of cobalt, titanium, zirconium, tantalum, nickel, and tungsten.   The method of any preceding claim, wherein the metal nitrogen compound layer (222) comprises at least one of titanium, tantalum, zirconium, tungsten, and nickel. Depositing metal on a conductive silicon-containing region in a plasma environment;
Supplying a nitrogen-containing gas to the plasma environment to deposit a metal nitrogen compound on the deposited metal;
Stopping the supply of the nitrogen-containing gas to deposit the metal on the metal nitrogen compound;
Heat treating the substrate (201) to form a metal silicide portion (208) formed substantially from a metal located between a conductive silicon-containing region and the metal nitrogen compound;
Forming a silicide portion in a conductive silicon-containing region formed on a substrate. Depositing a metal in the conductive silicon-containing region produces a first layer (221);
Depositing the metal nitrogen compound produces a second layer (222) that acts as an inert layer;
Depositing the metal on the metal nitrogen compound produces a third layer (223) that serves as a getter layer;
The method of claim 12.

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