JP2005520336A - System and method for positioning a dummy metal fill while preventing interference with device matching and selective capacity limitation - Google Patents

Abstract

Disclosed is a system and method for placing a dummy metal fill while preventing interference with device matching and selective capacity limiting. In general, a computer-automated method of positioning dummy fills in the manufacturing process of an integrated circuit is received as an integrated circuit input layout and device matching specification, and in accordance with a dummy law while maintaining device matching. Positioning the filling within the integrated circuit. The positioning of the dummy fill maintains the alignment of the repetitive element, which is the alignment by the element where the element alignment is repeated, and positioning the dummy fill along at least one symmetry axis where the element alignment exists along the symmetry axis. Positioning the dummy filler to do so.

Description

(Citation of related application)
This application is a co-pending US patent application no. 10 / 097,978, title of invention "System and method for limiting the increase in capacity due to metal filling used to improve the homogenization of the flattening profile" (submitted on March 12, 2002, all of which A continuation-in-part application, which is incorporated herein by reference).

(Background of the Invention)
(1. Technical field to which the invention belongs)
The present invention relates generally to semiconductor processing, and more particularly discloses a system and method for positioning a dummy metal fill while preventing interference with device matching and selective capacity limiting.

(2. Related technology)
Typically, an integrated circuit manufacturing process includes a series of layer formation steps in which metallization, dielectric, and other materials are applied to a semiconductor surface to form a layered wiring structure. In general, an integrated circuit formed from a wafer includes an interlayer circuit comprising a plurality of metal lines across a plurality of layers interconnected by metal filled vias. Thus, one of the critical steps in the manufacturing process is the formation of interlayer wiring that connects layers and semiconductor circuits, resulting in an integrated circuit device that is very complex and has a high circuit density.

  In particular, in a 0.35 submicron semiconductor device, it is important to satisfactorily planarize each layer of the integrated circuit before the next process in order to reduce the process yield from the next process in the manufacturing process. The planarized surface is often required to maintain the level required for the focus photolithography in the next process and to prevent the metal wiring from being deformed in the contour process.

  For example, the damascene method is often used for metallization of interlayer wiring. The damascene process requires the etching of vias or trench patterns into the planarizing dielectric layer that leads to the active layer of the device. Excess metal is typically deposited across the wafer surface to fill vias or trenches. Then, the excess metal layer is polished until it becomes a patterned metal surface, leaving a fine metal wire as a wiring. As with other steps in the manufacturing process, it is important that the polished damascene layer be flat.

  In order to achieve the flatness required for the fabrication of ultra-high density integrated circuits, a chemical mechanical polishing (planarization) (CMP) process is used to planarize the shape of the thin film or layer on the substrate. In general, the CMP process is a polishing process including selectively removing metal from a semiconductor wafer by rotating the polishing pad and the wafer relatively while applying a controlled amount of pressure while adding a chemical slurry. is there. CMP can be performed on oxides and metals, and good local planarization can be performed. After the CMP process, a smooth surface is obtained and prepared for the next process such as lamination.

However, in many cases, the flat profile obtained as a result of the CMP process depends on the pattern density of the lower layer, which results in variations exceeding 30% -40%. This dependence on the lower layer is described in the following document, for example. “An Integrated Charac- terization and Modeling Methodology for CMP Dielic Planarization”, Oma et al., Procedure for Interconnection Technology Conference, February 1998, pages 67-69, all cited herein for reference. )
One way to reduce the variation in CMP planarization profile caused by pattern dependence is through the use of dummy metal fills. In particular, a dummy metal filling or characteristic is inserted prior to the CMP process in order to more average pattern density, i.e., more average characteristic density between layouts. The averaging of the characteristic density improves the averaging of wafer processing for certain operations such as CMP. Thus, the dummy metal filling facilitates the reduction of the pattern dependence profile after CMP.

  The positioning of the dummy filling is generally performed according to the conventional dummy filling law in which an average density dummy with space available is arranged. (Dummy filling based on the law). For example, see below. "Analyzing the Effects of Dummy-Fills: From Feature Scale Analysis to Full-Chip RC Examination" Lee et al., IEDM 2001 Procedure, December 2001, all cited herein for reference. However, one problem with dummy packings based on the law is that the tolerance of dummy packings is generally so wide that the predetermined density is determined by trial and error for each design.

  Model-based dummy fill insertion can also be used to reduce pattern-dependent CMP planarization profile variability. In general, since the CMP averaging profile is proportional to the effective pattern density as a result of the averaging effect due to the rotation of the polishing pad, model-based dummy fill insertion is required to achieve the effective density within a predetermined range. By selectively inserting the filler, large flattening profile variations can be reduced. For example, see below. “Model-Based Dummy Features Placement for Oxide Chemical-Mechanical Polishing Manufacturability” Tian et al., IEEE Journal on Computer Aided Design of Integrated Circuits and Systems, Vol. 20, no. 7, July 2001, pages 902-910, all incorporated herein by reference.

  However, the insertion of the dummy metal filler adversely affects the electric field and the increase in capacity of the original metal wire. The increase in net capacity can exceed 25% for a given long critical net. Some nets span the entire chip, affecting chip-critical performance. The common critical net is an overall control signal such as a clock. In general, long interconnected nets are dominated by RC delay so that the net delay is directly proportional to the increase in net capacity. Thus, a 25% increase in net delay may be sufficient to cause a failure situation for circuit functionality.

  As Tian mentioned in the above quote, the capacity drops rapidly if there is a gap between the dummy metal and the original metal layer. Tian proposes to reduce the increase in capacity by maximizing the distance between the original metal line and the dummy metal in the cell, while the available area is constrained. According to the method proposed by Tian, the increase in capacity is reduced in all nets. However, it is difficult to reduce the capacity for all nets, and the method proposed by Tian cannot compensate for the decrease in capacity within a predetermined area of the long-term critical net.

  The insertion of the dummy metal filling may adversely affect other characteristics of the original circuit or device design. Thus, there is a need for systems and methods that improve the uniformity of post-CMP planarization profiles while maintaining circuit or device characteristics.

(Summary of Invention)
Disclosed is a system and method for positioning a dummy metal fill while preventing interference with device matching and selective capacity limiting. In the present system and method, consideration is given to the effect of dummy metal filling transferred to structures printed on the wafer, thereby limiting interference with device alignment and selectively limiting capacity increase. The present invention may be implemented in numerous ways, including processes, equipment, systems, methods and computer readable media such as computer readable storage media or computer networks in which program instructions are transmitted over optical and electronic lines. Please understand that you can. Inventive embodiments of the present invention are described below.

  A computer-automated method of positioning dummy fills in the integrated circuit manufacturing process is to accept integrated circuit layout input and integrated circuit element matching specifications and to integrate the integrated circuit in accordance with the dummy law while maintaining element matching. Including positioning the dummy fill. For example, an integrated circuit can have element matching by having at least one point symmetry in which the integrated circuit has element matching symmetry. As another example, an integrated circuit can have device matching by having matching of repeating elements such as rows, columns, or arrays. Thus, positioning of the dummy filling includes positioning the dummy filling along at least one of the axial symmetry along which the element matching is axially symmetric, and repetitive element matching in which the element matching is repeated element matching. Positioning the dummy filling to maintain

  In order to limit the capacity increase due to the dummy filling, the present invention specifies a critical net that is only a subset of all nets of the integrated circuit as at least one net of the integrated circuit and corresponds to the specified critical net Determining the metal conductors from the layout file and depicting a net block removal zone extending for each identified metal conductor to a minimum net block distance (NBD) distance from the metal conductor. The step of positioning the dummy filling includes the step of arranging the dummy filling outside the net block removal zone.

  The critical net can be accepted as input from the output of the user or CAD device. Further, the method can comprise setting a minimum NBD. Alternatively, the method sets a minimum allowable capacity increase (preferably to a level that can ensure circuit functionality) and sets a minimum NBD that limits the minimum capacity increase to a maximum capacity increase that can be tolerated. Determining. The minimum NBD can be determined using capacity simulation software such as PASCAL ™ and / or RAPHAEL ™, and can preferably be performed by evaluating only the designated critical net.

  In general, metal conductors corresponding to at least one designated critical net are included in the net tracking and / or layout file, for example when the layout file is in GDS-II, the net connectivity information. Is determined by labeling using a layout file. Generally, the layout file including the net connectivity information is either an annotated GDSII format or LEF / DEF (library exchange format, design exchange format). Generally, at least the net block removal zone includes a block zone in a designated signal net layer that includes a corresponding metal conductor or other layer within the minimum distance of the NBD from the corresponding metal conductor. Further, the positioning of the dummy filling may include a dummy filling process based on a model or a law.

  A system for positioning a dummy filling in an integrated circuit manufacturing process generally accepts input of data including the layout of the integrated circuit and a dummy filling locator that positions the dummy filling according to the dummy law while maintaining element alignment with the integrated circuit. With the specifications.

  In order to further limit the increase in capacity due to the dummy filling, data that designates only a subset of all nets as designated critical nets, and a metal conductor identification processor that identifies metal conductors corresponding to each designated critical file from the layout file, A removal zone processor that describes a net block removal zone that extends the minimum distance of the NBD from the metal conductor of each identified metal conductor can also be accepted by input. The dummy fill locator positions the dummy fill outside the netblock removal zone, for example, according to a dummy rule provided by the user while maintaining device alignment, such as a device symmetrical to the axis of symmetry or a matched element.

  Computer-aided dummy fill positioning methods in integrated circuit manufacturing processes generally read a layout file that specifies the layout of an integrated circuit, and an integrated circuit where the critical net is the only subset of all nets of the integrated circuit. Designate at least one net of the circuit as a critical net and draw a metal conductor corresponding to the net block removal zone extending for the distance of the minimum net block distance from the metal conductor for each identified metal conductor And positioning the dummy filling outside the net blocking removal zone.

  A system for positioning dummy fillings in an integrated circuit manufacturing process generally accepts data specifying only a subset of all nets as designated critical nets by input, and identifies metal conductors corresponding to each designated critical file from a layout file. A metal conductor identification processor, a removal zone processor describing a net block removal zone extending to the minimum distance of the NBD from the metal conductor of each identified metal conductor, and a dummy emphasis according to a dummy rule provided by the user, for example, A dummy emphasis locator can be included located outside the removal zone.

  These and other features and advantages of the present invention will be presented in the following description and accompanying drawings that illustrate, by way of example, the principles of the invention.

  The present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings, in which components are identified by the same reference numerals.

(Description of specific examples)
Disclosed is a system and method for positioning a dummy metal fill while preventing interference with device matching and selective capacity limiting. The following description does this to enable those skilled in the art to make and use the invention. By way of example only, specific examples and applications are described and various modifications will be apparent to those skilled in the art. The general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is recognized to the greatest extent, including many alternatives, modifications, and equivalents consistent with the principles and features disclosed herein. For the purpose of clarity, technical material that is known in the technical scope related to the invention is not described in detail to avoid unnecessarily obscuring the invention.

  FIG. 1 is a partial cross-sectional view of an integrated circuit (IC) chip 100 having a plurality of metal layers 102 and 106-112. Note that layer 112 is typically a substrate. 2 is a partial plan view of the signal net layer 102 including the designated signal net 104. FIG. 3 is a partial plan view of the metal layers 106 and 108 which are the upper and lower layers of the designated signal net layer 102 including the designated signal net 104. It is.

  The designated critical signal net represented by the fixed biased original metal 104 is located in the designated signal net layer 102. The upper and lower metal layers 106 and 108 are the upper and lower layers of the designated signal net layer 102, respectively. Furthermore, the ground layers 110 and 112 are upper and lower ground planes, respectively. The floating dummy metal filling 114 is positioned not only on the upper and lower metal layers 106 and 108 but also on the signal net layer 102.

  In an IC chip, such as the IC chip 100 partially shown in FIG. 1, the overall net delay consists of transistor delay and interconnect RC delay. For short nets, the interconnect RC delay is almost negligible and mostly consists of transistor delays. On the other hand, for long nets, transistor delay is almost negligible and most consists of interconnect RC delay. Thus, the capacity increase due to the dummy metal fill 114 is typically only important for long timing critical nets. Thus, in general, limiting the increase in capacity within a predetermined range of the long timing critical net is sufficient to ensure the function of the circuit.

  For a given IC chip, any suitable number of long timing critical nets can be selected as the designated critical signal net. The increase in capacity resulting from the dummy metal filling of the designated critical net can be selectively limited within a predetermined range to ensure the function of the circuit according to the following more detailed description. In addition or alternatively, the dummy metal fill preferably maintains device matching in the circuits described in more detail in connection with FIGS. 4-6 below.

  In order to suppress the capacity increase caused by the dummy metal filling within a predetermined range, the capacity increase introduced by the dummy metal filling rapidly decreases as the distance from the dummy metal filling to the original metal line increases. However, the removal of the dummy metal filling is very time consuming and it is practically impossible to remove several thousand transistor IC chips even when the dummy metal filling is removed only for the critical net.

  Thus, as shown in FIG. 1, the floating dummy metal fill 114 blocks from presence within a minimum or net block or buffer distance (NBD) 116 from the fixed biased original metal 104 of the designated signal net. Or excluded. By maintaining the distance between the NBD and the dummy metal filling and the original metal 104, the critical net capacity increase due to the dummy metal filling 114 can be limited.

  As shown in FIGS. 1-3, the dummy filling 114 is blocked from within the NBD distance from the designated signal net 104 in the X, Y, and Z directions. In particular, the dummy metal filling 114 is blocked from the designated signal net 104 in the X direction of the designated signal net layer 102. It should be understood that when the designated signal net 104 extends the length of the designated signal net layer 102 in the Y direction, the dummy metal filler 114 is removed from the designated signal net 104 in the Y direction of the designated signal net layer 102. Being within the NBD distance is blocked. In addition, the presence of dummy metal fill 114 is also blocked within the distance from the NBD from the designated signal net 104 in the Z direction, ie, perpendicular to the layers 102, 106, 108 shown in FIG.

  In the particular example shown, only the upper and lower layers 106, 108 are within the NBD 104 distance from the designated signal net in the Z direction. Each of the upper and lower metal layers 106 and 108 has an NBD exclusion zone similar to the designated signal net layer 102 as shown in the plan view of FIG. Although not shown, it should be understood that there can be a dummy metal fill 114 within the NBD distance from the designated signal net 104 with zero or more layers above and below the designated signal net 102. Don't be. For example, if the NBD is sufficiently small, the dummy metal filling 114 is prevented from being present only within the NBD distance from the designated signal net 104 designated in the signal net layer 102 and does not occur for other layers. As another example, when the NBD distance is large, not only in the designated signal net layer 102 but also in an additional layer above and / or below the designated signal net layer 102, the dummy metal filling is added to the designated signal net 104. Is prevented from being within the NBD distance from. In general, the number of layers obstructed by the dummy metal filling is the same as above and below the designated signal net layer 102.

  The NBD removal zone generally refers to the minimum NBD distance from the designated signal net 104. For example, the NBD removal zone can be defined by drawing a virtual sphere omnidirectionally with the designated signal net 104 as the center. In other embodiments, the NBD removal zone can be defined by drawing a virtual shape that extends to the NBD distance from the designated signal net 104 in each of the X, Y, and Z directions. Typically, the designated signal net 104 is generally a right-angled polyhedron with six sides where the rectangular prism or NBD removal zone is also a rectangular polyhedron. It should be understood that there are other suitable ways of drawing the NBD removal zone.

  The NBD is preferably determined in such a way as to keep the increase in capacity to a predetermined amount in order to ensure the functionality of the circuit. Preferably, the computer automation process is utilized to determine the placement of the dummy metal filler so as to remove the dummy filler within the NBD distance from the critical net. The computer automation process will be described with reference to FIG.

  As known in the industry, the element matching characteristics include, for example, noise cancellation. Thus, positioning the floating dummy metal fill while maintaining element matching facilitates maintaining the device's symmetry characteristics. Blocking alignment is provided by providing device symmetry along at least one axis of symmetry and / or providing alignment of repetitively sliding elements. Device matching can also be done in rows, columns or arrays. Element matching by providing device symmetry along at least one axis of symmetry will be described below with reference to FIGS. 4 and 5, and element matching provided by repeatedly providing matched elements. This will be described below with reference to FIG.

  FIG. 4 is a partial cross-sectional view of another example of an IC chip 150 having a plurality of metal layers 152, 156-162 and element matching obtained by device symmetry along the symmetry axis 168. FIG. 5 is a partial plan view of a layer 152 that is a designated signal net including designated signal nets 154, 154 ′ that are symmetrical about an axis of symmetry 168. As can be clearly seen, the integrated circuit chip 150 can have element matching by having an axis of symmetry 168 where the integrated circuit has element matching.

  As shown in FIG. 4, layer 162 is typically a substrate. Although only two IC chip elements are shown to match along a single axis of symmetry, a chip with a blocking match typically matches in contrast to rows, columns, arrays, etc. The appropriate number of elements can be provided. The IC chip 150 having axisymmetric device matching along the symmetry axis is itself similar to the IC chip shown and described above in connection with FIGS. 1-3, but similar elements and ideas are for purposes of clarity. Therefore, it will not be described in detail again.

  The signal net represented by the original metal 154, 154 ′ with the fixed bias can be designated as the critical signal net, and the signal net layer including the designated critical net can be designated as the designated signal net layer 152. . The upper and lower metal layers 156 and 158 are the upper and lower layers of the designated signal net layer 152, respectively. Furthermore, the ground layers 160 and 162 are upper and lower ground layers, respectively.

  The floating dummy metal filling 164 can be positioned not only on the upper and lower metal layers 156 and 158 but also on the designated signal net layer 152 so that device symmetry along the symmetry axis 168 is maintained. As described above, the floating dummy metal fill 164 is prevented from being within the minimum net blocking or buffer distance (NBD) 166 from the fixed biased original metal 154, 154 'of the designated signal net. Or can be removed. Further, as shown in FIGS. 4 and 5, the floating dummy metal filling 164 can be positioned to be targeted along the symmetry axis of each layer 152, 156, 158.

  FIG. 6 shows another IC chip example, an IC chip 150 'having element matching by including matched elements 140A, 140B, 140C. Repeated aligned elements 140A, 140B, 140C can be provided in a row, column or array. The floating dummy fill 164 is positioned within the aligned elements 140A, 140B, 140C so as to maintain repetitive element alignment. In other words, the floating dummy metal fill is positioned so that the matched elements 140A, 140B, 140C have the same number and dummy metal fill positioning 164, thereby maintaining matching between repeating elements.

  Preferably, for a given IC chip with device alignment, the symmetry axis and / or the aligned device are specified to facilitate positioning of the dummy metal while maintaining alignment. To selectively remove dummy metal from within the NBD distance from the critical net, while maintaining element alignment by maintaining symmetry along the specified symmetry axis, or maintaining repeating elements, Use computer automated processes. The computer automated process will be described with reference to FIG.

  FIG. 7 is a flow diagram of a computer-automated process 130 that determines the placement of the dummy metal fill to facilitate maintaining and / or limiting device alignment. This step can be executed by only the element matching characteristic, the capacity increase limitation, or a combination of both. As described above, the dummy metal fill is utilized to promote the uniformity of the flatness profile by helping to average the characteristic density over the layout. To ensure the functionality of the circuit, the dummy metal filling is performed by computer-automated process 130 in order to maintain device matching and / or limit the increase in capacity due to the dummy metal filling within a predetermined range of the timing critical net. Position. In particular, step 130 maintains device alignment and / or blocks or removes dummy metal fill from a safe distance of the buffer from the critical net.

  In step 132, device alignment of the integrated circuit is determined. As described above, device matching can be provided by having at least one axis of symmetry in which the integrated circuit has symmetrically matched elements and / or having repeated elements such as rows, columns, arrays, etc. .

  If, at step 130, the dummy metal fill cannot be blocked or removed from within the buffer distance from the critical net to limit capacity increase, proceed to step 140, described below, as indicated by the dotted arrow 142.

  In addition, in order to suppress the increase in capacity, if the process 130 promotes the block or removal of the dummy metal filling from within the distance of the buffer from the critical net, the net specified by the critical net and the maximum allowable capacity or dummy The increase in delay due to metal filling is determined by the user and / or CAD tool, for example, at step 132.

  Next, in step 134, the computerized process determines a minimum safe value or buffer distance NBD that suppresses the increase in capacity or delay due to the dummy metal filling to the maximum value in step 132. In principle, this is done separately from this step-specified critical net. As is apparent from the above, this step 134 can be performed before or after step 132 or simultaneously. The minimum safe distance can be determined using PASCAL (trademark), 3D capacity simulator published by Samsung Co., Ltd., Seoul, Korea, and capacity simulation software of general-purpose commercial (COTS). For example, Jin-Kyu Park et al. "General method featuring interconnect capacitance considering floating dummy emphasis through the use of an effective field solution algorithm" Semiconductor process and device simulation (SISPAD 2000, pages 98-100, This book is hereby incorporated by reference in its entirety on September 7, 2000. Other suitable 3D capacity simulators such as RAPHAEL (trademark) published by AVANTI Co., Ltd. (Flemment, Calif.) May alternatively be used. Can be used.

  In step 136, the computer-automated process determines the metal conductor corresponding to the critical net designated in step 132. This step can be achieved, for example, by net tracking using an integrated circuit input layout file such as GDS-II format. Alternatively, step 136 can be performed by labeling using an annotated circuit layout using the annotated GDS-II format.

  In step 138, for each metal conductor identified in step 136, the computer automated process 130 draws the NBD removal zone in the metal conductor layer or layers above and below the designated signal net in the NBD removal zone. If the upper and lower layers of the designated signal net are in the NBD removal zone, the block area or zone in each such similar layer under the designated signal net layer has a dummy metal filling positioned on it. Be disturbed.

  In step 140, the positioning of the dummy metal fill is selectively determined according to the blocked area in step 138, maintaining device alignment. In other words, the positioning of the dummy metal filling is symmetric along the axis of symmetry and / or matches only between the repeating elements and optionally in the tolerance region outside the block region or zone. In order to obtain a desired flat profile, an appropriate dummy metal filling method such as a dummy filling process based on a law or a model can be performed.

  It should be understood that step 130 is not limited to the predetermined order of the various steps shown herein. Rather, the various steps of step 130 can be performed in other suitable ways.

  The system and method described herein for maintaining device alignment and limiting the increase in capacity due to dummy metal fills can be used for certain wafer processing operations such as CMP. However, it should be noted that these systems and methods can generally be utilized for proper wafer processing operations.

  FIG. 8 is a block diagram illustrating a system 170 that is used to perform the process of FIG. 7 and place dummy fillings in an integrated circuit manufacturing process. In particular, system 170 includes an input 172 that accepts: (A) Specification for device matching, i.e. (i) axis of symmetry in which the integrated circuit has symmetric device matching and / or (ii) repetitively matched elements, (b) at least one net of the integrated circuit is designated critical Input to specify as net, (c) input to set either maximum allowable capacity increase or minimum NBD due to dummy filling, (d) layout file specifying integrated circuit layout, (e) dummy law, and / or ( f) Interconnect configuration information often referred to as technical files. In principle, the layout file is in GDSII format or annotated GDSII format known in the industry. Each input is accepted via input 172, but it should be understood that the dummy law is stored in system 170, for example. Note that each input data is listed and shown as a split input, but any or all data is accepted at input 172 with the appropriate number of split inputs. For example, the layout file also includes element matching specifications.

  Also, in general, inputs (b), (c) only if the system 170 facilitates blocking or removing metal filling from within the distance of the buffer from the critical net to limit capacity increase. Note that it requires In such a case, the system 170 can include a capacity simulator 174 that determines the minimum block distance. The capacity simulator determines the minimum net block distance that limits the maximum capacity increase and sets the capacity as soon as possible. As described above, the capacity simulator can execute appropriate capacity simulation software such as PASCAL ™ and / or RAPHAEL ™. For a given process, if a minimum netblock distance is provided as an input to system 170, capacity simulator 174 is not required as part of system 170 and need not be utilized for a particular process.

  Moreover, the system 170 can include a metal conductor determination processor 176 that determines metal conductors corresponding to each designated critical net. Each metal conductor is disposed in a corresponding designated signal net layer. As such, the system 170 can include a removal zone processor 178 that can set a net block removal zone in a designated signal net layer and other layers within the block distance of the metal conductor.

  System 170 includes a dummy fill locator 180 that places dummy fill according to dummy laws. The dummy filling locator 180 maintains the element matching characteristics by arranging the dummy filling while maintaining the element matching. For example, the dummy fill locator 180 places the dummy fill symmetrically along a predetermined axis of symmetry so as to maintain alignment between the repeating elements. The dummy fill locator 180 also selectively places the dummy fill outside the net block removal zone that facilitates when the system 170 blocks or removes the dummy metal fill to further limit capacity increase.

  Although each component or processor is shown and described as a split processor, it should be noted that any number of processors may be utilized to perform the functions described herein.

  FIGS. 9 and 10 are schematic and block diagrams, respectively, of a general purpose computer system 1001 suitable for executing software programs that implement the methods and processes described herein. The structure and configuration of the computer system 1001 shown and described herein is merely illustrative, and other computer structures and configurations may also be utilized.

  An exemplary computer system 1001 includes a display 1003, a screen 1005, a main body 1007, a keyboard 1009, and a mouse 1011. Generally, body 1007 executes one or more drives for reading computer-readable storage medium 1015, system memory 1053, and data used in, for example, the methods and processes or software programs described herein. A hard drive 1055 is housed that can be used to store and / or retrieve software programs that incorporate computer code to perform. CD and floppy disk 1015 are examples of computer-readable storage media that can be read by a corresponding CD-ROM or CD-RW drive 1013. In general, a computer-readable medium refers to a data storage device capable of storing data readable by a computer system. Computer-readable media include hard disks, floppy (registered trademark) disks, magnetic media such as magnetic tape, optical media such as CD-ROM, magneto-optical media such as professional disks, and application specific integrated circuits (ASICs) Programmable logic devices (PLDs), specially configured hardware devices such as ROM and RAM devices are included.

  A computer-readable medium can also include a data signal represented as a carrier wave, such as a data signal represented as a carrier wave carried on a network. Such a network can be an intranet in a company or other environment, the Internet, or a network in which multiple computers are connected to store and execute computer-readable code in a distributed fashion.

  The computer system 1001 can include various subsystems including a microprocessor 1051 (also referred to as a CPU or central processing unit), a system memory 1053, a fixed storage device 1063 (such as a hard drive), and a removable storage device 1057. (Such as a CD-ROM drive), display adapter 1059, sound card 1061, converter 1063 (such as speakers and microphone), network interface 1065 and / or printer / fax / scanner interface 1067. Computer system 1001 can also include a system bus 1069. However, the particular bus shown is merely an example of a connection scheme that links various subsystems. For example, a local bus can be utilized to connect a central processor to system memory or a display adapter.

  The methods and steps described herein can be performed on a single CPU 1051 and / or with a remote CPU sharing part of the processing, such as the Internet, an intranet network or a LAN (local area network). Can run on the network.

  While the present invention has been described and illustrated with reference to a preferred embodiment thereof, it is to be understood that these are merely examples and modifications may be made without departing from the spirit and scope of the invention. it can. Thus, the present invention defines only the following claims.

FIG. 1 is a partial cross-sectional view of a circuit example having a multilayer metal layer. FIG. 2 is a partial plan view of the metal layer of FIG. 1 including designated signal nets. FIG. 3 is a partial plan view of the metal layer of the circuit of FIG. 1 with the upper and lower layers including designated signal nets. FIG. 4 is a partial cross-sectional view of another example of a circuit having a plurality of metal layers for achieving element matching by symmetrically providing devices along the axis of symmetry. FIG. 5 is a partial plan view of the metal augmentation of the circuit of FIG. 4 including the designated signal net. FIG. 6 shows another example of a circuit having device matching by including repeated layer matching. FIG. 7 is a flow diagram illustrating a computer-automated process for determining the positioning of the dummy metal fill in maintaining device matching and / or limiting the increase in capacity due to the increase in dummy metal fill. FIG. 8 is a diagram illustrating a system utilized to perform the process of FIG. 7 for positioning dummy fills in an integrated circuit manufacturing process. FIG. 9 is an illustration of an example computer system that can be utilized by various embodiments of the methods and processes described herein. FIG. 10 is a block diagram showing a system of the computer system of FIG.

Claims (43)

A method of automatically positioning a dummy filling by a computer in an integrated circuit manufacturing process,
Receiving the integrated circuit input layout and integrated circuit device matching specifications;
Locating the dummy filling on the integrated circuit according to the dummy filling law while maintaining device matching.   The device matching specification is selected from the group consisting of a specification for element matching of an integrated circuit by at least one axis of symmetry and matching by repeated elements of the integrated circuit. The method according to 1. Said step for positioning the dummy filling is:
The device matching specification shall include at least one axis of symmetry, positioning the dummy filling along at least one axis of symmetry;
The device matching specification includes a specification for matching by repetitive elements of an integrated circuit, and comprises positioning a dummy fill so as to maintain matching of the repetitive elements. Method. The step includes at least one net of an integrated circuit as a critical net, and at least one critical net includes only a subnet of all nets of the integrated circuit; and
Determining a metal conductor corresponding to each critical net specified from the layout file, and describing, for each determined metal conductor, a net block removal zone extending to a distance of the minimum net block distance from the metal conductor. ,
The method of claim 1, wherein positioning the dummy fill further comprises positioning the dummy fill outside the net block removal zone. Positioning the dummy filling in the integrated circuit,
Reading a layout file that identifies the layout of the integrated circuit;
Designating at least one net of the integrated circuit as a critical net, wherein the at least one critical net comprises only a subnet of all nets of the integrated circuit;
Determining the metal conductor corresponding to each critical net specified from the layout file;
For each identified metal conductor, comprising drawing a net block removal zone extending to the distance of the minimum net block distance from the metal conductor,
The computer automated method, wherein positioning the dummy fill further comprises positioning the dummy fill outside the net block removal zone.   6. The method of claim 4 or 5, further comprising receiving a critical net input for at least one designated critical net, wherein the received input is an output from a user or a CAD tool. The method according to any one.   6. The method according to claim 4, further comprising receiving the minimum net block distance as input from one of a user input and a software program output.   6. The method of claim 4 or 5, further comprising setting a minimum net block distance. Receiving a maximum allowed capacity increase;
6. The method of claim 4 or 5, further comprising determining a minimum netblock distance that limits a maximum capacity increase to a set maximum allowable increase.   The method of claim 9, wherein the determination of the minimum net block distance includes the use of capacity simulation software.   11. The method of claim 10, wherein the capacity simulation software is one of PASAL (TM) or RAPHAEL (TM).   The method of claim 9, wherein the determination of the minimum net block distance is only to evaluate at least one designated critical net.   6. The method according to claim 4, wherein the determination includes determining all metal conductors corresponding to at least one designated critical net.   6. A method according to claim 4 or 5, wherein the determination includes net tracking or labeling using a layout file.   15. The method of claim 14, wherein the determining includes net tracking where the layout file is in GDS-II format and labeling where the layout file includes net connectivity information.   15. The method of claim 14, wherein if the layout file includes net connectivity information, the layout file is one of an annotated GDS-II format or a LEF / DEF format.   The block exclusion zone includes a designated signal net layer including a corresponding metal conductor and at least one blocked zone in another layer within a distance of a minimum net block distance from the corresponding metal conductor. The method according to claim 4 or 5.   6. The method according to claim 4, wherein the positioning of the dummy filling includes using at least one of a dummy filling process based on a model or a dummy filling process based on a law. A system for positioning dummy fillers in an integrated circuit manufacturing process,
Data reception input including integrated circuit layout and integrated circuit matching device specifications; and
A system comprising a dummy fill locator that positions a dummy fill on an integrated circuit according to a dummy law while maintaining device matching.   20. The element matching specification is selected from a group comprising at least one axis of symmetry specification in which the integrated circuit has element matching and a repeated matching element specification of the integrated circuit. system.   The dummy fill locator positions the dummy fill along at least one symmetry axis according to an element matching specification where the element matching specification includes at least one symmetry axis specification, and the element matching specification repeats for the integrated circuit. 21. The system of claim 20, wherein device alignment is maintained by positioning the dummy fill to maintain repetitive element alignment, including the use of element alignment. The input data designates at least one net of the integrated circuit as a designated critical net, and at least one critical net has only subnets equal to or less than the total number of nets of the integrated circuit, and
A metal conductor determination processor for determining a metal conductor corresponding to each designated critical net from the layout file;
A removal zone processor for drawing a net block removal zone extending for a distance of a minimum net block distance from the metal conductor for each identified metal conductor;
20. The system of claim 19, further comprising a dummy fill locator that positions the dummy fill outside the netblock removal zone according to a dummy law. A system for positioning dummy fillings in an integrated circuit manufacturing process,
Including a layout file identifying the layout of the integrated circuit and receiving data designating at least one net of the integrated circuit as a designated critical net, wherein the at least one critical net includes only one subnet or all nets of the integrated circuit; Inputs that are provided, and
A metal conductor determination processor for determining a metal conductor corresponding to each designated critical net from the layout file; and
A removal zone processor for drawing a net block removal zone for the metal conductor, extending the minimum net block distance from the metal conductor;
And a dummy filling locator for positioning the dummy filling outside the net block removal zone according to a dummy law.   24. A system according to claim 22 or 23, wherein the critical net input is from one of a user and a CAD tool.   24. The system according to claim 22, wherein the input further accepts a minimum net block distance as an input. The input further accepts the maximum capacity increase as input, and the system further
The system according to claim 22 or 23, wherein a minimum net block distance is determined, and the minimum net block distance is limited to a maximum capacity that has received an increase in maximum capacity.   27. The system of claim 26, wherein the maximum capacity increase input is a capacity increase that ensures the functionality of the integrated circuit.   27. The system of claim 26, wherein the minimum net block distance processor comprises capacity simulation software that determines a minimum net block distance.   29. The system of claim 28, wherein the capacity simulation software is one of PASCAL (TM) and RAPHAEL (TM).   27. The system of claim 26, wherein the minimum net block distance processor evaluates only at least one designated critical net.   24. The system according to claim 22, wherein the metal conductor determination processor determines all metal conductors corresponding to at least one critical net.   24. A system according to claim 22 or 23, wherein the metal conductor discrimination processor performs one of tracking and labeling using a layout file.   The metal conductor discrimination processor performs net tracking where the layout file is in GDS-II format, and the metal conductor discrimination processor performs labeling where the layout file is one of annotated GDS-II format and LEF / DEF. 33. The system of claim 32, wherein the system is performed.   The removal zone processor draws a net block removal zone so that at least the blocked zone is placed on a signal net layer that includes a corresponding metal conductor and other layers that are within a distance of the net block distance from the corresponding metal conductor. 24. A system according to any of claims 22 or 23, comprising:   24. The system of claim 22 or 23, wherein the metal filler locator is at least one of a dummy filler locator based on a model and a dummy filler locator based on a law. Multiple element matching layouts;
An integrated circuit comprising a plurality of dummy fills positioned in such a way as to maintain device alignment.   Device matching is provided by having at least one of device symmetry along at least one axis of symmetry, device symmetry with repeated element matching, row symmetry, column symmetry, and array symmetry. 37. The integrated circuit according to claim 36. The dummy fill is positioned along at least one symmetry axis, including the element alignment having at least one symmetry axis;
38. The integrated circuit of claim 37, wherein the dummy fill is positioned to maintain repetitive element alignment, including device alignment having repetitive element alignment. At least one signal net is designated as a critical signal net, the remaining signal nets are non-critical signal nets, and at least one critical signal net comprises all sub-integrated circuit subnets, each critical net associated with it Having a metal conductor,
A dummy filling is located outside the deblocking zone that extends the distance of the minimum net block distance from the metal conductor associated with each critical signal net;
37. The integrated circuit of claim 36, wherein at least some dummy fills are located within a minimum net block distance from a metal conductor associated with the non-critical signal net. At least one is designated as a critical signal net, the rest are non-critical signal nets, at least one critical signal net has fewer subnets than all signal nets in the integrated circuit, and each critical net has a metal conductor associated with it Multiple signal nets,
A dummy fill is located outside the net block removal zone that extends the minimum block distance distance from the metal conductor associated with each critical net, and at least some dummy fills are associated with the critical signal net. An integrated circuit comprising a dummy fill positioned within a minimum block distance from a metal conductor.   41. An integrated circuit according to claim 39 or 40, wherein the minimum net block distance depends only on at least one designated critical net.   The net block removal zone is in each designated signal net layer that includes a corresponding metal conductor associated with at least one critical signal net, or in other layers that are within a distance of the net block distance from the corresponding metal conductor. 41. The integrated circuit of claim 39 or 40, comprising at least one blocked zone.   41. The integrated circuit according to claim 39, wherein the dummy filling is positioned according to one of a dummy filling process based on a model or a dummy filling process based on a law.

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