JP2005353837A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2005353837A
JP2005353837A JP2004172861A JP2004172861A JP2005353837A JP 2005353837 A JP2005353837 A JP 2005353837A JP 2004172861 A JP2004172861 A JP 2004172861A JP 2004172861 A JP2004172861 A JP 2004172861A JP 2005353837 A JP2005353837 A JP 2005353837A
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insulating layer
semiconductor chip
layer
semiconductor device
electrode pad
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Toshio Kobayashi
敏男 小林
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To mount a semiconductor chip with high precision. <P>SOLUTION: In a semiconductor device 10, a semiconductor chip 12 is embedded between a first insulating layer 18 and a second insulating layer 20 which form an insulating layer 14, and a wiring pattern 24 formed on the first insulating layer 18 is directly connected to electrode pads 22 of the semiconductor chip 12. In the wiring pattern 24, a zincate treatment is performed to surfaces of the electrode pads 22 of the semiconductor chip 12, connection electrodes 23 are formed, a seed layer 28 is formed on a Pb containing resin layer 26 by electroless plating, and a re-wiring 30 is formed on the seed layer 28 by electrolytic solder plating. Furthermore, a third insulating layer 32 like solder resist is laminated so as to cover the re-wiring 30, a bump 34 is inserted and formed in a pierced hole 32a which is formed in the third insulating layer 32 so as to be continuously connected to the re-wiring 30, and the bump is connected to the re-wiring 30. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は半導体装置及びその製造方法に係り、特に半導体チップを高精度に実装するように構成された半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device configured to mount a semiconductor chip with high accuracy and a manufacturing method thereof.

近年、ＬＳＩ技術は、データ伝送の高速化、大容量化に伴い実装技術の高密度化が進められている。このような要望に応じるため、絶縁層に貼り付けた半導体チップ上に絶縁層と配線層とを積層して半導体チップを絶縁層間に埋め込むように構成することにより高密度に実装するパッケージ方法が研究されている。このようなパッケージ方法としては、例えば、基板に半導体チップの裏面を接着（ダイボンディング）し、半導体チップの電極パッドに接続される導体配線パターン及びスタッドビアを有する絶縁層とをビルドアップ法により積層する方法がある（例えば、特許文献１参照）。   In recent years, in LSI technology, as the speed of data transmission increases and the capacity increases, the density of packaging technology has been increased. To meet these demands, research has been conducted on a packaging method for mounting at a high density by stacking an insulating layer and a wiring layer on a semiconductor chip attached to an insulating layer and embedding the semiconductor chip between insulating layers. Has been. As such a packaging method, for example, a back surface of a semiconductor chip is bonded (die bonding) to a substrate, and a conductive wiring pattern connected to an electrode pad of the semiconductor chip and an insulating layer having a stud via are stacked by a build-up method. (For example, refer to Patent Document 1).

また、半導体チップをベース上に接着し、半導体チップ上に再配線やスタッドビアを形成して半導体チップ上を封止膜で覆い、さらに、封止膜上に上層絶縁膜や上層再配線を形成する方法がある（例えば、特許文献２参照）。
特開２００２−１６１７３号公報 特開２００４−７１９９８号公報 In addition, the semiconductor chip is bonded onto the base, rewiring and stud vias are formed on the semiconductor chip, the semiconductor chip is covered with a sealing film, and an upper insulating film and upper rewiring are formed on the sealing film. (For example, refer to Patent Document 2).
JP 2002-16173 A JP 2004-71998 A

しかしながら、上記特許文献１に記載された製造方法では、基板の凹部に半導体チップを挿入して貼り付けるため、半導体チップを所定の貼り付け位置に搬送する工程において、例えば、一辺が１４ｍｍの半導体チップを一辺が１５ｍｍの凹部の輪郭形状に対して半導体チップの４辺の位置を規定するようにして位置合わせを行うことになる。   However, in the manufacturing method described in Patent Document 1, in order to insert a semiconductor chip into a concave portion of a substrate and paste it, in the step of transporting the semiconductor chip to a predetermined bonding position, for example, a semiconductor chip with a side of 14 mm Is aligned so as to define the positions of the four sides of the semiconductor chip with respect to the contour shape of the recess having a side of 15 mm.

ところが、この製造方法では、パターニングの精度が±１μｍ程度であるのに対してダイシングにより切り取られた半導体チップの４辺の加工精度が±１０μｍ程度であるので、半導体チップを基板に貼り付ける際は、半導体チップの加工精度によって半導体チップの電極パッド（例えば、一辺が５０μｍ〜７０μｍ程度の四角形）の位置が基板上のビアホールの位置に対してずれることになるため、ビアホールを大径（例えば、電極パッドの４倍程度の直径）にしてスタッドビアと半導体チップの電極パッドとの接続を確保していた。このように、ビアホールの大径化に伴ってスタッドビアの間隔を広くしなければならないので、その分ＩＣパッケージの小型化を図ることが難しかった。   However, in this manufacturing method, the patterning accuracy is about ± 1 μm, whereas the processing accuracy of the four sides of the semiconductor chip cut by dicing is about ± 10 μm. Therefore, when the semiconductor chip is attached to the substrate, Depending on the processing accuracy of the semiconductor chip, the position of the electrode pad of the semiconductor chip (for example, a square having a side of about 50 μm to 70 μm) is shifted from the position of the via hole on the substrate. The connection between the stud via and the electrode pad of the semiconductor chip was ensured. As described above, since the distance between the stud vias must be increased as the via hole diameter increases, it is difficult to reduce the size of the IC package.

また、上記特許文献２に記載された製造方法では、シリコン基板上に接続パッド及び絶縁膜を形成し、さらに再配線及びスタッドビア、封止膜を形成したウエハレベルパッケージの半導体構成体をベース上に貼り付け、さらに２層に分けて形成された上層配線層を絶縁層間に形成し、複数の配線層の組み合わせによりバンプの間隔を広げていた。そのため、この製造方法では、ウエハレベルでシリコン基板上に接続パッド、再配線、スタッドビアを形成することにより各層の位置精度を高められる反面、半導体チップをウエハレベルパッケージにしてからベース上に配線層や絶縁層をビルドアップ法により形成することになり、製造コストが高価になるという問題があった。   In the manufacturing method described in Patent Document 2, a semiconductor structure of a wafer level package in which a connection pad and an insulating film are formed on a silicon substrate, and further, a rewiring, a stud via, and a sealing film are formed on the base. The upper wiring layer formed in two layers is formed between the insulating layers, and the interval between the bumps is widened by combining a plurality of wiring layers. For this reason, this manufacturing method can improve the positional accuracy of each layer by forming connection pads, rewiring, and stud vias on the silicon substrate at the wafer level. In other words, the insulating layer is formed by a build-up method, resulting in a high manufacturing cost.

そこで、本発明は上記課題を解決した半導体装置及びその製造方法を提供することを目的とする。   In view of the above, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that solve the above problems.

本発明は上記課題を解決するため、以下のような特徴を有する。   In order to solve the above problems, the present invention has the following features.

請求項１記載の発明は、支持板の表面に第１絶縁層を積層する第１工程と、前記第１絶縁層に半導体チップの電極パッドと接続するための孔を加工する第２工程と、前記孔に前記半導体チップの電極パッドを一致させるように位置合わせを行って前記半導体チップを前記第１絶縁層の表面に貼り付ける第３工程と、前記半導体チップを被覆するように第２絶縁層を前記第１絶縁層に積層する第４工程と、前記支持板を前記第１絶縁層から除去する第５工程と、を有することを特徴とする。   The invention according to claim 1 is a first step of laminating a first insulating layer on a surface of a support plate, a second step of processing a hole for connecting to an electrode pad of a semiconductor chip in the first insulating layer, A third step of aligning the electrode pads of the semiconductor chip with the holes and attaching the semiconductor chip to the surface of the first insulating layer; and a second insulating layer so as to cover the semiconductor chip A fourth step of laminating the first insulating layer on the first insulating layer, and a fifth step of removing the support plate from the first insulating layer.

請求項２記載の発明は、前記第２工程が、レーザ加工により前記孔を形成することを特徴とする。   The invention described in claim 2 is characterized in that the second step forms the hole by laser processing.

請求項３記載の発明は、前記第３工程が、前記半導体チップの回路形成面に対する電極パッドの位置を検出する工程と、前記半導体チップの電極パッドの位置を前記孔の位置に一致させるように前記半導体チップを搬送する工程と、前記半導体チップの回路形成面を前記第１絶縁層の表面に貼り付ける工程と、を有することを特徴とする。   According to a third aspect of the present invention, in the third step, the step of detecting the position of the electrode pad with respect to the circuit forming surface of the semiconductor chip and the position of the electrode pad of the semiconductor chip are made to coincide with the position of the hole. The method includes transporting the semiconductor chip and attaching a circuit forming surface of the semiconductor chip to the surface of the first insulating layer.

請求項４記載の発明は、請求項１に記載の半導体装置の製造方法であって、前記孔を介して前記半導体チップの電極パッドに接続される配線パターンを前記第１絶縁層の外面に形成する第６工程を有し、前記第６工程は、前記半導体チップの電極パッドの表面に接続電極を形成し、その後前記第１絶縁層の外面にシード層を形成し、次いで前記シード層の表面に電解めっきにより導体層を積層し、続いて、パターニング及びエッチングにより前記シード層及び前記導体層を所定形状の配線パターンとすることを特徴とする。   According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, a wiring pattern connected to the electrode pad of the semiconductor chip through the hole is formed on the outer surface of the first insulating layer. A sixth step of forming a connection electrode on the surface of the electrode pad of the semiconductor chip, and then forming a seed layer on the outer surface of the first insulating layer, and then the surface of the seed layer. The conductive layer is laminated by electrolytic plating, and then the seed layer and the conductive layer are formed into a predetermined wiring pattern by patterning and etching.

請求項５記載の発明は、半導体チップを封止する絶縁層と該絶縁層の外面に形成された配線層とを有する半導体装置であって、前記絶縁層を成す第１絶縁層と第２絶縁層との間に半導体チップを埋め込むように構成し、前記半導体チップの電極パッドに前記第１絶縁層の外面に形成される配線パターンを直接接続することを特徴とする。   According to a fifth aspect of the present invention, there is provided a semiconductor device having an insulating layer for sealing a semiconductor chip and a wiring layer formed on an outer surface of the insulating layer, the first insulating layer and the second insulating layer forming the insulating layer. A semiconductor chip is embedded between the semiconductor chip and a wiring pattern formed on the outer surface of the first insulating layer is directly connected to the electrode pad of the semiconductor chip.

本発明によれば、第１絶縁層に半導体チップの電極パッドと接続するための孔を加工し、孔に半導体チップの電極パッドを一致させるように位置合わせを行って半導体チップを第１絶縁層の表面に貼り付けることにより、半導体チップの電極パッドと孔内に形成されるスタッドビアとの接続を高精度に行うことが可能になり、その分小型化を図れると共に、ウエハレベルの再配線を行わないベアチップを使用してチップ搭載精度の高精度化を図れるので、製造コストを安価に抑えることができる。   According to the present invention, a hole for connecting to an electrode pad of a semiconductor chip is processed in the first insulating layer, and alignment is performed so that the electrode pad of the semiconductor chip is aligned with the hole. By attaching to the surface of the semiconductor chip, it becomes possible to connect the electrode pads of the semiconductor chip and the stud vias formed in the holes with high accuracy, thereby reducing the size and rewiring at the wafer level. Since the bare chip can be used to improve the chip mounting accuracy, the manufacturing cost can be reduced.

また、第１絶縁層と第２絶縁層との間に半導体チップを埋め込むように構成し、半導体チップの電極パッドに第１絶縁層に形成される配線パターンを直接接続することにより、配線長を短くできると共に、配線層及び絶縁層を何層も積層する必要がないので、薄型化を図ることができる。   Further, the semiconductor chip is embedded between the first insulating layer and the second insulating layer, and the wiring pattern formed on the first insulating layer is directly connected to the electrode pad of the semiconductor chip, thereby reducing the wiring length. It can be shortened, and it is not necessary to stack a number of wiring layers and insulating layers, so that the thickness can be reduced.

以下、図面と共に本発明の一実施例について説明する。   Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

図１は本発明になる半導体装置の一実施例を示す縦断面図である。図２乃至図１３は本発明になる半導体装置の製造方法の工程を順に示す縦断面図である。   FIG. 1 is a longitudinal sectional view showing an embodiment of a semiconductor device according to the present invention. 2 to 13 are longitudinal sectional views sequentially showing the steps of the semiconductor device manufacturing method according to the present invention.

図１に示されるように、半導体装置１０は、半導体チップ１２に絶縁層１４と配線層１６とが積層されており、絶縁層１４を成す第１絶縁層１８と第２絶縁層２０との間に半導体チップ１２を埋め込むように構成し、半導体チップ１２の電極パッド２２に第１絶縁層１８に形成される配線パターン２４を直接接続するように構成されている。   As shown in FIG. 1, the semiconductor device 10 includes a semiconductor chip 12 in which an insulating layer 14 and a wiring layer 16 are stacked. The semiconductor chip 12 is embedded, and the wiring pattern 24 formed on the first insulating layer 18 is directly connected to the electrode pad 22 of the semiconductor chip 12.

また、配線パターン２４は、半導体チップ１２の電極パッド２２の表面にジンケート処理を施して接続電極２３を形成した後、Pb（パラジウム）含有樹脂層２６に無電解めっきによりシード層２８を形成し、シード層２８に再配線３０を電解めっきにより形成したものである。そして、再配線３０を覆うようにソルダレジストなどの第３絶縁層３２が積層されており、再配線３０に連通するように第３絶縁層３２に形成された貫通孔３２ａ（再配線３０のランド部を露出するための孔）にはバンプ３４が挿入されるように形成され、再配線３０と接続されている。複数のバンプ３４は、再配線３０の延在位置（ランド部）に対応するように配置されており、互いに干渉しないように所定間隔おきに配置される。   Further, the wiring pattern 24 is formed by subjecting the surface of the electrode pad 22 of the semiconductor chip 12 to a zincate process to form the connection electrode 23, and then forming a seed layer 28 on the Pb (palladium) -containing resin layer 26 by electroless plating, A rewiring 30 is formed on the seed layer 28 by electrolytic plating. A third insulating layer 32 such as a solder resist is laminated so as to cover the rewiring 30, and a through hole 32 a (land of the rewiring 30 is formed in the third insulating layer 32 so as to communicate with the rewiring 30. Bumps 34 are formed so that the bumps 34 are inserted into the holes) and are connected to the rewiring 30. The plurality of bumps 34 are arranged so as to correspond to the extended positions (land portions) of the rewiring 30 and are arranged at predetermined intervals so as not to interfere with each other.

このように、半導体装置１０は、半導体チップ１２の電極パッド２２に第１絶縁層１８に形成される配線パターン２４を直接接続する構成とすることにより、従来のように配線層及び絶縁層を何層も積層する必要がないので、薄型化を図ることが可能になる。また、第１絶縁層１８を貫通するシード層２８のスタッドビア２８ａは、高精度に位置合わせされて電極パッド２２に接続されるため、配線パターン２４の配線長を短くできると共に、従来のものよりも小径化されており、その分配線のためのスペースを小さくして半導体装置１０の小型化を図ることが可能になる。   As described above, the semiconductor device 10 has a configuration in which the wiring pattern 24 formed in the first insulating layer 18 is directly connected to the electrode pad 22 of the semiconductor chip 12, so that the wiring layer and the insulating layer can be arranged as in the related art. Since it is not necessary to stack layers, it is possible to reduce the thickness. In addition, since the stud via 28a of the seed layer 28 penetrating the first insulating layer 18 is aligned with high precision and connected to the electrode pad 22, the wiring length of the wiring pattern 24 can be shortened and moreover than the conventional one. The size of the semiconductor device 10 can be reduced by reducing the space for wiring accordingly.

ここで、上記のように構成された半導体装置１０の製造方法の各工程について図２乃至図１３を参照して説明する。   Here, each process of the manufacturing method of the semiconductor device 10 configured as described above will be described with reference to FIGS.

図２に示す工程１では、捨て板となる支持板４０上にビルドアップ樹脂をラミネートして第１絶縁層１８を形成する。支持板４０は、第１絶縁層１８を支持するのに必要な強度を有すると共に、後述する工程で除去されるため、例えば、シリコン（Si）または銅板（Cu）またはガラスエポキシ板に銅を被覆したもの等により形成される。また、第１絶縁層１８は、熱硬化性フィルム（例えば、エポキシ系樹脂）をラミネートして形成される。尚、第１絶縁層１８に用いられる熱硬化性フィルムは、レーザ加工性に優れている。   In step 1 shown in FIG. 2, the first insulating layer 18 is formed by laminating a buildup resin on the support plate 40 serving as a discard plate. The support plate 40 has a strength necessary to support the first insulating layer 18 and is removed in a process described later. For example, a silicon (Si), a copper plate (Cu), or a glass epoxy plate is covered with copper. It is formed by what did. The first insulating layer 18 is formed by laminating a thermosetting film (for example, epoxy resin). The thermosetting film used for the first insulating layer 18 is excellent in laser processability.

図３に示す工程２では、レーザ加工機（図示せず）により第１絶縁層１８にビアホール（孔）１８ａを加工する。このビアホール１８ａは、予め設定された半導体チップ１２の電極パッド２２の位置に対応する座標位置に設けられる。尚、ビアホール１８ａの加工位置は、レーザ加工機の加工精度によって高精度に位置出しされている。   In step 2 shown in FIG. 3, a via hole (hole) 18 a is processed in the first insulating layer 18 by a laser processing machine (not shown). The via hole 18a is provided at a coordinate position corresponding to the position of the electrode pad 22 of the semiconductor chip 12 set in advance. The processing position of the via hole 18a is positioned with high accuracy according to the processing accuracy of the laser processing machine.

第１絶縁層１８は、熱硬化性樹脂であるので、レーザ光の照射により加熱された部分に微小なビアホール１８ａが貫通される。その際、ビアホール１８ａを加工するレーザ光は、ビアホール１８ａが貫通されると支持板４０の表面にも照射されるが、後の工程で支持板４０を削除するため、支持板４０の損傷は問題にならない。また、レーザ加工機によるビア加工は、レーザ光のエネルギの制御やマスクを使用して複数の孔を同時加工できるので、半導体チップ１２の配置数に応じて多数のビアホール１８ａを形成する場合でもビア加工を短時間で行える。   Since the first insulating layer 18 is a thermosetting resin, a minute via hole 18a penetrates a portion heated by laser light irradiation. At this time, the laser beam for processing the via hole 18a is also irradiated to the surface of the support plate 40 when the via hole 18a is penetrated. However, the support plate 40 is deleted in a later process, so that damage to the support plate 40 is a problem. do not become. In addition, via processing by a laser processing machine can simultaneously process a plurality of holes using laser light energy control and a mask, so even when a large number of via holes 18a are formed according to the number of semiconductor chips 12 arranged. Processing can be done in a short time.

尚、ビアホール１８ａの加工方法としては、レーザ加工以外の方法（例えば、フォトリソグラフィ法に基づいて露光、現像することにより孔を形成する方法）を用いることも可能である。   As a method for processing the via hole 18a, a method other than laser processing (for example, a method of forming a hole by exposure and development based on a photolithography method) can be used.

図４に示す工程３では、ベアチップからなる半導体チップ１２の回路形成面１２ａを下にしたフェイスダウンにより半導体チップ１２を第１絶縁層１８の表面に貼り付ける。その際、チップ実装装置（図示せず）により搬送される半導体チップ１２の電極パッド２２をビアホール１８ａに一致させるように位置合わせを行って半導体チップ１２を第１絶縁層１８に押し付ける。このように、前工程で高精度に形成された半導体チップ１２の電極パッド２２と、レーザ加工機により高精度に形成されたビアホール１８ａとの位置合わせにより、従来のように半導体チップ１２の輪郭を基準に位置合わせを行う場合よりも正確に位置合わせすることが可能になる。   In step 3 shown in FIG. 4, the semiconductor chip 12 is attached to the surface of the first insulating layer 18 by face-down with the circuit formation surface 12 a of the semiconductor chip 12 made of a bare chip down. At that time, the semiconductor chip 12 is pressed against the first insulating layer 18 by aligning the electrode pads 22 of the semiconductor chip 12 conveyed by a chip mounting apparatus (not shown) so as to coincide with the via holes 18a. Thus, by aligning the electrode pad 22 of the semiconductor chip 12 formed with high precision in the previous process with the via hole 18a formed with high precision by the laser processing machine, the outline of the semiconductor chip 12 can be made as in the past. It becomes possible to perform the alignment more accurately than the case where the alignment is performed based on the reference.

尚、位置合わせの方法としては、例えば、ＣＣＤイメージセンサ（図示せず）により半導体チップ１２の電極パッド２２の位置を検出して電極パッド２２とビアホール１８ａの位置を一致させるか、あるいは支持板４０をシリコンで形成した場合には、支持板４０の下方からＣＣＤイメージセンサ（図示せず）により電極パッド２２がビアホール１８ａと重なる位置に位置合わせしても良い。あるいは、半導体チップ１２の背面及び第１絶縁層１８上にアライメントマークを設けることにより、上方からＣＣＤイメージセンサ（図示せず）によりアライメントマークの位置合わせを行うことも可能である。   As a positioning method, for example, the position of the electrode pad 22 of the semiconductor chip 12 is detected by a CCD image sensor (not shown) and the positions of the electrode pad 22 and the via hole 18a are matched, or the support plate 40 is used. If the electrode pad 22 is formed of silicon, the electrode pad 22 may be aligned with the via hole 18a from below the support plate 40 by a CCD image sensor (not shown). Alternatively, alignment marks can be aligned from above by a CCD image sensor (not shown) by providing alignment marks on the back surface of the semiconductor chip 12 and on the first insulating layer 18.

また、半導体チップ１２を第１絶縁層１８に貼り付ける方法としては、接着剤あるいは粘着性を有する接着シートを介して第１絶縁層１８の表面に固着する方法がある。   In addition, as a method for attaching the semiconductor chip 12 to the first insulating layer 18, there is a method in which the semiconductor chip 12 is fixed to the surface of the first insulating layer 18 through an adhesive or a sticky adhesive sheet.

尚、本実施例では、第１絶縁層１８に対して２個の半導体チップ１２を貼り付けた状態を図示しているが、実際には２個以上の半導体チップ１２が貼り付けられるようになっており、説明の便宜上、このように図示している。また、図５乃至図１３においても、便宜上、第１絶縁層１８に２個の半導体チップ１２を貼り付けた状態を図示して説明する。   In the present embodiment, the state in which two semiconductor chips 12 are attached to the first insulating layer 18 is illustrated, but in reality, two or more semiconductor chips 12 are attached. For convenience of explanation, this is illustrated. 5 to 13, for convenience, the state in which the two semiconductor chips 12 are attached to the first insulating layer 18 will be illustrated and described.

図５に示す工程４では、第１絶縁層１８及び半導体チップ１２の表面にビルドアップ樹脂からなる第２絶縁層２０を形成する。第２絶縁層２０は、熱硬化性フィルム（例えば、エポキシ系樹脂）をラミネートして形成される。これにより、半導体チップ１２は、積層された絶縁層１８と２０との間に挟持される。   In step 4 shown in FIG. 5, the second insulating layer 20 made of buildup resin is formed on the surfaces of the first insulating layer 18 and the semiconductor chip 12. The second insulating layer 20 is formed by laminating a thermosetting film (for example, an epoxy resin). Thereby, the semiconductor chip 12 is sandwiched between the laminated insulating layers 18 and 20.

また、第１絶縁層１８上に載置された半導体チップ１２の表面に第２絶縁層２０を隙間無く密着させるため、真空ラミネーション法を用いる。そして、絶縁層１８，２０は、加熱により硬化して半導体チップ１２を絶縁層１４の内部に埋め込む。   Further, a vacuum lamination method is used in order to bring the second insulating layer 20 into close contact with the surface of the semiconductor chip 12 placed on the first insulating layer 18 without any gap. Then, the insulating layers 18 and 20 are cured by heating to embed the semiconductor chip 12 in the insulating layer 14.

図６に示す工程５では、支持板４０を第１絶縁層１８から分離させて除去する。支持板４０は、銅板により形成されている場合にはエッチングにより除去され、シリコンにより形成されている場合には、例えば、フッ酸(HF)を用いたウエットエッチング、あるいはバックグラインドにより削除される。   In step 5 shown in FIG. 6, the support plate 40 is separated from the first insulating layer 18 and removed. If the support plate 40 is formed of a copper plate, the support plate 40 is removed by etching. If the support plate 40 is formed of silicon, the support plate 40 is removed by wet etching using hydrofluoric acid (HF) or back grinding, for example.

続いて、電極パッド２２がアルミまたはアルミ合金からなる場合、シード層としてニッケル−リン（NiP）層を無電解めっきで形成する際の前処理液やめっき液により電極パッド２２が腐食しやすい。そのため、電極パッド２２のアルミ表面に接続電極２３を形成して被覆する。   Subsequently, when the electrode pad 22 is made of aluminum or an aluminum alloy, the electrode pad 22 is easily corroded by a pretreatment liquid or a plating liquid when a nickel-phosphorous (NiP) layer is formed as a seed layer by electroless plating. Therefore, the connection electrode 23 is formed and covered on the aluminum surface of the electrode pad 22.

この工程では、前処理として、電極パッド２２上に無電解めっきが施されるように電極パッド２２のアルミ表面に対してジンケート処理（Zincate treatment:亜鉛置換）を行う。このジンケート処理は、(a)電極パッド２２のアルミ表面を洗浄、(b)エッチングによりアルミ表面の酸化膜を除去、(c)アルミ表面に第１亜鉛置換膜（厚く、粗い置換膜）を形成、(d) 第１亜鉛置換膜を剥離、(e) アルミ表面に第２亜鉛置換膜（薄く、緻密な置換膜）を形成、の手順で行われる。続いて、無電解Ｎｉめっきにより電極パッド２２上にニッケル−リン（NiP）層を成膜して膜厚が５〜１０μｍの接続電極２３をＵＢＭ（Under Barrier Metal）として形成する。尚、このジンケート処理及び接続電極２３を形成する工程は、半導体チップとして固片化される前にウエハレベルで行うようにしても良い。   In this step, as a pretreatment, a zincate treatment (zincate treatment) is performed on the aluminum surface of the electrode pad 22 so that electroless plating is performed on the electrode pad 22. In this zincate treatment, (a) the aluminum surface of the electrode pad 22 is cleaned, (b) the oxide film on the aluminum surface is removed by etching, and (c) the first zinc replacement film (thick and rough replacement film) is formed on the aluminum surface. (D) The first zinc substitution film is peeled off, and (e) the second zinc substitution film (thin and dense substitution film) is formed on the aluminum surface. Subsequently, a nickel-phosphorus (NiP) layer is formed on the electrode pad 22 by electroless Ni plating to form a connection electrode 23 having a thickness of 5 to 10 μm as an UBM (Under Barrier Metal). Note that the step of forming the zincate process and the connection electrode 23 may be performed at the wafer level before being solidified as a semiconductor chip.

図７に示す工程６では、無電解めっきを促進するために触媒として作用するPb含有樹脂層２６を第１絶縁層１８の下面に形成する。   In Step 6 shown in FIG. 7, a Pb-containing resin layer 26 that acts as a catalyst to promote electroless plating is formed on the lower surface of the first insulating layer 18.

図８に示す工程７では、Pb含有樹脂層２６のうち第１絶縁層１８のビアホール１８ａ内に形成された柱状部２６ａにエッチング等によりビアホール１８ａより小径の貫通孔２６ｂを形成する。   In step 7 shown in FIG. 8, a through hole 26b having a smaller diameter than the via hole 18a is formed by etching or the like in the columnar portion 26a formed in the via hole 18a of the first insulating layer 18 in the Pb-containing resin layer 26.

図９に示す工程８では、Pb含有樹脂層２６の表面に無電解めっきまたはスパッタ法によりニッケル（Ni）または銅（Cu）を積層してシード層２８を形成する。   In step 8 shown in FIG. 9, a seed layer 28 is formed by laminating nickel (Ni) or copper (Cu) on the surface of the Pb-containing resin layer 26 by electroless plating or sputtering.

図１０に示す工程９では、シード層２８の表面に配線対応部分に開口を有するレジスト膜（図示せず）を形成し、レジスト膜の開口に銅（Cu）などからなる金属膜パターン（膜厚１０〜２０μｍ）を形成し、この金属膜パターンが再配線３０となる。そして、レジスト膜を除去してシード層２８を露出させ、その後、再配線３０をマスクしてシード層２８をエッチングすることにより、シード層２８と再配線３０とからなる配線パターン２４を得る。これにより、電極パッド２２が接続電極２３を介して配線パターン２４に電気的に接続された構造が得られる。   In step 9 shown in FIG. 10, a resist film (not shown) having an opening corresponding to the wiring is formed on the surface of the seed layer 28, and a metal film pattern (film thickness) made of copper (Cu) or the like is formed in the opening of the resist film. 10 to 20 μm), and this metal film pattern becomes the rewiring 30. Then, the resist film is removed to expose the seed layer 28, and then the seed layer 28 is etched using the rewiring 30 as a mask to obtain a wiring pattern 24 including the seed layer 28 and the rewiring 30. Thereby, a structure in which the electrode pad 22 is electrically connected to the wiring pattern 24 through the connection electrode 23 is obtained.

図１１に示す工程１０では、配線パターン２４及びシード層２８の表面にソルダレジストが積層されて第３絶縁層３２が形成される。   In step 10 shown in FIG. 11, a solder resist is laminated on the surfaces of the wiring pattern 24 and the seed layer 28 to form the third insulating layer 32.

図１２に示す工程１１では、フォトリソグラフィ法に基づいて露光、現像することにより開口３２ａを形成し、第３絶縁層３２に配線パターン２４に連通する開口３２ａを設ける。   In step 11 shown in FIG. 12, an opening 32a is formed by exposure and development based on a photolithography method, and an opening 32a communicating with the wiring pattern 24 is provided in the third insulating layer 32.

図１３に示す工程１２では、開口３２ａ内に露出する配線パターン２４部分（ランド部）に半田ボールを接続してバンプ３４を第３絶縁層３２の表面に突出させる。そして、ダイシングソー４２により隣接する各々の半導体チップ間で所定寸法に切断して図１に示す半導体装置１０を得る。   In step 12 shown in FIG. 13, solder balls are connected to the wiring pattern 24 portions (land portions) exposed in the openings 32 a so that the bumps 34 protrude from the surface of the third insulating layer 32. Then, the semiconductor device 10 shown in FIG. 1 is obtained by cutting the adjacent semiconductor chips to a predetermined size by a dicing saw 42.

このように、上記工程１〜１２に基づいて、第１絶縁層１８に半導体チップ１２の電極パッド２２と接続するための孔１８ａを加工し、孔１８ａに半導体チップ１２の電極パッド２２を一致させるように位置合わせを行って半導体チップ１２を第１絶縁層１８の表面に貼り付けることにより、半導体チップ１２の電極パッド２２と孔１８ａ内に形成されるスタッドビア２８ａとの接続を高精度に行うことが可能になり、その分小型化を図れると共に、ウエハレベルでの再配線を行わないベアチップを使用してチップ搭載精度の高精度化を図れるので、製造コストを安価に抑えることが可能になる。   As described above, based on steps 1 to 12, the hole 18a for connecting to the electrode pad 22 of the semiconductor chip 12 is processed in the first insulating layer 18, and the electrode pad 22 of the semiconductor chip 12 is made to coincide with the hole 18a. Thus, the semiconductor chip 12 is attached to the surface of the first insulating layer 18 by aligning the positions of the semiconductor chip 12 and the electrode pads 22 of the semiconductor chip 12 and the stud vias 28a formed in the holes 18a. As a result, it is possible to reduce the manufacturing cost by using a bare chip that does not perform rewiring at the wafer level and improving the chip mounting accuracy. .

本発明になる半導体装置の一実施例を示す縦断面図である。It is a longitudinal cross-sectional view which shows one Example of the semiconductor device which becomes this invention. 半導体装置の製造方法の工程１を示す縦断面図である。It is a longitudinal cross-sectional view which shows the process 1 of the manufacturing method of a semiconductor device. 半導体装置の製造方法の工程２を示す縦断面図である。It is a longitudinal cross-sectional view which shows the process 2 of the manufacturing method of a semiconductor device. 半導体装置の製造方法の工程３を示す縦断面図である。It is a longitudinal cross-sectional view which shows the process 3 of the manufacturing method of a semiconductor device. 半導体装置の製造方法の工程４を示す縦断面図である。It is a longitudinal cross-sectional view which shows the process 4 of the manufacturing method of a semiconductor device. 半導体装置の製造方法の工程５を示す縦断面図である。It is a longitudinal cross-sectional view which shows the process 5 of the manufacturing method of a semiconductor device. 半導体装置の製造方法の工程６を示す縦断面図である。It is a longitudinal cross-sectional view which shows the process 6 of the manufacturing method of a semiconductor device. 半導体装置の製造方法の工程７を示す縦断面図である。It is a longitudinal cross-sectional view which shows the process 7 of the manufacturing method of a semiconductor device. 半導体装置の製造方法の工程８を示す縦断面図である。It is a longitudinal cross-sectional view which shows the process 8 of the manufacturing method of a semiconductor device. 半導体装置の製造方法の工程９を示す縦断面図である。It is a longitudinal cross-sectional view which shows the process 9 of the manufacturing method of a semiconductor device. 半導体装置の製造方法の工程１０を示す縦断面図である。It is a longitudinal cross-sectional view which shows the process 10 of the manufacturing method of a semiconductor device. 半導体装置の製造方法の工程１１を示す縦断面図である。It is a longitudinal cross-sectional view which shows the process 11 of the manufacturing method of a semiconductor device. 半導体装置の製造方法の工程１２を示す縦断面図である。It is a longitudinal cross-sectional view which shows the process 12 of the manufacturing method of a semiconductor device.

符号の説明Explanation of symbols

１０ 半導体装置
１２ 半導体チップ
１４ 絶縁層
１６ 配線層
１８ 第１絶縁層
２０ 第２絶縁層
２２ 電極パッド
２４ 配線パターン
２６ Pb含有樹脂層
２８ シード層
３０ 再配線
３４ バンプ
４０ 支持板 DESCRIPTION OF SYMBOLS 10 Semiconductor device 12 Semiconductor chip 14 Insulating layer 16 Wiring layer 18 1st insulating layer 20 2nd insulating layer 22 Electrode pad 24 Wiring pattern 26 Pb containing resin layer 28 Seed layer 30 Rewiring 34 Bump 40 Support plate

Claims (5)

支持板の表面に第１絶縁層を積層する第１工程と、
前記第１絶縁層に半導体チップの電極パッドと接続するための孔を加工する第２工程と、
前記孔に前記半導体チップの電極パッドを一致させるように位置合わせを行って前記半導体チップを前記第１絶縁層の表面に貼り付ける第３工程と、
前記半導体チップを被覆するように第２絶縁層を前記第１絶縁層に積層する第４工程と、
前記支持板を前記第１絶縁層から除去する第５工程と、
を有することを特徴とする半導体装置の製造方法。 A first step of laminating a first insulating layer on the surface of the support plate;
A second step of processing a hole for connecting to an electrode pad of a semiconductor chip in the first insulating layer;
A third step of aligning the electrode pads of the semiconductor chip with the holes and attaching the semiconductor chip to the surface of the first insulating layer;
A fourth step of laminating a second insulating layer on the first insulating layer so as to cover the semiconductor chip;
A fifth step of removing the support plate from the first insulating layer;
A method for manufacturing a semiconductor device, comprising: 前記第２工程は、レーザ加工により前記孔を形成することを特徴とする請求項１に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 1, wherein in the second step, the hole is formed by laser processing. 前記第３工程は、
前記半導体チップの回路形成面に対する電極パッドの位置を検出する工程と、
前記半導体チップの電極パッドの位置を前記孔の位置に一致させるように前記半導体チップを搬送する工程と、
前記半導体チップの回路形成面を前記第１絶縁層の表面に貼り付ける工程と、
を有することを特徴とする請求項１に記載の半導体装置の製造方法。 The third step includes
Detecting a position of an electrode pad with respect to a circuit forming surface of the semiconductor chip;
Transporting the semiconductor chip so that the position of the electrode pad of the semiconductor chip matches the position of the hole;
Bonding the circuit forming surface of the semiconductor chip to the surface of the first insulating layer;
The method of manufacturing a semiconductor device according to claim 1, wherein: 請求項１に記載の半導体装置の製造方法であって、
前記孔を介して前記半導体チップの電極パッドに接続される配線パターンを前記第１絶縁層の外面に形成する第６工程を有し、
前記第６工程は、
前記半導体チップの電極パッドの表面に接続電極を形成し、その後前記第１絶縁層の外面にシード層を形成し、次いで前記シード層の表面に電解めっきにより導体層を積層し、続いて、パターニング及びエッチングにより前記シード層及び前記導体層を所定形状の配線パターンとすることを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device according to claim 1,
Forming a wiring pattern connected to the electrode pad of the semiconductor chip through the hole on the outer surface of the first insulating layer;
The sixth step includes
A connection electrode is formed on the surface of the electrode pad of the semiconductor chip, then a seed layer is formed on the outer surface of the first insulating layer, and then a conductor layer is stacked on the surface of the seed layer by electrolytic plating, followed by patterning And a method of manufacturing a semiconductor device, wherein the seed layer and the conductor layer are formed into wiring patterns having a predetermined shape by etching. 半導体チップを封止する絶縁層と該絶縁層の外面に形成された配線層とを有する半導体装置であって、
前記絶縁層を成す第１絶縁層と第２絶縁層との間に半導体チップを埋め込むように構成し、
前記半導体チップの電極パッドに前記第１絶縁層の外面に形成される配線パターンを直接接続することを特徴とする半導体装置。
A semiconductor device having an insulating layer for sealing a semiconductor chip and a wiring layer formed on the outer surface of the insulating layer,
A semiconductor chip is embedded between the first insulating layer and the second insulating layer forming the insulating layer;
A semiconductor device, wherein a wiring pattern formed on an outer surface of the first insulating layer is directly connected to an electrode pad of the semiconductor chip.
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