JP2005341492A - Gateway unit and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the data from not transferred within a specified transmission period. <P>SOLUTION: A gateway unit 1 is provided between communication busses 11, 12, and 13 connected to nodes 110, 120, and 130 respectively and a communication bus 14 which is different from the communication busses 11, 12, and 13 and is connected to a node 140, for data transfer between the communication busses 11-13 and the communication buss 14. It comprises a memory 25 for holding the data inputted from the communication busses 11-13, a memory control circuit 26 for sorting the data outputted from the memory 25 in the ascending direction of transmission cycle, and a frame transmission process circuit 24 which transfers data to the communication bus 14 in the order sorted by the memory control circuit 26. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a gateway apparatus and method for transferring data between a plurality of communication networks.

  Patent Document 1 below describes a gateway that performs communication across a plurality of networks that perform packet communication by dividing control data and frame data including the data. In this gateway, there is a monitoring unit that monitors communication performed across different networks based on packet transmission source and destination information, and packet communication across different networks based on the monitoring results of the monitoring unit. A data conversion unit that generates frame data in a plurality of network destination formats, places the packet in a data area in the frame data, and enables packet communication in the destination network. Yes.

Japanese Patent Laid-Open No. 11-8647

In Patent Document 1, the data transmission order when transmitting data is not described. If a cyclic transfer signal is required to finish transmission of data that passes through the gateway within a certain transmission period and a plurality of data with different periods are mixed, the data stored in the memory is transmitted in the order of reception, for example. There is a problem that data with a short transmission cycle may not be transferred within a certain transmission cycle due to waiting for transmission of data with a long transmission cycle.
An object of the present invention is to provide a gateway apparatus and method capable of preventing data transfer from being performed within a certain transmission cycle.

  In order to solve the above problems, the present invention provides at least two first buses to which a first device is connected, and at least one first bus that is connected to a second device and is different from the first bus. In the gateway device that transfers data to and from the second bus, the data holding unit that holds the data input from the first bus, and the data that is output from the data holding unit are rearranged in the order of short transmission cycle. Data rearranging means and data transfer means for transferring data to the second bus in the order rearranged by the data rearranging means are provided.

  ADVANTAGE OF THE INVENTION According to this invention, it can prevent that the transfer of data cannot be performed within a fixed transmission period, and can improve transmission efficiency.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings described below, components having the same function are denoted by the same reference numerals, and repeated description thereof is omitted.
Embodiment 1
<Constitution>
First, the overall configuration of the gateway device according to the first embodiment will be described. FIG. 1 is a diagram showing a configuration of a gateway device according to the first embodiment of the present invention. FIG. 2 is a diagram depicting a part of FIG.
In FIG. 1, 11 is a first communication bus, 12 is a second communication bus, 13 is a third communication bus, 14 is a fourth communication bus, 110, 120, 130, and 140 are communication buses 11 to 14. 1 is a gateway device, 1-1 is a data processing circuit, 1-2 is a data processing circuit, 21, 22 and 23 are frame reception processing circuits, 25 is a memory, and 26 is a memory. The control circuit, 24 is a frame transmission processing circuit, 27 is a transmission set ready signal, and 28 is a transmission frame preparation completion signal.
In the first embodiment, each of the communication buses 11 to 14 is cyclically communicated with a frame made of a packet signal, and a part of the frames of one communication bus 11 to 13 is transferred to the other by the gateway device 1. An example of transfer to the communication bus 14 is shown.
The gateway device 1 is connected between the communication buses 11 to 13 and the communication bus 14. The gateway device 1 includes data processing circuits 1-1 and 1-2. The data processing circuit 1-1 includes frame reception processing circuits 21 to 23, a memory 25, a memory control circuit 26, and a frame transmission processing circuit 24. The data processing circuit 1-2 has the same configuration as that of the data processing circuit 1-1.

FIG. 3 is a diagram illustrating a configuration of frames on the communication buses 11 to 14.
The frame 2 on each of the communication buses 11 to 14 includes a header portion 3 and a data portion 4 as shown in FIG. The header part 3 includes an ID part 31 for determining the priority on the communication buses 11 to 14 for identifying the frame 2, a transmission period information part 32, and other information part 33 if necessary.
For example, the position of the transmission cycle information portion 32 in the frame 2 can be varied. That is, the header portion 3 is composed of an ID portion 31 for identifying a frame and determining a priority order on the communication buses 11 to 14, and other information portion 33 if necessary, and a data portion 4 is a transmission cycle information portion. 32 and an actual data portion may be used.

FIG. 4 is a diagram showing an internal configuration of the frame reception processing circuits 21 to 23 in FIG. Reference numeral 51 denotes an ID sampling circuit for sampling the ID of the frame 2, 52 denotes a reference ID memory in which IDs to be passed through the frame reception processing circuits 21 to 23 are held, 53 denotes an ID comparison circuit, and 54 denotes a switch unit.
The ID sampling circuit 51 samples the ID of the ID portion (31 in FIG. 2) of the frame 2 received from the communication buses 11-13. The ID data sampled by the ID sampling circuit 51 is compared with the reference ID held in the reference ID memory 52 by the ID comparison circuit 28. When the sampled ID matches the reference ID, the switch unit 54 To turn on the packet data.

FIG. 5 is a diagram showing a state in which frames are accumulated in the memory 25 of FIG. The frames that have passed through the frame reception processing circuits 21 to 23 are stored in the memory 25 in the order of reception as shown in FIG.
FIG. 6 is a diagram showing an internal configuration of the frame transmission processing circuit 24 of FIG. Reference numeral 41 is a bus not busy detection circuit, 42 is an AND circuit, 43 is a transmission counter, 44 is a parallel-serial conversion circuit, 45 is a bus driver, and 46 is serial data. The bus not busy detection circuit 41 monitors the state of the communication bus 14 and detects that the communication bus 14 is not busy. When both the output of the bus not busy detection circuit 41 and the transmission frame preparation completion signal 28 become active via the AND circuit 42, the transmission counter 43 starts counting and outputs a transmission clock to the parallel-serial conversion circuit 44. send. When receiving the transmission clock from the transmission counter 43, the parallel-serial conversion circuit 44 converts the frame 2 into serial data 46 and outputs it to the bus driver 45. The transmission counter 43 stops when it counts up to the number of bits to be transmitted, and simultaneously transmits a transmission set enable signal 27 to the memory control circuit 26 (FIG. 1).

<Operation>
Next, the operation of each part of the gateway device 1 will be described.
The frame reception processing circuits 21 to 23 read the ID part (31 in FIG. 2) of the packet signals input from the communication buses 11 to 13, determine whether the packet signals are to be transferred to the communication bus 14, and transfer them. If it is a power ID, the frame is stored in the memory 25.
The frame transmission processing circuit 24 is a circuit for sending a frame read from the memory 25 to the communication bus 14. When transmission of the frame in the frame transmission processing circuit 24 is completed and there is no frame to be transmitted in the frame transmission processing circuit 24, a transmission set enable signal 27 is sent from the frame transmission processing circuit 24 to the memory control circuit 26.
When the memory control circuit 26 receives the transmission set enable signal 27, the memory control circuit 26 extracts the transmission cycle information portion (32 in FIG. 2) in the header portion (3 in FIG. 2) stored in the memory 25, The extracted transmission cycle information is compared to select a frame having the shortest transmission cycle and set in the frame transmission processing circuit 24.
The data processing circuit 1-2 also extracts a frame to be passed by the frame reception processing circuit (21 to 23). The difference from the data processing circuit 1-1 is that a frame to be passed (that is, a reference ID) is different. The other operations are the same as those of the data processing circuit 1-1.
In addition, by providing the same number of frame reception processing circuits (21 to 23) and frame transmission processing circuits (24) as the number of communication buses (11 to 14) to be connected, transfer processing is similarly performed regardless of the number of communication buses. It is possible.

FIG. 7 is a diagram showing a processing flow of the memory control circuit 26 of FIG.
1 receives the transmission set enable signal 27 from the frame transmission processing circuit 24, the memory control circuit 26 in FIG. 1 extracts transmission cycle information from the header of each frame stored in the memory 25 in S2. When the memory control circuit 26 does not receive the transmission set enable signal 27, the process returns to S1. Next, in S3, the shortest cycle is selected from the transmission cycle information, and the corresponding frame is extracted. Next, in S 4, the corresponding frame is transferred to the frame transmission processing circuit 24, and at the same time, a transmission frame preparation completion signal 28 is transmitted to the frame transmission processing circuit 24.

Next, details of the operation of the first embodiment will be described. 8 and 9 are diagrams for explaining the details of the operation of the first embodiment. 8 and 9 are similar, but FIG. 9 is a more detailed view.
In the first embodiment, the communication bus includes communication buses 11-14. Frames having three types of periods A, B, and C are transmitted to the communication buses 11 to 13, respectively. Cycle A <cycle B <cycle C, frames A1 and A2 are frames having cycle A, frames B1 to B6 are frames having cycle B, and frames C1 to C9 are frames having cycle C. All of these frames are set to be transferred to the communication bus 14 by the gateway device 1. The gateway device 1 stores the received frames in the memory 25 in the order received. When transmitting to the communication bus 14, the frame having the shortest cycle among the frames stored in the memory 25 is transmitted. The frame reception order is A1, A2, B1, C1, B2, C2, C3, B3, C4, B4, C5, C6, B5, C7, B6, A1, C8, A2, C9,. The transmission order to the bus 14 is A1, A2, B1, C1, B2, B3, B4, B5, A1, A2, B6, C2, C3, C4, C5, C6, C7, C8, C9,.

That is, the gateway device 1 according to the first embodiment has at least two communication buses 11, 12, and 13 connected to at least one node 110, 120, and 130, and at least one node 140 to communicate with each other. In the gateway device 1 provided between at least one communication bus 14 different from the buses 11, 12, and 13 and transferring data between the communication buses 11 to 13 and the communication bus 14, the communication buses 11 to 11 The memory 25 that holds the data input from the memory 13, the memory control circuit 26 that rearranges the data output from the memory 25 in the order of the shortest transmission cycle, and the data to the communication bus 14 in the order rearranged by the memory control circuit 26. And a frame transmission processing circuit 24 for performing the transfer.
In the gateway method of the first embodiment, at least two communication buses 11, 12, 13 each having at least one node 110, 120, and 130 connected thereto and at least one node 140 are connected to each other. In the gateway method for transferring data to at least one communication bus 14 different from 11, 12, 13, a data holding step for holding data input from the communication buses 11 to 13, and the data holding step A data rearrangement step for rearranging the data held in the order in which the transmission cycle is short, and a data transfer step for transferring data to the communication bus 14 in the order rearranged in the data rearrangement step.
That is, in the gateway apparatus 1 that connects a plurality of communication networks and performs data transfer between the plurality of nodes 110 to 140 connected to the respective communication buses 11 to 14, the transmitting side node 110 on the communication buses 11 to 13 is used. The memory control circuit 26 stores frames received from the gateway device 1 and received by the gateway device 1 in the memory 25, and sets the transfer order of frames transferred to the receiving side node 140 on the other communication bus 14 in the order of short transmission cycle. Have

Since the frames received in this way are not sent in the order received, but the frame with the short transmission cycle is transmitted first, the short transmission cycle data cannot be transferred within a certain transmission cycle due to the long transmission cycle data waiting to be transmitted. Can be prevented. The frames A1 and A2 having the shortest transmission cycle can be transmitted with almost no waiting even if the received frames are accumulated in the memory 25 in the gateway device 1. That is, since a frame with a short transmission cycle is transmitted early and a long frame is transmitted later, transmission efficiency can be improved.
Conventionally, when a cyclic transfer signal that requires transmission of data passing through a gateway device to be completed within a certain transmission cycle and a plurality of data with different cycles coexist, the data stored in the memory is transmitted in the order received. As a result, there is a problem that data having a short transmission cycle may not be transferred within a certain transmission cycle due to waiting for transmission of data having a long transmission cycle. That is, in the conventional gateway device, frames received from a plurality of reception side communication buses are transmitted to the transmission side communication bus in the order of reception. Although the interval for receiving the frame A1 is A, when it is transmitted on the transmission side communication bus, the frames received by the gateway device between A between the frames A1 and A1 (for example, B1 to B6) , C1 to C8) cannot be transmitted until frame A1 is transmitted. In FIG. 8, the reception interval of the frame A1 in the memory 25 is A, and the transmission interval of the frame A1 to the communication bus 14 is A + (1). If (1)> A, which could occur in the past, the periodic transmission of the frame A1 cannot be realized. On the other hand, since frames A1 and A2 with a short transmission cycle as shown in FIG. 8 are transmitted preferentially by transmitting in the short transmission cycle as in the first embodiment, The transfer within the cycle is completed ((1) <A). In addition, frames B1 to B6 and C1 to C9 whose transmission cycle is longer than A may be transmitted due to reception of frames A1 and A2 having a shorter transmission cycle. However, the waiting time depends on the transmission cycle. Since the frames B1 to B6 that are held are transmitted before the frames C1 to C9 that have the cycle C, there is a high possibility that the transfer will be completed within each cycle.

When there are a plurality of frames having the same transmission cycle, transmission is performed from the frame received in the earliest order in the frame having the shortest cycle. That is, in the data rearranged by the memory control circuit 26, when there are a plurality of data having the same transmission cycle, the frame transmission processing circuit 24 transfers the data to the communication bus 14 in the order of reception in the memory 25. It has become. Thereby, even when there are a plurality of data having the same transmission cycle, data can be transmitted efficiently.
For the gateway device 1, frame reception processing circuits (21 to 23) corresponding to the number of communication buses (11 to 13) on the reception side are prepared, and frame transmission processing circuits (24) corresponding to the number of communication buses (14) on the transmission side are prepared. By preparing this, data transfer processing between a plurality of communication buses can be performed in the same manner.

<< Embodiment 2 >>
The overall configuration of the gateway device of the second embodiment is the same as that of the first embodiment shown in FIG. 1, and the configurations of the frame, the frame reception processing circuit, and the frame transmission processing circuit are also shown in FIGS. Since it is the same as that of Embodiment 1 shown in FIG. 6, description is abbreviate | omitted. Differences from the first embodiment will be described below. The difference from the first embodiment is that, in the first embodiment, the frames from the communication buses 11 to 13 are stored in the memory 25 in the order of reception and transmitted to the communication bus 14 by the memory control circuit 26. Based on the cycle information, the frames are transmitted to the frame transmission processing circuit 24 in the shortest transmission cycle. On the other hand, in the second embodiment, the frames from the communication buses 11 to 13 are stored in the memory 25 by the memory control circuit 26 in the order of the shortest transmission cycle based on the transmission cycle information of the frames. Is transmitted to the frame transmission processing circuit 24 in the order stored in the memory 25 by the memory control circuit 26.

The operation of each part of the second embodiment will be described. The frame reception processing circuits 21 to 23 (see FIG. 1; the same applies hereinafter) read the ID part (31 in FIG. 3) of the frame input from each of the communication buses 11 to 13 and determine whether it is a frame to be transferred. If the ID is to be transferred, it is sent to the memory control circuit 26.
In the memory control circuit 26, the transmission cycle information (32 in FIG. 2) of the received frame is compared with the transmission cycle information of the frames already stored in the memory 25, and the frames in the memory 25 are ordered in ascending order of the transmission cycle. In order to arrange them, the location where the newly received frame is stored in the memory 25 is determined and stored.
The frame transmission processing circuit 24 is a circuit for sending a frame read from the memory 25 to the communication bus 14. When transmission of the frame in the frame transmission processing circuit 24 is completed and there is no frame to be transmitted in the frame transmission processing circuit 24, a transmission set enable signal 27 is sent from the frame transmission processing circuit 24 to the memory control circuit 26.
When the memory control circuit 26 receives the transmission set enable signal 27, the memory control circuit 26 takes out frames stored in the memory 25 in order from the shortest transmission cycle and takes them out in the shortest transmission cycle. Then, the extracted frame is set in the frame transmission processing circuit 24.
The data processing circuit 1-2 also extracts a frame to be passed by the frame reception processing circuit (21 to 23). The difference from the data processing circuit 1-1 is that a frame to be passed (that is, a reference ID) is different. The other operations are the same as those of the data processing circuit 1-1.
In addition, by providing the same number of frame reception processing circuits (21 to 23) and frame transmission processing circuits (24) as the number of communication buses (11 to 14) to be connected, transfer processing is similarly performed regardless of the number of communication buses. It is possible.

FIG. 10 is a diagram showing a processing flow of the memory control circuit 26, where (a) shows processing at the time of frame reception and (b) shows processing at the time of transmission.
In S1 of (a), when a frame is received, the transmission cycle information is extracted from the received frame in S2, and compared with the transmission cycle information of the frame already stored in the memory 25 in S3, Arrange the frames in the shortest order and store them. At the time of transmission of (b), when the transmission set enable signal 27 is received from the frame transmission processing circuit 24 in S1, if there are frames stored in the memory 25 in the order of the transmission cycle in S2, the transmission cycle in S3. The shortest frame is transferred to the frame transmission processing circuit 24, and at the same time, a transmission frame preparation completion signal 28 is transmitted to the frame transmission processing circuit 24.

FIG. 11 is a diagram showing a state in which frames are accumulated in the memory 25. The frames that have passed through the frame reception processing circuits 21 to 23 are rearranged by the memory control circuit 26 in ascending order of the transmission cycle as shown in FIG. Further, the memory control circuit 26 first extracts a frame having a short transmission cycle.
Next, details of the operation of the second embodiment will be described. FIG. 12 is a diagram for explaining the details of the operation of the second embodiment.
In the second embodiment, the communication bus includes communication buses 11-14. Frames having three types of periods A, B, and C are transmitted to the communication buses 11 to 13, respectively. Cycle A <cycle B <cycle C, frames A1 and A2 are frames having cycle A, frames B1 to B6 are frames having cycle B, and frames C1 to C9 are frames having cycle C. All of these frames are set to be transferred to the communication bus 14 by the gateway device 1. The frames received from the communication buses 11 to 13 are compared with the transmission cycle of the frames stored in the memory 25 by the memory control circuit 26 every time they are received, and are rearranged in the memory 25 in the order of the transmission cycles. Stored (see FIG. 11. In this example, the transmission cycle is A to C). When transmitting to the communication bus 14, the frames are transmitted in order from a frame with a short transmission cycle rearranged and stored in the memory 25. Also in the second embodiment, the frames A1 and A2 having a short transmission cycle are not stored in the memory 25 in the gateway device 1 because the frames are transmitted not from the reception order but from the frame having the short transmission cycle first. Although the received frames are accumulated, the frames can be transmitted to the communication bus 14 with almost no waiting. That is, since a frame with a short transmission cycle is transmitted early and a long frame is transmitted later, transmission efficiency can be improved. The frame reception order is A1, A2, B1, C1, B2, C2, C3, B3, C4, B4, C5, C6, B5, C7, B6, A1, C8, A2, C9,. The transmission order to the bus 14 is A1, A2, B1, C1, B2, B3, B4, B5, A1, A2, B6, C2, C3, C4, C5, C6, C7, C8, C9,.
For the gateway device 1, frame reception processing circuits (21 to 23) corresponding to the number of communication buses (11 to 13) on the reception side are prepared, and frame transmission processing circuits (24) corresponding to the number of communication buses (14) on the transmission side are prepared. By preparing this, data transfer processing between a plurality of communication buses can be performed in the same manner.

That is, the gateway device 1 according to the second embodiment also receives data input from the communication buses 11 to 13 in the gateway device 1 that transfers data between the communication buses 11, 12, and 13 and the communication bus 14. The memory 25 to be held, the memory control circuit 26 that rearranges the data output from the memory 25 in the order of short transmission cycle, and the frame transmission process that transfers the data to the communication bus 14 in the order rearranged by the memory control circuit 26 Circuit 24.
When the memory control circuit 26 rearranges the frames in the short transmission cycle, if there are a plurality of frames having the same transmission cycle, the frames are arranged in the order of the received frames. That is, in the data rearranged by the memory control circuit 26, when there are a plurality of data having the same transmission cycle, the memory control circuit 26 rearranges the data in the order of reception in the memory 25. Thereby, even when there are a plurality of data having the same transmission cycle, data can be transmitted efficiently.
The embodiment described above is described for facilitating the understanding of the present invention, and is not described for limiting the present invention. Therefore, each element disclosed in the above embodiment includes all design changes and equivalents belonging to the technical scope of the present invention.

  Further, the nodes 110, 120, and 130 are the first device in the claims, the node 140 is the second device, the first communication bus 11, the second communication bus 12, and the third communication bus 13 are. The first bus, the fourth communication bus 14 corresponds to the second bus, the memory 25 corresponds to the data holding means, the memory control circuit 26 corresponds to the data rearranging means, and the frame transmission processing circuit 24 corresponds to the data transfer means. .

It is a figure which shows the structure of the gateway apparatus of Embodiment 1 of this invention. FIG. 2 is a diagram depicting a part of FIG. 1. It is a figure which shows the structure of the flame | frame on a communication bus. It is a figure which shows the internal structure of the frame reception processing circuit of FIG. It is a figure which shows the state by which the flame | frame was accumulate | stored in the memory of FIG. It is a figure which shows the internal structure of the frame transmission processing circuit of FIG. It is a figure which shows the processing flow of the memory control circuit of FIG. It is a figure explaining the detail of operation | movement of Embodiment 1 of this invention. It is a figure explaining the detail of operation | movement of Embodiment 1 of this invention. (A) is a figure which shows the processing flow at the time of frame reception of the memory control circuit of Embodiment 2 of this invention, (b) is a figure which shows the processing flow at the time of transmission. It is a figure which shows the state by which the flame | frame was accumulate | stored in the memory of Embodiment 2 of this invention. It is a figure explaining the detail of operation | movement of Embodiment 2 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Gateway apparatus 1-1, 1-2 ... Data processing circuit 2 ... Frame 3 ... Header part 4 ... Data part 11 ... 1st communication bus 12 ... 2nd communication bus 13 ... 3rd communication bus 14 ... fourth communication bus 21, 22, 23 ... frame reception processing circuit 24 ... frame transmission processing circuit 25 ... memory 26 ... memory control circuit 27 ... transmission set ready signal 28 ... transmission frame ready signal 31 ... ID part 32 ... transmission Period information part 33 ... Other information part 41 ... Bus not busy detection circuit 42 ... AND circuit 43 ... Sending counter 44 ... Parallel serial conversion circuit 45 ... Bus driver 46 ... Serial data 51 ... ID sampling circuit 52 ... Reference ID memory 53 ... ID comparison circuit 54 ... switch 110, 120, 130, 140 ... node

Claims (4)

At least two first buses to which at least one first device is connected and at least one second bus to which at least one second device is connected and different from the first bus In the gateway device that is provided between and transfers data between the first bus and the second bus,
Data holding means for holding data input from the first bus;
Data rearranging means for rearranging the data output from the data holding means in the order of short transmission cycle;
Data transfer means for transferring the data to the second bus in the order rearranged by the data rearrangement means;
A gateway device comprising:   If there is a plurality of data having the same transmission cycle among the data rearranged by the data rearranging means, the data transfer means sends the data to the second bus in the order received by the data holding means. A gateway device characterized by transferring.   When there are a plurality of data having the same transmission cycle among the data rearranged by the data rearranging unit, the data rearranging unit rearranges the data in the order received by the data holding unit. Gateway device. At least two first buses to which at least one first device is connected and at least one second bus to which at least one second device is connected and different from the first bus In the gateway method of transferring data between
A data holding step for holding data input from the first bus;
A data rearrangement step of rearranging the data held in the data holding step in the order of short transmission cycle;
A data transfer step of transferring the data to the second bus in the order rearranged in the data rearrangement step;
A gateway method characterized by comprising:

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