JP2005327454A - Parallel test apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a parallel test apparatus in which a signal for semiconductor memory apparatus can be varied at high speed when a plurality of semiconductor memory apparatuses are tested and a test time can be shortened. <P>SOLUTION: The plurality of semiconductor memory apparatuses 1 are arranged on a plurality of test boards being divided, test boards TB<SB>1</SB>-TB<SB>n</SB>have corresponding test board synchronizing circuits TSC<SB>1</SB>-TSC<SB>n</SB>respectively. An external clock signal EXT.CLK externally given is synchronized with them by each test board synchronizing circuit TSC<SB>1</SB>and outputted to each semiconductor memory apparatus as a formed test board test signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a parallel test apparatus for a semiconductor memory device, and more particularly to a configuration of a parallel test apparatus for performing a test of a semiconductor memory device at high speed.

  As the memory capacity of a semiconductor memory device, particularly a dynamic RAM (hereinafter referred to as DRAM) increases, the time required for testing the semiconductor memory device has also increased dramatically.

  This is because, as the storage capacity of the semiconductor memory device increases, the number of word lines included in the semiconductor memory device also increases, so that the time for writing and reading memory cell information while the word lines are sequentially selected is markedly increased. This is a problem caused by the longer period.

  The above problem is more serious in an accelerated test such as a burn-in test. In this burn-in test, the semiconductor memory device is operated under conditions of high temperature and high voltage, the gate insulating film defect of the MOS transistor as a constituent element, the interlayer insulating film defect between the wirings, the wiring defect and the verticle mixed in during the manufacturing process. It is intended to reveal potential initial defects such as the resulting defects and eliminate defective products before shipment.

  The burn-in test as described above is an essential test for maintaining the quality of shipped products, and an increase in time required for this test directly leads to an increase in manufacturing cost of the semiconductor memory device.

  Such a problem of increase in test time is also a problem that occurs in reliability tests such as a life test.

FIG. 45 schematically shows a conventional apparatus configuration for performing a burn-in test.
In FIG. 45, on the test board TB, the semiconductor memory devices DR11 to DRmn are arranged in m rows and n columns. These semiconductor memory devices DR11 to DRmn are each connected via a signal bus SG.

  During the test period, a control signal and a clock signal are output from the test signal generation circuit TA to the test board TB. These control signals and clock signals are transmitted to each semiconductor memory device through a signal bus SG.

  In the burn-in test, for example, first, high level data is written into each of the memory cells DR11 to DRmn. Subsequently, row address strobe signal / RAS and an address signal are applied from test signal generation circuit TA to signal bus SG, and word lines are selected and sense amplifier circuits are operated in semiconductor memory devices DR11-DRmn. A malfunction of each semiconductor memory device is detected by comparing the memory cell information amplified by the sense amplifier circuit with the test data written in advance.

The above operation is performed continuously for a predetermined time under a predetermined acceleration condition.
FIG. 47 schematically shows an entire configuration of a conventional dynamic semiconductor memory device. In FIG. 47, dynamic semiconductor memory device 1 has a control circuit for generating internal control signals in response to external control signals / WE, / OE, / RAS and / CAS applied via external control signal input terminals 2-5. 18, a memory cell array 7 in which memory cells are arranged in a matrix, and external address signals A 0 to Ai given through address signal input terminal 8, and under control of control circuit 18, internal row address signals and internal Under the control of an address buffer 9 for generating a column address signal and a control circuit 18, an internal address generation circuit 10 for generating a refresh row address signal designating a row to be refreshed during a refresh operation, and a control of the control circuit 18 Below the address buffer 9 and internal address generation times Multiplexer 11 selectively passing one of the address signals from 10 and activated under the control of control circuit 18, decode the internal row address signal provided from multiplexer 11, and select the row of memory cell array 7 The row decoder 12 is included.

  Signal / WE applied to external control signal input terminal 2 is a write enable signal designating data writing. / OE given to the external control signal input terminal 3 is an output enable signal designating data output. Signal / RAS applied to external control signal input terminal 4 is a row address strobe signal that starts internal operation of the semiconductor memory device and determines the active time of internal operation.

  When this signal / RAS is activated, circuits related to the operation of selecting a row of memory cell array 7 such as row decoder 12 are activated. Signal / CAS applied to external control signal input terminal 5 is a column address strobe signal, which activates a circuit for selecting a column in memory cell array 7.

  The semiconductor memory device 1 is further activated under the control of the control circuit 18, decodes the internal column address signal from the address buffer 9, and generates a column selection signal for selecting a column of the memory cell array 7. A sense amplifier for detecting and amplifying data of the memory cells connected to the selected row of the memory array 7, and a selected column of the memory cell array 7 in response to a column selection signal from the column decoder 13 as an internal data bus. Under the control of the IO gate connected to a1 and the control circuit 18, internal write data is generated from the external write data DQ0 to DQj applied to the data input terminal 17 at the time of data writing, and sent to the internal data bus a1. When data is read under the control of input buffer 15 for transmitting and control circuit 6, the data is read to internal data bus a1. From Part read data generated external read data DQ0~DQj an output buffer 16 to be output to the data output terminal 17.

  In FIG. 47, the sense amplifier and the IO gate are shown as one block 14. Input buffer 15 is activated to generate internal write data when both signals / WE and / CAS attain an active low level. The output buffer 16 is activated according to the activation of the output enable signal / OE.

  As described above, the operation of the DRAM is controlled by the signals / WE, / OE, / RAS, / CAS and the address signals A0 to Ai given from the outside.

  Therefore, even during the burn-in test, these signals are supplied from the test signal generation circuit TA to the semiconductor memory devices DR11 to DRmn.

  In the burn-in test as described above, even when the memory capacity of each semiconductor memory device is increased, in order to suppress an increase in test time, control transmitted from the test signal generation circuit TA shown in FIG. 45 to the signal bus SG is performed. It can be considered that the time for which the word line is selected is shortened by changing the signal / RAS at a high speed.

  However, a large number of semiconductor memory devices DR11 to DRmn are connected to the signal bus SG, and the signal bus SG has a large parasitic capacitance Cp as shown in FIG. For this reason, a signal transmission delay occurs due to the wiring resistance of the signal bus SG and this large parasitic capacitance, and there is a limit to changing the signal at high speed.

  FIG. 46 shows an example of changes in control signal / RAS and address signal on signal bus SG.

  FIG. 46A shows an ideal signal waveform on the signal bus SG, and FIG. 46B shows a signal waveform on the signal bus SG in the conventional burn-in test. As shown in FIG. 46A, in the ideal state, the signal / RAS changes with a predetermined rise time and fall time without being affected by the signal propagation delay. The address signal requires a setup time Ts and a hold time Th for this signal / RAS. The setup time Ts is a time required for setting the signal / RAS before the signal / RAS falls. The hold time Th is a time required for the address signal to maintain a definite state after the signal / RAS falls.

  On the other hand, when the parasitic capacitance Cp of the signal bus SG is large, as shown in FIG. 46B, the rise time and fall time of the control signal / RAS become longer due to the signal propagation delay on the signal bus SG, and the waveform is distorted. become. For this reason, the control signal / RAS cannot be changed at high speed.

  At this time, the changing speed of the address signal is similarly lowered. In order to secure the address setup time Ts, it is necessary to change the address signal at a timing earlier than the address signal change timing of the ideal waveform (FIG. 46A). Since the address signal is changed when the control signal / RAS is at the high level of the inactive state, the period of the inactive state of the control signal / RAS is longer than that of the ideal waveform.

  As a result, the time of one cycle (word line selection cycle) of the burn-in test becomes long, the word lines cannot be sequentially selected at a high speed, and the burn-in test time cannot be shortened. It was.

  Also, in the burn-in test, predetermined storage information is written in advance in each memory cell, and this is compared with an expected value that is information that has been sequentially read and written by sequentially selecting word lines. Detect product defects by detecting data bit errors. For this reason, when it is difficult to change the control signal / RAS at high speed as described above, there is a problem that the test time increases even in a cycle in which the signal which is the expected value is written in advance. It was.

  Accordingly, an object of the present invention is to provide a parallel test apparatus capable of changing the signals for each of the semiconductor memory devices at high speed and reducing the test time when testing a plurality of semiconductor memory devices. Is to provide.

  In summary, when an operation test is performed in synchronization with a plurality of semiconductor memory devices divided into a plurality of subgroups in parallel according to the external clock signal, the external clock signal is set for each subgroup. A means for generating a synchronized internal test clock signal is provided, and these semiconductor memory devices are tested in parallel at high speed.

  That is, the parallel test apparatus according to the present invention is a parallel test apparatus that performs an operation test in synchronization with a plurality of semiconductor memory devices in parallel according to an external clock signal input from the outside, and is divided into a plurality of subgroups. An internal test clock generating means for generating an internal test clock signal that is synchronized with an external clock signal and is present in each subgroup of the plurality of semiconductor memory devices, and each semiconductor memory in the subgroup And a data bus line for transmitting to the device.

  Preferably, the internal test clock generating means and the data bus line provided for each subgroup are formed on one test board, and the plurality of semiconductor memory devices are arranged on the one test board.

  Preferably, a plurality of test boards are provided corresponding to each of the plurality of subgroups, and the internal test clock generating means and the data bus lines provided for each of the subgroups are formed on the corresponding test boards, Each semiconductor memory device in the group is arranged on the corresponding test board.

  In particular, the plurality of semiconductor memory devices are arranged in a matrix, and the internal test clock generation means is formed on one side of the four sides of the test board with respect to each semiconductor memory device in the subgroup, The test clock generating means receives the external clock signal from the one side.

(Function)
A parallel test apparatus according to the present invention divides a semiconductor memory device for performing a parallel test into a plurality of subgroups, and generates an internal test clock signal synchronized with the external clock signal input from the outside for each subgroup. .

  A parallel test apparatus according to the present invention divides a plurality of semiconductor memory devices to be tested in parallel into a plurality of subgroups, and the internal test is synchronized for each subgroup of the semiconductor memory devices according to an external clock signal from the outside. Since the internal test clock generating means for generating the clock signal is provided, it is possible to suppress the occurrence of distortion of the clock signal applied to each semiconductor memory device even when a large number of semiconductor memory devices are tested in parallel.

[First embodiment]
FIG. 1 schematically shows a whole structure of a semiconductor memory device according to a first embodiment of the present invention. In FIG. 1, the semiconductor memory device 1 has an external control signal EXT. / WE, EXT. / OE, EXT. / RAS, EXT. / CAS for generating various internal control signals, and an external test mode designating signal EXT. In response to the BI, the output of the internal clock signal CLK is started, and an internal cycle setting circuit 20 that changes the cycle of the internal clock signal CLK to be output according to the internal clock cycle control signal FS from the outside, and the internal clock signal CLK In response to the external control signal EXT. In response to BI, the internal clock signal CLK is output to the external terminal 5 to which the / CAS signal is input and the control gate circuit 22 that outputs to the control circuit 6, the output from the sense amplifier circuit and the input / output control circuit 14, and the internal clock signal CLK. In response to the external control signal EXT. While BI is active, clock signal CLK is output to output buffer 16, and signal EXT. During the inactive period of BI, a buffer input signal control circuit 24 that outputs an output signal from the sense amplifier and input / output control circuit 14 to the output buffer 16 is included.

  Internal clock signal CLK generated by internal cycle setting circuit 20 is applied to control circuit 18 as a row selection operation activation signal (internal RAS). Control circuit 18 receives external signal EXT. When the test mode is designated by BI, the row selection operation activation signal is activated in synchronization with clock signal CLK from internal cycle setting circuit 20. Other configurations are the same as those of the conventional semiconductor memory device shown in FIG. 47, and corresponding portions are denoted by the same reference numerals and description thereof is omitted.

  FIG. 2 is a diagram showing an example of the configuration of internal cycle setting circuit 20 shown in FIG. 2, the internal cycle setting circuit 20 includes a plurality of cascaded inverters 21a to 21d (four stages in FIG. 2), an output signal of the inverter 21d, and a test mode designation signal EXT. NOR gate 21e receiving BI via inverter 21f is included. The number of inverters 21a to 21d is appropriately set according to the period of the clock signal CLK to be generated.

  Therefore, when the circuit shown in FIG. 2 is used as the internal cycle setting circuit 20, the cycle of the output clock signal CLK is fixed to a predetermined cycle set in advance.

  FIG. 3 is a diagram showing another example of the configuration of the internal cycle setting circuit 20 shown in FIG. Referring to FIG. 3, internal cycle setting circuit 20 b includes K−1 (K is an odd number) delay time variable elements 110.1 to 110. Including K-1. Further, the internal cycle setting circuit 20b is connected to the final stage of the delay time variable elements connected in series, and the test mode designation signal EXT. Delay time variable element 110 whose start of operation is controlled by BI. K is included.

  The bias case circuit 100 includes P-channel MOS transistors 100 and 102 and N-channel MOS transistors 103 and 104. P channel MOS transistor 101 and N channel MOS transistor 103 are connected in series between power supply line 121 and ground potential line 122. P channel MOS transistor 102 and N channel MOS transistor 104 are connected in series between power supply potential line 121 and ground potential line 122. The gates of P channel MOS transistors 101 and 102 are connected in common and connected to the drain of P channel MOS transistor 101. That is, P channel MOS transistors 101 and 102 constitute a current mirror circuit. N channel MOS transistor 103 has its gate receiving internal clock cycle control signal FS. N channel MOS transistor 104 has its gate connected to its drain.

  A current Ia that increases or decreases in accordance with internal clock cycle control signal FS flows through N channel MOS transistor 103. Since the MOS transistors 103 and 101 are connected in series, the MOS transistors 101 and 102 constitute a current mirror circuit, and the MOS transistors 102 and 104 are connected in series, so that the same current Ia flows through the four MOS transistors 101 to 104. . However, the transistor sizes of the MOS transistors 101 and 102 are the same.

  Delay time variable element 110.1 includes P channel MOS transistors 111.1 and 112.1 and N channel MOS transistors 113.1 and 114.1 connected in series between power supply potential line 121 and ground potential line 122. . P channel MOS transistor 111.1 has its gate connected to the gate of P channel MOS transistor 102 of bias generation circuit 100. The gates of the MOS transistors 112.1 and 113.1 are connected in common, and the MOS transistors 112.1 and 113.1 constitute an inverter 115.1.

  N channel MOS transistor 114.1 has its gate connected to the gate of N channel MOS transistor 104 of bias generation circuit 100. Other delay time variable elements 110.2-1110. The same applies to K-1. Inverters 115.1-115. K-1 are connected in series. The input of the inverter 115.1 has a NAND circuit 115. K output is connected.

Next, the operation of the internal cycle generation circuit 20b shown in FIG. 3 will be described.
P-channel MOS transistors 111.1 to 111. The gates of K are both connected to the gate of P channel MOS transistor 102, and N channel MOS transistors 114. -114. Since the gates of K are both connected to the gate of the N-channel MOS transistor 104, the delay time variable elements 110.1 to 110. A current Ia corresponding to the internal clock cycle control signal FS also flows through K.

  When internal clock cycle control signal FS increases and current Ia increases, each inverter 115.1-115. K-1 and NAND circuit 115. The inversion time of K is shortened, and the oscillation period of the internal period setting circuit 20b is shortened.

  In addition, when internal clock cycle control signal FS decreases and current Ia decreases, each inverter 115.1-115. K-1 and NAND circuit 115. The inversion time of K becomes longer, and the oscillation period of the internal period setting circuit 20b becomes longer.

  Test mode designation signal EXT. During the period when BI is at “L” level, NAND circuit 115. Since K becomes inactive, the output of the internal cycle setting circuit 20b is stopped.

  With the above configuration, the test mode designation signal EXT. The start and stop of the operation are controlled by the BI, and the operation of the internal cycle setting circuit 20b in which the oscillation cycle is controlled by the internal clock cycle control signal FS is realized.

  FIG. 4 is a circuit diagram showing an example of the configuration of the buffer input signal control circuit 24 shown in FIG.

  The buffer input signal control circuit 24 includes an output signal Dout from the sense amplifier and input / output control circuit 14 and a test mode designating signal EXT. NAND circuit 240 that receives an inverted signal of BI, internal clock signal CLK that is the output of internal cycle setting circuit 20, and test mode designating signal EXT. A NAND circuit 242 having BI as an input is included. Test mode designation signal EXT. During the period when BI is at the “L” level, the NAND gate 240 is opened and the signal Dout is output.

  On the other hand, test mode designation signal EXT. During the period when BI is at “H” level, the NAND gate 242 is opened and the internal clock signal CLK is output.

  With the above configuration, the output buffer circuit can be continuously operated even during the test mode period, and the acceleration test of the output buffer circuit can be simultaneously performed in an acceleration test such as a burn-in test.

  In this embodiment, only the output buffer circuit 16 is configured to be in the operating state during the test period, but it is needless to say that both the input buffer circuit 15 and the output buffer circuit 16 are configured to be in the operating state during the test mode period. It is.

FIG. 5 is a signal waveform diagram for explaining the operation of the present invention.
Test mode designation signal EXT. After BI rises from the “L” level to the “H” level, the semiconductor memory device 1 operates by the internal clock signal CLK output from the internal cycle setting circuit 20, the word line is driven, and the memory cell Corresponding to the information, the potential difference between the bit line pair (BL, / BL) is amplified. Therefore, even when a large number of semiconductor memory devices are arranged on one board and an operation test is simultaneously performed as shown in FIG. 45, each semiconductor memory device has no relation to the distortion of the waveform of the test signal from the outside. The internal clock signal can maintain a predetermined cycle and a predetermined waveform.

  Therefore, test mode designating signal EXT. By providing the BI, each semiconductor memory device 1 can operate at high speed without being affected by parasitic capacitance or the like existing on the board.

[Second Embodiment]
FIG. 6 is a schematic block diagram showing the configuration of the semiconductor memory device 1 according to the second embodiment of the present invention.

  The difference from the first embodiment is that the internal clock cycle control signal FS for controlling the cycle of the internal clock signal CLK, which is the output of the internal cycle setting circuit 20, is not externally transmitted, but the value of the signal FS is set to be non-volatile. This is because the configuration is provided from the period setting circuit 26 that can be stored in the memory.

  FIG. 7 is a schematic block diagram showing a connection relationship between the cycle setting circuit 26 and the internal cycle setting circuit 20b shown in FIG.

  The output of period setting circuit 26 is input to the gate of N channel MOS transistor 103 in bias generation circuit 100.

FIG. 8 is a circuit diagram showing the configuration of the cycle setting circuit 26 in more detail.
Resistors 234, 236, 238 and 240 are connected in series between the constant current source 242 and the ground potential. A fuse element 228 is connected to the resistor 234, a fuse element 230 is connected to the resistor 236, and a fuse element 232 is connected to the resistor 238 in parallel. The potential at the connection point between the constant current source 242 and the resistor 234 is output as the internal clock cycle control signal FS.

  By cutting fuse elements 228, 230, and 232 by laser trimming or the like, the combined value of the resistance values of the resistors viewed from the constant current source 242 side is changed, so that the value of internal clock cycle control signal FS is changed. Is possible.

  Semiconductor memory devices have different specifications such as operating conditions depending on the type. Further, if the design is different, it is necessary to change the test conditions and the like. However, according to the present embodiment, the cycle of the internal clock CLK during the test mode period can be flexibly and easily changed according to the type of the semiconductor memory device. It is possible.

  In the above embodiment, the method for shortening the test time of the acceleration test such as the burn-in test by increasing the cycle of the internal clock signal CLK as the test condition during the test mode period has been described. In order to change the acceleration condition of the acceleration test, not only the cycle of the internal clock signal CLK is increased, but also the internal power supply voltage Vci supplied to the internal circuit after being stepped down from the external power supply voltage Vce is supplied to the external power supply. There is also a method of increasing to a voltage.

  FIG. 9 is a block diagram showing a configuration of an internal power supply voltage supply circuit that enables the acceleration conditions as described above to be set.

  P channel MOS transistor 246 and load 250 are connected to a direct current between external power supply voltage Vce and the ground potential. The gate of P channel MOS transistor 246 receives the output of differential amplifier 244 that receives output Vref and knife power supply voltage Vci from a reference voltage generation circuit (not shown). Internal power supply voltage Vci is taken out as a potential at the connection point of P channel MOS transistor 246 and load 250. Therefore, this circuit has a function of forming a negative feedback loop based on the output value of the internal power supply voltage Vci and holding the voltage Vci at the reference voltage Vref. N channel MOS transistor 248 is connected between the output of differential amplifier 244 and the ground potential, and the gate potential thereof is set to test mode designating signal EXT. Controlled by BI. That is, during the test mode period, the test mode designation signal EXT. When BI becomes “H” level and N channel MOS transistor 248 is rendered conductive, the gate potential of P channel MOS transistor 246 is lowered to the ground potential. Therefore, P channel MOS transistor 246 is completely turned on, and internal power supply voltage Vci is pulled up to external power supply voltage Vce.

  FIG. 10 is a diagram showing the difference between the normal use region and the acceleration test region described above, with the external power supply voltage on the horizontal axis and the internal power supply voltage on the vertical axis.

  In the normal use region, the internal power supply voltage remains constant even when the external power supply voltage fluctuates, but in the accelerated test region, the internal power supply voltage matches the external power supply voltage.

  Therefore, the internal circuit of semiconductor memory device 1 operates at an external power supply voltage that is higher than that during normal operation, and a burn-in test or the like can be performed under more accelerated conditions.

[Third embodiment]
FIG. 11 is a schematic block diagram showing the configuration of the semiconductor memory device 1 according to the third embodiment of the present invention.

  The difference from the first embodiment is that the test mode designation signal EXT. It is not a configuration in which BI is directly applied from the outside, but external control signals / RAS, / CAS, / WE and address signals A0 to Ai are received as inputs, and a test mode is designated by a combination of these signals This is a configuration including a test mode control circuit 19 for detection.

  In an on-wafer test or the like, a test signal or the like can be input from an external terminal for testing. However, after the semiconductor memory device 1 is housed in a mold package or the like in the product stage, an external control signal is transmitted. Input must be provided from an external pin.

  FIG. 12 is a diagram showing an example of a specific configuration of control circuit 18 and test mode control circuit 19 shown in FIG. 12, control circuit 18 receives external control signal / RAS (EXT./RAS) applied to external control signal input terminal 4 and outputs internal row address strobe signal / RAS. RAS buffer 30 and external control signal EXT. Provided to external control signal input terminals 4 and 5, respectively. / RAS and EXT. / BRAS to detect that CBR condition (condition for lowering external control signal EXT./CAS to low level first before falling of external control signal EXT./RAS) is set , In response to a CBR detection signal from the CBR detector 31, a one-shot pulse generation circuit 32 that generates a one-shot pulse signal in response to the CBR detection signal from the CBR detector 31, and activated in response to the CBR detection signal from the CBR detector 31, While the CBR detection signal is in an active state, a timer 33 for supplying an activation signal to the one-shot pulse generation circuit 32 at predetermined intervals and an external control signal EXT. / WE, EXT. / OE, EXT. / RAS and EXT. / CAS, these external control signals are WCBR condition (Write Cas Before Ras condition: EXT./WE is high level and CBR condition is satisfied) and a predetermined address signal is super Vcc condition (normal high A test mode setting circuit 80 for outputting a test mode designating signal BI indicating that the test mode has been set when the condition of a potential higher than the Vcc potential as a level) is satisfied; / RAS, EXT. / CAS and EXT. Self-refresh mode setting detection circuit 34 that receives / WE and outputs a self-refresh mode designating signal φss indicating that the self-refresh mode is set when these control signals satisfy a predetermined condition.

  One shot pulse generation circuit 32 is activated for a predetermined time period in response to activation of a CBR detection signal from CBR detector 31 and activation of a signal (refresh instruction signal) from timer 33, respectively. Generates a one-shot pulse signal.

  Control circuit 18 further includes a two-input NOR gate 35 that receives internal row address strobe signal / RAS output from RAS buffer 30 and a CBR detection signal output from CBR detector 31, and a CBR detection signal output from CBR detector 31. A two-input AND circuit 50 that receives a self-refresh designation signal φss from the self-refresh mode setting circuit, a two-input OR gate 52 that receives an output of the AND circuit 50 and a test mode designation signal BI from the test mode setting circuit 80, In response to the clock signal CLK from the internal cycle setting circuit 20, the transfer gate 38 that selectively passes the output signal of the OR gate 52, the clock signal CLK from the internal cycle setting circuit 20 and the output signal of the transfer gate 38 Receive 2-input AND gate 3 A 2-input AND gate 44 that receives an inverted signal of the output signal of OR gate 52 and an output signal of one-shot pulse generation circuit 32; an output signal of NOR gate 35; and output signals of AND gates 39 and 44 A 3-input OR gate 40, a 2-input OR gate 41 receiving the output signal of the AND gate 44 and the output signal of the AND gate 39, and a circuit related to the row selection operation in response to the output signal φRAS from the OR gate 40 are predetermined. RAS control circuit 42 that is activated at the timing shown in FIG. In FIG. 12, the RAS system control circuit 42 controls the activation / inactivation of the row decoder 12.

  The NOR gate 35 outputs a high level signal when the signal / RAS from the RAS power-up 30 is at a low level and the output signal of the CBR detector 31 is at a low level. That is, during normal operation (when the CBR condition is not set), the NOR gate inverts the signal from the RAS buffer 30 and outputs it. When the CBR condition is set, the NOR gate 35 is set to the inactive low level regardless of the logic level of the output signal of the RAS buffer 30. Thereby, when the CBR condition is set, the external control signal EXT. Row selection operation under the control of / RAS is prohibited.

  The AND gate 50 has a high level when the CBR detection signal from the CBR detector 31 is in the active high level and the self refresh mode designating signal φss from the self refresh mode setting circuit 34 is in the active high level. An active signal is output. The OR gate 52 outputs a high level active state signal when the output of the AND gate 52 is high level or when the test mode designating signal BI from the test mode setting circuit 80 is high level indicating the active state. To do. That is, OR gate 52 outputs a high-level active state signal only when the self-refresh mode or the test operation mode is designated and the operation of sequentially selecting the word lines is performed.

  Transfer gate 38 is formed of, for example, a P-channel MOS transistor, and is rendered conductive when clock signal CLK from internal cycle setting circuit 20 is at a low level. Thus, even if the clock signal CLK is at the high level when the end of the test mode is designated, the clock signal CLK is prevented from immediately falling to the low level. The test mode operation is terminated after the clock signal CLK falls to a low level. Memory cell data is prevented from being destroyed due to incomplete word line selection. Therefore, the transfer gate 38 has a function of a latch circuit that latches the output signal of the AND gate 37 every time the clock signal CLK rises.

  The OR gate 40 activates a word line selection operation that becomes active at a high level when any of the output signal of the AND gate 39, the output signal of the AND gate 44, and the output signal of the NRO gate 35 is set to a high level. Signal (internal RAS signal) φRAS is output. This signal φRAS is applied to RAS system control circuit 42. The RAS control circuit 42 is shown to control only the row decoder 12 in FIG. 12, but also controls the operation of other sense amplifier circuits and bit line equalize / precharge circuits (not shown). To do.

  An output signal of OR gate 41 is applied to internal address generation circuit 10. The internal address generation circuit 10 increments or decrements the address value indicated by the output address signal every time the output signal of the OR circuit 41 falls.

  Therefore, in the semiconductor memory device 1 controlled by the control circuit 18 having the above configuration, when the self-refresh mode or the test mode is designated by the external control signal and the address signals A0 to Ai, the internal cycle setting circuit The word lines are sequentially selected by the internal clock signal CLK which is an output signal from 20, and the refresh operation is performed on the memory cells belonging to the row designated by the internal address generation circuit 10.

  In FIG. 12, in order to control the cycle of the internal clock signal CLK, which is an output signal of the internal cycle setting circuit 20, from the outside, the internal clock cycle is supplied with the signal FS from a specific control pin. The test mode setting circuit 80 may set the value of the clock cycle control signal by a combination of predetermined address signals A0 to Ai and output the value to the internal cycle setting circuit 20.

[Fourth embodiment]
FIG. 13 is a schematic block diagram showing the configuration of the semiconductor memory device 1 according to the fourth embodiment of the present invention.

  The difference from the first embodiment is that the test mode designation signal EXT. When the test mode is designated by BI, an external clock signal applied from the outside, for example, external row strobe signal EXT. An internal synchronization circuit 70 for receiving an internal row strobe signal φRAS generated corresponding to / RAS and generating an internal clock signal CLK synchronized therewith is provided.

  As described in the prior art, when testing a plurality of semiconductor memory devices in parallel, the external clock signal given from the outside is distorted due to signal transmission delay on the test board. Become. In the present embodiment, the internal clock signal synchronized with the external clock signal is generated by the internal synchronization circuit 70, thereby shaping the shape of the internal clock signal that controls the operation of the internal circuit in the semiconductor memory device 1. Objective.

  Internal row strobe signal φRAS is external low strobe signal EXT., Similar to control circuit 18 shown in FIG. It is assumed that / RAS is an internal signal after passing through the RAS buffer circuit 30.

  As the configuration of the internal synchronization circuit 70, a configuration such as a phase locked loop circuit (PLL circuit) or a delay locked loop circuit (DLL circuit) can be considered.

  FIG. 14 is a schematic block diagram showing a configuration when a DLL circuit is used as the internal synchronization circuit 70.

  Referring to FIG. 14, the DLL circuit includes clock buffers 91 and 96, a phase comparator 92, a charge pump circuit 93, a loop filter 94 and a voltage control delay circuit 95.

  As shown in FIG. 15, the clock buffer 91 includes M inverters 91.1 to 91.M connected in series (M is a positive integer). M, the external clock signal φRAS is amplified and the clock signal ECLK is output. Clock signal ECLK is applied to phase comparator 92 and voltage control delay circuit 95. Inverters 91.1 to 91. The size of the symbol M is determined by the inverters 91.1 to 91. M represents the magnitude of the load driving capacity of M, and inverters 91.1 to 91. The load driving capability of M gradually increases toward the output end. Subsequent inverters 91.2 to 91. The load driving capacity of M is the previous inverter 91.1-91. It is set to about 3 to 4 times the load driving capacity of M-1.

  Inverters 91.1 to 91. The number M is set according to the capacities of the phase comparator 92 and the voltage control delay circuit 95.

  As shown in FIG. 16, the clock buffer 96 includes N inverters 96.1 to 96. connected in series (N is a positive integer). N, and amplifies output ECLK ′ of voltage control delay circuit 95 to output internal clock signal CLK and clock signal RCLK. The internal clock signal CLK is supplied to the control gate circuit 22 as in the first embodiment. Clock signal RCLK is applied to phase comparator 92. Inverters 96.1 to 96. constituting clock buffer 96. Similarly to the clock buffer 90, the load driving capability of N gradually increases toward the output end. The number N of 96.1 to 96N is set according to the size of the load capacity. The inverter (96.4 in the figure) that outputs clock signal RCLK is selected so that the phase difference between external clock signal φRAS and internal clock signal CLK becomes a predetermined value.

  Next, the phase comparator 92 shown in FIG. 14 will be described. FIG. 17 is a circuit diagram showing a configuration of the phase comparator 92. In the figure, the phase comparator 92 includes inverters 300 to 304, two-input NAND gates 305 to 310, three-input NAND gates 311 and 312, and a four-input NAND gate 313.

  Inverter 300 receives clock signal ECLK from clock buffer 91. Inverter 301 receives clock signal RCLK from clock buffer 96. NAND gate 305 receives the output of inverter 300 and the output of NAND gate 311 and outputs signal φ 305. NAND 306 receives the outputs of NAND gates 305 and 307 and outputs signal φ 306. NAND gate 307 receives the outputs of NAND gates 306 and 313, and NAND gate 308 receives the outputs of NAND gates 309 and 313. NAND gate 309 receives the outputs of NAND gates 308 and 310 and outputs signal φ309. NAND gate 310 receives the output of inverter 301 and the output of NAND gate 312, and outputs signal φ310.

  NAND gate 313 receives signals φ305, φ306, φ309, and φ310 from NAND gates 305, 306, 309, and 310, and outputs a reset signal RES. NAND gate 311 receives signals φ305, φ306, and RES from NAND gates 305, 306, and 313, and outputs up signal / UP through inverters 302 and 303. NAND gate 312 receives signals φ 309, φ 310, RES from NAND gates 309, 310, 313 and outputs down signal DOWN via inverter 304.

  FIG. 18 shows the clock signal ECLK, the clock signal RCLK, the output of the 2-input NAND gate 305 (namely, signal φ305), the output of the 2-input NAND gate 310 (namely, signal φ310), and the output of the 4-input NAND gate 313 (namely, the reset signal RES). ), A timing chart showing the mutual relationship between the up signal / UP and the down signal DOWN.

  Prior to the description of FIGS. 17 and 18, first, consider a case where both of the clock signals ECLK and RCLK are at the “H” level. In this case, the gates 305 and 310 always output “H” level. If the outputs of the gates 306 and 309 are “H” level, the output of the gate 313 is “L” level, the outputs of the gates 307 and 308 are “H” level, and eventually the gates 306 and 309 are output. Output becomes “L” level. Therefore, it can be seen that the gates 311 and 312 always output the “H” level as long as both the clock signals ECLK and RCLK are at the “H” level. If the clock signals ECLK and RCLK change to “L” level after such a state, the outputs of the gates 305 and 310 become “L” level, and the gates 306 and 309 output “H” level. Become.

  Thereafter, as shown in FIG. 18, the case where the clock signal ECLK first rises and then the clock signal RCLK rises with a delay of the phase T1 will be described. In response to the rise of clock signal ECLK, output φ 305 of gate 305 turns to “H” level. However, since the clock signal RCLK remains at the “L” level, the output φ310 of the gate 310 continues to be at the “L” level, and the output RES of the gate 313 does not change from the “H” level. For this reason, the output of the gate 311 changes to the “L” level. On the other hand, the output of the gate 312 remains at “H” level.

  Next, when the clock signal RCLK rises, the output φ310 of the gate 310 changes to “H” level, all four inputs of the gate 313 become “H” level, and the output RES of the gate 313 changes to “L” level. To do. As a result, the output of the gate 311 changes from the “L” level to the “H” level again, and the gate 311 outputs a pulse signal reflecting the phase difference between the clock signal ECLK and the clock signal RCLK.

  On the other hand, the output of the gate 312 changes to the “L” level in response to the change of the output of the gate 310 to the “H” level, but immediately after that, the output of the gate 313 changes to the “L” level. Return to H ”level. For this reason, the gate 312 outputs a pulse signal having a constant width irrespective of the phase difference between the clock signal ECLK and the clock signal RCLK.

  When the clock signal RCLK first falls and then the clock signal ECLK rises, the relationship between the up signal / UP and the down signal DOWN is the same except that the description is omitted.

  That is, as shown in FIG. 19, when the phase of the clock signal ECLK is delayed from the clock signal CLK, the phase comparator 92 has a pulse width corresponding to the up signal / UP having a constant pulse width and the phase difference. When the down signal DOWN is output and the phases of the clock signals ECLK and RCLK match, the signals / UP and DOWN having the same pulse width are output, and the phase of the clock signal ECLK is ahead of the clock signal RCLK Outputs a down signal DOWN having a constant pulse width and an up signal / UP having a pulse width corresponding to the phase difference.

  FIG. 20 is a circuit diagram showing configurations of charge pump 93 and loop filter 94 shown in FIG. Referring to FIG. 20, charge pump 93 includes a constant current source 123, a P-channel MOS transistor 124, an N-channel MOS transistor 125, and a constant current source 126 that are DC-connected between power supply potential line 121 and ground potential line 122. .

  The gate of P channel MOS transistor 124 receives up signal / UP, and the gate of N channel MOS transistor 125 receives down signal DOWN. A connection node N124 between the P channel MOS transistor 124 and the N channel MOS transistor 125 serves as an output node of the charge pump 93. Loop filter 94 includes a resistor 127 and a capacitor 12 connected in series between output node N124 of charge pump 93 and ground potential line 122.

  Next, operations of the charge pump 93 and the loop filter 94 shown in FIG. 20 will be described. When up signal / UP and down signal DOWN are both at "L" level, P channel MOS transistor 124 is turned on and N channel MOS transistor 125 is turned off, and power supply line 122 → constant current source 123 → Charge is supplied to capacitor 127 via P-channel MOS transistor 124 → node N 124 → resistor 127. As a result, the voltage at the node N124, that is, the control voltage VCOin gradually increases.

  On the other hand, when up signal / UP and down signal DOWN both attain "H" level, P channel MOS transistor 124 is turned off and N channel MOS transistor 125 is turned on, capacitor 128 → resistor 127 → node. The charge of the capacitor 128 flows out through the path of N124 → N-channel MOS transistor 125 → constant current source 126 → ground potential line 122. Therefore, the control voltage VCOin gradually decreases.

  Further, when the up signal / UP becomes “L” level and the down signal DOWN becomes “H” level, both the MOS transistors 124 and 125 become conductive, and the amount of charge flowing into the node 124 and the amount of charge flowing out from the node N124 become smaller. And the control voltage VCOin does not change.

  On the contrary, when the up signal / UP becomes “H” level and the down signal DOWN becomes “L” level, both the MOS transistors 124 and 125 become nonconductive, the node N124 becomes floating, and the control voltage VCOin does not change.

  That is, the control voltage VCOin that is the output of the charge pump 93 and the loop filter 94 gradually decreases when the phase of the clock signal ECLK is delayed from the clock signal RCLK, and the phases of the clock signals ECLK and RCLK match. If the phase of the clock signal ECLK is higher than that of the clock signal RCLK, the clock signal ECLK gradually increases.

  FIG. 21 is a circuit diagram in which the configuration of the voltage control delay circuit 95 shown in FIG. 14 is partially omitted.

  Since the configuration of this circuit is basically the same as that of the internal cycle setting circuit 20b described in FIG. 3, the details of the description of the configuration and operation are omitted, and only the differences will be described below.

  That is, in FIG. 3, the output voltage VCOin from the charge pump circuit 93 and the loop filter 94 in response to the internal clock cycle control signal FS given from the outside in order to control the oscillation frequency of the internal cycle setting circuit 20b is Input to the gate of the N-channel MOS transistor 101.

  On the other hand, in internal cycle setting circuit 20b, NAND circuit 141. The output of K is connected to the input of the inverter 145.1. However, in the voltage control delay circuit 95, the clock signal ECLK is input to the input of the inverter 145.1, and the NAND circuit 141. The output of K is taken out as a clock signal ECLK ′.

Therefore, the operation of the voltage control delay circuit 95 is as described below.
That is, P channel MOS transistors 141.1-141. The gates of K are both connected to the gate of P channel MOS transistor 102, and N channel MOS transistors 144.1 to 144. Since the gates of K are both connected to the gate of the N-channel MOS transistor 104, each delay time variable element 140.1-140. Also in K, current Ia flowing in N channel MOS transistors 101 and 104 flows in accordance with control voltage VCOin.

  When the control voltage VCOin increases and the current Ia increases, the inversion times of the inverters 145, 1-145, K-1 and NAND circuits 145, K are shortened, and the delay time of the voltage control delay circuit 95 is shortened.

  Further, when the control voltage VCOin decreases and the current Ia decreases, the inverters 145.1 to 145. K-1 and NAND circuit 145. The inversion time of K becomes longer, and the delay time of the voltage control delay circuit 95 becomes longer.

  Next, the operation of the DLL circuit shown in FIG. 14 will be described based on the operation of each component block described above. When the phase of the clock signal RCLK is delayed from the clock signal ECLK, the phase comparator 92 generates an up signal / UP having a pulse width corresponding to the phase difference between the clock signals ECLK and RCLK and a down signal DOWN having a predetermined pulse width. Is output. In response to this, the charge pump 93 supplies charges to the loop filter 94, whereby the control voltage VCOin rises and the delay time of the voltage control delay circuit 95 is shortened. Therefore, the phase of the clock signal RCLK advances, and the phase difference between the clock signals ECLK and RCLK becomes small.

  Conversely, when the phase of the clock signal RCLK is ahead of the clock signal ECLK, the phase comparator 92 causes the down signal DOWN having a pulse width corresponding to the phase difference between the clock signals RCLK and ECLK and the up signal having a predetermined pulse width. / UP is output. In response to this, charge flows out from the loop filter 94 to the charge pump 93, whereby the control voltage VCOin decreases and the delay time of the voltage control delay circuit 95 becomes longer. Therefore, the phase of the clock signal RCLK is delayed, and the phase difference between the clock signals RCLK and ECLK is reduced. Such a process is repeated, and finally the phase difference between the clock signals RCLK and ECLK matches.

  FIG. 23 is a timing chart for explaining the operation of the semiconductor memory device 1 having the internal synchronization circuit 70 performing the above operation.

  That is, when a plurality of semiconductor memory devices 1 are arranged on the test board, the clock signal EXT. CLK has a distorted waveform as shown in FIG. 23 due to signal transmission delay on the board.

  However, test mode designating signal EXT. When BI becomes “H” level and the internal synchronization circuit 70 starts to operate, the internal clock signal CLK output from this circuit becomes a rectangular wave synchronized with the external clock signal.

  Therefore, even when the external clock signal waveform on the board is distorted, the circuit operation within the semiconductor memory device is not affected.

[Fifth embodiment]
FIG. 24 is a block diagram showing a configuration of the internal synchronization circuit 70 in the semiconductor memory device 1 according to the fifth embodiment of the present invention. Test mode designation signal EXT. After BI becomes “H” level, external clock signal EXT. In response to the first rise of CLK, output of internal clock signal CLK needs to be started. This is because it is necessary to prevent memory cell data from being destroyed due to an incomplete word line selection operation, and because the internal timer randomly starts oscillation, the phase of the external clock This is because when the deviation is large, the time required to match the phase with the external clock differs for each semiconductor memory device 1.

  In the third embodiment shown in FIG. 12, after the test mode is designated by the test mode designation signal by the latch operation of the transfer gate 38 and the AND circuit 39, the internal clock signal CLK is raised after the first oscillation waveform rises. Was configured to be output. Also in the present embodiment, it is possible to overcome the above problems by adopting the same configuration.

  Further, as shown in FIG. 24, after the test mode designating signal becomes “H” level by the logic circuit 72 by the test mode designating signal, the rising edge of the first external clock signal is detected and the voltage control is performed. A configuration in which the operation of the delay circuit 95 is started is also possible.

FIG. 25A is a circuit diagram showing an example of the configuration of such a logic circuit 72.
A difference from the voltage control delay circuit shown in FIG. 21 is that the variable delay element NAND circuit 145. K to NOR circuit 145. K, and one input thereof has a test mode designation signal EXT. BI and external clock signal EXT. The output of the SR flip-flop circuit 160 to which CLK is input is input, and the inverter 145. This is a configuration in which the output of K-1 is input.

  As shown in FIG. 25 (b), the output of the SR flip-flop circuit 160 is the test mode designating signal EXT. After BI becomes “H” level, external clock signal EXT. When CLK first becomes “H” level, it changes from “H” level to “L” level. Therefore, voltage control delay circuit 95 has the first external clock signal EXT. The operation starts in response to the rise of CLK.

  With the above circuit configuration, it is possible to prevent an incomplete word line selection operation from occurring.

[Sixth embodiment]
FIG. 26 is a schematic block diagram showing the configuration of the semiconductor memory device 1 according to the sixth embodiment of the present invention.

  FIG. 27 is a principal block diagram showing in more detail the configuration of the semiconductor memory device 1 shown in FIG.

  The difference from the fourth embodiment is that, first, the test mode setting circuit 86 in the test mode control circuit 82 is connected to the external control signal EXT. / RAS, EXT. / CAS, EXT. In response to receiving / WE and address signals A0 to Ai, when it is detected that the test mode is designated, a test mode designation signal BI is output, and the internal synchronization circuit 70 starts operating in response thereto. is there.

  Secondly, the switching circuit 84 receives the output of the internal cycle setting circuit 20 and the output of the internal synchronization circuit 70, and outputs the output from the internal synchronization circuit 70 during the period when the test mode designating signal BI is active. However, when the test mode designating signal BI is in the inactive period and the self refresh mode designating signal φss is in the active period, the output of the internal cycle setting circuit 20 is output as the internal clock.

  Other configurations of the circuit are the same as those in FIG. 12, and the same portions are denoted by the same reference numerals and description thereof is omitted.

  With the above configuration, the external control signal EXT. / RAS, EXT. CAS and EXT. When the self-refresh mode is designated by the combination of / WE, the semiconductor memory device 1 performs a self-refresh operation according to the internal clock signal CLK that is the output of the external cycle setting circuit 20, and the external control signal EXT. RAS, EXT. / CAS, EXT. / WE and address signals A0 to Ai, when a test mode is designated, an external clock signal EXT. CLK, for example, external row strobe signal EXT. The test mode operation is performed using the output from internal synchronization circuit 70 synchronized with the clock signal applied as RAS as internal clock signal CLK.

FIG. 28 is a timing chart showing the operation of the internal synchronization circuit 70 shown in FIG.
External write enable signal EXT. / WE is at "H" level and the external control signal EXT. / RAS and EXT. / CAS satisfies the CBR condition and external address signal EXT. When Add satisfies the super Vcc condition, test mode setting circuit 86 detects that the test mode is designated, and outputs “H” level test mode designation signal BI. When the test mode designating signal BI is input to the NOR circuit 52, an “H” level signal is input to the transfer gate 38. Therefore, when the internal clock signal CLK that is the output of the internal cycle setting circuit 70 is input from the switching circuit 84 to the AND circuit 39, the internal row strobe signal φRAS corresponding to the internal clock signal CLK is input to the RAS control circuit 42. Then, the word lines are sequentially selected.

  With the above circuit configuration, during the test mode period, the semiconductor memory device 1 is operated by the shaped internal clock signal output from the internal synchronization circuit in synchronization with the external clock signal.

  Therefore, external clock signal EXT. The distortion of the waveform of CLK does not directly affect the operation of the internal circuit of the semiconductor memory device 1.

[Seventh embodiment]
In the sixth embodiment, internal clock signal CLK is external clock signal EXT. The signal is supplied to the internal circuit as a signal synchronized with CLK, but another external control signal for performing the test operation is supplied to each semiconductor memory device 1 via data bus line SG on the test board. The configuration was FIG. 29 is a schematic block diagram showing the configuration of the semiconductor memory device 1 according to the seventh embodiment of the present invention. The difference from the sixth embodiment is that the self-test circuit 400 is built in the semiconductor memory device 1.

  Self test circuit 400 includes a test vector generation unit 402, a self test control unit 404 and a determination unit 406.

The test vector generation unit 402 includes a counter, a ROM, or an LFSR (Linear Feedback Shift Register) for generating pseudo random numbers. For example, an n-bit LFSR can generate 2 ⁿ −1 types of pseudo-random test vectors. The self-test control unit starts the operation in response to the test mode designation signal, and controls the test vector generation in the test vector generation unit 402 and the write operation to the memory cell. On the other hand, the test vector written in the memory cell is read to the determination unit 406 based on the control of the self-test control unit 404, and a bit error is detected by comparing with the expected value.

  The above writing and reading can be performed alternately, but in order to improve the test efficiency, it is also possible to compress the output a plurality of times and compare only once at the end.

  With the circuit configuration as described above, once the test mode is designated from the outside, the semiconductor memory device 1 causes the external clock signal EXT. While operating according to the internal clock signal CLK synchronized with CLK, the self-test operation is continued until a bit error is detected, and the efficiency of an accelerated test such as a burn-in test can be greatly improved.

[Eighth embodiment]
FIG. 30 is a schematic block diagram showing the configuration of the semiconductor memory device 1 according to the eighth embodiment of the present invention.

  FIG. 31 is a principal block diagram showing in more detail the configuration of semiconductor memory device 1 shown in FIG.

  The difference from the sixth embodiment is that the internal synchronization circuit 70 in the test mode control circuit 82 is connected to an external clock signal such as EXT. This is an internal multiplication circuit 72 that receives / RAS and outputs an internal clock signal CLK multiplied by the cycle.

  Other configurations of the circuit are the same as those in FIG. 27, and the same portions are denoted by the same reference numerals and description thereof is omitted.

FIG. 32 is a schematic block diagram showing the configuration of the internal multiplication circuit 72 in FIG.
The configuration of internal multiplication circuit 72 is different from the configuration of internal synchronization circuit 70 shown in FIG. 14 in that frequency dividing circuit 98 that receives output signal RCLK from clock buffer 96 and divides the frequency into a predetermined frequency dividing ratio is provided. It is the point which has composition.

  The phase comparator 92 receives the output signal ECLK from the clock buffer 91 and the output signal nRCLK from the frequency dividing circuit 98. For example, when the frequency dividing ratio of the frequency dividing circuit 98 is 16, a signal having a period 16 times the output signal ECLK ′ of the voltage control delay circuit 95 is input to the phase comparator 92 and the external clock signal EXT. Charge pump circuit 93 is controlled so that the phase of ECLK, which is a signal corresponding to / RAS, matches.

  Therefore, internal clock signal CLK output from clock buffer 96 is external clock signal EXT. The signal has a period of 1/16 of / RAS.

  That is, external clock signal EXT. A signal obtained by multiplying / RAS is output as the internal clock signal CLK.

  Therefore, even when the external clock signal is operating at a sufficiently slow cycle, the internal clock signal CLK can operate at a high speed. External clock signal EXT. / RAS on the test board is affected by the waveform distortion caused by the external clock signal EXT. Since the / RAS cycle is shorter, the effect becomes more prominent. Therefore, it is possible to reduce the influence of waveform distortion on the test board by the above configuration.

  Also in this embodiment, the internal clock signal is EXT. / CAS terminal 5 and other external terminals, or by changing the division ratio of frequency divider circuit 98 by internal clock cycle control signal FS, the cycle of internal clock signal CLK can be made variable. Of course it is possible.

  Similarly, it is possible to adopt a configuration in which the output buffer circuit can be simultaneously accelerated by inputting the multiplied internal clock signal CLK to the output buffer circuit.

FIG. 33 is a timing chart showing the operation of the eighth embodiment. Similar to the sixth embodiment, the external control signal EXT. / RAS, EXT. / CAS and EXT. / WE specifies the WCBR condition, and the address signal EXT. By setting Add to the super _Vcc condition, the test mode is entered. An internal clock signal CLK obtained by multiplying the cycle of the / RAS signal is output.

[Ninth Embodiment]
FIG. 34 is a schematic block diagram showing the configuration of the parallel test apparatus according to the ninth embodiment of the present invention.

  Up to the seventh embodiment, each semiconductor memory device 1 has an oscillating circuit or a synchronous circuit in order to shape the distortion of the waveform of the external clock signal on the test board.

  External clock signal EXT. As a method of correcting the waveform distortion of CLK, it is possible to adopt a configuration in which a plurality of synchronization circuits are provided on each board and an external clock signal is shaped on the test board.

  In order to obtain the same effect, the test board is divided into a plurality of parts, and the external clock signal EXT. It is also possible to generate a test clock signal RCLK on the test board in synchronization with CLK.

In FIG. 34, a plurality of semiconductor memory devices 1 are divided and arranged on a plurality of test boards, and each test board TB _{1 to} TB _n has a corresponding test board synchronization circuit TSC _{1 to} TSC _n . External clock signal EXT. CLK is synchronized to the respective test board synchronizing circuit TSC _i, and is outputted to the semiconductor memory device as the shaped test board test signal.

  Therefore, by adopting the configuration of the parallel test apparatus as described above, the external clock signal EXT. The waveform of the CLK is distorted due to the signal delay due to the parasitic capacitance Cp on the test board, and the operation of each semiconductor memory device becomes non-uniform, so that the acceleration conditions such as the burn-in test differ for each semiconductor memory device. Can be prevented.

[Tenth embodiment]
Up to the ninth embodiment, when an accelerated test such as a burn-in test is performed according to an externally applied clock signal or test signal, the semiconductor memory device operable even when the cycle of the external clock signal is increased. The configuration and the configuration of the parallel test apparatus were described.

  In order to perform a parallel acceleration test, etc. at high speed, not only the operating clock signal is made high speed, but also in the acceleration test of a semiconductor memory device, comparison with the expected value after writing and reading of the data is required. It is important to reduce the time to do it.

  The tenth embodiment shows a configuration of a semiconductor memory device capable of writing test storage information to memory cells in the semiconductor memory device 1 at high speed.

  FIG. 35 is a cross-sectional view showing the structure of a memory cell portion in a typical DRAM. In FIG. 35, a DRAM memory cell 614 stores memory cell transistors and charges formed by an N-type high concentration layer 606 to which a bit line 611 is connected and an N-type high concentration layer 606 to which a word line 605 and a storage node 609 are connected. And a memory cell capacitor formed by a cell plate 610 that is a counter electrode of the capacitor.

  Each element is separated by an isolation oxide film 604, and a P-type well 603 and an N-type well 602 are formed on the substrate 1 on the substrate side. The P-type well 603 is supplied with a potential from the wiring 613 through the P-type high concentration layer in order to fix the potential.

  FIG. 36 is an equivalent circuit diagram of the memory cell portion of FIG. In FIG. 36, a storage node 609 which is a charge storage capacitor electrode of a memory cell is connected to a P well 603 by a diode configuration. Thereby, charges can be transferred to the storage node 609 through the P well 603.

  That is, in FIG. 35, by independently controlling the potential of the wiring 613 and the cell plate 610 connected to the P well 603 via the P-type high concentration layer 607, the storage node 609 is controlled from the P well 603 side. Charge injection can be performed. The charge injection method will be described in detail below.

  FIG. 37 is a diagram for explaining a method of writing “H” level data to each memory cell in a lump.

  As an example, a method of writing “H” data to a memory cell in the case of a power supply voltage of 4 volts and a cell plate voltage of 2 volts will be described.

  In FIG. 37A, a positive voltage is applied from the wiring 613 to the P well 603. As a result, positive charges can be injected into the storage node 609. The injected charge amount at this time is a value considering the forward voltage drop of the PN junction between the P well 603 and the N-type high concentration layer 606. At this time, the potential of the cell plate 610 is set to -1 V, and the positive potential on the P well side is set to the following value.

(Positive potential on the P well side) = + 1+ (Forward voltage drop of the PN junction between the P well 3 and the N-type high concentration layer 6) (V)
With the above setting, the potential of the storage node 609 becomes + 1V.

  In FIG. 37B, a negative potential is supplied to the P well 3 through the wiring 613. At this time, the negative potential to be supplied is low enough that the leakage current when the N-type high concentration layer 606 and the P well 603 connected to the storage node 609 in the DRAM are biased in the reverse direction does not interfere with the charge retention characteristics of the memory cell. In addition, the leakage current between the N-type high-concentration layers 606 of the adjacent memory cells must be at a level that can be kept low enough not to disturb the charge retention characteristics of each memory cell. Furthermore, the negative potential must be such that the subthreshold current of the switching transistor of the memory cell does not interfere with the charge retention characteristics of the memory cell.

  In FIG. 37B, the charge held in the storage node 609 is held by the negative potential of the cell plate 610.

  In FIG. 37 (c), when the potential of the cell plate 610 is raised to + 2V, the storage node 609 via the dielectric film 612 raises the potential due to dielectric coupling. Therefore, “H” data (corresponding to +4 V) is written in the memory cell.

  FIG. 38 is a diagram showing a method of writing “L” level data to the memory cells of semiconductor memory device 1 at once.

  Hereinafter, as an example, a method of writing “L” level data to a memory cell when the power supply voltage is 4 V and the cell plate voltage is 2 V will be described.

  In FIG. 38A, first, by applying a positive voltage from the wiring 613 to the P well 603, charges can be injected into the storage node 609. The implantation addition amount at this time is a value considering the forward voltage drop of the PN junction between the P well 603 and the N-type high concentration layer 606. At this time, the potential of the cell plate 610 is set to +3 V, and the positive potential on the P well side is set to the following value.

(Positive potential on the P well side) = + 1+ (Forward voltage drop of the PN junction between the P well 3 and the N-type high concentration layer 6) (V)
With the above setting, the potential of the storage node 609 becomes + 1V.

  In FIG. 38B, a negative potential is supplied to the P well 603 through the wiring 613. At this time, the negative potential to be supplied is such that the request current when the N-type high concentration layer 606 and the P well 603 connected to the storage node 609 in the DRAM are biased in the reverse direction does not interfere with the charge retention characteristics of the memory cell. It must be low and low enough that the leakage current between the N-type high concentration layers 606 of adjacent memory cells does not interfere with the charge retention characteristics of each memory cell. Further, the negative potential needs to be kept low enough that the subthreshold current of the switching transistor of the memory cell does not interfere with the charge retention characteristics of the memory cell.

  In FIG. 38B, the charge held in the storage node 609 is held by the negative potential of the cell plate 610.

  In FIG. 38C, when the potential of the cell plate 610 is lowered to + 2V, the storage node 609 causes a potential drop due to coupling via the dielectric film 612. Therefore, “L” level data is written in the memory cell.

  FIG. 39 is a schematic block diagram showing an example of a circuit configuration of the semiconductor memory device 1 that enables the batch writing method of data to the memory cells as described above.

  Memory cells 622 are arranged at intersections of bit line pairs 628a to 628h and word lines 624a to 624f, respectively. For example, when reading stored information in memory cell 622 arranged at the intersection of word line 624a and bit line pair 628a, the potential of word line 624a is set to "H" level. As a result, the memory cell transistor becomes conductive, and the charge held in the memory cell capacitor generates a potential difference in the potential of the bit line pair 628a. This minute potential difference is amplified by the sense amplifier 623 and connected to the I / O line by the selector 625, whereby this data is read out to the outside.

In the semiconductor memory device 1 of FIG. 39, the potential V _C of the cell plate 610 is held at the potential V _CP generated by the cell plate potential generation circuit 520 in the normal operation. The output V _CP of the cell plate potential generation circuit is connected to the wiring 560 connected to the cell plate of each memory cell by the switching circuit 530. On the other hand, the potential V _W of the P well 603 in each memory cell is held at a constant value V _BB by the substrate potential generation circuit 522 in normal operation. The output of the substrate potential generation circuit is connected via a switching circuit 532 to a wiring 570 that is connected to the P well 3 of each memory cell.

When performing the batch write operation of data to the memory cells described with reference to FIGS. 37 and 38, outputs V _CQ and V _{WC of} cell plate potential / P well potential setting circuit 524 are supplied via switching circuits 530 and 532, respectively. The cell plate and the P well 603 are supplied. The cell plate / P well potential setting circuit 524 controls the cell plate potential and the P well potential in accordance with the control signal CCP from the outside, thereby collectively “H” level data or “L” to the memory cells. Write level data.

  FIG. 40 is a schematic block diagram showing a circuit configuration enabling a DRAM test method having the above data writing method. In the cell plate potential / P well potential setting circuit 524, the memory cell write data of each memory cell array 620 divided into four is determined, and after performing the write operation, the data is read from each memory cell array and the expected value A defect is detected by comparison. At this time, the number of data read simultaneously can be arbitrarily set by devising the circuit or adopting an array multi-partition architecture. In addition, data comparison of a plurality of data read at the same time has a configuration in which the coincidence detection circuit 526 is provided in the semiconductor memory device 1 so that a plurality of data read from each memory cell array is judged to be inconsistent. Yes.

[Eleventh embodiment]
FIG. 41 is a schematic block diagram showing the configuration of the semiconductor memory device according to the eleventh embodiment of the present invention.

  The difference from the tenth embodiment is that the cell plate potential and the P-well potential can be controlled from the external terminals 580 and 582 via the switching circuits 530 and 532 during the test mode period.

  In the semiconductor memory device 1 configured as described above, when performing a test operation, first, the test mode is designated by an external control signal, so that the switching circuits 530 and 532 are externally connected by the test mode designation signal BI. Terminals 580 and 582 are connected to the cell plate and P well, respectively.

  In an external tester, predetermined memory cell data is written to each memory cell array 620 by controlling the cell plate potential and the P well potential. In this case, even if “H” data is written in the entire memory cell array, both “H” level and “L” level are output as the read data depending on the arrangement of the memory cells as shown in FIG. It will be. For example, when the word line 624a is activated, "H" level data is output from the memory cell 622. When the word line 624b is activated, the bit line connected to the memory cell 622 is "L". "Become level.

  Therefore, when comparing with the expected value, it is necessary to recognize beforehand the inversion state of these data on the external tester side. 41, four bit line pairs, for example, bit line pairs 628a, 628b, 628c, 628d and bit line pairs 628e, 628f, 628g, 628h are connected to the comparator 627 via the selector circuit 625. Therefore, when word line 624a is activated, "H" data is output from memory cell 622 of bit line pair 628a and bit line pair 628b. However, when the word line 624b is activated, “L” data is output from the memory cell 622 of the bit line pair 628a and the bit line pair 628b.

  Therefore, an expected value of data to be read in advance is stored in the external tester, and the value is input to the comparator 627 in advance. Thereafter, the read operation is performed to activate the transistor 626, and the output from the selector circuit 625 is input to the comparator 627, so that the comparison between each bit data and the expected value can be performed in parallel. .

  Each comparator outputs the comparison result with the expected value to the outside via the signal line DV. As described above, by using this test method, it is possible to detect the bit error of each memory cell in parallel and collectively, so that the test time of the semiconductor memory device 1 can be greatly shortened. It becomes.

[Twelfth embodiment]
In the tenth embodiment and the eleventh embodiment, the test time of the semiconductor memory device 1 can be shortened by making it possible to write the test data to the memory cells all at once. . However, the disadvantage of the above test method is that the influence of interference due to the change of the data pattern from the memory cell, that is, the memory cell pattern dependency cannot be detected. This is because only the same data can be written to the memory cells connected to the same cell plate. Usually, memory cells connected to any bit line pair are connected to the same cell plate. is there.

  FIG. 42 is a schematic block diagram showing a configuration of the semiconductor memory device 1 for solving the above problems. The difference from the tenth embodiment is that the wiring connecting the cell plates in common is divided into two groups as described below.

  That is, with respect to the diagonal direction of the bit line pair and the word line connected to each memory cell, the first cell plate wiring 590 is connected to the cell plate of the memory cell belonging to that array every other array.

On the other hand, the second cell plate wiring 592 is commonly connected to the remaining memory cells to which the first cell plate wiring 731 is not connected. The cell plate potential / P well potential setting circuit 524 includes a potential between the first cell plate wiring 590 and the P well wiring 570 (V _CQ1 and V _WC ) and a potential between the second cell plate wiring 592 and the P well wiring 570 (V _CQ2 and V _WC ) can be controlled independently.

  FIG. 43 is a diagram showing a state in the case where test data is collectively written in the memory cells in the semiconductor memory device 1 having such a configuration.

  43, the first cell plate wiring 731 is used for “L” level writing and the second cell plate wiring 732 is used for “H” level writing by the method described in FIGS. 37 and 38. It is a figure which shows the state of the data written in each memory cell when it did. According to FIG. 43, since the cell plates are obliquely separated, the “H” level state and the “L” level state of the memory cells are continued in an oblique stripe shape. Therefore, for memory cells connected to the same word line, “H” level data and “L” level data are alternately arranged, and the data of adjacent memory cells are inverted, so that the memory cells This is a pattern in which the influence on the data due to interference can be detected.

[Thirteenth embodiment]
FIG. 44 is a schematic block diagram showing the configuration of the semiconductor memory device 1 according to the thirteenth embodiment of the present invention.

  In the thirteenth embodiment, the potential between the first cell plate wiring 590 and the P well wiring 570 and the second cell plate wiring 592 controlled by the cell plate potential / P well potential setting circuit 524 in the twelfth embodiment are described. The potential between the P well wiring 570 and the P well wiring 570 can be controlled from the external terminals 580, 581 and 582 as in the eleventh embodiment.

  Except for the fact that different test data can be written to the memory cells connected to the first cell plate 590 and the memory cells connected to the second cell plate 592 independently of each other, Since the embodiment and its operation are the same, detailed description thereof will be omitted.

  With the configuration as shown in FIG. 44, with respect to the memory cells connected to the same word line, the data to the memory cells is arranged so that the data of the “H” level and the “L” level are alternately arranged by the external tester. It becomes possible to write, and it is possible to form a pattern capable of detecting the influence on data due to interference between memory cells.

1 is a schematic block diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention. It is a circuit diagram which shows the 1st example of the internal period setting circuit in 1st Example of this invention. It is a circuit diagram which shows the 2nd example of the internal period setting circuit in 1st Example of this invention. It is a circuit diagram which shows the control gate circuit in 1st Example of this invention. It is a wave form diagram which shows operation | movement of the 1st Example of this invention. It is a schematic block diagram which shows the structure of the semiconductor memory device of the 2nd Example of this invention. It is a schematic block diagram which shows the structure of the period memory circuit and internal period setting circuit of 2nd Example of this invention. It is a circuit diagram which shows the structure of the periodic memory circuit in the 2nd Example of this invention. It is a schematic block diagram which shows the structure of an internal step-down circuit. FIG. 6 is a correspondence diagram between an external power supply voltage and an internal power supply voltage during an acceleration test. It is a schematic block diagram which shows the structure of the semiconductor memory device of the 3rd Example of this invention. It is a block diagram which shows the detail of the control circuit in the 3rd Example of this invention, and a test mode control circuit. It is a schematic block diagram which shows the structure of the semiconductor memory device of the 4th Example of this invention. It is a schematic block diagram which shows the structure of the internal synchronizing circuit in the 4th Example of this invention. FIG. 15 is a partially omitted circuit diagram illustrating a configuration of a clock buffer 91 illustrated in FIG. 14. FIG. 15 is a partially omitted circuit diagram illustrating a configuration of a clock buffer 96 illustrated in FIG. 14. FIG. 15 is a circuit diagram showing a configuration of a phase comparator 92 shown in FIG. 14. 15 is a timing chart showing the operation of the phase comparator 92 shown in FIG. 15 is another timing chart showing the operation of the phase comparator 92 shown in FIG. FIG. 15 is a circuit diagram illustrating configurations of a charge pump 93 and a loop filter 94 illustrated in FIG. 14. FIG. 15 is a partially omitted circuit diagram illustrating a configuration of a voltage control delay circuit illustrated in FIG. 14. 15 is a timing chart showing the operation of the DLL circuit shown in FIG. It is a timing chart which shows the operation | movement of the 4th Example of this invention. It is a schematic block diagram which shows the structure of the internal synchronizing circuit 70 of the 5th Example of this invention. (A) is a schematic block diagram showing the configuration of the fifth embodiment of the present invention, and (b) is a timing chart showing the operation of the fifth embodiment. It is a schematic block diagram which shows the structure of the semiconductor memory device of the 6th Example of this invention. It is a principal part schematic block diagram which shows the structure of the semiconductor memory device of the 6th Example of this invention. It is a timing chart which shows the operation | movement of the 6th Example of this invention. It is a schematic block diagram which shows the structure of the semiconductor memory device of the 7th Example of this invention. It is a schematic block diagram which shows the structure of the semiconductor memory device of the 8th Example of this invention. It is a principal part schematic block diagram which shows the structure of the semiconductor memory device of the 8th Example of this invention. It is a schematic block diagram which shows the structure of the internal multiplication circuit in the semiconductor memory device of the 8th Example of this invention. It is a timing chart which shows the operation | movement of the 8th Example of this invention. It is a schematic block diagram which shows the structure of the parallel test apparatus of the 9th Example of this invention. It is sectional drawing of the memory cell in the semiconductor memory device of the 10th Example of this invention. FIG. 36 is a circuit diagram showing an equivalent circuit of the memory cell shown in FIG. 35. It is sectional drawing which shows the flow of operation | movement of the 10th Example of this invention. It is other sectional drawing which shows the operation | movement flow of the 10th Example of this invention. It is a principal part schematic block diagram which shows the structure of the semiconductor memory device of the 10th Example of this invention. It is a schematic block diagram which shows the structure of the 10th Example of this invention. It is a principal part schematic block diagram which shows the structure of the semiconductor memory device of 11th Example of this invention. It is a principal part schematic block diagram which shows the structure of the semiconductor memory device of 12th Example of this invention. It is a pattern diagram which shows the memory cell memory pattern after the Example of the 12th Example of this invention. It is a principal part schematic block diagram which shows the structure of the semiconductor memory device of 13th Example of this invention. It is a schematic block diagram which shows the structure of the conventional parallel test apparatus. It is a wave form diagram which shows the clock signal in the conventional parallel test apparatus. It is a schematic block diagram which shows the structure of the conventional semiconductor memory device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor memory device, 7 Memory array, 9 Address buffer, 10 Internal address generation circuit, 11 Multiplexer, 12 Row decoder, 13 Column decoder, 14 Sense amplifier + IO block, 15 Input buffer, 16 Output buffer, 18 Control circuit, 19 Test Mode control circuit, 20 internal cycle setting circuit, 26 cycle setting circuit, 30 RAS buffer, 31 CBR detector, 34 test mode setting circuit, 22 control gate circuit, 24 buffer input signal control circuit, 70 internal synchronization circuit, 72 internal multiplication Circuit, 80 test mode setting circuit, 82 test mode control circuit, 84 switching circuit, 91 clock buffer, 92 phase comparator, 93 charge pump, 94 loop filter, 95 voltage control delay circuit, 96 clock buffer §, 98
Dividing circuit, 400 Self-test circuit, 520 Cell plate potential generating circuit, 522 Substrate potential generating circuit, 524 Cell plate / P well potential setting circuit, 530, 532 Switching circuit, 560, 570 Wiring, 580, 582 External terminal, 590 First cell plate wiring, 592 Second cell plate wiring.

Claims (4)

A parallel test apparatus that performs an operation test in synchronization with a plurality of semiconductor memory devices in parallel according to an external clock signal input from the outside,
An internal test clock generating means for receiving the external clock signal and generating a synchronized internal test clock signal for each of the plurality of semiconductor memory devices divided into a plurality of subgroups;
And a data bus line for transmitting the internal test clock signal to each semiconductor memory device in the subgroup.   The internal test clock generating means and the data bus line provided for each subgroup are formed on one test board, and the plurality of semiconductor memory devices are arranged on the one test board. The parallel test apparatus according to 1. A plurality of test boards are provided corresponding to the plurality of subgroups,
The internal test clock generation means and the data bus line provided for each subgroup are formed on a corresponding test board, and each semiconductor memory device in the subgroup is arranged on the corresponding test board. The parallel test apparatus according to claim 1. The plurality of semiconductor memory devices are arranged in a matrix,
The internal test clock generation means is formed on one side of the four sides of the test board for each semiconductor memory device in the subgroup,
The parallel test apparatus according to claim 2 or 3, wherein the internal test clock generation means receives the input of the external clock signal from the one side.

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