JP2005311311A - Semiconductor device, manufacturing method of the semiconductor device, and semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device including a MOS transistor, having a source-to-body tie structure which can efficiently absorb positive holes generated by impact ionization phenomenon, and to provide its manufacturing method. <P>SOLUTION: The semiconductor device comprises an insulating layer 8; a semiconductor layer 10 arranged above the insulating layer 8; a gate insulating layer 20 arranged in the upper part of the semiconductor layer 10; a gate electrode 22 arranged in the upper part of the gate insulating layer 20; a source region 26a and a drain region 26b which are arranged in the semiconductor layer 10; a body region 12 in the semiconductor layer 10 but not belonging to the source region 26a and the drain region 26b; and a body contact region 30, which is arranged so that the source region 26a is divided into a plurality of regions, and joints with the body region 12. The body contact region 30 is a compound, consisting of the semiconductor of the semiconductor layer 10 and a metal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a so-called source body tie structure in which a body region and a source region are connected, a method for manufacturing the semiconductor device, and a semiconductor integrated circuit.

  An insulated gate transistor provided in a semiconductor layer (SOI layer: Silicon On Insulator layer) provided over an insulating layer can realize low power consumption and high-speed operation as compared with the case where it is formed in a bulk semiconductor layer. In recent years, research and development has been progressing as a device. Some insulated gate field effect transistors provided in such an SOI layer have a so-called source / body tie structure in which a source region and a body region are connected. FIG. 8 is a plan view of a semiconductor device including a source / body tie structure MOS transistor according to a conventional example. FIG. 9A is a cross-sectional view taken along line AA in FIG. B) shows a cross-sectional view along the line BB. As an example of a conventional semiconductor device, an n-channel MOS transistor is provided on an SOI layer. The semiconductor device according to the conventional example includes a gate insulating layer 120 and a gate electrode 122 provided on the semiconductor layer 110. The semiconductor layer 110 is provided with a source region 126a and a drain region 126b made of an n-type high concentration impurity region. The source region 126a is divided into a plurality by the body contact region 130. Body contact region 130 is formed of a p-type impurity region and is provided to be joined to body region 112.

Contact portions 140 are provided in the source region 126a and the drain region 126b, respectively. Holes generated by impact ionization below the gate electrode 122 are absorbed by the contact part 140 through the void contact region 130. Since the MOS transistor having the source-body tie structure can absorb holes generated by impact ionization in this way, a semiconductor device with reduced substrate floating effect can be provided.
JP 2002-111005 A

  As described above, in the conventional semiconductor device, impact ions generated under the gate electrode 122 are absorbed from the contact portion 140 from the body region 112 through the body contact region 130. In other words, holes generated by impact ionization are absorbed by moving over a long distance, and under the recent demand for high-speed switching characteristics, the effects of the source / body tie structure may not be fully demonstrated. there were.

  An object of the present invention is to provide a semiconductor device including a MOS transistor having a source / body tie structure capable of efficiently absorbing holes generated by an impact ionization phenomenon and a method for manufacturing the same.

  Another object of the present invention is to provide a semiconductor integrated circuit to which a MOS transistor having a source / body tie structure is applied.

1. Semiconductor device The semiconductor device of the present invention comprises an insulating layer,
A semiconductor layer provided above the insulating layer;
A gate insulating layer provided above the semiconductor layer;
A gate electrode provided above the gate insulating layer;
A source region and a drain region provided in the semiconductor layer;
A body region other than the source region and the drain region in the semiconductor layer;
A body contact region provided so as to divide the source region into a plurality and joined to the body region;
The body contact region is a compound of a semiconductor and a metal in the semiconductor layer.

  According to the semiconductor device of the present invention, the body region and the body contact region form a Schottky junction. Therefore, holes generated by the impact ionization phenomenon when the MOS transistor is operated can be directly absorbed into the body contact region without moving to the contact portion. As a result, holes generated in the body region can be favorably absorbed, and even when a high voltage is applied, a substrate floating effect is reduced, and a semiconductor device with good characteristics can be provided.

  In the present invention, the B layer provided above a specific A layer includes the case where the B layer is provided directly on the A layer and the B layer via another layer on the A layer. Is provided.

  In the semiconductor device of the present invention, the body contact region can be made of a silicide compound. According to this aspect, it is possible to provide a semiconductor device in which the body contact region is formed by a simpler process.

  In the semiconductor device of the present invention, the body region and the body contact region can be Schottky joined.

  In the semiconductor device of the present invention, a silicide layer may be provided at least on the source region, and the source region and the silicide layer may be in ohmic contact.

  The semiconductor device of the present invention may further include a contact portion provided so as to be in contact with the source region and the body contact region.

2. Manufacturing method of semiconductor device The manufacturing method of the semiconductor device of the present invention includes:
(A) forming a gate insulating layer above the semiconductor layer provided on the insulating layer;
(B) forming a gate electrode above the gate insulating layer;
(C) forming a source region and a drain region by introducing an impurity into the semiconductor layer after forming a mask layer covering a predetermined region of the semiconductor layer;
(D) forming a body contact region so as to divide the source region by forming a silicide layer in a region covered by the first mask layer.

  According to the method for manufacturing a semiconductor device of the present invention, the source region and the drain region are formed after forming the mask layer covering the region where the body contact region formed in the subsequent process is formed. Thereafter, a silicide layer is formed in a region covered with the mask layer, thereby forming a body contact region so as to divide the source region. As a result, a semiconductor device in which the body region and the body contact region are Schottky bonded can be manufactured.

  In the method for manufacturing a semiconductor device of the present invention, the step (c) includes forming another silicide layer on the source region and the drain region after forming the source region and the drain region. it can. According to this aspect, another silicide layer different from the silicide layer constituting the body contact region can be formed above the source region and the drain region.

  In the method of manufacturing a semiconductor device according to the present invention, the step (d) can be performed after forming another mask layer covering a region other than the region where the body contact region is formed. According to this aspect, the silicide layer constituting the body contact region and the silicide layer formed above the source region and the drain region can be made separately.

3. Semiconductor integrated circuit The semiconductor integrated circuit of the present invention comprises: The semiconductor device described in the section is used as a pass transistor. When an SOI device according to the prior art is used as a pass transistor, holes generated by impact ions cannot be efficiently extracted to the source electrode, which causes problems in stable operation and high-speed operation of the integrated circuit. The semiconductor device according to the present invention is the above-described source-body tie transistor, and can efficiently extract holes by the provided Schottky junction, so that low power consumption and high-speed operation are possible. . As a result, according to the present invention, it is possible to provide a semiconductor integrated circuit with low power consumption and high speed. In the present invention, a pass transistor is a transistor for connecting one circuit block to the other circuit block.

  An example of the embodiment of the present invention will be described below.

1. First Embodiment (Semiconductor Device)
FIG. 1 is a plan view schematically showing the semiconductor device of the present embodiment, FIG. 2A is a cross-sectional view taken along the line AA in FIG. 1, and FIG. It is sectional drawing along the BB line of FIG.

A gate insulating layer 20 and a gate electrode 22 are formed on the semiconductor layer 10. As shown in FIG. 1, a drain region 26b is provided in one semiconductor layer 10 with a gate electrode 22 interposed therebetween, and a source region 26a is provided in the other semiconductor layer 10. In the source and drain regions 26a and 26b, contact portions 40a and 40b for connecting to wiring (not shown) provided in an upper layer are formed. The source region 26 a is provided by being divided by the body contact region 30. The body contact region 30 is made of a compound of a semiconductor and a metal of the semiconductor layer 10 and is provided to connect the body region 12 and the contact portion 40a. The compound of the semiconductor and the metal constituting the body contact region 30 can be, for example, silicide. At this time, the impurity concentration of the body region is set to 10 ¹⁹ [cm ⁻³ ] or less for adjusting the threshold value of the semiconductor device (transistor). Therefore, the body region 12 which is a semiconductor and the body contact region 30 which is a silicide are separated from each other. Schottky contact.

  A silicide layer 32 is formed on the source region 26a and the drain region 26b. The silicide layer 32 is formed of a material having a work function different from that of the silicide layer that can form the body contact region 30. Specifically, the silicide layer 32 is formed of a material that forms an ohmic contact with the source region 26a.

  The contact portion 40a provided in the source region 26b is provided so as to be in contact with both the source region 26a and the body contact region 30. By taking such an aspect, the one contact part 40a can also serve as absorption of holes from the body contact region 30.

  The advantages of the semiconductor device of this embodiment are as follows.

  In the semiconductor device of the present embodiment, in a source / body tie transistor in which the body region 12 and the source region are connected, the body contact region 30 is formed of a compound of the semiconductor of the semiconductor layer 10 and a metal. In order to compare the advantages of the semiconductor device of this embodiment with the semiconductor device according to the conventional example, for example, an n-channel transistor will be described with reference to FIGS. 10A and 10B show energy band diagrams of the body region 12 and the body contact region 30 of the semiconductor device according to the present embodiment. FIG. 10A shows a state before the gate voltage is applied, and FIG. It is a figure which shows the state after a voltage is applied. FIG. 11 shows energy band diagrams of the body region 112 and the body contact region 130 when the MOS transistor of the semiconductor device according to the conventional example shown in FIGS. 8 and 9 is operated. As shown in FIG. 11, in the semiconductor device according to the conventional example, holes generated by impact ionization at the boundary between the drain region and the body region must run in a long gentle potential. Therefore, even when a source / body tie structure is adopted to suppress the substrate floating effect, sufficient high-speed operation may not be ensured depending on the voltage applied to the drain region. Next, the semiconductor device of this embodiment will be described. As shown in FIG. 10A, a Schottky barrier is formed so that the Fermi level of the low-concentration p-type impurity region that is the body region 12 is balanced with the Fermi level of the silicide layer that is the body contact region 30. When the transistor is operated, the energy band is modulated as shown in FIG. 10B under the influence of the electric field from the gate electrode 22. Therefore, holes generated by impact ionization can flow into the body contact region 30 formed of the silicide layer because there is no barrier. Due to this phenomenon, in the semiconductor device of the present embodiment, holes generated by impact ionization can be favorably absorbed by the body contact region 30. As a result, it is possible to provide a semiconductor device that suppresses the kink effect such as the substrate floating effect and achieves low power consumption and high-speed operability. The above advantages are not limited to the n-channel type.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. In the manufacturing method described below, the numerical values described as specific examples describe the case where an n-channel MOS transistor is formed. 5-7, (A) shows the manufacturing process of the location applicable to FIG. 2 (A), (B) shows the manufacturing process of the location applicable to FIG. 2 (B). .

  (1) First, as shown in FIG. 3, an SOI substrate 10A made of a semiconductor layer 10 provided on an insulating layer 8 on a support substrate 6 is prepared. As the SOI substrate 10A, a case where a substrate in which the insulating layer 8 and the semiconductor layer 10 are stacked on the support substrate 6 is used will be described as an example. However, the SOI substrate 10A is not limited to this, and is not limited to this. A bonded substrate, a laser annealing substrate, or the like can be used. As the semiconductor layer 10, for example, Si, Si—Ge, GaAs, InP, GaP, GaN, or the like can be used. When the thickness of the semiconductor layer 10 of the prepared SOI substrate 10A is different from the desired thickness, the thickness is adjusted by performing sacrificial oxidation or wet etching using hydrofluoric acid.

Next, as shown in FIG. 3, impurities of a predetermined conductivity type are introduced into the semiconductor layer 10 in order to adjust the threshold value. This impurity can be introduced by an ion implantation method. For example, in the case where an n-channel MOS transistor is formed using a single crystal silicon layer having a thickness of 50 nm as the semiconductor layer 10, BF ₂ is used as an impurity and 1 to 5E ¹² / cm ² at an energy of 30 keV. You can type in.

  (2) Next, as shown in FIG. 4, the gate insulating layer 20 and the gate electrode 22 are formed. As the gate insulating layer 20, a silicon oxide film can be formed by, for example, a thermal oxidation method. Next, a conductive layer (not shown) for the gate electrode 22 is formed on the gate insulating layer 20. As the conductive layer, for example, a polycrystalline silicon layer can be deposited to a thickness of about 200 nm. Then, the gate electrode 22 is formed by patterning this conductive layer by a known lithography and etching technique.

  (3) Next, as shown in FIGS. 5A and 5B, a sidewall insulating layer 24 is formed on the side surface of the gate electrode 22. The sidewall insulating layer 24 can be formed as follows, for example. An insulating layer (not shown) is formed over the entire surface of the semiconductor layer 10. As the insulating layer, a silicon nitride film, a silicon oxide film, or a stacked film thereof can be used. Thereafter, by performing anisotropic etching on the insulating layer, the sidewall insulating layer 24 can be formed on the side surface of the gate electrode 22.

  Next, as shown in FIG. 5A, a protective film M1 is formed in a region where the body contact region (see FIG. 1) is formed. At this time, the protective film M1 is not formed in the region where the source region is formed, as shown in FIG. The protective film M1 is formed, for example, by forming an insulating layer (not shown) such as a silicon oxide layer over the entire surface of the semiconductor layer 10 and patterning it.

Next, impurities of a predetermined conductivity type are introduced into the semiconductor layer 10 in order to form the source / drain regions 26a, 26b. For example, using P as an impurity, an amount of about 2E ¹⁵ / cm ² can be implanted with an energy of 10 keV. At this time, no impurity is introduced into the region covered with the protective layer M1. In this ion implantation, an oblique ion implantation method is used to introduce impurities into the semiconductor layer 10 covered with the sidewall insulating layer 24 as shown in FIGS. 5A and 5B. it can. Thereafter, heat treatment is performed to activate the introduced impurities. This heat treatment can be performed, for example, by the RTA method at a processing temperature of 1000 ° C. and a processing time of 30 sec.

  (4) Next, the silicide layer 32 (see FIG. 2) is formed on the source region 26a and the drain region 26b. This process will be described with reference to FIGS. 6 (A) and 6 (B). This step is performed in a state in which the protective film M1 formed in the above step (3) remains. The silicide layer 32 can be formed as follows, for example. First, as shown in FIGS. 6A and 6B, a metal layer 32 a for forming the silicide layer 32 is formed on the entire surface above the semiconductor layer 10. As the metal layer 32a, for example, about 20 nm of Ti is deposited by sputtering. As the silicide layer 32, a material that is in ohmic contact with the source region 26a can be used. By adopting this mode, it is only necessary to introduce an impurity capable of adjusting the threshold value into the body region 12, and it is not necessary to implant a high concentration impurity into the body region 12. The metal layer 32a may be Ti, Co, Ni, Mo, Pt, or Rb.

(5) Next, the first heat treatment is performed to cause the metal layer 32a and the semiconductor layer 10 to undergo a silicidation reaction. Thereby, as shown in FIG. 7, the silicide layer 32 is formed on the source region 26a and the drain region 26b. This first stage heat treatment can be performed, for example, using the RTA method at a processing temperature of 600 ° C. to 700 ° C. Next, the unreacted metal layer 32a is removed. The unreacted metal layer 32a can be removed by wet etching using a mixed solution of NH ₄ OH, H ₂ O ₂ and H ₂ O. Thereafter, a second heat treatment is performed to make the silicide layer 32 more stable and form a low-resistance silicide layer 32. The second-stage heat treatment can be performed under a condition where the treatment temperature is 800 ° C. or higher. Thereafter, the protective film M1 is removed. In this step, since the body contact region is performed while being covered with the protective film M1, the silicide layer 32 is not formed.

  Next, the body contact region 30 (see FIG. 2) is formed. The body contact region 30 is made of a compound of the semiconductor of the semiconductor layer 10 and a metal. As the body contact region 30, for example, a silicide layer can be used. In this embodiment, the case where a silicide layer is formed is described. First, as shown in FIG. 7, a metal layer 34 a is formed on the entire upper surface of the semiconductor layer 10. As the metal layer 34a, for example, Pt can be formed by sputtering. Next, heat treatment for silicidation reaction is performed. As described in the above step (4), the heat treatment for silicidation may be performed by two-step heat treatment. Depending on the material of the metal layer, when only the first-step heat treatment is sufficient, 1 Only the heat treatment at the stage may be used. Thereafter, the unreacted metal layer 34a is removed. The removal of the metal layer 34a can be performed in the same manner as described in the above step (4). The compound constituting the body contact region 30 is preferably a material that can match the Fermi level of the body region 12. More preferably, the material can be in a flat band state with the body region 12 when the MOS transistor is not operated.

  Next, contact portions 40a and 40b (see FIG. 1) are formed on the source region 26a and the drain region 26b. The contact portions 40a and 40b are formed by forming a conductive layer and patterning the conductive layer. At this time, the contact portion 40a formed in the source region 26a is formed so as to be in contact with both the source region 26a and the body contact region 30.

  According to the method of manufacturing the semiconductor device according to the first embodiment, after forming the protective layer (mask layer) M1 covering the region where the body contact region 30 is formed, the source region 26a and the drain region 26b are formed. Done. Thereafter, the semiconductor of the semiconductor layer in the region covered by the protective layer M1 is silicided, thereby forming the body contact region 30 so as to divide the source region 26a. As a result, a semiconductor device in which the body region 12 and the body contact region 30 are joined by a Schottky junction can be manufactured. As a result, as described above, in the source / body tie MOS transistor, it is possible to manufacture a semiconductor device in which the efficiency of absorbing holes generated by the impact ionization phenomenon is improved.

(Modification)
The semiconductor device according to the first embodiment is not limited to the above-described embodiment, and can be modified within the scope of the gist of the present invention. As a modification, for example, the semiconductor device shown in FIGS. 12 is a cross-sectional view schematically showing a semiconductor device according to a first modification, FIG. 13 is a cross-sectional view schematically showing a semiconductor device according to a second modification, and FIG. It is a top view which shows typically the semiconductor device concerning a 3rd modification. 12 and 13 are cross-sectional views showing the same portions as the cross-sectional view of FIG.

  In the semiconductor device according to the first modification, as shown in FIG. 12, an LDD (Light Doped Drain) region 28 is provided between the drain region 26b and the channel region (semiconductor layer 10 under the gate insulating layer 20). be able to. In this aspect, since electric field relaxation is achieved at the boundary between the drain region 26b and the body region 12, it is possible to suppress the occurrence of an impact ionization phenomenon. As a result, generation of holes that cause the substrate floating effect can be suppressed, and a semiconductor device with low power consumption and improved high-speed operability can be provided. Note that the semiconductor device of this aspect is manufactured by introducing impurities of a predetermined conductivity type before forming the sidewall insulating layer 24 in the step (3) of the present embodiment.

  As shown in FIG. 13, the semiconductor device according to the second modification differs from the semiconductor device of the present embodiment in that an extension region 29 is provided between the drain region 26b and the channel region. Is a point. This aspect has an advantage that the short channel effect can be suppressed. Therefore, a finer semiconductor device capable of high-speed operation can be provided. When manufacturing the semiconductor device according to the second modification, impurities of a predetermined conductivity type are introduced before the sidewall insulating layer 24 is formed in the step (3) of the present embodiment. Done.

  As shown in FIG. 14, the semiconductor device according to the third modification is different from the semiconductor device of the present embodiment in the contact portion 40a. The shape of the contact portion 40 a is not particularly limited as long as it is in contact with both the source region 26 a and the body contact region 30. For example, as shown in FIG. 14, the contact portion 40 a may have a shape straddling the body contact region 30.

2. Second Embodiment Next, a second embodiment of the present invention will be described with reference to FIGS. The second embodiment is an example in which the semiconductor device according to the present invention is applied to a semiconductor integrated circuit. This is an example in which the source / body tie type MOS transistor of the present invention is applied to a transistor 50 connecting two inverters schematically showing a semiconductor device. 15 is a plan view showing the layout of the semiconductor device according to the present embodiment, FIG. 16 is a cross-sectional view taken along the line II of FIG. 15, and FIG. 17 is the line II-II of FIG. It is sectional drawing along a line.

  As shown in FIG. 15, the semiconductor device according to the present embodiment includes a first inverter 52, a second inverter 54, and a transistor 50 that connects the first inverter 52 and the second inverter 54. Have The first inverter 52 includes a P-channel MOS transistor 100P and an N-channel MOS transistor 100N.

  The first inverter 52 will be described with reference to FIG. As shown in FIG. 17, semiconductor layers 10 </ b> P and 10 </ b> N in which element formation regions are defined are provided on the insulating layer 8. A P-channel MOS transistor 100P is provided in the semiconductor layer 10P. The P-channel MOS transistor 100P includes a gate insulating layer 102 provided on the semiconductor layer 10, a gate electrode 104 provided on the gate insulating layer 102, and a sidewall 106 provided on a side surface of the gate electrode 104. And an impurity region 108 to be a source region or a drain region. Similarly, an N channel MOS transistor 100N is provided in the semiconductor layer 10N.

  Interlayer insulating layer 60 is provided to cover P channel transistor 100P and N channel transistor 100N. A contact layer 62 is provided on the interlayer insulating layer 60, and a wiring 64 is provided on the interlayer insulating layer 60. Via contact layer 62 and wiring 64, drain region 108 of P-channel MOS transistor 100P and source region 108 of N-channel MOS transistor 100N are connected.

  Next, the MOS transistor 50 that connects the first inverter 52 and the second inverter 54 will be described with reference to FIG. As shown in FIG. 16, the MOS transistor 50 includes a gate insulating layer 20, a gate electrode 22 on the gate insulating layer 20, a side wall 24 on the side surface of the gate electrode 22, and a drain region 26b, as in the transistor shown in FIG. And a body contact region 30.

  According to the semiconductor integrated circuit according to the second embodiment, the first inverter (corresponding to one circuit block) and the second inverter (corresponding to the other circuit block) are included in the present embodiment. The MOS transistors 50 having such a source / body tie structure are connected. Since the MOS transistor 50 has a Schottky junction formed between the body portion and the source electrode as described above (FIG. 10B), holes generated by impact ions can be efficiently extracted to the source electrode side. Therefore, the stable operability and high-speed operability of the two connected inverters can be improved. By using the MOS transistor 50 having such characteristics as a pass transistor connecting a plurality of circuit blocks, it is possible to provide a semiconductor integrated circuit with reduced power consumption and improved high-speed operability.

  The semiconductor device manufacturing method according to the present embodiment can be performed in the same manner as the method described in the section of the semiconductor device manufacturing method according to the first embodiment.

3. Third Embodiment Next, a third embodiment of the present invention will be described with reference to FIG. The third embodiment is an example in which the source-body type MOS transistor described in the first embodiment is applied to a transfer gate transistor of an SRAM. This transfer gate transistor is a so-called pass transistor for connecting a flip-flop circuit and a circuit for driving a memory cell via a word line or a bit line. FIG. 18 shows a circuit diagram of the SRAM cell.

  As shown in FIG. 18, in the SRAM cell, a CMOS type first inverter 52 and a second inverter 54 have their input terminals and output terminals crossed (cross-coupled) with each other. The first inverter 52 includes an N channel MOS transistor 100N and a P channel MOS transistor 100P. Similarly, the second inverter 54 includes an N channel MOS transistor 100N and a P channel MOS transistor 100P. The output terminals of the first inverter 52 and the second inverter 54 are connected to the bit lines BL and / BL via an N channel MOS transistor 50 which is a transfer gate transistor, respectively. This N-channel MOS transistor 50 is the transistor having the source / body tie structure shown in the first embodiment.

  According to the present embodiment, by applying the above-described MOS transistor 50 to a transfer gate transistor that requires good switching characteristics, the electrical signals from the first inverter 52 and the second inverter 54 can be obtained. It can be sent to an external interface circuit (not shown) stably and at high speed. In the third embodiment, the case where the source-body tie transistor according to the first embodiment is used as the transfer gate transistor of the SRAM cell is illustrated, but the present invention is not limited to this. The present invention can be applied to selection transistors such as DRAM and FeRAM.

  In addition, this invention is not limited to embodiment mentioned above, A various deformation | transformation is possible. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

FIG. 2 is a plan view schematically showing the semiconductor device according to the first embodiment. (A) is sectional drawing along the AA line of FIG. (B) is sectional drawing along the BB line of FIG. FIG. 3 is a plan view schematically showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 3 is a plan view schematically showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 3 is a plan view schematically showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 3 is a plan view schematically showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 3 is a plan view schematically showing the manufacturing process of the semiconductor device according to the first embodiment. The top view which shows typically the semiconductor device concerning a prior art example. (A) is sectional drawing along the AA line of FIG. (B) is sectional drawing which followed the BB line of FIG. FIG. 3 is a diagram for explaining the operation of the semiconductor device according to the first embodiment. 8A and 8B illustrate operation of a semiconductor device according to a conventional example. The top view which shows typically the semiconductor device concerning a 1st modification. The top view which shows typically the semiconductor device concerning a 2nd modification. The top view which shows typically the semiconductor device concerning a 3rd modification. FIG. 5 is a plan view showing a layout of a semiconductor integrated circuit according to a second embodiment. FIG. 16 is a cross-sectional view schematically showing a cross section taken along line II in FIG. 15. Sectional drawing which shows typically the cross section along the II-II line | wire of FIG. FIG. 6 is a diagram for explaining a semiconductor integrated circuit according to a third embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 6 ... Support substrate, 8 ... Insulating layer 10, 10P, 10N ... Semiconductor layer, 12 ... Body region, 20 ... Gate insulating layer, 22 ... Gate electrode, 24 ... Side wall insulating layer, 26a ... Source region, 26b ... Drain Region, 28 ... LDD region, 29 ... extension region, 30 ... body contact region, 32 ... silicide layer, 40a, 40b ... contact part, 50 ... MOS transistor, 52 ... first inverter, 54 ... second inverter, 60 DESCRIPTION OF SYMBOLS ... Interlayer insulating layer 62 ... Contact layer 64 ... Wiring 100P ... P channel MOS transistor 100P, 100N ... N channel MOS transistor 102 ... Gate insulating layer 104 ... Gate electrode 106 ... Side wall 108 ... Impurity region ( Source region or drain region

Claims (9)

An insulating layer;
A semiconductor layer provided above the insulating layer;
A gate insulating layer provided above the semiconductor layer;
A gate electrode provided above the gate insulating layer;
A source region and a drain region provided in the semiconductor layer;
A body region other than the source region and the drain region in the semiconductor layer;
A body contact region provided so as to divide the source region into a plurality and joined to the body region;
The body contact region is a semiconductor device which is a compound of a semiconductor and a metal in the semiconductor layer. In claim 1,
The body contact region is a semiconductor device made of a silicide compound. In claim 1 or 2,
The semiconductor device, wherein the body region and the body contact region are in a Schottky junction. In any one of Claims 1-3,
A semiconductor device, wherein a silicide layer is provided at least on the source region, and the source region and the silicide layer are in ohmic contact. In any one of Claims 1-4,
And a contact portion provided in contact with the source region and the body contact region. (A) forming a gate insulating layer above the semiconductor layer provided on the insulating layer;
(B) forming a gate electrode above the gate insulating layer;
(C) forming a source region and a drain region by introducing an impurity into the semiconductor layer after forming a mask layer covering a predetermined region of the semiconductor layer;
(D) A method for manufacturing a semiconductor device, comprising forming a body contact region so as to divide the source region by forming a silicide layer in a region covered with the mask layer. In claim 6,
The method (c) includes forming a silicide layer on the source region and the drain region after forming the source region and the drain region. In claim 6,
(D) is a method of manufacturing a semiconductor device, which is performed after forming another mask layer covering the region other than the region where the body contact region is formed.   A semiconductor integrated circuit, wherein the semiconductor device according to claim 1 is used as a pass transistor.

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