JP2005304218A - Power supply driver device and switching power supply device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a switching power supply device reduced in power loss, improved in responsiveness to a variation in output and reducible in size, and a power supply driver module suitable for the same. <P>SOLUTION: In the module (100) in which power transistors (Q1, Q2) that make currents flow to a coil (L0) and a driver IC (110) that drives them are sealed into one package, and which constitutes the switching power supply device that outputs a voltage obtained by stepping down an input voltage by controlling an output voltage by a PWM method, a power supply voltage (HVCC) of a gate drive circuit (111) that generates a gate drive voltage of the high-side power MOS transistor (Q1), and a power supply voltage (LVCC) of a gate drive circuit (112) that generates a gate drive voltage of the low-side MOS transistor (Q2) are made to individually be set from the outside. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technology effective when applied to a power supply device that generates a DC voltage, and further to a switching regulator that requires a low voltage, a large current output, and excellent response characteristics, for example, a power transistor for switching and driving it TECHNICAL FIELD The present invention relates to a driver module in which a driver IC (semiconductor integrated circuit) that is encapsulated in one package and a technology effective when used for a switching power supply using such a module.

  In recent years, many electronic devices are equipped with a microprocessor as a system control device. In addition, the operating frequency of a microprocessor (hereinafter referred to as CPU) tends to be higher, and the maximum operating current increases with an increase in operating frequency. By the way, in a portable electronic device or the like with a built-in CPU, a method is often adopted in which a battery voltage is stepped down by a switching regulator and an operating current is supplied to the CPU. However, as a switching regulator for such a microcomputer system in recent years. Therefore, there is a demand for a voltage that is low in voltage to be generated and that can output a large current.

  In addition, a module in which a power transistor that supplies current to a coil of a switching regulator and a driver IC that drives the power transistor are enclosed in one package (hereinafter referred to as a power supply driver module) has been proposed. The module incorporating the power transistor and the driver IC has an advantage that the wiring from the driver IC to the power transistor can be shortened, so that the parasitic inductance component can be reduced and the power efficiency can be improved. Therefore, the present inventors examined a power supply driver module having a configuration as shown in FIG. 1 and a step-down switching regulator using the same. In FIG. 1, reference numeral 100 denotes a driver module, 110 denotes a driver IC, and Q1 and Q2 denote power transistors made up of MOSFETs (insulated gate field effect transistors).

  In the power supply driver module having the configuration as shown in FIG. 1, as shown in FIG. 2, a power MOS transistor that supplies current to the coil L0 based on a PWM (pulse width modulation) control pulse PWM supplied from the controller 200. Gate control signals PHG and PLG that complementarily turn on and off Q1 and Q2 are generated inside the driver IC 110. At this time, if the high-level periods overlap due to variations in the delay times of the signals PHG and PLG, a through current flows through the power MOS transistors Q1 and Q2. Therefore, as one method for reliably preventing this through current, the control logic 120 in the driver IC 110 has a gate control in which the high level periods of the gate control signals PHG and PLG do not overlap so as to have a so-called dead time. A system for forming signals PHG and PLG is known.

When the high-side power MOS transistor Q1 is turned on, the voltage LX at the output end rises toward the input voltage Vin, so that the gate-source voltage of Q1 becomes small. At this time, if an N-channel MOS transistor is used as the power MOS transistor Q1, Q1 will not turn on unless a voltage higher than the input voltage Vin by the threshold voltage is applied to the gate terminal. Therefore, a gate strap circuit D1 and a capacitor C1 are connected between the power supply voltage terminal PVCC and the output terminal OUT to operate the gate drive circuit 111 in the previous stage of the power MOS transistor Q1 with the boosted voltage Vboot. Has been done. In addition, as a technique regarding a power supply driver module, for example, there is one described in Non-Patent Document 1.
"ISL6571" data sheets p1 to p10 issued by Intersil

  In the power supply driver module of FIG. 1, the power supply voltages of the previous stage gate drive circuits 111 and 112 that drive the gate terminals of the high-side power MOS transistor Q1 and the low-side power MOS transistor Q2 are common (PVCC), and Q1 , Q2 have the same gate-source voltage Vgs.

  However, as described above, a switching regulator for a microcomputer system is required to be capable of outputting a large current at a low voltage, for example, 1.2V based on a voltage such as 12V. In a step-down switching regulator that generates a low voltage, the duty of the PWM control pulse is as small as 10%. Therefore, the time during which the low-side power MOS transistor Q2 is turned on is considerably longer than the high-side power MOS transistor Q1. Therefore, in such a low voltage, large output current switching regulator, it is important to suppress the power loss in the low-side power MOS transistor Q2 in order to improve the efficiency of the regulator.

  In order to suppress conduction loss among power losses in the power MOS transistor, it is preferable to increase the drive voltage to lower the on-resistance of the MOS. However, increasing the drive voltage increases the on / off switching time. In other words, since there is a trade-off between reducing conduction loss and shortening the on / off switching time, it is important to find an optimal gate drive voltage. On the other hand, from the viewpoint of reducing the size of the regulator, it is desirable to increase the switching frequency, but if the switching frequency is increased, the switching loss increases. In order to reduce this switching loss and improve the module responsiveness to changes in output, it is effective to increase the operating speed of the power MOS transistor.

  Further, in the driver module of FIG. 1, the high-side power MOS transistor Q1 and the low-side power MOS transistor Q2 are not necessarily the same semiconductor chip. Depending on the use conditions, power MOS transistors Q1 and Q2 having characteristics suitable for the high side and the low side are modularized. Therefore, the optimum gate drive voltage may be different between the high-side power MOS transistor Q1 and the low-side power MOS transistor Q2.

  In order to solve the above-described problems, the present inventors have made it possible to separately set the gate drive voltage of the high-side power MOS transistor Q1 and the gate drive voltage of the low-side power MOS transistor Q2. A conclusion was reached that this was desirable. However, in the power supply driver module having the configuration as shown in FIG. 1 examined by the present inventors, the gate drive voltages of the high-side and low-side power MOS transistors are the same, so that the efficiency is improved sufficiently and the response is improved. It became clear that there was a defect that could not be achieved.

An object of the present invention is to provide a power supply driver module suitable for a switching power supply device with a low voltage and a large current output.
Another object of the present invention is to provide a highly efficient switching power supply device with less power loss and a power supply driver module suitable for the switching power supply device.
Still another object of the present invention is to provide a switching power supply device that is excellent in response characteristics to changes in output and can be reduced in size, and a power supply driver module suitable for the switching power supply device.
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

Outlines of representative ones of the inventions disclosed in the present application will be described as follows.
That is, a switching power supply device that encloses a power transistor that passes current through a coil as an inductor and a driver IC that drives the same, and outputs a voltage obtained by stepping down the input voltage by switching the power transistor using a PWM method. Power supply of a gate drive circuit that generates a gate drive voltage of a high-side power MOS transistor among two power MOS transistors connected in series between two power supply voltage terminals The power supply voltage of the gate drive circuit that generates the gate drive voltage of the low-side power MOS transistor is set separately from the outside, or the power supply voltage of the gate drive circuit that generates the gate drive voltage of the high-side power MOS transistor is set Fixed and low power Supply voltage of the gate drive circuit for generating a gate drive voltage of the OS transistor is obtained by configured to be variably from outside.

  Here, a specific method for setting the power supply voltage of each gate drive circuit for generating the gate drive voltage of the high-side power MOS transistor and the gate drive voltage of the low-side power MOS transistor to a different voltage from the outside is as follows. A method of separately providing a terminal for applying a power supply voltage from the power supply or a method of providing a power supply circuit such as a series regulator inside to provide a terminal for controlling the voltage output from the regulator from the outside.

  According to the above-described means, the gates of the high-side power MOS transistor and the low-side power MOS transistor can be driven with optimum voltages, respectively, thereby reducing the loss in the power MOS transistor and using this driver module. Thus, the power efficiency of the power supply device can be improved. In particular, in a low-voltage, large-current output switching power supply device in which power loss in the low-side power MOS transistor is a problem, the gate drive voltage of the low-side power MOS transistor is increased to reduce the on-resistance, thereby reducing the power loss. Can be reduced.

  Also, a constant voltage circuit and a level shift circuit for converting the signal level are provided in the driver IC, and a gate drive circuit for generating a gate drive voltage for the high-side power MOS transistor and a gate drive for the low-side power MOS transistor. A transistor having a relatively low gate withstand voltage is used for each MOS transistor constituting the gate driving circuit for generating a voltage.

  According to the above-described means, it becomes possible to operate at high speed by using a transistor having a low gate breakdown voltage, and it is possible to improve the response characteristics with respect to the change in output, and the switching loss does not increase so much even if the switching frequency is increased. Thus, it is possible to output a sufficiently large current while reducing the size of the power supply device using a coil with low inductance.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
That is, according to the present invention, a power supply driver module suitable for a switching power supply device with a low voltage and a large current output can be realized.
Further, according to the present invention, a highly efficient switching power supply device with less power loss and a power supply driver module suitable for the switching power supply device can be realized.

  Furthermore, according to the present invention, it is possible to realize a switching power supply device that is excellent in response characteristics with respect to changes in output and can be reduced in size, and a power supply driver module suitable for the switching power supply device.

Preferred embodiments of the present invention will be described below with reference to the drawings.
FIG. 3 shows a first embodiment of a power supply driver module according to the present invention and a step-down switching regulator to which the power supply driver module is applied. In this specification, a plurality of semiconductor chips and discrete components are combined with metal wiring such as bonding wires so that each component plays a predetermined role, so that it can be handled as one electronic component. This is called a module. Although not particularly limited, the power supply driver module is enclosed in a package such as ceramic to be a finished product.

  The switching regulator of FIG. 3 has a pair of source / drain paths connected in series between a voltage input terminal P0 to which a DC voltage Vin supplied from a DC power source such as a battery is input and a ground point (GND). Are connected between the output terminal OUT of the module 100 and a load. The power supply driver module 100 has a built-in power MOS transistor Q1, Q2 as an output transistor and a driver IC 110 for driving the gate terminals of the transistors Q1, Q2. A coil L0 as an inductor, a smoothing capacitor C0 connected between the load-side node n1 of the coil L0 and the ground point, and an output voltage connected in parallel with the smoothing capacitor C0. Detecting resistors R1 and R2 in series and the potential at the connection node n2 of the resistors R1 and R2 And a like PWM control pulse PWM generates and supplies the controller (PWM control circuit) 200 to the driver IC110 based on FB.

  In the power supply driver module 100 of the embodiment, the power MOS transistors Q1 and Q2 formed as semiconductor chips separate from the driver IC 110 are incorporated together with the driver IC 110. The power MOS transistors Q1 and Q2 are both N-channel MOSFETs (field effect transistors). This is because an N-channel MOSFET can operate at a higher speed with a lower on-resistance than a P-channel MOSFET.

  The driver IC 110 includes a gate drive circuit 111 that generates a gate drive voltage for the power MOS transistor Q1 on the input voltage Vin side (referred to as the high side) and a gate drive for the power MOS transistor Q2 on the ground potential GND side (referred to as the low side). Based on the PWM control pulse PWM from the controller 200 and the gate drive circuit 112 that generates the voltage, the power MOS transistors Q1 and Q2 are simultaneously turned on and have a dead time and are complementary. The control logic 120 generates the input signals PHG and PLG of the gate driving circuits 111 and 112 so as to be turned on and off.

  In this embodiment, an external power supply terminal P1 for applying the power supply voltage HVCC of the gate drive circuit 111 to the driver IC 110, an external power supply terminal P2 for applying the power supply voltage LVCC of the gate drive circuit 112, External power supply terminals P3 for applying the power supply voltage VCC of the control logic 120 are provided. A diode D1 is connected between the terminal P1 of the power supply voltage HVCC and the power supply terminal of the gate drive circuit 111 that generates the gate drive voltage of the high-side power MOS transistor Q1, and the cathode terminal ( The external terminal P4 connected to the power supply terminal of the gate drive circuit 111 is provided, and the capacitor C1 is connected between the external terminal P4 and the output terminal OUT of the module, whereby the diode D1 and the capacitive element C1. Constitutes a bootstrap circuit that boosts the power supply voltage of the gate drive circuit 111.

  The gate driving circuits 111 and 112 cause the high-side power MOS transistor Q1 and the low-side power MOS transistor Q2 to be complementarily turned on and off according to the pulse width of the input PWM control pulse PWM, thereby causing the coil L0 to move. A current is passed, and a voltage Vout corresponding to the duty ratio of the PWM control pulse is output. For example, when the input voltage Vin is 12V and the output voltage is 1.2V in the switching regulator of the embodiment, the duty of the PWM control pulse PWM is about 10%.

  In the switching regulator of this embodiment, in the control logic 120 in the driver IC 110, based on the PWM control pulse PWM supplied from the controller 200, the gate control signals PHG, PLG is generated. At this time, if a high level period overlaps due to variations in delay time of the signals PHG and PLG, a through current flows through the power MOS transistors Q1 and Q2. , PLG gate control signals PHG, PLG having a dead time are formed so as not to overlap the high-level periods of PLG (see FIG. 5).

  In the module of the present embodiment, the external power supply terminals P1 and P2 for supplying the power supply voltages HVCC and LVCC of the gate drive circuits 111 and 112 are separately provided, so that the high-side and low-side power MOS transistors Q1 are provided. , Q2 can be optimized separately. The power supply voltages HVCC and LVCC are determined so as to obtain a desired operating speed and reduce loss according to the characteristics of the power MOS transistors Q1 and Q2 to be used.

  FIG. 5 shows voltage waveforms at various parts in the switching regulator to which the module of this embodiment is applied. As is apparent from comparison with FIG. 2 showing voltage waveforms at various parts in the regulator of FIG. 1 examined prior to the present invention, in the regulator of FIG. 1, the high-side and low-side power MOS transistors Q1, Q2 are connected between the gate and source. In this embodiment, the voltages HG-LX and LG applied to the same PVCC are HVCC and LVCC, respectively.

  FIG. 4 shows a modification of the embodiment of FIG. In this modified example, the diode D1 constituting the bootstrap circuit is connected as an external element instead of being built in the chip of the driver IC 110, and thus the embodiment of FIG. In comparison, there is an advantage that the number of external terminals to be provided in the driver IC 110 can be reduced.

  In the embodiment of FIG. 3, the power supply voltage HVCC for the gate drive circuit 111 and the power supply voltage VCC for the control logic 120 are separated, but a series for generating the power supply voltage HVCC for the gate drive circuit 111 inside the chip. A power supply circuit such as a regulator is provided, and the power supply circuit generates a voltage HVCC of a desired level from the power supply voltage VCC and supplies the voltage HVCC to the gate drive circuit 111 via the diode D1 constituting the bootstrap circuit. Also good. With this configuration, the number of external terminals provided in the driver IC 110 can be reduced as compared with the embodiment of FIG.

FIG. 6 shows a second embodiment of the power supply driver module according to the present invention.
In the second embodiment, constant voltage circuits 131 to 133 and level shift circuits 141 to 143 are provided in the gate drive circuits 111 and 112 in the first embodiment, and the control logic 120 and the gate drive circuits 111, 112 is provided with a power supply circuit 130 for generating power supply voltages such as level shift circuits 141 to 143 and logic gate circuits INV1 and INV2. The power supply circuit 130 is composed of a series regulator or the like, and generates an internal power supply voltage Vcc_LL having a level of, for example, 5V necessary for the operation of the internal circuit based on a power supply voltage VCC such as 12V supplied from the outside, and controls it. This is supplied to the logic 120, the level shift circuits 141 to 143 in the gate drive circuits 111 and 112, and the inverters INV1 and INV2. The internal power supply voltage Vcc_LL is set to a potential that is higher by Vref (for example, 5 V) than the ground potential GND.

  As described above, the constant voltage circuits 131 to 133 and the level shift circuits 141 to 143 are provided because the use of elements having a low gate breakdown voltage as the MOS transistors constituting the gate drive circuits 111 and 112 increases the circuit speed. This is because of this. Hereinafter, the reason will be described in detail. Since the constant voltage circuit and the level shift circuit itself can be the same as a known circuit, illustration and description of a specific circuit are omitted. The constant voltage circuits 131 to 133 may be series regulators, or may be constituted by constant voltage power supply circuits using operational amplifiers, Zener diodes, or the like.

  In order to reduce the loss in the power MOS transistors Q1 and Q2, it is necessary to increase the gate voltages of Q1 and Q2 to lower the on-resistance. For this purpose, relatively high power supply voltages HVCC and LVCC are applied to the gate drive circuits 111 and 112, respectively. It is desirable to operate. Further, in order to reduce the switching loss in the power MOS transistors Q1 and Q2, it is necessary to shorten the on / off switching time. For this purpose, the MOS transistors at the output stage of the gate drive circuits 111 and 112 are operated at high speed. Is good.

  However, as is well known, in the MOS transistor, when the gate oxide film is thickened to increase the gate breakdown voltage, the threshold voltage Vth increases and the current capability decreases. In order to compensate for this, the size (gate width) may be increased, but if this is done, the gate capacitance increases, and high-speed operation cannot be performed. For high-speed operation, it is preferable to use a thin gate oxide film, that is, a low breakdown voltage MOS transistor.

  On the other hand, for the switching regulator, in order to shorten the on / off switching time of the power MOS transistors Q1 and Q2, a transistor having a low withstand voltage but capable of operating at high speed is used as an output stage MOS transistor of the gate drive circuits 111 and 112. The power supply voltages HVCC and LVCC of the gate drive circuits 111 and 112 are preferably increased so that a high voltage can be output in order to reduce the on-resistance of the power MOS transistors Q1 and Q2. In this case, the gate drive circuits 111 and 112 There is a possibility that a high voltage is applied to the gate of the MOS transistor in the output stage and the gate insulating film is destroyed. Therefore, the driver IC of this embodiment uses low withstand voltage (5 to 6 V) transistors for the MOS transistors MP1 to MN2 in the output stage of the gate drive circuits 111 and 112, as well as constant voltage circuits 131 to 133 and a level shift circuit. 141 to 143 are provided in the gate drive circuits 111 and 112 so that the output MOS can output a high voltage and operate at high speed without causing gate breakdown.

  In the driver IC of this embodiment, the high-side gate drive circuit 111 includes an inverter INV1 that receives the signal PHG from the control logic 120, and a first level shift circuit 141 that level-shifts the output signal of the inverter INV1. And a second level shift circuit 142, a P-channel MOS transistor MP1 connected in series between the power supply voltage terminal HVCC and the output terminal OUT, and receiving a signal level-shifted by the first level shift circuit 141 at the gate terminal; An N-channel MOS transistor MN1 that receives a signal level-shifted by the second level shift circuit 142 at its gate terminal, and a voltage Vboot boosted by the bootstrap circuit (D1, C1) as a reference, a predetermined level Vref. The first level A constant voltage circuit 131 that supplies the second level shift circuit 141, a constant voltage circuit 132 that generates a voltage higher than the output voltage Vout (level LX) by a predetermined level Vref and supplies the voltage to the second level shift circuit 142. It is comprised by. The present invention is not limited to the circuit configuration described above, and the present invention is effective even if there is a pre-driver circuit or the like before the output stage composed of MP1 and MN1, respectively.

  The low-side gate drive circuit 112 includes an inverter INV2 that receives the signal PLG from the control logic 120, a third level shift circuit 143 that level-shifts the output signal of the inverter INV2, a power supply voltage terminal LVCC, and a ground point. A P-channel MOS transistor MP2 connected in series to GND and receiving the signal level-shifted by the third level shift circuit 143 at the gate terminal and an N-channel MOS transistor MN2 receiving the output signal of the inverter INV2 at the gate terminal; A constant voltage circuit 133 that generates a voltage lower than the power supply voltage LVCC applied to the external terminal by a predetermined level Vref and supplies the voltage to the third level shift circuit 143 is formed. The present invention is not limited to the circuit configuration described above, and the present invention is effective even if there is a pre-driver circuit or the like before the output stage composed of MP2 and MN2, respectively.

  The first level shift circuit 141 converts a signal having an amplitude Vcc_LL to GND into a signal having an amplitude Vboot to (Vboot−Vref). Further, the second level shift circuit 142 converts a signal having an amplitude Vcc_LL to GND into a signal having an amplitude (LX + Vref) to LX. Further, the third level shift circuit 143 converts the signal having the amplitude Vcc_LL to GND into a signal having the amplitude LVCC to (LVCC−Vref). As a result, the gate-source voltages MP1_Vgs, MN1_Vgs, MP2_Vgs, and MN2_Vgs of the MOS transistors MP1 to MN2 in the output stage of the gate drive circuits 111 and 112 are limited to Vref regardless of the power supply voltages HVCC and LVCC as shown in FIG. Thus, even if the MOS transistors MP1 to MN2 are low breakdown voltage elements, it is possible to prevent the gate breakdown.

FIG. 8 is a circuit configuration diagram of a third embodiment of the power supply driver module according to the present invention, and FIG. 9 is a timing chart thereof.
In this embodiment, the high-side gate drive voltage in the second embodiment of FIG. 6 is a fixed voltage determined by the constant voltage circuit 130, and only the low-side gate drive voltage can be set by the power supply voltage LVCC. Only the low-side gate drive circuit 112 is provided with a constant voltage circuit 133 so that the level shift circuit 143 shifts the level of the gate control signal HLG of the output stage MOS transistor MP2. Only the low-side gate drive voltage can be set when the module input voltage Vin is 12V and the output voltage of the regulator is low, such as 1.2V. The duty of the PWM control pulse is about 10%. Therefore, the time during which the low-side power MOS transistor Q2 is turned on becomes longer, and it is more important to reduce the loss in Q2 than in Q1.

  Therefore, in this embodiment, an element having a size larger than that of the high-side power MOS transistor Q1 is used as the low-side power MOS transistor Q2. At the same time, the MOS transistors MP2 and MN2 at the output stage of the low-side gate drive circuit 112 are composed of elements that can operate at high speed with low withstand voltage (5 to 6V), and apply a relatively high voltage LVCC to the gate drive circuit 112. However, the gate terminal of the low-side power MOS transistor Q2 is driven at a relatively high voltage to reduce the on-resistance and the switching loss while preventing gate breakdown. Since the high-side gate drive circuit 111 operates with a relatively low internal power supply voltage Vcc_LL supplied from the power supply voltage 130, the MOS transistors MP1 and MN1 in the output stage can be configured with low breakdown voltage elements. However, since the power supply voltage on the low potential side of the MOS transistors MP1 and MN1 in the output stage is the output potential (potential of the output terminal OUT) LX, the gate drive signal IHG of MP1 and MN1 must also be based on LX. A level shift circuit 144 is provided.

  FIG. 10 shows a modification of the embodiment of FIG. In this modification, a power supply device is configured by a driver IC 110, power MOS transistors Q1 and Q2, a controller 200, and the like without taking the form of a module. This modification has an advantage that an element having optimum characteristics for the system can be selected and used as the power MOS transistors Q1 and Q2. More specifically, for example, a power MOS transistor is selected by selecting a power MOS transistor having such a characteristic that the loss is minimized according to the ratio between the input voltage Vin to be used and the generated voltage Vout, that is, the duty ratio of the PWM control pulse PWM. Thus, the power efficiency of the power supply device can be improved.

FIG. 11 shows a fourth embodiment of the power supply driver module according to the present invention.
In this embodiment, in the module of the embodiment of FIG. 8, the output potential LX and the gate voltage LG of the low-side power MOS transistor Q2 are fed back to the control logic 120 and the signal FBHG in the middle of the gate drive circuit 111 is controlled. By feeding back to the logic 120 and adjusting the timings of the control signals PHG and PLG of the gate drive circuits 111 and 112 according to changes in these signals, the high-side and low-side power MOS transistors Q1 and Q2 are simultaneously turned on. It is possible to reliably avoid a situation where a through current flows due to a state.

  Here, a method of feeding back only the output potential LX to the control logic 120 and adjusting the timings of the control signals PHG and PLG of the gate drive circuits 111 and 112 according to the change of the output potential is also conceivable. However, in the step-down switching regulator as described above, when the load suddenly becomes lighter, the falling speed of the output potential LX becomes considerably slower than the rising speed, thereby changing the output voltage Vout. There is a problem that it ends up.

  Therefore, in this embodiment, a delay circuit (or timer circuit) 121 that delays the signal FBHG fed back from the middle of the gate drive circuit 111 by a predetermined time is provided in the control logic 120, and an output node is connected to the NAND gate G1. The potential LX of the signal FBHG is compared with the timing of the signal FBHG delayed by a predetermined time, and one input of the AND gate G2 is changed in accordance with the earlier change of the falling timing to control the gate driving circuit 112. The timing of the signal PLG is adjusted.

  As a result, when the load suddenly becomes light, the timing of the control signal PLG of the gate drive circuit 112 can be advanced so that the fall of the output potential LX can be accelerated, thereby suppressing the fluctuation of the output voltage Vout and stabilizing. There is an advantage that can be made. Since the rise of the output potential LX is relatively fast regardless of the magnitude of the load, the output of the gate drive circuit 112, that is, the low level is connected to the other inverting input terminal of the AND gate G3 that receives the PWM control pulse PWM from the controller 200 as one input. The gate voltage LG of the side power MOS transistor Q2 is input, and the control signal PHG of the high side gate drive circuit 111 is raised at the fall timing.

  In the present embodiment, the signal FBHG that is extracted from the middle of the gate drive circuit 111 and fed back to the control logic 120 is a signal that is shifted to the LX reference by the level shift circuit 144 and is based on the ground potential GND reference of the control logic. A level shift circuit 145 is provided for matching with other input signals. The potential LX of the output node is a signal having an amplitude of the input voltage Vin to the ground potential GND, and a voltage clamp circuit 146 is provided to match the amplitude of other signals of the control logic.

  FIG. 12 shows a modification of the control logic 120 in the power supply driver module of the fourth embodiment. In this modified example, the signal FBHG is clamped with reference to the ground potential in the control logic 120 together with the level shift circuit 145 and the delay circuit 121 for level-shifting the signal FBHG drawn from the middle of the gate drive circuit 111 and fed back. Voltage clamp circuit 146, and the output of voltage clamp circuit 146 and the output of delay circuit 121 are input to NAND gate G1. By connecting the signal FBHG to the voltage clamp circuit 146, the output potential LX and the gate drive voltage of the high-side power MOS transistor can be monitored simultaneously, and the output potential LX has a large noise such as ringing due to the influence of an external constant. Even in this case, a stable signal can be transmitted to the NAND gate G1.

  FIG. 13 shows a specific circuit example of the voltage clamp circuit 146.

  The voltage clamp circuit of this embodiment includes an input-side CMOS inverter composed of MOS transistors M11 and M12 connected in series between a power supply terminal to which the voltage Vcc_LL generated by the regulator 130 is applied and a ground point GND. The MOS transistor M13 connected between the signal input terminal and the gate terminal of M11, the MOS transistor M14 and the capacitor Ci connected in parallel between the gate terminal of M11 and the ground point GND, and the drain of M12 A MOS transistor M15 connected in series between the terminal and the ground point GND, and MOS transistors M16 and M17 connected in series between the power supply terminal and the ground point GND, and having a gate terminal connected to the drain terminal of M12. And an output side CMOS inverter. The output signal Vo of the output side CMOS inverter circuit is fed back to the gate terminal of the MOS transistor M15.

  MOS transistors M11 and M16 are P-channel MOSFETs, and MOS transistors M12, M13, M15 and M17 are N-channel MOSFETs. The MOS transistor M13 is a high breakdown voltage LDMOS (Laterally Diffused MOSFET) in which terminals are diffused laterally on a semiconductor chip. The MOS transistor M14 is a depletion type MOS transistor, and functions as a current source for supplying a predetermined current by coupling a gate and a source. This current source may be composed of an enhancement type N-channel MOSFET in which a predetermined voltage is applied to the gate, or may be composed of a high resistance element composed of a polysilicon layer or the like. The capacitor Ci can be composed of a MOS capacitor. The gate capacitance is configured using, for example, MOSFETs corresponding to several tens of MOS transistors M12, and is formed to have a capacitance value of about 1 pF.

  In the input side CMOS inverter circuit of the clamp circuit of this embodiment, when the output signal Vo is at a low level, the MOS transistor M15 is turned off and has a first logic threshold value corresponding to the conductance ratio of the MOS transistors M11 and M12. To be done. In contrast, when the output signal Vo is at a high level, the MOS transistor M15 is turned on, the MOS transistors M12 and M15 are in parallel, and the CMOS inverter circuit on the input side is lower than the first logic threshold value. Changes to a logical threshold. Thus, the hysteresis transfer characteristic is such that when the input signal Vi changes from the low level to the high level, the high first logic threshold value is obtained, and when the input signal Vi changes from the high level to the low level, the low second logic threshold value is obtained. Have to have. Accordingly, when the input signal Vi becomes equal to or higher than the first logic threshold voltage, the output signal Vo does not change unless the input signal Vi becomes lower than the second logic threshold voltage lower than the first logic threshold voltage. Even if noise occurs near the logic threshold voltage, the output signal Vo does not change in response to it, so that a stable output can be obtained.

  The voltage clamp circuit of FIG. 13 converts an input signal Vi having an amplitude such as Vboot-LX into a signal having an amplitude of Vcc_LL-GND and outputs the signal. At this time, the power supply voltage Vcc_LL is supplied to the gate of the MOS transistor M13 as a voltage to be limited. As a result, when the input voltage Vi is higher than the power supply voltage Vcc_LL (Vi = Vboot), M13 is turned on, the source voltage of M13, that is, the gate voltage of the MOS transistor M12 is clamped to Vcc_LL−Vthn, and the output side inverter The output Vo becomes high level (Vcc_LL). Here, Vthn is a threshold voltage of the MOS transistor M13.

  When the input signal Vi is low level (LX) and LX <VthL, the output Vo of the output side inverter is low level (GND). Here, VthL is the logic threshold voltage of the input side inverters (M11, M12). In this embodiment, in order to perform the voltage clamping operation by the MOS transistor M13 stably and at high speed, a direct current component can be passed between the source terminal of M13 and the ground potential of the circuit. A MOS transistor M14 is provided as a simple current source.

  Further, in this embodiment, the drain voltage of M14 is applied to the base of the transistor M13. The reason is that if the base of the MOS transistor M13 is connected to the input terminal side, the M13 becomes an element having the same function as a diode connected in the direction from the input terminal to the input side inverter, and the voltage clamping effect is This is because it cannot be obtained. Although the base of the MOS transistor M13 may be connected to the ground point GND, the threshold voltage Vthn increases due to the substrate bias effect, and the input signal Vi becomes the logic threshold value of the input inverter circuit at the next stage. Failure to do so may cause malfunction. Therefore, in this embodiment, the MOS transistor M13 is formed in a P-type well region electrically isolated from the substrate, and the P-type well (channel region) is connected to the drain terminal of M14 which is the output side of the MOS transistor M13. It is connected. Thereby, a clamp operation can be performed stably. The clamped potential is discriminated by the inverter on the input side, transmitted to the inverter on the output side, and output. As a result, a clamp output can be obtained at a higher speed than a normal clamp circuit.

  When the capacitor Ci = 0, that is, when the capacitor Ci does not exist, the clamp voltage rises by about 7.8 V due to the coupling by the parasitic capacitance Cds between the source and drain of the MOS transistor M13, and then the current source (M14 ) And discharge is gradually reduced. That is, the input capacity of the CMOS inverter circuit composed of the MOS transistors M11 and M12 is small, and the voltage is increased by about 7.8V due to the voltage division with the parasitic capacity Cds.

  When the capacitance value of the capacitor Ci is Ci = 0.5 pF, Ci = 1 pF, Ci = 1.5 pF, and Ci = 2 pF, the clamp voltage is about 3.6 V, 3 V, 2. It is suppressed like 6V and 2.2V. Since the capacitor Ci is also an input capacitance of the input circuit, if the capacitance value is increased, the charging time to the clamp voltage through the MOS transistor M13 or the discharging time at the falling time becomes longer. Possible Ci is set to 1 pF. In the coupling operation with the parasitic capacitance Cds, by appropriately setting the capacitance value of the capacitor Ci, the rising and falling of the clamp voltage can be accelerated using the coupling.

FIG. 14 shows a configuration example of a multiphase system as a power supply system using a plurality of power supply driver modules according to the present invention.
The power supply system of FIG. 14 is a system suitable for a load that requires a current larger than the current supply capability of one switching regulator. In FIG. 14, reference numerals 100A, 100B,..., 100N are attached to a power supply driver module with a built-in power MOS having the configuration shown in FIGS. 3, 4, 6, 8, and 11. The plurality of power driver modules are PWM-controlled by one controller 200. In addition, current sense resistors Rs1, Rs2,... RsN are connected in series to the coils L1, L2,... LN through which currents are passed by the respective power driver modules, and the voltages at both terminals of these sense resistors are connected. VCS11, VCS12; VCS21, VCS22;... VCSN1, VCSN2 are fed back to the controller 200, and the output Vout is also fed back to the controller 200. The voltage to be fed back may be a voltage divided by resistors R1 and R2 provided between the output terminal and the ground as shown in FIG.

  The controller 200 determines the duty of the PWM control pulse as a whole system based on the fed back output voltage Vout so that the voltage becomes the target voltage, and the voltage across the terminals of the current sense resistors Rs1, Rs2,. VCS11, VCS12; VCS21, VCS22;... According to VCSN1, VCSN2, the individual PWM control pulses PWM_1, of the power supply driver modules 100A to 100N so that the currents flowing through the coils L1, L2,. PWM_2, ... is configured to generate and control PWM_N. As a result, it is possible to avoid an excessive current flowing through some of the coils to cause damage or deterioration of characteristics.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in the embodiment, the external terminal for supplying the power supply voltage of the gate drive circuit for generating the gate drive voltage of the low-side power MOS transistor is used as the gate drive circuit for generating the gate drive voltage of the high-side power MOS transistor. The driver IC chip is provided with a power supply circuit such as a series regulator and a terminal or register for controlling the voltage output from the regulator from the outside. It is also possible to generate the power supply voltage of the other gate drive circuit from the power supply voltage of the gate drive circuit and to arbitrarily set the voltage level from the outside according to the system.

  In the above description, the step-down switching regulator that uses the invention made by the present inventor as the power supply device of the electronic equipment, which is the field of use behind the invention, has been described. It can also be used widely.

It is a circuit block diagram which shows the structural example of the power supply driver module examined prior to this invention, and the pressure | voltage fall type switching regulator to which it is applied. 2 is a timing chart showing timing of signals in a module in the regulator of FIG. 1 is a circuit configuration diagram showing a first embodiment of a power supply driver module according to the present invention and a configuration example of a step-down switching regulator to which the first embodiment is applied. FIG. 5 is a circuit configuration diagram showing a modification of the power supply driver module of the first embodiment of FIG. 3. It is a timing chart which shows the timing of the signal in the module in the regulator of FIG. It is a circuit block diagram which shows the 2nd Example of the power supply driver module which concerns on this invention, and the structural example of the pressure | voltage fall type switching regulator to which it is applied. It is a timing chart which shows the timing of the signal in the module in the regulator of FIG. It is a circuit block diagram which shows the 3rd Example of the power supply driver module which concerns on this invention, and the structural example of the pressure | voltage fall type switching regulator to which it is applied. It is a timing chart which shows the timing of the signal in the module in the regulator of FIG. FIG. 10 is a circuit configuration diagram showing a modification of the power supply driver module of the third embodiment of FIG. 8. It is a circuit block diagram which shows the 4th Example of the power supply driver module which concerns on this invention, and the structural example of a pressure | voltage fall type switching regulator to which it is applied. It is a logic block diagram of the control logic which shows the modification of the power supply driver module of 4th Example of FIG. It is a circuit block diagram which shows the specific circuit example of a voltage clamp circuit. It is a block diagram which shows the structural example of the multiphase system as a power supply system which uses multiple power supply driver modules concerning this invention.

Explanation of symbols

100 Power Driver Module 110 Driver IC
111, 112 Gate drive circuit 120 Control logic 121 Delay circuit (timer circuit)
130 Internal power supply circuit 131-133 Constant voltage circuit 141-145 Level shift circuit 200 Controller Q1, Q2 Power MOS transistor C1 Bootstrap capacitance D1 Bootstrap diode L0 Inductor (coil)

Claims (16)

A power supply driver device having a power transistor for passing a current to an inductor and a driver IC for driving the power transistor, and outputting a voltage obtained by stepping down the input voltage by switching the power transistor using a pulse width modulation (PWM) method.
Comprising two power transistors connected in series between first and second power supply voltage terminals;
Of the two power transistors, the power supply voltage of the first gate drive circuit that generates the gate drive voltage of the power transistor on the first power supply voltage terminal side and the gate drive voltage of the power transistor on the second power supply voltage terminal side are A power supply driver device, wherein the power supply voltage of the second gate drive circuit to be generated can be set separately. The driver IC is enclosed in one package,
The driver IC is
A first external terminal capable of arbitrarily setting the power supply voltage of the first gate driving circuit from the outside;
A second external terminal capable of arbitrarily setting the power supply voltage of the second gate drive circuit from the outside;
The power supply driver device according to claim 1, further comprising: A control logic circuit for generating an input signal of the first gate driving circuit and an input signal of the second gate driving circuit so that conduction periods of the two power transistors do not overlap;
The power supply driver device according to claim 2, further comprising a third external terminal that supplies a power supply voltage of the control logic circuit from outside. The two power transistors and the driver IC are enclosed in one package,
The power supply driver device is
A first external terminal capable of arbitrarily setting the power supply voltage of the first gate driving circuit from the outside;
A second external terminal capable of arbitrarily setting the power supply voltage of the second gate drive circuit from the outside;
The power supply driver device according to claim 1, comprising: A power driver device that outputs a voltage obtained by stepping down an input voltage by switching a power transistor in a PWM method by enclosing a power transistor that passes current through an inductor and a driver IC that drives the power transistor in a single package,
A power supply voltage of a gate drive circuit including two power transistors connected in series between the first and second power supply voltage terminals and generating a gate drive voltage of at least the power transistor on the second power supply voltage terminal side is A power supply driver device that is variable from the outside of a package.   6. The power supply driver device according to claim 5, further comprising an external terminal capable of arbitrarily setting a power supply voltage of the second gate drive circuit from the outside. The control logic circuit that generates the input signal of the first gate drive circuit and the input signal of the second gate drive circuit and the external terminal are separately provided so that the conduction periods of the two power transistors do not overlap. An internal power supply circuit that generates an internal power supply voltage based on a power supply voltage supplied from a third external terminal provided,
Generating a boosted voltage based on a potential of a connection node of the two power transistors to which the inductor is connected, from a power supply voltage generated by the internal power supply circuit;
The control logic circuit is operated by a power supply voltage generated by the internal power supply circuit,
The power supply driver device according to claim 6, wherein the first gate driving circuit is configured to be operated by the boosted voltage and a power supply voltage generated by the internal power supply circuit. An internal power supply circuit that generates an internal power supply voltage based on the power supply voltage supplied from the third external terminal;
A first level conversion circuit for converting a level of a signal generated by the control logic circuit and supplied to the first gate drive circuit;
A second level conversion circuit for converting the level of a signal generated by the control logic circuit and supplied to the second gate drive circuit;
A constant voltage circuit that generates a constant voltage lower than the voltage by a predetermined potential with reference to the power supply voltage supplied from the external terminal;
The internal power supply voltage and the constant voltage generated by the constant voltage circuit are configured to be applied to the second gate drive circuit and the second level conversion circuit,
The internal power supply voltage or a voltage higher than the predetermined potential is not applied to the gate of the MOS in the output stage of the second gate drive circuit regardless of the power supply voltage supplied from the external terminal. 7. The power supply driver device according to 6.   9. The power supply driver device according to claim 8, wherein output potential differences between the internal power supply voltage and the power supply generated by the constant voltage circuit are substantially equal.   The output stage of the first gate driving circuit is operated by a voltage boosted from the power supply voltage generated by the internal power supply circuit with reference to the potential of the connection node of the two power transistors to which the inductor is connected. The power supply driver device according to claim 1, wherein the power supply driver device is configured as described above.   9. The power supply driver device according to claim 1, wherein a diode element constituting a booster circuit for generating the boosted voltage is formed in the driver IC.   The power supply driver device according to claim 11, further comprising an external terminal connected to a capacitor element forming a booster circuit for generating the boosted voltage.   The power supply driver device according to any one of claims 1 to 12, an inductor connected to the power supply driver device, a smoothing capacitor for storing a current passed through the inductor, and a voltage generated in the smoothing capacitor. And a control device that generates and supplies a PWM control pulse to be supplied to the power driver device. A power supply driver semiconductor integrated circuit that outputs a voltage obtained by stepping down an input voltage by complementary switching control of two power transistors that are connected in series between the first and second power supply voltage terminals and flow current through an inductor by a PWM method. A circuit,
Of the power transistors, the power supply voltage of the first gate drive circuit that generates the gate drive voltage of the power transistor on the first power supply voltage terminal side and the gate drive voltage of the power transistor on the second power supply voltage terminal side are A power supply driver semiconductor integrated circuit, wherein the power supply voltage of the second gate drive circuit to be generated can be set separately from the outside. A power supply driver device sealed in one package,
A first power supply voltage terminal;
A second power supply voltage terminal;
A first output transistor having a source / drain path coupled between an output terminal, the first power supply voltage terminal, and the output terminal;
A second output transistor having a source / drain path coupled between the output terminal and the second power supply voltage terminal;
A first gate driving circuit for supplying a driving voltage to the gate electrode of the first output transistor;
A second gate driving circuit for supplying a driving voltage to the gate electrode of the second output transistor;
A first external terminal coupled to the first gate driving circuit and supplied with a power supply voltage of the first gate driving circuit;
A second external terminal coupled to the second gate driving circuit and supplied with a power supply voltage of the second gate driving circuit;
A power supply driver device comprising: The first output transistor is a first semiconductor chip,
The second output transistor is a second semiconductor chip,
16. The power driver device according to claim 15, wherein the first and second gate driving circuits are third semiconductor chips.

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