JP2005300579A - Display apparatus and layout method in display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that complication of layout is increased due to increase of the number of wirings and opening ratio of a pixel is reduced when a pixel electrode of a unit pixel is divided into more sub pixel electrodes for improving deviation of a center of gravity of sub pixel electrodes or complicated layout of the sub pixel electrodes is adopted, in an active matrix type liquid crystal display wherein gradation is expressed by an area gradation method. <P>SOLUTION: In the active matrix type liquid crystal display wherein gradation is expressed by the area gradation method, layouts each having a plurality of sub pixel electrodes 31 to 35 are made upside-down for every one unit pixel e.g. in the horizontal direction, so that the layouts each having the plurality of sub pixel electrodes 31 to 35 are made different between unit pixels adjacent to each other in the horizontal direction, and the layouts each having the plurality of sub pixel electrodes 31 to 35 are made irregular between the adjacent unit pixels. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a display device and a layout method in the display device, and more particularly to a display device that expresses a gray scale by an area gray scale method and a layout method of unit pixels in the display device.

  In a display device in which a large number of unit pixels including an electro-optic element are arranged in a matrix, for example, a liquid crystal display device using a liquid crystal cell as an electro-optic element, the cost of the entire system is reduced, the power consumption is reduced, and the yield rate is improved. An area gray scale method is known as a driving method made for the purpose. In this area gradation method, a pixel electrode serving as a display region of a unit pixel is divided into a plurality of area-weighted subpixel electrodes, and gradation display is performed by combining the areas of these subpixel electrodes (for example, , See Patent Document 1).

  An example of the shape and layout of a plurality of subpixel electrodes is shown in FIGS. The unit pixels having the shape and layout of the sub-pixel electrodes are regularly arranged in a matrix so that the layout of the plurality of sub-pixel electrodes is the same among the unit pixels. However, as is apparent from FIGS. 10 and 11, since the center of gravity of the sub-pixel electrode of the most significant (MSB) bit is biased with respect to the center of the unit pixel, depending on the display data, the vertical direction, the horizontal direction, or the oblique direction There is a high probability of occurrence of false contours and stripes, and the influence is also great. For this reason, conventionally, as shown in FIG. 12 or FIG. 13, by adopting a configuration in which the pixel electrode of the unit pixel is divided into a larger number of sub-pixel electrodes or a complicated layout of the sub-pixel electrodes is adopted. The deviation of the center of gravity of the pixel electrode has been improved from a microscopic viewpoint (see, for example, Patent Document 2).

JP-A-10-68331 JP 2002-333870 A

  However, in the above-described conventional technology, the number of wirings increases as the number of subpixel electrodes increases, so the complexity of the layout increases, and the number of parts to be divided increases as the number of subpixel electrodes increases. As the number of portions increases, the number of portions that can be removed by the etching process at the time of division increases, resulting in a problem that the aperture area ratio of the pixel decreases. In addition, although the influence of false contours and stripes in the vertical, horizontal or diagonal directions that occur when returning to a macro viewpoint is reduced, the sub-pixel electrode of the most significant bit is always adjacent between the upper, lower, left and right unit pixels. Therefore, there is a problem that the appearance frequency of false contours and stripes in the vertical direction, the horizontal direction, or the oblique direction increases.

  The present invention has been made in view of the above problems, and the object of the present invention is to prevent false contours or stripes in the vertical, horizontal, or diagonal directions while suppressing a decrease in the aperture area ratio of the unit pixel. It is an object of the present invention to provide a display device and a layout method in the display device that can reduce the influence and the appearance probability.

  In order to achieve the above object, according to the present invention, unit pixels obtained by dividing a pixel electrode into a plurality of area-weighted sub-pixel electrodes are two-dimensionally arranged in a matrix, and gradation is obtained by an area gradation method. In the display device to be expressed, a configuration is adopted in which the plurality of sub-pixel electrodes in the unit pixel are laid out differently between adjacent unit pixels in at least one of the horizontal direction and the vertical direction.

  In the display device having the above configuration, the plurality of subpixel electrodes are laid out so as to be different between adjacent unit pixels in the horizontal direction, the vertical direction, or both the horizontal and vertical directions, so that the plurality of subpixel electrodes are provided between the adjacent unit pixels. Due to the irregular layout, the vertical and horizontal directions depend on the display data, without having to divide the pixel electrode of the unit pixel into a larger number of sub-pixel electrodes or adopt a complicated layout of the sub-pixel electrodes. Alternatively, it is possible to reduce the influence and appearance probability of a false contour or stripe pattern in an oblique direction.

  According to the present invention, it is not necessary to divide the pixel electrode of the unit pixel into a larger number of sub-pixel electrodes or to have a complicated layout of the sub-pixel electrodes, thereby reducing the aperture area ratio of the unit pixel. While suppressing, it is possible to reduce the influence and the probability of appearance of false contours and stripes in the vertical direction, horizontal direction or diagonal direction.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a system block diagram showing an outline of the configuration of a display device to which the present invention is applied. Here, as an example, an active matrix liquid crystal display device using a liquid crystal cell as an electro-optical element of a pixel will be described as an example.

  As is apparent from FIG. 1, the active matrix type liquid crystal display device according to this embodiment includes a pixel array unit 11, an interface (I / F) 12, a timing generator (TG) 13, a vertical drive circuit 14, and a horizontal drive circuit 15. And a driver circuit integrated type in which an interface 12, a timing generator 13, a vertical drive circuit 14, and a horizontal drive circuit 15 which are drive circuits of the pixel array unit 11 are integrally provided on the same substrate as the pixel array unit 11. It becomes the composition of.

  In the pixel array unit 11, pixels 20 including liquid crystal cells as electro-optical elements are two-dimensionally arranged in a matrix on a transparent insulating substrate, for example, a first glass substrate (not shown), and m rows of the pixels 20 are arranged. In the arrangement of n columns, scanning lines 16-1 to 16-m are wired for each row, and signal lines 17-1 to 17-n are wired for each column. The first glass substrate is disposed opposite to the second glass substrate with a predetermined gap, and a liquid crystal material is sealed between the first glass substrate and the display panel 18 is configured. .

  A master clock mck, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync are input to the display panel 18 from the outside, and are supplied to the interface 12. The interface 12 converts (boosts) the level of the master clock mck, the horizontal synchronization signal Hsync, and the vertical synchronization signal Vsync having the voltage amplitude of the external power source into the voltage amplitude of the internal power source necessary for driving the liquid crystal, and the master clock MCK, horizontal synchronization. The signal HD and the vertical synchronization signal VD are supplied to the timing generator 13.

  The timing generator 13 generates a vertical start pulse VST and a vertical clock pulse VCK based on the master clock MCK, the horizontal synchronization signal HD, and the vertical synchronization signal VD, and supplies the vertical start pulse VST and the vertical clock pulse VCK to the horizontal drive circuit 14. A pulse HCK is generated and applied to the horizontal drive circuit 15, and a common potential (counter electrode potential) VCOM applied to each pixel in common with respect to the counter electrode of the liquid crystal cell, a control pulse FRP in phase with the common potential VCOM, and a reverse phase A control pulse XFRP is generated and applied to the pixel array unit 11.

  The vertical drive circuit 14 is disposed, for example, on the right side of the pixel array unit 11. Here, the configuration in which the vertical drive circuit 14 is arranged on the right side of the pixel array unit 11 is shown as an example, but the vertical drive circuit 14 is arranged on the left side of the pixel array unit 11 or on both the left and right sides of the pixel array unit 11. It is also possible to adopt a configuration in which The vertical drive circuit 14 is configured by a shift register, a buffer circuit, and the like. When the vertical start pulse VST is given, the vertical drive circuit 14 sequentially outputs the vertical scanning pulses φV1 to φVm in synchronization with the vertical clock pulse VCK. The pixels 20 are sequentially selected in units of rows by giving them to the scanning lines 16-1 to 16-m.

  For example, 6-bit R (red), G (green), and B (blue) digital image data is supplied to the horizontal drive circuit 15. The horizontal drive circuit 15 applies signal lines 17-1 to 17- for each pixel 20, for each pixel, or for all the pixels at the same time for each pixel 20 in a row selected by vertical scanning by the vertical drive circuit 14. Write the display data via n.

[Pixel circuit]
FIG. 2 is a block diagram illustrating an example of a configuration of a pixel circuit provided for each pixel 20. As is apparent from FIG. 2, the pixel circuit has a pixel configuration with an SRAM function having three switch elements 21 to 23, a latch unit 24, and a liquid crystal cell 25. FIG. 3 is a timing chart for explaining the operation of the pixel circuit.

  The switch element 21 has one end connected to the signal line 17 (17-1 to 17-n), and is turned on (closed) when a vertical scanning pulse φV (φV1 to φVm) is applied from the vertical drive circuit 14. The display data SIG supplied via the signal lines 17 (17-1 to 17-n) is taken in. The latch unit 24 includes inverters 241 and 242 connected in parallel in opposite directions, and holds (latches) a potential corresponding to the display data SIG captured by the switch element 21.

  One of the switch elements 22 and 23 is turned on in accordance with the polarity of the holding potential of the latch unit 24, and the liquid crystal cell 25 in which the common potential VCOM is applied to the counter electrode is in phase with the common potential VCOM. The control pulse FRP or the anti-phase control pulse XFRP is applied to the pixel electrode. As is apparent from FIG. 3, when the holding potential of the latch unit 24 is negative polarity, the pixel potential of the liquid crystal cell 25 is in phase with the common potential VCOM, so that black display is performed, and the holding potential of the latch unit 24 is positive polarity. In this case, since the pixel potential of the liquid crystal cell 25 is in a phase opposite to the common potential VCOM, white display is performed.

  FIG. 4 is a circuit diagram showing a specific circuit example of the pixel circuit. In the figure, parts corresponding to those in FIG.

  In FIG. 4, the switch element 21 includes, for example, an Nch MOS transistor Qn10 having a source / drain connected to the signal line 17 (17-1 to 17-n) and a gate connected to the scanning line 16 (16-1 to 16-m). It is. The switch element 22 is a transfer switch in which an Nch MOS transistor Qn11 and a Pch MOS transistor Qp11 are connected in parallel to each other. The switch element 22 is a transfer switch in which an Nch MOS transistor Qn12 and a Pch MOS transistor Qp12 are connected in parallel to each other.

  Inverter 241 is a CMOS inverter in which the gates and drains of NchMOS transistor Qn13 and PchMOS transistor Qp13 are connected in common. Inverter 242 is a CMOS inverter in which the gates and drains of NchMOS transistor Qn14 and PchMOS transistor Qp14 are connected in common.

  Pixels 20 having pixel circuits based on the above circuit configuration are rotated in the horizontal direction and the vertical direction and arranged in a matrix. In addition to the scanning lines 16 (16-1 to 16-m) for each row and the signal lines 17 (17-1 to 17-n) for each column, the control pulses FRP, Control lines 25 and 26 for transmitting XFRP and power lines 27 and 28 for the positive power supply VDD and the negative power supply VSS are wired for each column.

  As described above, in the active matrix liquid crystal display device according to this embodiment in which a large number of pixels with a SRAM function (pixel memory) 20 having a latch unit 24 that holds a potential corresponding to display data are arranged in a matrix, In order to realize multi-bit colorization of the pixel memory, an area gray scale method that divides the pixel electrode serving as the display region of the pixel 20 into a plurality of area-weighted sub-pixel electrodes, The selected pixel potential is energized to the area-weighted sub-pixel electrode (corresponding to the reflective plate in the reflective type, and equivalent to the transmissive window in the transmissive type), and the gradation is expressed by a combination of the weighted areas.

  In the active matrix type liquid crystal display device according to this embodiment using this area gradation method, the plurality of subpixel electrodes divided by area weighting are naturally selected as appropriate according to the gradation to be displayed. Will be driven. Therefore, the pixel circuits having the configurations shown in FIGS. 2 and 4 are separately provided for each of the plurality of subpixel electrodes.

  In the active matrix liquid crystal display device having such a configuration, in the present invention, a plurality of sub-pixel electrodes defining the display area of the unit pixel 20 are arranged in the horizontal direction (left-right direction in FIG. 1) and the vertical direction (up-down direction in FIG. 1). The layout is characterized in that at least one of the adjacent unit pixels is laid out differently. Hereinafter, examples of the layout of the sub-pixel electrodes will be described.

  The shapes of the plurality of subpixel electrodes are basically the same for each unit pixel 20. In addition, since the active matrix liquid crystal display device according to the present embodiment is color-compatible as described above, three pixels adjacent in the horizontal direction correspond to the three primary colors R, G, and B (in any order). (Hereinafter, these three pixels are referred to as pixels 20R, 20G, and 20B). These three pixels (unit pixels) 20R, 20G, and 20B constitute one pixel, and each of the pixels 20R, 20G, and 20B is a sub-pixel.

(Example 1)
FIG. 5 is a plan pattern diagram illustrating the layout of the sub-pixel electrodes according to the first embodiment. Here, only one pixel, that is, three pixels 20R, 20G, and 20B adjacent to each other is illustrated. One pixel is developed in the horizontal direction and the vertical direction to form the pixel array unit 11.

  In FIG. 5, the pixels 20R, 20G, and 20B have pixel electrodes divided into, for example, five sub-pixel electrodes 31 to 35 (here, only the pixel 20R is given a sign for simplification of the drawing). ing. The sub-pixel electrodes 31 to 35 have a rectangular shape having the same width as the pixel width, and are set to an area ratio corresponding to digital display data. Specifically, the area of the subpixel electrode 31: the area of the subpixel electrode 32: the area of the subpixel electrode 33: the area of the subpixel electrode 34: the area of the subpixel electrode 35 = 1: 2: 4: 8: 16 Is set.

  In the pixel 20R, the least significant bit (LSB) subpixel electrode 31 is located at the bottom of the figure, and the most significant bit (MSB) subpixel electrode 35 is located at the top of the figure. They are laid out in order. The pixel 20B skipped by one pixel has the same layout as the pixel 20R. In contrast, in the pixel 20G located between the pixels 20R and 20B, the sub-pixel electrode of the most significant bit 35 is located at the bottom of the figure, and the sub-pixel electrode 31 of the least significant bit is located at the top of the figure. Thus, the layout is performed in order from the upper bit.

  These three pixels 20R, 20G, and 20B are developed as one pixel in the horizontal direction and the vertical direction. As a result, in the matrix-like pixel arrangement, the layout of the sub-pixel electrodes 31 to 35 is inverted up and down for each unit pixel (pixels 20R, 20G, and 20B individually) in the horizontal direction (left-right direction in the figure). . As described above, the sub-pixel electrodes of the three pixels 20R, 20G, and 20B are appropriately driven according to the digital display data by the pixel circuit having the configuration shown in FIGS. Specifically, for example, each of the sub pixel electrodes 31 to 35 of the pixel 20R is supplied with a pixel potential corresponding to the digital display data from the pixel circuits 20-1 to 20-5.

  In this way, in the active matrix liquid crystal display device that expresses gradation by the area gradation method, the layout of the plurality of subpixel electrodes 31 to 35 is vertically inverted for each unit pixel in the horizontal direction, so that the plurality of subpixel electrodes Since the plurality of subpixel electrodes 31 to 35 have an irregular layout between adjacent unit pixels by laying out 31 to 35 so as to be different between adjacent unit pixels in the horizontal direction, It is possible to reduce the influence and the appearance probability of horizontal or oblique false contours and stripes. In other words, it is not necessary to divide the pixel electrode of the unit pixel into a larger number of subpixel electrodes or to have a complicated layout of the subpixel electrodes. The purpose of the period can be achieved.

  In the first embodiment, the layout of the sub-pixel electrodes 31 to 35 is vertically inverted for each unit pixel in the horizontal direction, but is inverted vertically for each unit pixel in the vertical direction (the vertical direction in the figure). Alternatively, it may be inverted one unit pixel at a time in both horizontal and vertical directions. Further, the number of division of the pixel electrode of the unit pixel into the sub-pixel electrodes is not limited to 5, and the division number can be arbitrarily set.

  In the first embodiment, the pixel electrode of the unit pixel is divided into a plurality of subpixel electrodes in the vertical direction, and the layout of the plurality of subpixel electrodes is inverted vertically for each unit pixel. It is also possible to divide the pixel electrodes into a plurality of sub-pixel electrodes in the left-right direction and to invert the layout of the plurality of sub-pixel electrodes left and right for each unit pixel.

(Example 2)
FIG. 6 is a plan pattern diagram illustrating the layout of the sub-pixel electrodes according to the second embodiment. Here, the layout of sub-pixel electrodes for two upper and lower pixels, that is, six pixels is illustrated. These two pixels are expanded in the horizontal direction and the vertical direction to form the pixel array unit 11. In FIG. 6, for simplification of the drawing, a pixel circuit that applies a pixel potential corresponding to digital display data to each subpixel electrode of a unit pixel is not shown, and only the layout of the subpixel electrode is omitted. Is illustrated.

  In FIG. 6, the pixels 20R, 20G, and 20B have pixel electrodes divided into, for example, five sub-pixel electrodes 41 to 45 (here, for simplification of the drawing, only the pixel 20R is provided with a reference numeral). ing. The sub-pixel electrodes 41 to 45 have a rectangular shape in which some pixel electrodes have a width different from the pixel width, and are set to an area ratio corresponding to digital display data. Specifically, the area of the subpixel electrode 41: the area of the subpixel electrode 42: the area of the subpixel electrode 43: the area of the subpixel electrode 44: the area of the subpixel electrode 45 = 1: 2: 4: 8: 16 Is set.

  In the pixel 20R, for example, the upper 3 bits of sub-pixel electrodes 43, 44, and 45 are laid out in order from the bottom of the figure. Here, the upper 2 bits of the sub-pixel electrodes 44 and 45 have rectangular cutouts at adjacent portions on one side of the pixel. Then, the sub-pixel electrodes 41 and 42 of lower 2 bits are arranged in the regions of the notches of the sub-pixel electrodes 44 and 45. The pixel 20B skipped by one pixel has the same layout as the pixel 20R. On the other hand, the pixel 20G located between the pixels 20R and 20B has a layout obtained by rotating the layout of the sub-pixel electrodes 41 to 45 of the pixel 20R by 180 degrees.

  These three pixels 20R, 20G, and 20B are developed as one pixel in the horizontal direction and the vertical direction. As a result, in the matrix pixel arrangement, the layout of the sub-pixel electrodes 41 to 45 is rotated by 180 degrees for each unit pixel (pixels 20R, 20G, and 20B individually) in the horizontal direction.

  As described above, in the active matrix liquid crystal display device that expresses gradation by the area gradation method, the layout of the plurality of subpixel electrodes 41 to 45 is rotated and inverted by 180 degrees for each unit pixel in the horizontal direction. Since the pixel electrodes 41 to 45 are laid out so as to be different between adjacent unit pixels in the horizontal direction, the plurality of sub-pixel electrodes 41 to 45 have an irregular layout between the adjacent unit pixels. It is possible to reduce the influence and appearance probability of false contours and striped patterns in the direction, horizontal direction or oblique direction. That is, it is not necessary to divide the pixel electrode of the unit pixel into a larger number of sub-pixel electrodes or to have a complicated layout of the sub-pixel electrodes. The purpose of the period can be achieved.

  In the second embodiment, the layout of the sub-pixel electrodes 41 to 45 is rotated 180 degrees for each unit pixel in the horizontal direction, but may be rotated 180 degrees for each unit pixel in the vertical direction. Alternatively, it may be rotated 180 degrees for each unit pixel in both the horizontal and vertical directions. Further, the number of division of the pixel electrode of the unit pixel into the sub-pixel electrodes is not limited to 5, and the division number is arbitrarily set.

  Further, in addition to the configuration in which the layout of the sub-pixel electrodes 41 to 45 is rotated by 180 degrees for each unit pixel in the horizontal direction, a configuration in which the layout is vertically inverted for each unit pixel in the vertical direction as shown in FIG. It is also possible. In addition, in the case of adopting a configuration that rotates 180 degrees for each unit pixel in the vertical direction, it may be configured to be inverted up and down for each unit pixel in the horizontal direction.

  Furthermore, in the second embodiment, the layout of the sub-pixel electrodes 41 to 45 is configured to rotate 180 degrees for each unit pixel in at least one of the horizontal direction and the vertical direction, but the rotation angle is limited to 180 degrees. Instead, it is possible to set an arbitrary rotation angle such as 90 degrees or 270 degrees.

(Example 3)
FIG. 8 is a plan pattern diagram illustrating the layout of the sub-pixel electrodes according to the third embodiment. The shape of the sub-pixel electrode according to the third embodiment is the same as the shape of the sub-pixel electrode according to the second embodiment. Also here, the layout of the sub-pixel electrodes for the upper and lower 2 pixels and 6 pixels is shown. These two pixels are expanded in the horizontal direction and the vertical direction to form the pixel array unit 11.

  In the second embodiment, the layout of the sub-pixel electrodes 41 to 45 is configured to be rotated by an arbitrary angle for each unit pixel in at least one of the horizontal direction and the vertical direction. As in the first embodiment, the layout of the subpixel electrodes 41 to 45 is vertically inverted for each unit pixel in the horizontal direction.

  In this way, in the active matrix liquid crystal display device that expresses gradation by the area gradation method, the layout of the plurality of subpixel electrodes 41 to 45 is inverted vertically for each unit pixel in the horizontal direction, and the plurality of subpixel electrodes Since the plurality of sub-pixel electrodes 41 to 45 have an irregular layout between the adjacent unit pixels by laying out 41 to 45 so as to be different between the adjacent unit pixels in the horizontal direction, It is possible to reduce the influence and the appearance probability of horizontal or oblique false contours and stripes. That is, it is not necessary to divide the pixel electrode of the unit pixel into a larger number of sub-pixel electrodes or to have a complicated layout of the sub-pixel electrodes. The purpose of the period can be achieved.

  In the third embodiment, the layout of the sub-pixel electrodes 41 to 45 is inverted upside down for each unit pixel in the horizontal direction. However, as shown in FIG. It may be inverted, or may be inverted vertically for each unit pixel only in the vertical direction.

  In the above embodiment, the case where the present invention is applied to an active matrix liquid crystal display device in which pixels with SRAM functions are two-dimensionally arranged in a matrix has been described as an example. However, other memory functions (for example, DRAM) functions are described. An active matrix liquid crystal display device in which attached pixels are two-dimensionally arranged in a matrix, and not only a liquid crystal display device using a liquid crystal cell as an electro-optical element of a pixel, but also an organic EL (electroluminescence) element as an electro-optical element of a pixel. ) Applicable to all display devices that express gradation by the area gradation method, such as organic EL display devices using elements.

1 is a system block diagram showing an outline of a configuration of an active matrix liquid crystal display device to which the present invention is applied. It is a block diagram which shows an example of a structure of the pixel circuit provided for every pixel. 6 is a timing chart for explaining the operation of the pixel circuit. It is a circuit diagram which shows the specific circuit example of a pixel circuit. 3 is a plan pattern diagram illustrating a layout of subpixel electrodes according to Embodiment 1. FIG. 6 is a plan pattern diagram illustrating a layout of sub-pixel electrodes according to Embodiment 2. FIG. 10 is a plan pattern diagram illustrating a layout of subpixel electrodes according to a modification of Example 2. FIG. 10 is a plan pattern diagram illustrating a layout of sub-pixel electrodes according to Embodiment 3. FIG. 10 is a plan pattern diagram illustrating a layout of subpixel electrodes according to a modification of Example 3. FIG. It is a plane pattern figure which shows the shape and layout of the several sub pixel electrode which concerns on the prior art example 1. FIG. It is a plane pattern figure which shows the shape and layout of the several sub pixel electrode which concerns on the prior art example 2. FIG. It is a plane pattern figure which shows the shape and layout of the several sub pixel electrode which concerns on the prior art example 3. FIG. It is a plane pattern figure which shows the shape and layout of the several sub pixel electrode which concerns on the prior art example 4. FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Pixel array part, 12 ... Interface (I / F), 13 ... Timing generator (TG), 14 ... Vertical drive circuit, 15 ... Horizontal drive circuit, 16 (16-1 to 16-m) ... Scanning line, 17 (17-1 to 17-n) ... signal line, 18 ... display panel, 20, 20R, 20G, 20B ... unit pixel, 20-1 to 20-5 ... pixel circuit, 24 ... latch part, 25 ... liquid crystal cell, 31-35, 41-45 ... Sub-pixel electrodes

Claims (6)

A display device in which unit pixels obtained by dividing a pixel electrode into a plurality of area-weighted sub-pixel electrodes are two-dimensionally arranged in a matrix,
The display device, wherein a layout of the plurality of sub-pixel electrodes in the unit pixel is different between adjacent unit pixels in at least one of a horizontal direction and a vertical direction. The plurality of sub-pixel electrodes have the same shape in each of the unit pixels;
The display device according to claim 1, wherein the layout of the plurality of subpixel electrodes is inverted vertically or horizontally for each unit pixel in at least one of the horizontal direction and the vertical direction. The plurality of sub-pixel electrodes have the same shape in each of the unit pixels;
The display device according to claim 1, wherein the layout of the plurality of subpixel electrodes is rotated 90 degrees or 180 degrees for each unit pixel in at least one of the horizontal direction and the vertical direction. A layout method in a display device in which unit pixels obtained by dividing a pixel electrode into a plurality of area-weighted sub-pixel electrodes are two-dimensionally arranged in a matrix,
A layout method in a display device, wherein the plurality of sub-pixel electrodes in the unit pixel are laid out so as to be different between adjacent unit pixels in at least one of a horizontal direction and a vertical direction. The plurality of sub-pixel electrodes have the same shape in each of the unit pixels;
5. The layout method for a display device according to claim 4, wherein the plurality of subpixel electrodes are laid out by being inverted vertically or horizontally for each unit pixel in at least one of a horizontal direction and a vertical direction. The plurality of sub-pixel electrodes have the same shape in each of the unit pixels;
The layout method for a display device according to claim 4, wherein the plurality of subpixel electrodes are laid out by being rotated 90 degrees or 180 degrees for each unit pixel in at least one of a horizontal direction and a vertical direction.

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