JP2005285017A - Duplication controller system, controllers thereof, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make appropriate a system operation verification before main working operation. <P>SOLUTION: A control section 15 of an active CPU module 1 executes and controls equalization processing during a multi-equalization mode regardless of modes. Thus, an equalization data transfer is performed each time a fixed cycle program is run, even during a single equalization mode but level information of a fixed cycle program that is run at that time, is given to the transfer data. A control section 25 of a reserve CPU module 2 discards transfer data other than a bottom level, by referring to level information of transfer data during the single equalization mode, thereby realizing equalization processing substantially during the single equalization mode. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a duplex controller system.

  Currently, in plants, factories, etc., FA (factory automation) is realized by using many controllers such as programmable controllers for sequence control of machines such as machine tools and measuring devices.

  In such a programmable controller system, there is a case where the CPU module (controller main body) has a standby redundant dual configuration in order to improve reliability. In the redundant redundant configuration of standby redundancy, two CPU modules are set as one set, one is the active system, the other is the standby system, the active CPU module is monitored by the standby CPU module, and the active CPU module fails. If a switching factor such as this occurs, the standby CPU module is switched to the active system.

FIG. 7 shows a general system configuration of the controller which is duplicated to provide redundancy.
The illustrated duplex controller system includes a CPU module 101-1, a CPU module 101-2, and a plurality of I / O units 102-1 to 102-n that perform data input / output with each control target device (not illustrated). The I / O group 102 is configured. Here, a case where the CPU module 101-1 is an active system and the CPU module 101-2 is a standby system will be described as an example.

  The CPU module 101 that is an active system executes each control program (for example, a program that is executed at a fixed period; a fixed period program) stored therein so that each of the I / O units 102-1 to 102- Control data is output to n (or a sensor measurement value or the like is read from each I / O unit) to control each control target device.

  On the other hand, the standby CPU module 101-2 monitors the active CPU module 101-1, and if any switching factor such as a failure occurs in the active CPU module 101-1, the active / standby CPU module 101-1 is activated. By executing the switching process, the CPU module 101-2 becomes the active system, and the process performed by the CPU module 101-1 is taken over.

  The CPU module 101-1 and the CPU module 101-2 store a plurality of fixed-cycle programs that are activated and executed at a fixed cycle (here, three fixed-cycle programs A, B, and C). Only the CPU module 101-1 in the active system executes these periodic programs to perform control processing of the I / O device, and the CPU module 101-2 in the standby system executes these periodic programs. Is not executed. These fixed-cycle programs have priority levels (priority level: A> B> C). When the startup cycle of a fixed-cycle program with a high priority level is reached, the fixed-cycle program being executed with a low priority level is interrupted. The fixed-cycle program with a high priority level is preferentially executed.

  The CPU module 101-1, the CPU module 101-2 and the I / O group 102 are connected by a system bus 103, and the active system CPU module 101-1 is connected to each I / O unit 102-1 via the system bus 103. Output data (control data) to 102-n, and input data such as measured values from connected control target devices is received from the I / O units 102-1 to 102-n. Yes.

  Further, an equalization bus 104 is provided between the duplicated CPU module 101-1 and CPU module 101-2 so that the control data is consistent when switching between the active system and the standby system occurs. Therefore, the equalization processing is performed by transmitting control data from the active CPU module 101-1 to the standby CPU module 101-2 via the equalization bus 104.

  As shown in FIG. 8, in the conventional duplex controller, when the periodic programs A, B, and C are executed by the active system CPU module 101-1, the periodic programs A and B are first executed by the interrupt. After execution, the process returns to the fixed cycle program C having the lowest priority level, and after the calculation processing by the fixed cycle program C is completed, all control data used in the fixed cycle programs A, B, and C are equalized. Do. Therefore, the execution order of each process performed in the periodic programs A, B, and C is input processing → program calculation → output processing, and the periodic program C having the lowest priority level is subjected to equalization processing. The execution order is input processing → program operation → control data equalization → output processing. In the figure, “ON” means input processing, “Den” means program calculation, “etc.” means control data equalization, and “OUT” means output processing.

  In FIG. 8, when an active / standby system switching factor occurs during the calculation of each periodic program of the active system CPU module 101-1, the CPU module newly switched to the active system by switching the active / standby system. In order to guarantee the consistency of the control data, 101-2 executes the periodic program in the form of taking over the process from the state at the time t1 in the figure when the control data is finally equalized.

  For example, when a CPU switching factor occurs during the execution of the calculation by the fixed-period program B shown in the figure, the CPU module 101-2 that newly becomes the active system executes the program from the state at the time t1. However, in this case, since the output data associated with the execution of the fixed cycle program A has already been transmitted to the I / O unit at the time t2 shown in the figure, since the equalization processing is not performed, the control data and the I / O unit May cause inconsistent output status. In addition, since the control data is finally returned to the equalized state and the process is taken over, the return time may be increased.

  Further, in the conventional controller, when the active / standby CPU is switched, there is a problem that the execution cycle time of the fixed cycle program and the execution order of the fixed cycle programs cannot be maintained in the processing after the switching.

  In the conventional controller, when the active / standby CPU module is switched, there is a problem that the execution cycle time of the fixed cycle program and the execution order of the fixed cycle programs cannot be maintained in the processing after the switching.

The related art described above is described in, for example, Patent Document 1, Non-Patent Document 1, and the like.
With respect to the problems described above, there is an invention described in Patent Document 2 as a conventional technique that has already been proposed by the applicant of the present application.

  Although not specifically shown here, the duplex controller system of Patent Document 2 has a CPU module a and a CPU module b (not shown), and is equivalent between the CPU module a and the CPU module b as in the configuration of FIG. It is assumed that an equalization bus is provided and equalization is performed via the equalization bus. In the following description, it is assumed that the CPU module a is an active system and the CPU module b is a standby system.

  As shown in FIG. 9, in the duplex controller of Patent Document 2, when the periodic program A, B, C (priority level: A> B> C) is executed in the active system CPU module a, each periodic program The processing execution order is: input processing → program calculation → control data equalization → output processing. That is, each time the fixed-cycle programs A, B, and C are executed, control data equalization processing is performed (hereinafter, such equalization is referred to as “multi-equalization”. The conventional equalization of 1 etc. is called “single equalization”). By performing such multi-equalization, when operation / standby switching occurs, consistency between the equalized data and output data to the I / O unit can be ensured, and at the time of operation / standby switching. The effect that the overhead can be reduced is obtained.

  In addition, in the conventional single equalization process, user data used by the user is equalized, whereas in the multi-equalization process of Patent Document 2, program interrupt information, program execution schedule information, etc. System information is also equalized. The program interrupt information includes, for example, a program counter, various flags, register values, and the like. The program execution schedule information is, for example, for each fixed cycle program, a fixed cycle setting time that is the execution cycle of the fixed cycle program, an execution cycle elapsed time that indicates an elapsed time after the previous fixed cycle program is executed, and the like. . The program counter indicates the last executed program (row) for each fixed cycle program.

The CPU module b that has been switched to active / standby and becomes a new active system uses the program interrupt information that has been equalized to continue the program execution that was interrupted from the state at the time of interruption. Can be done. That is, for example, in the example of FIG. 9, since the program counter value at the time of interruption of the periodic program B is transferred to the standby side at the time of equalization processing accompanying execution of the periodic program A, the periodic program B is being executed. When the operation / standby switching occurs due to an abnormality in the CPU module b, the CPU module b that has newly become an active system can continue to execute processing from the point at which the periodic program B is interrupted.
JP 2002-149212 A JP 2003-296133 A "Control function of the control station of the integrated control system MICREX-IX"; Fuji Time Report Vol. 67 NO. 6, 1994, pages 345-348

  In the dual controller system of Patent Document 2, as described above, when switching between operation / standby occurs, the CPU module b that has newly become an active system is interrupted based on the equalized system information. The periodic programs B and C can be continued and controlled from the state at the time of interruption. However, such control is premised on that the fixed cycle program held by the CPU module a matches the fixed cycle program held by the CPU module b.

  However, as shown in FIG. 9, if the fixed cycle program held by the active CPU module a is not the same as the fixed cycle program held by the standby CPU module b (in the illustrated example, The system CPU module a holds the periodic program B, and the standby CPU module b holds the periodic program B ′ (B ′ is a modified version of B, ie, a modified version, an upgraded version, etc.)). When the operation / standby switching occurs in this state, for example, the fixed-cycle program B ′ is executed without matching the program counters, and there is a problem that normal control cannot be performed.

In response to such problems, the applicant of the present application has already proposed the invention of Japanese Patent Application No. 2003-327647 (hereinafter referred to as a prior application).
In the invention of this earlier application, the operating system controller normally executes a multi-equalization process for equalizing system information every time each periodic program is executed. Then, the active system controller and the standby system controller read each other's fixed-cycle program, check whether they match the fixed-cycle program of the own controller, and if it is determined that they do not match, system information is required. Switch to the equalization process in the single equalization mode.

  In this way, in the prior application, when different programs are stored in the active system and the standby system, both are temporarily switched to the single equalization mode (conventional method of Patent Document 1 or the like). . In the single equalization mode, since the program cannot be continuously executed from the point of interruption of the fixed cycle program, the above problem does not occur. The above collation processing is executed, for example, at the time of system initialization, at startup, at the time of changing the periodic program.

  However, normally, when a new programmable controller system is constructed, a system engineer or the like, for example, mainly enters an active system CPU module into a new application program (such as a fixed-cycle program) before entering the actual operation. The system verification is performed to confirm whether or not it operates as described above. In the above-mentioned prior application, the single equalization mode may be temporarily entered during the actual operation, but normally it operates in the multi-equalization mode. That is, normally, during the actual operation, the same periodic program should be stored in both the active system and standby system CPU modules, and in this case, both operate in the multi-equalization mode. Therefore, the system verification must verify the operation in the multi-equalization mode.

  However, at the time of system verification, there are not a few cases where a standby CPU module is not mounted or a new application is not downloaded to the standby CPU module. Therefore, it becomes a single equalization mode. In particular, system verification is often performed at a factory on the producer side before installation on the customer side. In that case, each CPU module alone (that is, in a state where the paired CPU modules are not connected). Since the operation is often checked, the single equalization mode is set.

For this reason, the following problem arises.
Here, FIG. 10 shows a fixed-cycle program execution timing in the conventional multi-equalization mode. FIG. 11 shows the fixed-cycle program execution timing in the conventional single equalization mode.

  As shown in FIG. 10, in the multi-equalization mode, the execution times of the periodic programs A, B, and C of the active CPU module are Ta, Tb, and Tc, respectively, and equalization is performed for Ta, Tb, and Tc. Data collection / transfer time is included. On the other hand, in the single equalization mode of FIG. 11, the execution times of the periodic programs A, B, and C of the active CPU module are Ta ′, Tb ′, and Tc ′, respectively, and equal to Ta ′ and Tb ′. Data collection / transfer time is not included. Therefore, naturally, the execution time in the multi-equalization mode is longer than the execution time in the single equalization mode. Therefore, even if the system is verified at the execution timing in the single equalization mode, it is different from the execution timing in the multi-equalization mode. . In other words, proper system verification could not be performed.

  The problem of the present invention is that, in a dual controller system that normally performs multi-equalization processing, that is, control data equalization processing every execution of each periodic program, the periodic programs differ between the active system and the standby system. It is possible to provide a dual controller system, a method, a program, and the like that enable control after operation / standby switching without any problem, and also perform system verification before actual operation without any problem. .

  The duplex controller system of the present invention has an active system and a standby system controller, and in the duplex controller system that executes a plurality of fixed-cycle programs, the active system controller and the standby system controller are respectively Sometimes the other controller's fixed-cycle program and its own controller's fixed-cycle program are collated, and if they match, the multi-equalization mode is set, and if they do not match, the single equalization mode is set. The operating system controller waits for equalized data to which an equalized program level is added for each execution of each periodic program regardless of the mode determined by the equalized mode determining means. First equalization processing means for transmitting to the system controller, wherein the standby system controller has a single equalization mode In addition, when the equalization program level is the lowest level, the received equalization data is distributed to a predetermined storage area to establish an equalization process. A second equalization processing means for discarding the equalized data is provided.

  In the above configuration, the active system controller operates in the multi-equalization mode regardless of the mode. Thereby, at the time of system verification before the actual operation, the system operation at the actual operation can be verified regardless of the single equalization mode. On the other hand, during the actual operation, in the single equalization mode, even if the active controller is operating in the multi-equalization mode, the received equalization data other than those at the lowest level on the standby controller side will be received. Since it is discarded, the processing in the single equalization mode can be substantially realized.

  Since the operating side operates regardless of the mode, the process itself for determining the mode may not be performed.

  According to the duplex controller system, the method, the program, etc. of the present invention, in the duplex controller system that normally performs multi-equalization processing, that is, control data equalization processing every execution of each periodic program, It is possible to perform control after operation / standby switching without any problem even if the fixed-cycle programs are different between the standby system and the standby system, and to perform system verification before actual operation without any problem.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a configuration block diagram of a programmable controller main body (CPU module) in a duplex controller system according to the present embodiment.

  The duplex controller system shown in FIG. 1 includes a CPU module 1 and a CPU module 2, and the CPU module 1, the CPU module 2, and various I / O groups (not shown) are connected via a system bus 4. ing. Further, an equalization bus 3 is provided between the CPU module 1 and the CPU module 2. In the following description, it is assumed that the CPU module 1 is an active system and the CPU module 2 is a standby system.

The CPU modules 1 and 2 are programmable controller bodies, but only the configuration relating to the description of this example is shown here, and the other configurations are omitted.
In FIG. 1, the active CPU module 1 includes a program RAM 11, a data RAM 12, an equalization bus control unit 13, a reception buffer RAM 14, a control unit 15, and the like. Other configurations are omitted because they are not particularly relevant to the description here, as described above.

  The program RAM 11 stores a user program 11a and the like. The user program 11a is, for example, the above-mentioned periodic program, but the system of this example also stores a second application program for realizing the processing of the CPU module 1 shown in FIG. ing.

  The data RAM 12 has a user data area 12a. For example, equalization data (control data (user data)) corresponding to each fixed cycle program is stored in the user data area 12a. Further, as already described, in the multi-equalization mode, the system information is also transferred to the standby side. This system information is held in the memory inside the control unit 15 or stored in the data RAM 12. .

  The equalization bus control unit 13 is a configuration dedicated to equalization processing for performing equalization via the equalization bus 3. When the equalization data is passed from the control unit 15, the equalization bus control unit 13 In conjunction with the equalization bus control unit 23, the equalization data is stored in the standby reception buffer RAM 24. The equalization bus control units 13 and 23 correspond to, for example, “SGM (Sameness data Gather Memory control)” described in Non-Patent Document 1.

  The control unit 15 is a central processing unit (CPU chip or the like) that controls the CPU module 1 as a whole, and using the second application program stored in the program RAM 11, as in the prior application, usually a multi-processor or the like. In a situation where it is necessary to execute equalization processing by valueization and confirm the coincidence / non-coincidence of the periodic program, in the case of program mismatch by executing the program collation processing, temporarily use the single equalization mode, etc. Shift to value processing.

  In other words, the control unit 15 uses the second application program to perform equalization for each execution of the fixed-cycle program and execute multi-equalization processing that includes system information in the equalized data. The equalization processing function to be performed, the fixed-period program of the standby CPU module 2 is read, a verification function for verifying whether or not it matches the fixed-cycle program of its own CPU module, and this verification function determines that there is a mismatch. In the case of an equalization process, the equalization mode switching function for switching the above equalization process to the equalization process in the single equalization mode, and the multi-equalization mode regardless of whether the current mode is single or multi An equalization processing function for performing time equalization processing is realized.

  The standby CPU module 2 includes a program RAM 21, a data RAM 22, an equalization bus control unit 23, a reception buffer RAM 24, a control unit 25, and the like. Since this configuration itself is the same as that of the active CPU module 1, although not specifically described, the control unit 25 uses a third application program stored in the program RAM 21 to perform the CPU shown in FIG. The processing on the module 2 side, the processing in FIG. Further, unlike the control unit 15, the control unit 25 does not execute each periodic program. However, this is a story when the CPU module 2 is a standby system, and when it is an active system, the control unit 25 also executes each periodic program.

  Here, each of the CPU modules 1 and 2 performs the equalization mode determination process according to the collation result of the fixed-cycle program of each other, as in the prior application. However, in this example, as described above, the active CPU module executes the equalization process in the multi-equalization mode regardless of the mode. Therefore, the active system CPU module does not necessarily need to perform the equalization mode determination process, but will be described as being performed here.

  As described above, the equalization mode determination process of the prior application is executed at the time of system initialization, at startup, at the time of changing the periodic program, and the like. As an example, FIG. 2 shows a processing flowchart when the standby system is activated while the active system is already in operation. Note that, when the active system and the standby system are activated almost simultaneously, the same process as that of FIG. 2 is performed. In addition, when the fixed cycle program is changed, the CPU module on the changed side performs almost the same processing as the processing on the standby side in FIG. 2 due to the change. That is, in any case, only the trigger condition for starting the process is different, and the processing content itself is almost the same as that in FIG.

  In FIG. 2, for example, one of the CPU modules needs to be replaced due to a failure, so that a new CPU module (becomes a standby system) is activated by initial processing while only the other CPU module is operating. In this case, the standby CPU module 2 first issues a periodic program verification request to its own CPU to start the equalization mode determination process. At that time, it is checked whether or not the active CPU module 1 is in operation, and if it is in operation, a fixed-cycle program verification request command is issued to the active CPU module 1 (step S21). When the active CPU module 1 receives this periodic program collation request command, it issues the collation request to its own CPU and starts the equalization mode determination process (step S11).

After the above process is started, the active system and the standby system are the same, and therefore, the operation system will be described as an example here.
When starting the above equalization mode determination process, the active CPU module 1 forcibly sets the single equalization mode regardless of what the previous equalization mode is (step S12). In other words, the equalization process in the single equalization mode is executed during the equalization mode determination process according to the fail-safe concept. Next, a program read command is transmitted to the standby CPU module 2, and a response is returned by the processing in step S 23 on the standby CPU module 2 side. The periodic program is received and stored in a buffer (not shown), for example (step S13).

  In addition, when a program read command is sent from the standby CPU module 2 side by the process of step S24 on the standby CPU module 2 side, the active CPU module 1 is executed by, for example, interrupt processing. The process of returning the fixed-cycle program on the side to the standby CPU module 2 is performed (step S14).

  Next, the active CPU module 1 collates the fixed-cycle program on the standby CPU module 2 side received and stored in step S13 with its own fixed-cycle program, and determines whether or not they match. Determination is made (step S15). For this collation / coincidence determination, an existing method may be used. For example, each program is compared line by line to determine coincidence / non-coincidence. In addition, here, it is not assumed that the program mismatch is completely different. For example, it is assumed that the same periodic program A has different versions. Therefore, for example, the collation compares and collates the fixed cycle program A of the active CPU module 1 with the fixed cycle program A of the standby CPU module 2. Of course, other periodic programs B, C, etc. are similarly compared and verified. When all the fixed cycle programs match, it is determined that they match.

  If it is determined that they match, the equalization processing is changed to the multi-equalization mode (because the processing in step S12 is in the single equalization mode), and if it is determined that they do not match, The equalization process remains in the single equalization mode (step S16).

  In the multi-equalization mode, as described above, equalization is performed every execution of each periodic program and equalization processing is performed so that the equalization data includes system information. Mode. In the single equalization mode, as described above, after the computation processing of the fixed cycle program with the lowest priority level is completed, the equalization processing is executed for all control data used in all the fixed cycle programs. In this mode, system information does not need to be equalized.

  Here, in this method, the equalization process in the single equalization mode is different from the conventional technique and the prior application. That is, first, the active CPU module 1 performs equalization in the single equalization mode with the same execution time as in the multi-equalization mode. That is, the equalization process is performed every execution of each periodic program. In other words, the active system CPU module 1 collects equalized data at every fixed-cycle program end regardless of whether the current mode is a single equalization mode or a multi-equalization mode. The standby CPU also transmits this to the module 2. That is, processing in the multi-equalization mode is performed regardless of the mode (thus, not only the control data but also the system information is transferred to the standby side). However, in this method, the equalization data to be collected / transmitted is not limited to the equalization data related to the fixed-cycle program executed at that time, but equalization related to all fixed-cycle programs. Data. In other words, the equalization data itself becomes equalization data in the single equalization mode. Further, in this method, the equalized program level information is added to the equalized data and transmitted to the standby side. The equalized program level information is the priority level of the fixed cycle program executed at that time.

FIG. 3 shows an example of an equalized data frame transmitted to the standby side.
As shown in the figure, the active system CPU module 1 adds the equalized program level information in the header of the equalized data frame when transmitting the equalized data to the standby side. Is notified of the equalization data of the fixed-cycle program end.

On the other hand, the standby CPU module 2 executes the equalized data distribution process shown in FIG. 4 every time it receives the equalized data transmitted from the operating side regardless of the current mode.
In FIG. 4, when the current mode is the multi-equalization mode (step S31, NO), the standby CPU module 2 unconditionally distributes the received equalized data (equivalent data). Is distributed and stored in a predetermined storage area (user data area 22a and the like). On the other hand, when the current mode is the single equalization mode (step S31, YES), the received equalization data is registered at a fixed period of the lowest level by referring to the equalization program level information. If the data is equalized data of a fixed-cycle program other than the program (step S32, NO), it is discarded without performing the distribution process. On the other hand, when the received equalization data is the equalization data of the fixed-period program registered at the lowest level (step S32, YES), the received equalization data is distributed.

  With the above method, in the active system CPU module 1, even in the single equalization mode, the execution time of the periodic program is the same as the execution time in the actual operation (that is, in the multi-equalization mode). Therefore, system verification can be performed normally.

FIG. 5 shows an operation example of the periodic program execution and equalization processing in the single equalization mode by the above method.
As shown in FIG. 5, the active system CPU module 1 is equivalent to the multi-equalization mode even in the single equalization mode, and equalization processing (equalization data of the equalization data) Collection / transmission). In the illustrated example, it is assumed that the priority levels of the periodic programs A, B, and C are A>B> C. Therefore, the periodic program of the lowest level is the periodic program C. In this case, the active system CPU module 1 performs the equalization process even when each of the periodic programs A and B is executed, but the standby system CPU module 2 discards the received equalized data. On the other hand, the standby CPU module 2 that has received the equalized data during the execution of the periodic program C performs distribution processing. That is, in the single equalization mode, even if the active system CPU module 1 performs the same processing as in the multi-equalization mode, the equalization processing at the time of executing the periodic programs A and B is established as a whole. As a result, the equalization processing in the single equalization mode is substantially performed.

  Therefore, first, the execution times Ta ″, Tb ″, Tc ″ of the periodic programs A, B, C in the active CPU module 1 in the single equalization mode shown in FIG. Since it is the same as the execution time at the time, normal system verification can be performed as described above. Furthermore, as described above, since the equalization processing in the single equalization mode is substantially performed, even if the periodic program is different between the active system and the standby system, (Similar) There is no problem when switching between operation and standby. That is, as shown in FIG. 6, even when the fixed-cycle program B is stored on the operating side and the fixed-cycle program B ′, such as an upgraded version, is stored on the standby side, When the standby side becomes a new active system due to some abnormality during the execution of program B, the equalization process is established immediately before that when the fixed-cycle program C is executed. Since the process is a process, the periodic program is executed in the form of taking over the process from here (that is, at the time point t1 in FIG. 8) in the new operating system, so that the process can be taken over without any problem as in the prior application.

  In the description of the above-described embodiment, the active CPU module performs the same processing operation regardless of whether the equalization mode is single or multi, but the process for mode determination shown in FIG. However, the present invention is not limited to this example, and the active CPU module may be configured not to perform the process of FIG. However, even in this case, the process of step S14 in FIG. 2 is performed. That is, even in this case, since the standby side needs to perform processing for mode determination, when the operation side receives a program read command from the standby side, it sends its fixed-cycle program to the standby side. Process to do.

It is a block diagram of the programmable controller main body (CPU module) in the duplex controller system according to the present embodiment. It is a flowchart figure of an equalization mode determination process. It is a figure which shows an example of the equalization data frame transmitted to a standby side. It is a process flowchart figure at the time of equalization data reception in a standby system CPU module. It is a figure which shows the operation timing at the time of a single equalization mode. It is a figure which shows the program execution state in the case of operation / standby switching at the time of a single equalization mode. It is a figure which shows the general system structure of the controller which duplicated and gave the redundancy. It is a figure which shows the operation | movement at the time of the fixed-cycle program execution state of a conventional system, and active / standby switching. It is a figure for demonstrating the problem when a fixed period program differs by operation and standby. It is a figure which shows the fixed cycle program execution timing at the time of the conventional multi-equalization mode. It is a figure which shows the fixed cycle program execution timing at the time of the conventional single equalization mode.

Explanation of symbols

1 CPU module 2 CPU module 3 Equalization bus 4 System bus 11 Program RAM
11a User program 12 Data RAM
12a User data area 13 Equalization bus control unit 14 Receive buffer RAM
15 Control unit 21 Program RAM
21a User program 22 Data RAM
22a User data area 23 Equalization bus controller 24 Receive buffer RAM
25 Control unit

Claims (8)

In a dual controller system that has active and standby controllers and executes multiple periodic programs,
The active system controller and the standby system controller are respectively
At any time, the fixed-cycle program of the other controller and the fixed-cycle program of its own controller are collated, and if they match, the multi-equalization mode is set. A mode selection means,
The operating system controller transmits the equalized data to which the equalized program level is added to the standby system controller for each execution of the periodic program regardless of the mode determined by the equalized mode determining means. 1 equalization processing means,
The standby controller distributes the received equalized data to a predetermined storage area and establishes an equalization process when the equalization program level is the lowest level in the single equalization mode. A duplex controller system comprising second equalization processing means for discarding received equalized data when the level is not the lowest level. In a dual controller system that has active and standby controllers and executes multiple periodic programs,
The operating system controller has a first equalization processing means for transmitting equalization data to which an equalization program level is added to the standby system controller for each execution of the periodic program.
The standby controller is
The equalization mode determining means for comparing the fixed period program of the active system controller with the fixed period program of the own controller and setting the multi-equalization mode if they match and the single equalization mode if they do not match When,
In the single equalization mode, when the equalization program level is the lowest level, the received equalization data is distributed to a predetermined storage area to establish the equalization process, and is not at the lowest level Includes a second equalization processing means for discarding the received equalized data;
A duplex controller system characterized by comprising:   3. The duplex controller system according to claim 1, wherein the equalized data is equalized data related to all fixed-cycle programs. In the operating system controller in the duplex controller system that has an operating system and a standby system controller and executes a plurality of periodic programs,
At any time, the fixed-cycle program of the standby controller and the fixed-cycle program of its own controller are collated, and if they match, the multi-equalization mode is set, if they do not match, the single equalization mode is set. A value mode determination means;
Regardless of the mode determined by the equalization mode determination means, equalization processing means for transmitting equalization data to which an equalization program level is added to the standby system controller for each execution of each periodic program;
An operating system controller characterized by comprising: In the operating system controller in the duplex controller system that has an operating system and a standby system controller and executes a plurality of periodic programs,
An active system controller comprising first equalization processing means for transmitting equalized data to which an equalized program level is added to a standby system controller for each execution of a regular program. In the standby system controller in the duplex controller system having an active system and a standby system controller and executing a plurality of fixed-cycle programs,
The equalization mode determining means for comparing the fixed period program of the active system controller with the fixed period program of the own controller and setting the multi-equalization mode if they match and the single equalization mode if they do not match When,
When the current mode is the single equalization mode, the equalization program level is the lowest level every time the equalization data with the equalization program level added is sent from the operating system controller. The equalization processing means for distributing the received equalization data to a predetermined storage area to establish the equalization processing, and discarding the received equalization data if not at the lowest level;
A standby controller characterized by comprising: A computer of the active system controller in a duplex controller system having an active system and a standby system controller and executing a plurality of periodic programs,
A function that compares the fixed-cycle program of the standby controller and the fixed-cycle program of its own controller at any time, and if they match, sets the multi-equalization mode, and if they do not match, sets the single-equalization mode When,
Regardless of the determined mode, a function of transmitting equalization data to which an equalization program level is added to the standby system controller for each execution of each periodic program;
A program to realize In the computer of the standby system controller in the duplex controller system having an active system and a standby system controller and executing a plurality of periodic programs,
A function that collates the fixed cycle program of the active system controller with the fixed cycle program of its own controller, and if it matches, sets the multi-equalization mode, and if it does not match, sets the single equalization mode,
When the current mode is the single equalization mode, the equalization program level is the lowest level every time the equalization data with the equalization program level added is sent from the operating system controller. A function of distributing the received equalized data to a predetermined storage area to establish an equalization process, and discarding the received equalized data if it is not the lowest level;
A program to realize

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