JP2005269627A - Semiconductor relay device and manufacturing method of wiring board thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor relay device suitable for miniaturizing without the impairment of performance. <P>SOLUTION: An LED 3, a photovoltaic IC 4, an MOS-FET 5, and 3 chips are mounted on a silicon substrate 2 with two projections 1 located nearly in parallel, each of the projections having a slanting side including a curve with an inflection point. The LED 3 is mounted on an LED-connected electrode 10 arranged between the two projections 1, and is connected to another LED-connected electrode 10 arranged between the projections 1 by a gold wire 11. The photovoltaic IC 4 is placed on the upper part of the projection so as to oppose the LED 3, and is connected through a gold bump 12. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor relay device suitable for downsizing a semiconductor relay device and a method for manufacturing a wiring board thereof.

  In recent years, measuring instruments such as semiconductor testers are increasingly using non-contact relays such as semiconductor relay devices in place of conventional contact relays for the purpose of improving reliability and downsizing.

  The operation principle of the semiconductor relay device will be described with reference to FIG. A light emitting diode (hereinafter referred to as LED) 55 and a photovoltaic IC 56 are arranged to face each other, and a photovoltaic IC 56 and a metal oxide silicon field effect transistor (hereinafter referred to as MOS-FET) 57 are connected to each other. The light from the LED 55 is photoelectrically converted by the photovoltaic IC 56. The MOS-FET 57 is driven by the voltage generated here, and NO / OFF of the current flowing between A and B in FIG. 4 is performed in the MOS-FET 57. In order to apply light from the LED 55 to the entire photodiode array on the surface of the photovoltaic IC 56, the LED 55 and the photovoltaic IC 56 need to be separated to some extent.

In a semiconductor tester, thousands of relays are used in a device, and a board on which the relays are mounted is very expensive. By downsizing the semiconductor relay device, it is possible to reduce the size of the semiconductor tester and reduce the price of the board mounted on the tester. Therefore, there is a demand from the market for miniaturization of the semiconductor relay device.

  Due to such market background, various semiconductor relay devices have been invented. One semiconductor relay device will be described with reference to FIG. This semiconductor relay device has a wiring board 37. The wiring board 37 has a recess 36 provided in the approximate center thereof and a wiring pattern (not shown). An LED 38, which is a light emitting element, is mounted on the bottom surface of the recess 36, and an LED surface electrode and a substrate electrode (not shown) are connected by a metal wire 39. A photovoltaic IC 40 that is a light receiving element is disposed so as to cover the opening of the recess 36 and face the LED 38, and is flip-chip bonded to the wiring substrate 37 via the bumps 41.

  On the same surface as the surface on which the photovoltaic IC 40 of the wiring board 37 is mounted, a MOS-FET 42 as an output element is flip-chip bonded via a bump 43. The photovoltaic IC 40 and the MOS-FET 42 are electrically connected by a wiring pattern (not shown) on the wiring board 37. A transparent resin 44 is filled between the LED 38 and the photovoltaic IC 40, and the portions of the photovoltaic IC 40 and the MOS-FET 42 on the wiring board 37 side are sealed with a light shielding resin 45, respectively.

  In this semiconductor relay device, the photovoltaic IC 40 and the MOS-FET 42 are mounted on the wiring substrate 37 by flip-chip bonding, thereby reducing the package size compared to the case of mounting by conventional wire bonding. can do. As the MOS-FET 42 used in this semiconductor relay device, it is necessary to use a Lateral Double-Diffusion MOS-FET (hereinafter referred to as a lateral MOS-FET) having a gate electrode, a source electrode, and a drain electrode on the same surface of the chip. (For example, refer to Patent Document 1).

  In the case of a normal MOS-FET in which the drain electrode is provided on the back surface of the chip, as shown in FIG. 6, a hole 46 for mounting the LED and two holes 47 and 48 for mounting the MOS-FET are provided and mounted on the substrate. . In this case, the MOS-FET is mounted by wire bonding. In this case, it is necessary to provide a space for accommodating the chip and a space for accommodating a wire bonding capillary, and the package size is significantly increased.

An example of a conventional method for manufacturing a silicon substrate will be described with reference to FIG. First, a hole 50 is provided from the surface side of the silicon wafer 49 (FIG. 7A). Next, a silicon oxide layer 51 serving as an insulating film is formed on the substrate surface by thermal oxidation treatment (FIG. 7B). Then, an adhesion layer 52 such as a titanium film is formed in the hole 50 and on the substrate surface by sputtering, and the hole 50 is filled with copper 53 by plating (FIG. 7C). Then, both surfaces of the substrate are mechanically polished to penetrate the holes (FIG. 7D). An insulating film 54 is formed on the front and back surfaces of the substrate by chemical vapor deposition (CVD) (FIG. 7E), and necessary portions are opened by reactive ion etching (RIE) (FIG. 7F). Thereafter, wiring is formed on the substrate surface as necessary.
JP-A-11-163705

  The above-described conventional semiconductor relay device has the following problems.

  In the semiconductor relay device introduced in FIG. 5, the connection path between the external connection terminal and the MOS-FET terminal arranged on the bottom surface of the substrate becomes long, and sufficient high-frequency signal passing characteristics cannot be obtained.

  In the substrate as shown in FIG. 6, the semiconductor relay device becomes very large due to the routing of the wire, and the connection path between the external connection terminal and the MOS-FET terminal becomes long.

  In addition, it is difficult to manufacture a substrate for a small semiconductor relay device having such a shape using a conventional ceramic substrate or resin substrate in terms of electrode position system and flatness. When a silicon substrate with high dimensional accuracy is selected, it is difficult to manufacture a substrate in which large protrusions are provided on the surface and the front and back electrodes are connected by through electrodes. For example, in the conventional method, the convex portion and the through electrode are formed from the surface side of the silicon wafer, but it is difficult to hold the wafer in the polishing step in which the through electrode is exposed to the back surface.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a structure of a semiconductor relay device and a substrate manufacturing method suitable for downsizing without impairing performance.

  In order to solve the above-mentioned problem, the present invention has at least two convex portions on one surface, and is formed on the surface with at least one first electrode formed on the convex end portion of the angular convex portion. And the electrode formed on the surface and the second electrode formed on the other surface are through-electrodes. A substrate electrically connected to the light emitting element, a light emitting element disposed between the convex parts, a light receiving part opposed to the light emitting element, and an electrode connected to the convex end part A light-receiving element to be bonded; an output element to be bonded to the substrate; a light-transmitting resin that is filled between the light-emitting element and the light-receiving element and transmits light emitted from the light-emitting element; Light shielding covering the light-sensitive resin, the light emitting element, and the light receiving element It is and a fat.

  At this time, at least one of the side surfaces of the convex portion of the substrate is an inclined surface with respect to a surface formed by another portion of the substrate, and at least one of the inclined surfaces includes the wiring. It is preferable that

  In addition, it is preferable that an inclination angle of the slope formed by the side surface of the convex portion near the convex end portion and near one surface of the substrate is gentler than an intermediate inclination angle of the slope.

  Moreover, it is preferable that the slope formed by the side surface of the convex portion is formed by a curved surface having a curved surface having an inflection point in its cross section.

  The second electrode is preferably formed in a rectangular groove formed on the other surface of the substrate.

  Further, it is preferable that the substrate is mainly formed of silicon or a silicon compound, a wiring portion of the substrate is formed on an insulating layer, and the through electrode is covered with the insulating layer.

  According to another aspect of the present invention, there is provided a method of manufacturing a wiring board having a convex portion on a front surface, a step of providing a non-through hole on the back surface of the wafer, a step of forming an insulating layer on the back surface of the wafer and the non-through hole, A step of filling the conductor, a step of processing the wafer surface by etching to provide two convex portions, a step of processing and exposing the bottom surface of the non-through hole from the back surface from the substrate surface, and forming an insulating layer on the wafer surface And a step of opening a through hole portion of the insulating layer on the wafer surface side, and a step of forming an electrode pad and a conductive pattern connecting them on the wafer surface.

  At this time, it is also possible to use a hardened paste containing metal particles with a diameter of 20 nm or less as the conductor filling the non-through holes.

  It is also possible to form a conductive pattern on the wafer surface by applying a paste containing metal particles having a diameter of 20 nm or less.

According to such a structure and manufacturing method, it is possible to drastically reduce the size of the semiconductor relay device without reducing productivity or quality.

  According to the present invention, the structure of the semiconductor relay device can be reduced without impairing performance.

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 and 2.

FIG. 1 is a diagram showing a cross-sectional structure of the semiconductor relay device according to the first embodiment of the present invention. The external shape of the semiconductor relay device is 2.0 × 2.0 × 1.2 (mm ³ ). An LED 3 (light emitting element), a photovoltaic IC 4 (light receiving element), and a MOS-FET 5 (output element) are mounted on a silicon substrate 2 (substrate) having two convex portions 1 arranged substantially in parallel. That is, three chips are mounted.

The size of the LED ³ is 0.2 × 0.2 × 0.2 (mm ³ ). The external dimensions of the photovoltaic IC 4 and the MOS-FET 5 are the same and are 0.6 × 1.2 × 0.2 (mm ³ ). The convex portion 1 and the base plate 6 of the silicon substrate 2 are formed of a single block.

The size of the base plate 6 is 2.0 × 2.0 × 0.2 (mm ³ ), and the size of the convex portion 1 is 0.35 × 0.95 × 0.45 (mm ³ ). Each convex portion 1 has an inclined surface 7 (side surface) on one of its side surfaces. The inclination angle of the inclined surface 7 is about 45 °.

  A wiring 8 (wiring) is provided on the inclined surface 7. The side surface is formed of a curved surface including a curve having an inflection point so that the wiring 8 is not cut at the boundary between the inclined surface 7 and the flat surface. Thereby, the upper end of the inclined surface 7 that is the convex end of the convex portion 1 and the lower end of the inclined surface 7 that is the base end portion of the convex portion 1 are the surfaces formed by the planar portion other than the convex portion 1 of the silicon substrate 2, respectively. On the other hand, it is connected with a slightly gentle inclination angle.

  The electrode on the front side of the silicon substrate 2 and the back electrode 17 (electrode) are connected by a through electrode 16 (through electrode). The back electrode 17 serves as an external connection terminal. The LED 3 is mounted on the LED mounting electrode 9 (electrode) disposed between the two protrusions 1 and is connected to another LED connection electrode 10 disposed between the protrusions 1 by a gold wire 11. Yes. The photovoltaic IC 4 is disposed on the upper surface 15 of the convex portion so as to face the LED 3, and is connected via the gold bump 12. The photovoltaic IC 4 is formed with a photodiode array and a MOS-FET driving circuit on its surface layer.

  The MOS-FET 5 is disposed substantially parallel to the photovoltaic IC 4 in the opening direction of the two convex portions 1 and is connected to the substrate electrode via a gold bump, like the photovoltaic IC 4. A substantially transparent silicone rubber 13 (translucent resin) is injected between the LED 3 and the photovoltaic IC 4, and the upper surface of the base plate 6 is entirely covered with a black epoxy resin 14 (epoxy resin). Yes.

  FIG. 2 shows the positional relationship between the silicon substrate 2 and the chip as viewed from above the package. Four electrodes are provided on the upper surface 15 of the convex portion and six electrodes are provided on the base plate 6. Two of the four convex upper surface electrodes are connected to the electrode of the base plate 6. Further, four of the six base electrodes are connected to the four back electrodes 17 by through electrodes 16 penetrating the substrate. The electrode has a four-layer structure of titanium / copper / nickel / gold. The MOS-FET 5 used this time is a lateral MOS-FET having two drain electrodes 18 (electrodes), a source electrode 19 (electrodes), and a gate electrode 20 (electrodes) on the chip surface side. The drain electrode 18 is connected to the back electrode 17 by the through electrode 16. The source electrode 19 is connected to the cathode electrode 21 (first electrode) of the photovoltaic IC 4. The gate electrode 20 is connected to the anode electrode 22 (second electrode) of the photovoltaic IC 4. The photovoltaic IC 4 has two electrodes, a cathode electrode 21 and an anode electrode 22, and the remaining two electrodes are dummy electrodes for increasing the bonding strength between the chip and the substrate.

  This semiconductor relay device operates as described below. The signal current on the input side flows to the LED 3 and the LED 3 emits light. The photodiode array of the photovoltaic IC 4 receives the light from the LED 3 and applies the generated voltage to the gate electrode 20 of the MOS-FET 5. By applying this voltage, the current flowing between the two drain electrodes 18 of the MOS-FET 5 is turned ON / OFF.

  FIG. 3 shows a manufacturing process of the semiconductor relay device of the present invention. The substrate was manufactured using a silicon wafer 23 having a thickness of 0.65 mm and a diameter of 150 mm, and about 3000 substrates were manufactured per silicon wafer. In FIG. 2, only a portion corresponding to one relay device is extracted and described.

  First, a hole 25 (non-through hole) having a depth of 200 μm and a diameter of φ100 μm and a hole 26 (non-through hole) having a depth of 200 μm and a diameter of φ200 μm were provided on the back surface 24 of the silicon wafer 23 by RIE ( FIG. 3 (a)). For this RIE, a method called a Bosch process was used, in which a CF deposited film was provided on the side wall and silicon was etched while protecting it.

  Next, a thermal oxide film 27 (first insulating layer) was formed to a thickness of about 1 μm on the entire back surface including the holes 25 and 26 (FIG. 3B). Then, a titanium film with a thickness of 100 nm was formed on the entire back surface by sputtering, and copper was formed thereon with a thickness of 300 nm. That is, a 400 nm thick metal film 28 made of titanium and copper was formed on the entire back surface (FIG. 3C). Next, copper 29 (conductor) was filled in the holes 25 and 26 by electroplating, and copper was formed to a thickness of 10 μm on the entire back surface (FIG. 3D). Unnecessary portions other than the holes 25 and 26 and the back electrode were removed by wet etching to form the back electrode 17 (FIG. 3E).

  After completing the process from the back surface, which is one surface (FIGS. 3A to 3E), the silicon was processed so that the two convex portions 1 remain by RIE from the surface side of the silicon wafer 23 which is the other surface. (FIG. 3 (f)). On the processed surface, the silicon oxide film 31 (second insulating layer) was formed to a thickness of about 1 μm by using Plasma Chemical Vapor Deposition (P-CVD) (FIG. 3G).

  Next, the portion 32 corresponding to the holes 25 and 36 was opened from the surface side using RIE (FIG. 3 (h)). The portion 32 corresponding to the holes 25 and 36 is a portion that becomes the through electrode 16. Next, a titanium film having a thickness of 10 nm was formed by sputtering on the entire surface, and a copper film having a thickness of 300 nm was formed thereon. That is, a 310 nm thick metal film 33 made of titanium and copper was formed on the entire surface. Then, unnecessary portions of the metal film 33 were removed by wet etching (FIG. 3 (i)). In this etching, the resist is applied by spray coating.

  Then, a nickel plating film 34 having a thickness of 1 μm and a gold plating film 35 having a thickness of 0.2 μm were formed on the front and back surfaces of the silicon wafer (FIG. 3J). Both nickel and gold were electroless plated. Accordingly, the wiring 8, the LED mounting electrode 9, the LED connection electrode 10, the drain electrode 18, the source electrode 19, the gate electrode 20, the cathode electrode 21, and the anode electrode 22 shown in FIGS. Is formed.

  Silver paste was applied to the LED mounting electrode 9 between the two convex portions 1 of the silicon substrate 2, and the LED 3 was mounted thereon. This LED 3 is of a type having electrodes on the upper and lower surfaces of the chip. After mounting, the silver paste was cured by heating at 150 ° C. for 5 minutes. The LED connection electrode 10 between the electrode on the upper surface of the LED 3 and the two convex portions 1 was connected by wire bonding.

In normal wire bonding, a wire is connected from a chip electrode to a substrate electrode. But,
In this method, the distance between the gold wire and the photovoltaic IC is shortened, and the relay characteristics are deteriorated. Therefore, a gold ball bump was formed on the upper electrode of the LED 3, and the substrate electrode was wired to the chip electrode. The reason why the bumps are formed on the upper electrode of the LED 3 is to prevent cracking of the electrode. The diameter of the gold wire used was φ28 μm, and a gold ball of φ75 μm was formed at the wire tip. The bonding temperature was 200 ° C.

  Next, a photovoltaic IC in which a gold ball bump was previously formed on the electrode was pressed with a 6 N load with a bonding tool (not shown), and ultrasonic vibration was applied for 200 ms for bonding. The amplitude of the ultrasonic wave is about 1.5 μm. The bonding temperature was 200 ° C., the same as that for wire bonding. Under this condition, a shear strength of about 6N per bump is obtained. Subsequently, a MOS-FET in which a gold ball bump was previously formed on the electrode was similarly flip-chip bonded (FIG. 3 (k)).

  In order to ensure the optical path of the light emitted from the LED 3, the silicone rubber 13 was injected between the LED 3 and the photovoltaic IC 4 by a dispenser (not shown) and cured (FIG. 3 (l)). Then, a black epoxy resin 14 was applied to the entire upper surface of the substrate and cured, and cut into individual packages using a diamond blade (FIG. 3 (m)).

Although one embodiment of the present invention has been described above, the present invention can be variously modified in addition to this. This will be described below. In the present embodiment, the LED 3 is electrically connected by the gold wire 11 by wire bonding. However, for example, a light emitting element having electrodes only on one plane with a chip may be mounted by flip chip bonding. Absent.

  In the mounting of the photovoltaic IC and the MOS-FET, bumps are formed on the chip electrodes and then flip-chip bonded to the substrate. However, the bumps may be formed on the substrate side.

Moreover, although flip chip bonding is performed by ultrasonic thermocompression bonding using gold ball bumps, similar effects can be obtained by soldering or bonding using a conductive resin. Although the silicone rubber 13 is filled between the LED 3 and the photovoltaic IC 4, the silicone rubber 13 may be circulated to the back surface of the photovoltaic IC 4.

  Moreover, about the board | substrate, in order to open the space | interval of LED3 and photovoltaic IC4, the part in which LED3 of the board | substrate 23 is mounted may be dug further toward the other surface side.

  Further, after forming the metal film 28 made of titanium and copper on the entire back surface, filling the holes 25 and 26 with copper 29 and forming the copper film on the entire back surface, Unnecessary portions other than 26 and the back electrode 17 are removed. However, after the metal film 28 made of titanium and copper is formed, unnecessary portions other than the holes 25 and 26 and the back electrode are removed by wet etching, and then the copper 29 is filled into the holes 25 and 26 by electroplating. May be.

  Further, the order of the steps can be changed. For example, the convex portion 1 may be first formed on the surface side of the silicon wafer 23.

  The present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Moreover, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment.

The figure which shows the cross-section of the semiconductor relay apparatus which concerns on 1st embodiment of this invention. The figure which showed the relationship between the board | substrate electrode arrangement | positioning and chip position of the semiconductor relay apparatus which concerns on 1st embodiment of this invention. The figure which shows the manufacturing process of the semiconductor relay apparatus which concerns on 1st embodiment of this invention. The figure which shows the principle of operation of a semiconductor relay apparatus. The figure which shows the 1st example of the structure of the conventional semiconductor relay apparatus. The figure which shows the 2nd example of the structure of the conventional semiconductor relay apparatus. The figure which shows the manufacturing process of the conventional silicon substrate.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Convex part, 2 ... Silicon substrate (substrate), 3 ... LEC (light emitting element), 4 ... Photovoltaic IC (light receiving element), 5 ... MOS-FET (output element), 7 ... Inclined surface (side surface), DESCRIPTION OF SYMBOLS 8 ... Wiring, 9 ... LED mounting electrode (electrode), 10 ... LED connection electrode (electrode), 13 ... Silicone rubber (translucent resin), 14 ... Epoxy resin (light-shielding resin), 16 ... Through electrode, 17 ... Back electrode, 18 ... drain electrode (electrode), 19 ... source electrode (electrode), 20 ... gate electrode (electrode), 21 ... cathode electrode (electrode), 22 ... anode electrode (electrode), 23 ... silicon wafer (wafer) , 25 ... hole (non-through hole), 26 ... hole (non-through hole), 27 ... thermal oxide film (first insulating layer), 29 ... copper (conductor), 31 ... silicon oxide film (second insulation) film).

Claims (9)

At least one first electrode formed on a convex end portion of each convex portion and at least two convex portions on one surface, and an electrode formed on the surface are side surfaces of the convex portion. The electrode formed on the surface and the second electrode formed on the other surface are electrically connected by the through electrode. A substrate,
A light emitting element disposed between the convex portions;
A light receiving element that is disposed so that a light receiving part faces the light emitting element and is bonded so that an electrode is connected to the convex end part;
An output element bonded to the substrate;
A light-transmitting resin that is filled between the light-emitting element and the light-receiving element and transmits light emitted from the light-emitting element;
A light-shielding resin that covers the light-transmitting resin, the light-emitting element, and the light-receiving element;
A semiconductor relay device comprising:   Of the side surfaces of the convex portion of the substrate, at least one surface is an inclined surface with respect to a surface formed by another portion of the substrate, and the wiring is formed on at least one surface of the inclined surface. The semiconductor relay device according to claim 1.   3. The semiconductor according to claim 2, wherein an inclination angle of the inclined surface formed by the side surface of the protruding portion in the vicinity of the protruding end portion and in the vicinity of one surface of the substrate is smaller than an intermediate inclination angle of the inclined surface. Relay device.   3. The semiconductor relay device according to claim 2, wherein the slope formed by the side surface of the convex portion is formed by a curved surface having a curved surface having an inflection point in cross section.   2. The semiconductor relay device according to claim 1, wherein the second electrode is formed in a rectangular groove formed on the other surface of the substrate.   2. The substrate according to claim 1, wherein the substrate is mainly formed of silicon or a silicon compound, a wiring portion of the substrate is formed on an insulating layer, and the through electrode is covered with the insulating layer. Semiconductor relay device. In the method of manufacturing a wiring board having a convex portion on the surface,
Providing a non-through hole on the back surface of the wafer;
Forming a first insulating layer on the back surface of the wafer and the non-through hole;
Filling the non-through holes with a conductor;
Processing the surface of the wafer by etching to provide two protrusions;
Processing and penetrating the bottom surface of the non-through hole from the wafer surface;
Forming a second insulating layer on the surface of the wafer;
Opening the through hole portion of the second insulating layer;
Forming electrode pads and conductive patterns connecting them to the surface of the wafer;
A method for manufacturing a wiring board, comprising:   8. The method of manufacturing a wiring board according to claim 7, wherein the conductor filled in the non-through hole is a hardened paste containing metal particles having a diameter of 20 nm or less.   8. The method of manufacturing a wiring board according to claim 7, wherein the conductive pattern is formed on the surface of the wafer by applying a paste containing metal particles having a diameter of 20 nm or less.

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