JP2005267097A - Electric power source controller, image forming device, image forming system, electric power source control method, computer program, and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate a current flowing into an ASIC in a power source interrupted side to realize a low electric power consumption. <P>SOLUTION: This electric power source controller provided with a main CPU 101 and a sub-CPU 280 to control a power source of the main CPU 101 by the sub-CPU 280 is provided with a power source control part 251 for setting an I/O terminal 261 of a connection terminal to a main CPU 101 side of the sub-CPU 280, to a high impedance, the power source control part 251 sets the I/O terminal 261 of the sub-CPU 280 to the high impedance, before interrupting the power source of the main CPU 101, and holds the I/O terminal 261 in a high impedance condition, during the power source of the main CPU 101 is interrupted. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an energy saving operation of a network interface such as a printer, a copy, and an MFP (multifunction peripheral), and in particular, a power control device for performing energy saving control, a printer connected to a network including the power control device, An image forming apparatus such as a copy, an MFP, an image forming system including the image forming apparatus, a power control method, a computer program for realizing each step of the power control method by a computer, and a recording medium storing the computer program .

  As an image processing apparatus such as a printer having a low power consumption mode (hereinafter referred to as an energy saving mode) for realizing low power consumption, for example, the inventions disclosed in Patent Documents 1 to 4 are known. Among them, Patent Document 1 discloses a signal line switching unit that connects or opens a signal line from a CPU to a built-in device, a detection unit that detects the start and end of use of the built-in device, and the built-in device by the detection unit. An invention is disclosed that includes means for controlling connection of the signal line switching means when the start of use is detected, and controlling the opening of the signal line switching means when the end of use of the built-in device is detected. .

  Further, in Patent Document 2, a control unit is operated by an input from a host computer via a host I / F circuit, and the image forming unit creates image formation data under the control of the control unit. A printer device in which a printing operation is performed by a printing unit based on formation data, and an energy saving mode setting unit is provided for setting the control unit to an energy saving mode by setting a reset mode to the control unit. Is disclosed.

  Patent Document 3 discloses a printer controller that converts print information transmitted from a printer and a host into output image data and outputs the output image data, a power supply device that supplies power to the printer and the printer controller, and In an energy saving standby image forming apparatus having means for switching power supply from the power supply device to the load of the printer to an energy saving mode / operation mode, the power supply lines to the circuit elements of the printer controller are divided into a plurality of systems, There is disclosed an energy-saving standby image forming apparatus comprising means for selectively turning on / off a system.

Further, Patent Document 4 discloses a printer interface for forming an image in an image forming apparatus based on control information and image information sent from the image processing apparatus via a printer interface, and the power source of the image forming apparatus is Control system interface for sending control information that can be used while it is on, and image information that is disabled when it is in a power saving state even when the image forming apparatus is turned on. A printer interface characterized by having an image-based interface is disclosed.
JP 2000-228202 A JP 2001-191616 A JP 2001-328313 A JP 2003-72198 A

  By the way, in the inventions disclosed in the above publications of Patent Documents 1-4, when the end of use of the built-in device is detected, the signal line switching unit is controlled to be opened or the reset mode is set to the control unit. The control means is set to the energy saving mode, the power supply line to the circuit elements of the printer controller is divided into a plurality of systems, and each system is selectively turned on / off, or the image forming apparatus is turned on. A control system interface for sending usable control information, and an image system interface for sending image information that cannot be used when the image forming apparatus is in a power saving state even when the image forming apparatus is turned on. Although various devices have been devised to save power, the state of the terminal when the energy saving mode was entered was not considered. For this reason, a current may flow into a control unit that is turned off when the power is off. If the current flow causes a malfunction or a large current flows, the control unit is configured in an extreme case. There was also a risk of ASIC destruction.

  The present invention has been made in view of the actual situation of the prior art, and an object thereof is to eliminate the current flowing into the ASIC on the side where the power is cut off, and to realize further reduction in power consumption. It is in.

  Another object is to eliminate the possibility of malfunction caused by the flow of current and the destruction of the ASIC constituting the control unit.

  In order to achieve the above object, the first means comprises a plurality of ASICs, and one of the ASICs is provided with a function of shutting off the power of other ASICs connected to the ASIC. And a means for setting the I / O terminal of the first ASIC which is the one ASIC to high impedance.

  The second means is that in the first means, the means for setting the high impedance is to set the I / O terminal of the first ASIC to high impedance before powering off the second ASIC which is the other ASIC. It is characterized by setting.

  According to a third means, in the second means, the means for setting the high impedance sets the I / O terminal of the first ASIC to the high impedance state while the power supply of the second ASIC is shut off. It is characterized by holding.

  The fourth means is characterized in that, in the third means, the high impedance state is held by latching a register.

  The fifth means is the third means wherein the means for setting the high impedance is the I / O terminal of the first ASIC after the power is turned on to the second ASIC that has been turned off. The high impedance state is canceled.

  The sixth means is characterized in that, in the first to fifth means, the second ASIC notifies the first ASIC that the power supply preparation for the second ASIC has been completed.

  The seventh means is the first to sixth means when the first ASIC performs processing that cannot be processed by the first ASIC when the power of the second ASIC is shut off. The ASIC is characterized in that the power supply of the second ASIC is turned on.

  According to an eighth means, in the third to seventh means, the first ASIC is informed that the second ASIC has been turned on after the second ASIC, which has been turned off, is turned on. It is characterized by notifying.

  According to a ninth means, in the first to eighth means, the high impedance setting of the I / O terminal of the first ASIC and the power interruption of the second ASIC are shifted from the normal mode to the low power consumption mode. It is characterized by being performed.

  According to a tenth means, in the first to eighth means, the power-off release of the second ASIC and the release of the high impedance setting of the I / O terminal of the first ASIC are normally performed from the low power consumption mode. It is performed when shifting to the mode.

  An eleventh means is characterized in that, in the first to tenth means, at least one ASIC is substituted for the plurality of ASICs, and a circuit not using the ASIC is substituted for the other ASICs.

  A twelfth means is characterized in that, in the eleventh means, the at least one ASIC and a circuit not using the ASIC are mounted on one board.

  The thirteenth means is characterized in that an image forming apparatus is constituted by the power control apparatus according to the first to twelfth means and image forming means for forming an image on a recording sheet.

  According to a fourteenth aspect, in the thirteenth aspect, the other ASIC includes a main CPU, and the first ASIC includes a sub CPU, and image formation by the image forming means is executed under control of the main CPU. Features.

  According to a fifteenth aspect, the image forming apparatus according to the thirteenth or fourteenth means and a plurality of client computers are connected via a network, and the image forming apparatus is operated by an operation command from the client computer. The image forming system is configured to perform the formation.

  A sixteenth means includes a plurality of ASICs, and one ASIC is the one ASIC before shutting off the power in the power control method for shutting off the power of the other ASIC connected to the ASIC. A first step of setting the I / O terminal of the first ASIC to high impedance, and setting the I / O terminal of the first ASIC to high impedance, and then connecting to the second ASIC which is another ASIC And a third step of maintaining the I / O terminal in a high impedance state while the power is cut off.

  A seventeenth means in the sixteenth means is to release the high impedance state of the I / O terminal of the first ASIC after the power is turned on to the second ASIC that has been turned off. 4 is further provided.

  An eighteenth means is the sixteenth means, wherein the first and second steps are executed when shifting from the normal mode to the low power consumption mode.

  A nineteenth means is the seventeenth means, wherein the fourth step is executed when shifting from the low power consumption mode to the normal mode.

  A twentieth means is characterized in that, in the sixteenth to nineteenth means, at least one ASIC is substituted for the plurality of ASICs, and a circuit not using the ASIC is substituted for the other ASICs.

  The twenty-first means is characterized in that a computer program is configured including a procedure for realizing the power control method according to the sixteenth to twentieth means by a computer.

  The twenty-second means is characterized in that the computer program according to the twenty-first means is read by a computer and recorded on a recording medium in an executable manner.

  In the following embodiment, the second ASIC is connected to the main CPU 101, the first ASIC is connected to the sub CPU 280, the I / O terminal is set to 261, and the means for setting the high impedance is a power control unit (Power ctl.). In 251, setting the I / O terminal of the first ASIC to high impedance before the power supply of the second ASIC is cut off is performed in step S114 while the power supply of the second ASIC is cut off. Holding the I / O terminal of the ASIC in the high impedance state means that the means for setting the high impedance at the timing between step S114 and step S162 is to turn on the second ASIC that has been turned off. After the high impedance state of the I / O terminal of the first ASIC is released in step S162, the second ASI Notifying the first ASIC from the second ASIC that the power supply preparation for the second ASIC is completed cannot be processed by the first ASIC in step S113 when the second ASIC is powered off. When processing occurs, the first ASIC powers on the second ASIC in step S151. After powering on the second ASIC that was powered off, the second ASIC is powered on. Notifying the first ASIC that this has been done is step S158. The high-impedance setting of the I / O terminal of the first ASIC and the power-off of the second ASIC are shifted from the normal mode to the low power consumption mode. In step S114, S115, and S116, the power to the second ASIC is released and the high impedance of the I / O terminal of the first ASIC is performed. The cancellation of the dance setting is performed in steps S151, S152, and S162 when shifting from the low power consumption mode to the normal mode, the first step in step S114, the second step in step S116, and the third step. The process corresponds to step S162 to step S162, and the fourth process corresponds to step S162.

  These controls are executed by the main CPU 101 in the second ASIC and the sub CPU 280 in the first ASIC.

  According to the present invention, since the I / O terminal of one ASIC on the side that shuts off the power source connected to the other ASIC on the side where the power source is shut off can be set to high impedance, the power source is shut off. The current flowing into the ASIC on the other side can be eliminated, and further reduction in power consumption can be realized. Further, since there is no current flow, it is possible to eliminate the possibility of malfunction caused by the current flow or the destruction of the ASIC constituting the control unit.

  Hereinafter, the best mode for carrying out the present invention will be described.

1. 1. System Configuration 1.1 Overall System Configuration FIG. 1 is a diagram showing a configuration of a network system according to an embodiment of the present invention. In FIG. 1, a network system according to the present embodiment includes an image forming apparatus (multifunction machine) 1 having a plurality of functions such as a copying machine and a printer, a printer 2, and a PC using these image forming apparatus 1 or printer 2. (Personal computers) 3, 4 and 5 are connected to the network 6. Note that the number of MFPs 1, printers 2, PCs 3, 4, and 5 connected to the network 6 is an example, and a large-scale system in which many of these are connected or a small-scale system having fewer terminals. It is the same. In this example, it is possible to send a print instruction from any of the PCs 3, 4, 5 to the multifunction device 1 or the printer 2 for printing. The network 6 uses Ethernet (registered trademark) in this embodiment.

  The image forming apparatus 1 and the printer 2 are provided with image forming means having a known structure such as an electrophotographic system or an ink jet system. Since such an image forming apparatus and printer itself are known, a mechanical structure is used here. Details of the configuration and electrical configuration are omitted.

1.2 System Configuration Related to Image Forming Apparatus FIG. 2 is a block diagram showing the configuration of the control unit of the image forming apparatus according to the embodiment of the present invention, and FIG. 3 is a block diagram showing the configuration of the main part. Part 100, an interface part (interface ASIC) 200, and a PCI bus 300 for connecting them.

  The controller unit 100 includes a main CPU 101, an ASIC (Application Specific Integrated Circuit) 102, a memory 103 for storing image data sent via a network, and an HDD 104. The main CPU 101 and image data sent via a network. Are connected to the ASIC 102, and the ASIC 102 is connected to the PCI bus 300. The main CPU 101 controls an image forming apparatus (not shown), and the ASIC 102 controls input / output of data to / from the main CPU 101, the memory 103 that stores image data sent via the network, and the HDD 104.

  An IEEE 1394 board 301 and a wireless run board 302 are connected to the PCI bus 300, and an interface ASIC 200 is connected to the PCI bus 300.

  The interface ASIC 200 is connected to the USB 210, IEEE 1284 (220), the network 230 (corresponding to the network 6 in FIG. 1), the external factor input 240, and the power control line 250. The power control line 250 is connected to the power circuit 310 to control power. In response to a command output via the line 250, power is supplied from the power supply circuit 310 to the controller unit 100, and thus to the main CPU 101 via the power supply line 311.

Further, the PCI bus 300 is connected to the PCI 260 through the PCI 260, and this connection is established by the I / O terminal 261 of the PCI 260. The PCI 260 is connected to an arbiter 270 and a system interface (system i / f) 271 as components on the interface ASIC 200 side. Hereinafter, the interface is also abbreviated as I / F or if.

  A USB physical layer (USB Phy) 211, a USB SIE 212, and a DMAC (Direct Memory Access Controller) 213 are connected to the USB 210, and the DMAC 213 is connected to an arbiter 270.

  IEEE 1284 (221) and DMAC 222 are connected to the IEEE 1284 connection line, and DMAC 222 is further connected to arbiter 270.

  An Ethernet (registered trademark) physical layer (Ethernet (registered trademark) Phy) 231 and a MAC IP (Mediea Access Control Internet Protocol) 232 are connected to the network 230. The MAC IP 232 is provided with a tx buffer 232t and an rx buffer 232r, the MAC_txif 233 and MAC_rxif 235 are connected to the former, respectively, and a DMAC_tx 234 and a DMAC_rx 237 are connected via the bus 289, and the DMAC_tx 234 and the DMAC_rx 237 are further connected to the arbiter 270. Yes. Reference numerals 212a, 221a, 233a, and 235a are bus switching circuits, respectively, and mac_config 225 is for setting MAC_IP, mac_txif, and mac_rxif.

  The mac_rxif 235 is also connected with an rx RAM 236 and a wake-on-run (also referred to as Wake On Lan-WON) 238, and the wake-on-run 238 is connected via a power management unit 241 and a bus 289. It is connected to an interrupt controller (INT Controller) 239. An external factor 240 and an internal factor 241 are input to the power management unit 241, and a control signal is output to the power control unit (Power Controller) 251. The wake-on-run 238 is provided with a pattern filter. In the energy saving mode, as will be described later, if a specific pattern is included in the transmitted packet, the power management unit 241 causes the power control unit 251 to The main CPU 101 (controller unit 100) is instructed to turn on the power.

  The power management unit 241 is connected to the bus 289, the power control unit 251, the sub CPU 280, the ROM 281, the RAM 282, the RAM 286, and the master interface (master i / f) 287 are connected to the bus 290, and the RAM 286 is connected to the bus 290 and the bus 291. Are connected to each other via a RAM i / f 285. The master i / f 287 is also connected to the arbiter 270, and the arbiter 270 responds to a signal from the master i / f 287 according to the DMAC 213, 222, DMAC. tx234, DMAC. The connection state of rx237 is arbitrated. Further, the bus 289, the bus 290, and the bus 291 are connected to the bus arbiter 283, and the bus arbiter 283 arbitrates the use of the buses 289, 290, and 291. A system register (sysreg) 284 is connected to the bus 291, and an expansion i / f 288 is connected to the bus 290. The system register 284 stores version information of the interface ASIC 200 in this embodiment. Thereby, it is used for version upgrade or identification when a bug is found in the ASIC 200.

  The sub CPU 280 controls on / off of the power source of the main CPU 101 in the energy saving mode, and executes the processing when processing can be performed without using the main CPU 101 in the energy saving mode. Conversely, in the normal mode in which the main CPU 101 operates, the sub CPU 280 is set in an energy saving state (low power consumption state).

1.3 Internal Configuration of mac_rxif FIG. 4 is a block diagram showing details of the internal configuration of mac_rxif. In the figure, mac_rxif 235 is a MAC rxi / f 235-1 that functions as an interface with MAC IP 232, WOLi / f 235-2 that functions as an interface with wake-on-run 238, a packet type filter (packet type filter-TCP Header Same as Filter) 235-3, rx buffer interface (rx buffer i / f) 235-4 functioning as an interface with the rx buffer 232r, packet entry generator (packet entry gen.) 235-5 packet entry register (packet entry reg 235-6, mask register (msk reg) 235-7, interrupt register (int reg) 235-8, cpu i / f 235-9, selector 235-10 and dmac i / f 235-11.

  With this configuration, transmission data from the network 6 input from the MAC IP 232 is input to the WOLi / f 235-2, the packet type filter 235-3, and the rx buffer interface 235-4, and from the WOLi / f 235-2 to the WOL 238. The packet type filter 235-3 can input information to the interrupt register (int reg) 235-8 and the packet entry generator 235-5 from the rx buffer interface 235-4 to the rx RAM 236, respectively. In addition, information from the rx RAM 236 is input to the dmac i / f 235-11 or the CPU i / f 235-9 by the selector 235-10 operating according to an instruction from the sub CPU 280.

  The packet type filter 235-3 selects only a packet in which preset information is written in the energy saving mode, and notifies the packet entry generator 235-5 whether or not the packet should be selected. Based on the notification, the register 235-6 instructs the rx buffer interface 235-4 to store information in the rx RAM 236, and only the information selected by the packet type filter 235-3 is stored in the rx RAM 236. become. This stored information is processed by the sub CPU 280 although it will be described later.

  FIG. 5 is a diagram showing a memory map of the rx RAM 236. As can be seen from FIG. 5, the rx RAM 236 includes a TYPE 236-1, a LENGTH 236-2, a packet 236-3, and a Status 236-4. TYPE 236-1 stores the numbers of packet filters and pattern filters, and this number indicates which filter has been received. LENGTH 236-2 indicates the length of the received packet, and the content of the received packet (here, the content of Packet 1) is stored in Packet 236-3. In Status 236-4, received packet information, that is, packet information from MAC IP 232 is stored.

  The packet entry register 235-6 has an address management function for registering where and what packet is written in the rx RAM 236, and stores the head address of the received packet N in the rx RAM 236. In the normal mode, since the packet type filter 235-3 does not function, all information is temporarily stored in the rx RAM 236, sent from the dmac i / f 235-11 to the controller unit 100 via the DMAC_rx 237, and the main mode. Processed by the CPU 101.

  An interrupt signal is output from the registers (int reg. 235-8, msk reg. 235-7), and this interrupt signal is sent to the interrupt controller (INT controller) 239 to perform a predetermined interrupt. The mask register 235-7 outputs a mask signal for masking the input terminal of the interface ASIC 200 so as not to be affected by the outside.

2. Operation 2.1 Normal mode (normal operation mode)
In the control unit configured as described above, in the normal mode, the main CPU 101 receives print data from the network, the ASIC 102 writes the data in the memory 103, and then sends the data to the print engine to perform printing. At this time, the sub CPU 280 is set to the low power consumption mode, and the sub CPU 280 is in a state where a minimum power consumption is required. In this embodiment, the power of the sub CPU 280 is not turned off, but the clock is set to 0 (clock is stopped) so that the operation of the sub CPU 280 is not performed.

  In this state, the print data is input from the network 6 to the memory 103 via the Ethernet (registered trademark) physical layer 231 via the MAC IP232 rx buffer 232r, mac_rxif235, DMAC_rx237, arbiter 270, PCI260, PCI bus 300, and ASIC102. Is drawn in the memory 103. Conversely, when data stored in the memory 103 or HDD 104 is transmitted to another device, the data is the ASIC 102, PCI bus 300, PCI 260, arbiter 270, DMAC_tx234, mac_txif233, MAC IP232 tx buffer 232t, Ethernet (registration). Trademark) is sent to the network 6 through the physical layer 231. In this normal operation state, the data input to the mac_rxif 235 is temporarily stored in the rx RAM 236 and then extracted in the stored order and output from the mac_rxif 235 to the DMAC_rx 237 side.

  Further, data is transmitted / received from / to the controller unit 100 via the USB physical layer 211 via the USB SIE 212, DMAC 213, arbiter 270 and PCI 260 from the USB 210, and from the IEEE 1284 (220), the IEEE 1284 (221), the DMAC 222, the arbiter 270. In addition, data is transmitted to and received from the computer unit 100 via the PCI 260.

  At this time, the low power consumption state is set to the sub CPU 280, the ROM 281 storing the program of the sub CPU 280, and the RAM 282 functioning as a work area of the sub CPU 280.

2.2 Energy saving mode (low power consumption mode)
In this energy saving mode, when data is not input to the control unit from the outside for a predetermined time, or a PC connected to the control unit of the image forming apparatus (not shown) or the network 6 (corresponding to PC 3, 4, 5 in FIG. 1). In this mode, power is not supplied to the controller 100 including the main CPU 101. That is, the power supply circuit 310 that supplies power to the controller 100 is not energized. This energization control is performed by the power control unit 251 via the power control line 250, and the power control unit 251 turns on / off the energization to the controller unit 100 according to an instruction from the power management unit 241 or an instruction from the sub CPU 280. Control.

  The transition from the normal mode to the energy-saving mode and the transition from the energy-saving power mode to the normal mode will be described later. In the energy-saving mode, the driving power is not supplied to the controller unit 100 including the main CPU 101, so the main CPU 101 does not operate. The memory 103 and the HDD 104 cannot be used. In this state, the parts related to the network 6, the external factor 240, and the power control line 250 are energized, and the parts related to the USB SIE 212 and IEEE 1284 (221) are not energized.

  In the energy saving mode, the power supply to the controller unit 100 is cut off, and communication with the network 6 is controlled by the sub CPU 280. If the data input via the network 6 can be processed by the sub CPU 280, the energy saving mode is continued as it is. However, if the print data is input via the network 6, the sub CPU 280 cannot process it, so the controller 100 starts energization and shifts from the energy saving mode to the normal mode.

  In the energy saving mode, packets input to the image forming apparatus 1 from the network 6 are filtered by the packet type filter (TCP Header Filter) 235-3 of the mac_rxif 235, in other words, preset in the input packets. A packet in which information is written is selected by the filter 235-3 and stored in the rx RAM 236, and a packet in which the information is not written is overwritten and is not substantially stored.

2.3 Transition from Normal Mode to Energy Saving Mode FIG. 6 is a diagram showing the operating states of the main CPU 101 and the sub CPU 280 and the processing timing when shifting from the normal mode to the energy saving mode. In the figure, in the normal mode, the main CPU 101 is in an operating state (energized state), and the sub CPU 280 is in a DOZE state (clock is stopped). Therefore, although the sub CPU 280 is energized, the clock is not supplied, so that the power is not substantially consumed. Even in this state, there is a leakage current, so the power consumption is not zero, but the power consumption is a minimum.

  In this state, the main CPU 101 first enables the packet type filter (TCP Header Filter in the figure) 235-3 (step S101), and then enables the pattern filter provided in the WOL 238 (step S102). Then, an interrupt is generated from the interrupt controller 239, and an energy saving mode transition request is output to the sub CPU 280 (step S103). The energy saving mode transition request is output when a preset time has elapsed since the end of the last job, or when there is an energy saving mode transition instruction from any of the PCs 3, 4, and 5 connected to the network 6. Is done. In some cases, the input is performed from the operation panel of the image forming apparatus 1. In the following description including FIG. 6, INT indicates an interrupt.

  When the energy saving mode transition request is output to the sub CPU 280 in this way, the sub CPU 280 confirms the cause of the energy saving mode transition. The factor in this case is confirmed by the output of the pattern filter. When the sub CPU 280 confirms the cause of the energy saving mode transition, the sub CPU 280 starts the energy saving mode transition processing (step S104). In the energy saving mode transition process, the sub CPU 280 first accesses the main CPU 101 and checks the setting information with respect to the main CPU 101 (step S105). In this case, the setting information is information related to the network 6 and paper information in the image forming apparatus 1. The main CPU 101 receives the setting information confirmation from the sub CPU 280 and transmits the setting information (step S106).

  The sub CPU 280 receives confirmation of the setting information from the main CPU 101 and transmits a migration preparation completion notification to the main CPU 101 (step S107). The main CPU 101 confirms the transition preparation completion notification (step S108), and enters the preparation stage of the main CPU 101 for shifting to the energy saving mode. In the sub CPU 280, after preparation for shifting to the energy saving mode is completed in step S107, the packet switching bus 289 is switched to the sub CPU 280 side by the bus switching circuits 233a and 235a, respectively, and transmission / reception processing in the sub CPU 280 is started (step S109). . Then, the sub CPU 280 waits for the elapse of the cancellation cancellation grace monitoring time T1 to the energy saving mode, and when a factor that prevents the transition to the energy saving mode does not occur before the grace monitoring time T1 elapses, the sub CPU 280 requests to stop the DMAC_rx237. Is output to the main CPU 101 (step S110). The grace monitoring time T1 is set to a time at which the main CPU 101 completes at least the processing of the packet transmitted from the network 6 after the sub CPU 280 completes preparation for shifting to the energy saving mode. As a result, communication between the network 6 and the system of the image forming apparatus 1 is not interrupted, and the transferred packet to be processed is always processed by the main CPU 101 or the sub CPU 280. In addition, even if the sub CPU 280 switches the packet transfer path to the sub CPU 280 side in step S109, the grace monitoring time T1 is transferred to the sub CPU 280, and packets that have not been processed yet by the main CPU 101 remain in the DMAC. This also corresponds to the time for processing those packets. If this grace period elapses, processing on the main CPU 101 side has already ended even if DMAC_rx 237 is stopped, so that an unprocessed packet does not occur.

  The main CPU 101 receives the DMAC 234, 237 stop request from the sub CPU 280 and stops the DMA transfer (step S111). When the main CPU 101 receives an interrupt from the DMACs 234 and 237 and confirms that the DMA transfer is stopped (step S112), the main CPU 101 outputs an energy saving mode transition request to the sub CPU 280 (step S113).

  When the sub CPU 280 receives the request for shifting to the energy saving mode from the main CPU 101, an input / output terminal is connected to the sub CPU 280 side, so that unnecessary power consumption is not generated from the external terminal when the main CPU 101 is turned off. I / O terminal processing is executed (step S114), and power supply to the controller unit 100 including the main CPU 101 is stopped for shifting to the energy saving mode on the main CPU 101 side (step S115). As a result, the power supply to the main CPU 101 is cut off, and the controller unit 101 including the main CPU 101 enters a shutdown state (step S116). Thus, the transition to the energy saving mode is completed, the control right is transferred from the main CPU 101 to the sub CPU 280, and the sub CPU 280 controls the image forming apparatus 1 until the energy saving mode is canceled.

  Note that the monitoring time T1 from step S107 to step S110 is a period provided to cope with a factor that hinders the transition to the energy saving mode after the preparation for shifting to the energy saving mode is completed. When print information is included in the transmitted information, the main CPU 101 has to perform print processing, so it is prepared to cancel the transition to the energy saving mode and return to the normal mode.

2.4 Canceling Transition to Energy Saving Mode FIG. 7 is a diagram showing operation states and processing timings of the main CPU 101 and the sub CPU 280 when a factor inhibiting the energy saving mode transition occurs before the monitoring time T1 elapses. . Here, from step S101 to step S109, the same processing as in the case of shifting to the energy saving mode is executed at the same timing.

  Therefore, in step S109, the packet transfer bus 288 is switched to the sub CPU 280 side, transmission / reception processing in the sub CPU 280 is started, and a factor that inhibits the transition to the energy saving mode occurs on the sub CPU 280 side during the transition cancellation grace monitoring time T1 by the sub CPU 280. When it is done, the energy saving mode transition preparation is canceled (step S121), and a message to that effect is sent to the main CPU 101. In response, the main CPU 101 cancels the energy saving mode transition (step S122). On the other hand, when a factor that hinders the transition to the energy saving mode occurs on the main CPU 101 side, the preparation for shifting to the energy saving mode is canceled (step S123), and a message to that effect is transmitted to the sub CPU 280. In response, the sub CPU 280 cancels the energy saving mode transition (step S124). Then, after the monitoring time T1 has elapsed, if there is a packet that has already been received on the sub CPU 280 side and should be processed on the main CPU 101 side, it is handed over to the main CPU 101 side (step S125), and the main CPU 101 receives this (step S125). S126).

  For example, when a magic packet described later is transferred to the wake-on-run 238, or when print data is input from the USB 210 or IEEE 1284 (220) to the power management unit 241 as a factor that inhibits the transition to the energy saving mode. Data that the main CPU prints from the network 6 when an instruction to perform an operation related to an image forming operation such as pressing the start button or operating the ADF pressure plate is input from the operation unit of the image forming apparatus 1 as an external factor. Such as when has been transferred. If such a factor occurs, printing cannot be performed when the mode is shifted to the energy saving mode. Therefore, the operation is performed in the normal mode without shifting to the energy saving mode.

  On the sub CPU 280 side, after transferring data in step S125, the packet transfer bus 288 switched in step S109 is returned to the main CPU 101 side, and transmission / reception processing in the sub CPU 280 is stopped (step S127). After the packet transfer bus 288 is switched to the main CPU 101 side, the main CPU 101 permits the sub CPU 280 to shift to DOZE (step S128). The sub CPU 280 confirms the external factor and the internal factor, and if there is no problem in the DOZE transition, stops the clock transfer and shifts to the DOZE state (step S129). In this state, since the sub CPU 280 is also returned to the normal mode, the control by the main CPU 101 is executed, and the packet filter is disabled (step S130) and the pattern filter is disabled (step S131). Return to normal mode.

  By controlling in this way, even after the transition processing to the energy saving mode is started, it is possible to return to the normal mode without shifting to the energy saving mode, and during the transition and return period, both the main CPU 101 and the sub CPU 280 operate. Because communication is not interrupted on the network. As a result, no data is lost.

2.5 Return from Energy Saving Mode to Normal Mode FIG. 8 is a diagram showing the operation states of the main CPU 101 and the sub CPU 280 and processing timing when returning from the energy saving mode to the normal mode. In the state of FIG. 8, the main CPU 101 is in a power-off (shutdown) state, and the sub CPU 280 is operating in an energy saving mode. In this state, when a factor for returning from the energy saving mode to the normal mode occurs in the sub CPU 280 (step S151), the main CPU 101 is turned on (step S152). As will be described later, the cause of returning from the energy saving mode to the normal mode is that if a packet sent from the network 6 by the packet type filter 235-3 includes a specific packet, here a SYN packet (SYN flag), the power source When a signal is input from the USB 210 or IEEE 1284 (220) to the management unit 241, an operation signal before image forming processing is input from the outside, such as when an input from the operation unit or the ADF pressure plate is operated. In this case (external factor), the pattern filter provided in the WOL 238 detects a pattern indicating a return factor.

  The power supply is turned on when a power supply control unit 251 sends a signal for supplying power to the main CPU 101 via a power supply control line 250 to a power supply unit (Power Supply Unit-PSU) 310. When the main CPU 101 is powered on in this way, the main CPU 101 executes a boot process and executes a series of processes for starting up. On the other hand, the sub CPU 280 continues the packet processing as the pattern filter is disabled (step S153) (T2). This is because the main CPU 101 is in the power-on state, but is in the boot state, and the main CPU 101 still cannot process packets. Then, the packet processing is continued until the sub CPU 280 detects the return factor packet (in this embodiment, SYN packet) (step S154), and when the return factor packet is detected, the sub CPU 280 stops the packet processing, and the main CPU 101 Wait for an interrupt (T3). The detection of the interrupt factor in step S154 means that the packet processing of the sub CPU 280 proceeds after the packet is not input from the pattern filter by disabling the pattern filter in step S153, which becomes a return factor. This means that a packet is detected, and after that, even if processing is performed on the main CPU 101 side, it means that there is no packet processed on the sub CPU 280 side.

  Therefore, the main CPU 101 confirms the power-on factor at the end of the boot process (step S155), and then enters the operating state. Then, the sub CPU 280 is accessed to confirm the setting conditions (step S156), and the transmission / reception buffers (tx buffer 232t and rx buffer 232s) are initialized (step S157). Since it is possible to return to the normal mode in this state, an interrupt is issued to notify the sub CPU 280 that preparation for shifting to the normal mode is completed (step S158). Since the sub CPU 280 waits for an interrupt from the main CPU 101 at T3, the sub CPU 280 shifts to the DOZE state when the interrupt is confirmed in step S158 (step S159). Since the main CPU 101 has returned to the normal mode, DMA transfer is started (step S160), and the packet type filter (TCP Header Filter) 235-3 is disabled (step S161). As a result, the packet input to the mac_rxif 235 once enters the rx RAM 236, but without being subjected to filter processing, it is transmitted to the controller unit 100 as it is, stored in the memory 103, and then processed by the main CPU 101.

  It should be noted that the pattern filter disable in step S153 is preferably set at an early timing after the return factor is generated in step S151. This is because the earlier the timing, the lower the possibility of overlapping power-on signals. The packet type filter 235-3 in step S161 is set to be disabled after the sub CPU 280 shifts to the DOZE state. This is to eliminate the possibility that packet processing to be processed by the sub CPU 280 remains, so that the packet processing to be processed on the sub CPU 280 side is surely completed and the network 6 is not operated in the state where the sub CPU 280 is not operated. All packets transferred through the network are sent to the main CPU 101 side.

  This prevents communication from being interrupted on the network when returning from the energy saving mode to the normal mode.

2.6 Processing when Power is Turned On FIG. 9 is a diagram showing operation states of the main CPU 101 and sub CPU 280 and processing timing when power is turned on. In this embodiment, the story is mixed, but since the sub CPU 280 controls the power of the CPU 101, the power of the sub CPU 280 is first turned on as shown in FIG. 9 when the power is turned on (step S171). Then, the main CPU 101 is turned on (step S172). Thereafter, both perform boot processing, the sub CPU 280 rises first, sets the status of the sub CPU 280 in the RAM 286 (step S173), stops the clock, and enters the DOZE state.

  On the other hand, after confirming the power-on factor, that is, the set contents written in the RAM 286 (step S174), the main CPU 101 starts up, initializes the network-related parts, and enables communication with the network 6 (step S175). ), DMA transfer and communication are started (step S176). As a result, the main CPU 101 is activated and operates in the normal mode. At this time, the sub CPU 280 is in the DOZE state, and the sub CPU 280 side is in the energy saving state.

3. I / O terminal processing The I / O terminal processing executed in step S114 is processing as described below.
In the system shown in FIGS. 2 and 3, the I / O terminal used in the PCI bus is controlled to the Hi-Z (high impedance) state before the power is shut off, and the Hi-Z state is also kept during the power shut-off. Thus, the current flowing into the ASIC on the side where the power is cut off is eliminated, and the reduction in power consumption is promoted. By maintaining the Hi-Z state in this manner, not only low power consumption but also malfunctions and control reliability are intended. In other words, if the power supply is cut off, the electric charge accumulated when the power supply is cut off will flow to the unintended side, causing a malfunction, or short-circuiting, causing a large current to flow and destroying the element. become. Therefore, in this embodiment, the I / O terminal 261 is set to the Hi-Z state so that such a situation does not occur.

  In order to hold the Hi-Z state, for example, an enable bit for setting the Hi-Z state is prepared in advance in a register (not shown), and the sub CPU 280 rewrites the corresponding bit in the register so that the enable bit is flip-flop (see FIG. (Not shown). Even when the Hi-Z state is released, the sub CPU 280 rewrites the corresponding bit. Basically, the enable bit is prepared for each related I / O terminal (for each function) such as for PCI bus, general-purpose I / O, or SD card. In this embodiment, the I / O terminal 261 is referred to, but the I / O terminal 261 is also referred to as an I / O pin or simply a pin.

  FIG. 10 is a diagram showing the state of the I / O terminal with respect to the state when the power is turned on in FIG. 9. In FIG. 10, the I / O terminal is controlled to Hi-Z of the ASIC on the power source control side. The state of the I / O terminal that can be performed is shown. In this embodiment, the main CPU 101 is equal to the state of the ASIC on the side where the power is controlled, and the sub CPU 208 is equal to the state of the ASIC on the side where the power is controlled, so the state of the I / O terminal controlled by the sub CPU 280 is changed. Show.

  Immediately after the system is turned on, the I / O terminal that can be controlled to Hi-Z is not controlled to the Hi-Z state. That is, when the main CPU 101 (the ASIC on the power source control side) is in the active state, the I / O terminal of the sub CPU 208 (the ASIC on the power source control side) is not controlled to Hi-Z. However, the Hi-Z state may occur for an arbitrary time as a part of the normal function.

  When shifting to the low power consumption mode (energy saving mode), as described with reference to FIG. 6, when the energy saving transition request is notified from the main CPU 101 (step S113), I / O terminal processing is executed (step S113). In step S114, the I / O terminal of the sub CPU 208 (the power-off ASIC) connected to the main CPU 101 (the controlled ASIC) is controlled to the Hi-Z state. Thereafter, immediately after the sub CPU 280 shifts to the energy saving mode in step S116, the power source of the main CPU 101 is shut off (in the shutdown state in FIG. 6). During the energy saving mode, the I / O terminal of the sub CPU 280 connected to the main CPU 101 is held in the Hi-Z state. By these operations, it is possible to eliminate the current flowing into the main CPU 101 in the low power consumption mode, and it is possible to further reduce the power consumption.

  FIG. 11 is a diagram showing operation states of the main CPU 101 and the sub CPU 280 and processing timing when returning from the energy saving mode to the normal mode. When returning from the energy saving mode to the normal mode, as shown in FIG. 11, the main CPU 101 (the ASIC on which power is first shut off) is turned on in step S152, and then the sub CPU 280 (power is turned off). The ASIC on the side that performs the I / O terminal process (step S162) releases the Hi-Z state of the I / O terminal connected to the main CPU 101 (the ASIC on the power-off side). By these operations, it is possible to eliminate the current flowing into the main CPU 101 (the ASIC on which the power has been cut off) when the power is turned on when shifting from the energy saving mode to the normal mode. Other processes that are not specifically described are the same as those in FIG.

  In this embodiment, as shown in FIG. 2, a circuit having two ASICs such as an interface ASIC 200 and an ASIC 102 of the controller unit 100 is described. However, the controller unit 100 is used as a power supply circuit that does not use the ASIC 102. It can also be configured as a circuit that is mounted on the same board as the ASIC 200. Even in this case, the I / O terminal 261 on the ASIC (here, the interface ASIC 200) side is controlled to the Hi-Z (high impedance) state before the power is shut off, and is kept in the Hi-Z state even while the power is shut off. Thus, it is possible to eliminate the current flowing into the circuit on the side where the power is cut off and promote the reduction in power consumption. The board can also be applied to an option board such as a network board.

The actual control procedure is shown in the flowchart of FIG.
In this figure, when the preparation for transition from the normal mode to the low power consumption mode is completed (steps S181 and S182—corresponding to step S107 in FIG. 6), the sub CPU 280 (the ASIC on the power cut-off side) The I / O terminal connected to the ASIC on the side to be shut off is set to the Hi-Z state (corresponding to step S114 in FIG. 6), and then the main CPU 101 (ASIC on the side to be shut off) Is turned off (corresponding to step S 184 -step S 116 in FIG. 6). During the energy saving mode, the I / O terminal of the sub CPU 280 (the ASIC on the power cut-off side) connected to the main CPU 101 (the ASIC on the power cut-off side) remains in the Hi-Z state.

  Here, during the energy saving mode, when processing that cannot be processed by the sub CPU 280 (ASIC on the side that shuts off the power supply) occurs (normal mode transition factor occurs) (step S185—corresponding to step S151 in FIG. 11). Then, the main CPU 101 (the ASIC on which the power was cut off) is turned on (step S186—corresponding to step S152 in FIG. 11). Thereafter, the Hi-Z state of the I / O terminal of the sub CPU 280 connected to the main CPU 101 (the ASIC connected to the ASIC that cuts off the power supply) is canceled (step S187—to step S162 in FIG. 11). To the normal mode (step S189). To the normal mode, the sub CPU 280 enters the DOZE state in step S159 in FIG. 11, and is completely restored by disabling the packet type filter (TCP Header Filter) in step S161 in FIG.

4). Network Filter As described above, in this embodiment, a packet transmitted by the packet type filter (TCP Header Filter) 235-3 and the pattern filter is selected, and a predetermined process is executed.

4.1 Packet Type Filter (TCP Header Filter)
4.1.1 IP Packet FIG. 13 is a diagram showing the structure of an IP packet filtered by the packet type filter 235-3. In the figure, an IP packet 200 includes an IP header 201, a TCP header 202, and TCP data 203. The TCP header 202 and the TCP data 204 constitute a TCP datagram 205, and the TCP datagram 205 and the IP header 201 indicate IP data. Gram 206 is constructed.

4.1.2 IP Header Format FIG. 14 is a diagram showing the format of the IP header 201 of FIG. 13, that is, the internal structure of the IP header format. The IP header format includes a version information field 201a, a header length field 201b, a TOS (type of service) field 201c, a total length (tos_len) field 201d, an identification (ID) field 201e, a flag field 201f, a fragment offset field 201g, and a TTL field 201h. Protocol field 201i, header checksum field 201j, source IP address field 201k, destination IP address field 201l, and option field 201m.

  In this configuration, the version information field 210a is fixed to 4, and the header length (IP header length) field 210b indicates the header length including the option area. The TOS field 210c indicates a guideline for what is given priority in packet processing. The total length (IP packet length) field 210d indicates the length of the entire IP packet 200. The identification (ID) field 210e and the fragment offset field 210g are used to realize IP level fragmentation (packet division) and reassembly. The TTL field 210h indicates the remaining lifetime of the IP packet on the network. The header checksum 210j is a checksum of only the IP header portion.

4.1.3 TCP Header Format FIG. 15 is a diagram showing the format of the TCP header 202 of FIG. 13, that is, the internal structure of the TCP header format. The TCP header format includes a source port number (source) field 202a, a destination port number (dest) field 202b, a sequence number field 202c, an acknowledgment (AKC) number field 202d, a header length field 202e, a reservation field 202f, and a flag field 202g. , A window size field 202h, a TCP checksum 202i, an urgent pointer field 202j, and an option field 202k.

  The source port number field 202a indicates the source TCP port number, and the destination port number 202b indicates the destination TCP port number. The sequence number field 202c indicates where the packet is located in the data stream, and the response number (ACK) sequence number for the received packet is written in the acknowledgment number field 202d, indicating how far the received packet has been received. Notify the other party. The header length field 202e indicates the TCP header length, and the header length changes depending on the presence or absence of the option field 202e. Six types of flags from URG to FIN are written in the flag field 202g, and the window size field 202h notifies the size of the reception window. The TCP checksum 202i is calculated for both the TCP header and data (also using some information of the IP head). The emergency pointer field 202j points to the end of the emergency data.

  The six types of flags in the flag field 202g are shown as drawn with a leader line, as shown in URG flag 202g-1, ACK flag 202g-2, PSH flag 202g-3, RST flag 202g-4, SYN flag 202g-5, FIN It consists of a flag 202g-6. The URG (urgent) flag 202g-1 indicates that the emergency pointer in the emergency pointer field 202j is valid. The ACK (response) flag 202g-2 indicates that the confirmation response number 202d in the confirmation response number field is valid. Normally this flag is always on. The PSH (PUSH) flag 202g-3 indicates that transmission is performed as soon as possible. An RST (RESET) flag 202g-4 is a flag for requesting a connection reset. The SYN flag 202g-5 is a flag requesting the probability of connection, and the FIN flag 202g-6 is a flag requesting termination of the connection.

  FIG. 16 is a diagram showing a basic connection sequence of the TCP protocol. In this connection sequence, when an ARP (address resolution protocol) request is sent from the PC to the GW, an ARP response is returned from the GW and the address is resolved, a SYN is sent from the PC to the GW, and an ACK is returned from the GW. A TCP session is established, and further, SYN / ACK is sent from the PC to the GW for communication.

4.2 Pattern Filter In this embodiment, in addition to the packet type filter (TCP Header Filter) 235-3 provided in the mac_rxif 235, a pattern filter is provided in the wake-on-run 238, which is a packet called a so-called magic packet. Are filtered by pattern matching to execute a predetermined process.

  The function of the wake-on-run 238 is a function that can be activated from another machine on the network, here, a PC. The PC is a wake-up frame (when the image forming apparatus 1 is in the energy saving mode). A so-called magic packet) is transmitted. If this frame includes the correct MAC address, the image forming apparatus returns from the standby or suspend state and functions in the normal mode.

  For this magic packet selection, for example, a 64 byte pattern matching field is provided in the transmitted packet, and the data written in this field and the pattern filter of the wake on run 238 are set in advance. The pattern matching with the data is taken, and when the pattern matching is taken, the wake on run 238 wakes up the system. The system wakes up by pattern matching the packet sent to the wake on run 238 via the network 6, MAC IP232, mac_rxif235-1, WOLi / f235-2. It is determined that a magic packet has been transmitted when Based on this determination, the wake-on-run 238 instructs the power management unit 241 to turn on the main CPU 101 by the power control unit 251. Based on this instruction, the power control unit 251 outputs an instruction to supply power from the power control line 250 to the power supply unit 310, and power is supplied to the controller unit 100 including the main CPU 101. This procedure corresponds to step S151 and step S152 in FIG. 8 in which the main CPU 101 is turned on due to the return of the magic packet and the normal mode is restored from the energy saving mode.

  At this time, in FIG. 8, the return factor is generated for the sub CPU 280 (step S151), but this figure only shows that the sub CPU 280 is operating at this time, and the sub CPU 280 is in the energy saving mode. The operation to return to normal mode from is not performed. In addition, since the procedure for detecting the magic packet and returning from the energy saving mode to the normal mode has been started, it is not necessary to keep the pattern filter functioning or to avoid the risk of malfunction due to the pattern filter. In step S153, the pattern filter is disabled.

4.3 Filter control 4.3.1 Necessity of filter control In this way, whether or not the packet type filter and the pattern filter are to be functioned is determined by the energy saving mode and the normal mode.
In this embodiment, the SYN flag 202g-5 is detected by a packet type filter (TCP Header Filter) 235-3 provided in the subsequent stage of mac_rxif 235-1 in the energy saving mode (see FIG. 4), and the SYN flag 202g-5 is detected. After the packet main CPU 101 is activated, the main CPU 101 processes the packet. However, in the normal mode, since the main CPU 101 performs all control, it is not necessary to distinguish between those that include the SYN flag and those that do not. Therefore, it is necessary to turn on / off the packet type filter (TCP Header Filter) 235-3, and set operation or non-operation according to the mode or processing status. The pattern filter only needs to function in the energy saving mode, and does not need to function in the normal mode. Further, since the main CPU 101 is already in the power-on state when functioning in the normal mode, the power-on control is further performed in the power-on state, which may cause a malfunction. Therefore, the pattern filter also needs to be set to be activated or deactivated according to the mode or processing status.

4.3.2 Energy saving state transition (1)
FIG. 17 is an energy saving state transition diagram showing a transition state when there is a request for shifting to the energy saving mode and when there is a request for returning to the energy saving mode. As shown in this figure, when the power is turned on (step S301), first, it operates in the normal mode (step S302). At this time, both the packet type filter (TCP Header Filter) 235-3 and the pattern filter are off. In this state, when there is a request for shifting to the energy saving mode from the main CPU 101 to the sub CPU 280 (step S103 [step S303]), the mode shifts to the energy saving mode (steps S115 and S116 [step S304]). Both the TCP Header Filter) 235-3 and the pattern filter are on (steps S101 and S102). When a return factor is generated (step S151) and the normal mode is returned by the energy saving return request (step S305), the pattern filter is turned off in step S153, and the packet type filter 235-3 is turned off in step S161. . Such filter control is repeated in the energy saving mode ready state (normal mode) and the energy saving mode to execute the energy saving control.

4.3.3 Energy saving state transition (2)
FIG. 18 is an energy saving state transition diagram showing a transition state when there is an energy saving mode transition request including the energy saving mode transition canceling processing shown in FIG. 7 and an energy saving mode return request. This transition of the energy saving state shows a case where the processing of steps S121 to S124 of FIG. 7 is included in the transition diagram of FIG. That is, when the power is turned on (step S401), first, it operates in the normal mode (step S402). At this time, both the packet type filter (TCP Header Filter) 235-3 and the pattern filter are off. In this state, when there is an energy saving request (energy saving mode transition request (step S103)) from the main CPU 101 to the sub CPU 280, the energy saving mode transition is started (step S105), and when the transition preparation is completed (steps S107 and S108), The packet transfer bus is switched (step S109), and it is monitored whether or not there is a migration cancellation by the sub CPU 280 (step S404). This is referred to herein as an energy saving standby mode. In this monitoring state, the packet type filter (TCP Header Filter) 235-3 and the pattern filter are both turned on in steps S101 and S102.

  In the energy saving standby mode 404 of step S404, when the SYN flag is detected by the packet type filter (TCP Header Filter) 235-3, the probability of the connection of the network 6 is requested. Transfer to the CPU 101 side (corresponding to step S408-step S121). As a result, the main CPU 101 returns to the ready state (step S402), and both the packet type filter (TCP Header Filter) 235-3 and the pattern filter are turned off in steps S130 and S131.

  Further, in the energy saving standby mode 404 in step S404, when the packet type filter 235-3 does not detect the SYN flag before the sub-cancel grace monitoring time T1 elapses by the sub CPU 280, an energy saving transition request is made (step S405). Transition to energy saving mode (corresponding to step S113) (corresponding to step S406-steps S115 and S116). When a return factor occurs (step S151), an energy saving return request (step S407) makes a transition from the energy saving state to the normal mode (step S158), the pattern filter is turned off in step S153, and the packet type filter 235-3 is turned off in step S161. Then, the ready state is entered (step S402). Until the power is turned off, the ready state (step S402), the energy saving standby state (step S404), and the energy saving mode state (step S406) are changed to the energy saving request (step S403), the energy saving cancellation request (step S408), and the energy saving transition request (step S405), transition is made according to each request of energy saving return request (step S407), and energy saving control is executed.

  Each of these steps is realized by a computer program. The program data is stored in the ROM in advance. However, the CD-ROM, the SD card, the optical disk loaded on a server connected to the network or a recording medium driving device (not shown) when necessary or requested by a version upgrade or the like. It is also possible to read and download from a known recording medium such as a magnetic disk.

It is a figure which shows the structure of the network system based on the Example of this invention. 2 is a block diagram illustrating a configuration of a control unit of the image forming apparatus according to the exemplary embodiment of the present invention. FIG. It is a block diagram which shows the principal part of the control part of FIG. FIG. 4 is a block diagram illustrating details of an internal configuration of mac_rxif in FIGS. 2 and 3. It is explanatory drawing which shows the structure of the memory of rx ROM. It is a figure which shows the operation state of the main CPU at the time of transfer from normal mode to energy saving mode, and sub CPU, and the timing of a process. It is a figure which shows the operation state of a main CPU and a sub CPU, and the timing of a process when the factor which inhibits energy-saving mode transfer occurs before monitoring time passes. It is a figure which shows the operation state of the main CPU and the sub CPU and the processing timing when returning from the energy saving mode to the normal mode. It is a figure which shows the operation state and timing of a process of main CPU at the time of power activation, and sub CPU. FIG. 10 is a diagram illustrating a state of an I / O terminal with respect to a state when power is turned on in FIG. 9. It is a figure which shows the operation state of the main CPU and the sub CPU and the processing timing when returning from the energy saving mode to the normal mode. It is a flowchart which shows the process sequence when it transfers to energy saving mode from normal mode, and also transfers to energy saving mode from normal mode. It is a figure which shows the structure of the IP packet filtered by a packet type filter. It is a figure which shows the internal structure of the IP header format which is a format of the IP header of FIG. It is a figure which shows the internal structure of the TCP header format which is a format of the TCP header of FIG. It is a figure which shows the basic connection sequence of TCP protocol. It is an energy-saving state transition diagram which shows the transition state when there exists a request | requirement of an energy-saving mode transfer, and when an energy-saving mode return request | requirement exists. It is an energy-saving state transition diagram which shows the transition state at the time of the energy-saving mode transition request | requirement including the energy cancellation mode transition cancellation process, and an energy-saving mode return request | requirement.

Explanation of symbols

1 Image forming device (multifunction machine)
2 Printer 3, 4, 5 PC (personal computer)
6 Network 20 IP packet 100 Controller 101 Main CPU
103 memory 200 interface ASIC
201 IP header 202 TCP header 202g flag 202g-5 SYN flag 203 TCP data 204 TCP datagram 205 IP datagram 210 USB terminal 220 IEEE1284
232 MAC IP
232t tx buffer
232r rx buffer
233 MAC_txif
234 DMAC_tx
235 MAC_rxif
235-3 Packet Type Filter (TCP Header Filter)
236 rx RAM
237 DMAC_rx
238 Wake on run 239 INT controller 240 External factor 241 Power management
242 Internal factor 250 Power control line 251 Power control unit (Power ctl.)
260 PCI
261 I / O terminal 270 Arbiter 280 Sub CPU
283 Bus Arbiter 289, 290, 291 Bus 300 PCI bus

Claims (22)

In a power supply control device comprising a plurality of ASICs, one of the ASICs having a function of shutting off the power supply of another ASIC connected to the ASIC,
A power supply control device comprising means for setting the I / O terminal of the first ASIC, which is the one ASIC, to high impedance.   The means for setting to high impedance sets the I / O terminal of the first ASIC to high impedance before powering off the second ASIC which is the other ASIC. Power control device.   3. The means for setting to the high impedance holds the I / O terminal of the first ASIC in a high impedance state while the power supply of the second ASIC is shut off. Power control device.   4. The power supply control device according to claim 3, wherein the high impedance state is held by latching a register.   The means for setting to the high impedance cancels the high impedance state of the I / O terminal of the first ASIC after the power is turned on to the second ASIC that has been cut off. The power supply control device according to claim 3.   6. The power supply control device according to claim 1, wherein the second ASIC notifies the first ASIC that preparation for shutting off the power supply of the second ASIC is completed. 7. .   The first ASIC powers on the second ASIC when processing that cannot be processed by the first ASIC occurs when the power of the second ASIC is shut off. The power supply control device according to any one of claims 1 to 6.   8. The first ASIC is notified that the second ASIC is powered on after the second ASIC that has been powered off is turned on. The power supply control device according to item 1.   9. The high impedance setting of the I / O terminal of the first ASIC and the power-off of the second ASIC are performed when shifting from the normal mode to the low power consumption mode. The power supply control device according to any one of the above.   The power supply cutoff of the second ASIC and cancellation of the high impedance setting of the I / O terminal of the first ASIC are performed when shifting from the low power consumption mode to the normal mode. The power supply control device according to any one of 1 to 8.   11. The power supply control device according to claim 1, wherein at least one ASIC is substituted for the plurality of ASICs, and a circuit that does not use the ASIC is substituted for the other ASICs.   12. The power supply control device according to claim 11, wherein the at least one ASIC and a circuit that does not use the ASIC are mounted on a single board. The power supply control device according to any one of claims 1 to 12,
Image forming means for forming an image on recording paper;
An image forming apparatus comprising: The other ASIC includes a main CPU, and the first ASIC includes a sub CPU.
The image forming apparatus according to claim 13, wherein image formation by the image forming unit is executed under control of a main CPU. The image forming apparatus according to claim 13 or 14,
Multiple client computers;
Are connected via a network, and the image forming apparatus is operated by an operation command from the client computer to form an image. In a power supply control method comprising a plurality of ASICs, and one of the ASICs shuts off the power supply of another ASIC connected to the ASIC.
A first step of setting the I / O terminal of the first ASIC, which is the one ASIC, to high impedance before shutting off the power;
A second step of cutting off a power source connected to a second ASIC, which is another ASIC, after setting the I / O terminal of the first ASIC to high impedance;
A third step of maintaining the I / O terminal in a high impedance state while the power is shut off;
A power supply control method comprising:   And a fourth step of releasing the high impedance state of the I / O terminal of the first ASIC after the power is turned on to the second ASIC that has been turned off. The power supply control method according to claim 16.   17. The power supply control method according to claim 16, wherein the first and second steps are executed when shifting from the normal mode to the low power consumption mode.   18. The power supply control method according to claim 17, wherein the fourth step is executed when shifting from the low power consumption mode to the normal mode.   20. The power supply control method according to claim 16, wherein at least one ASIC is substituted for the plurality of ASICs, and a circuit that does not use the ASIC is substituted for the other ASICs.   21. A computer program comprising a procedure for realizing the power control method according to any one of claims 16 to 20 by a computer. 22. A recording medium on which the computer program according to claim 21 is read and recorded so as to be executable.

Images