JP2005251820A - Heterojunction field effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a heterojunction field effect transistor, in which the steep potential distribution by planar doping is sustained and deterioration in device characteristics, e.g. lowering of channel layer electron mobility or increase in gate leak current, is suppressed. <P>SOLUTION: The heterojunction field effect transistor, having a compound semiconductor epitaxial multilayer film formed on a semi-insulating substrate as a constitutive element is arranged, such that planar doped carrier supply layers 103 and 107 exist, respectively, above and below a channel layer 105 via spacer layers 104 and 106, and the sheet concentration of dopant in the planar doped layer is not lower than the lower limit concentration for supplying carriers to the channel layer and is not higher than the upper limit of concentration, where dopant does not diffuse into the channel layer. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a heterojunction field effect transistor, and more particularly to a heterojunction field effect transistor formed by stacking a plurality of compound semiconductor epitaxial films on a semi-insulating substrate.

  BACKGROUND ART A heterojunction field effect transistor (HFET) made of a compound semiconductor epitaxial film stacked on an InP substrate has attracted attention because it exhibits excellent characteristics as a high-frequency low-noise device. As an example of the layer structure, a structure described in Patent Document 1 below will be described with reference to FIG.

  As shown in FIG. 6, in this structure, a buffer layer 202 made of undoped InAlAs is formed on a substrate 201 made of InP, and a channel layer 203 made of undoped InGaAs is formed thereon.

  A spacer layer 204 made of undoped InAlAs is formed on the channel layer 203, and Si is added to the InAlAs spacer layer 204 in a planar shape so that n-type carriers are generated. A planar doped (also referred to as delta doped) layer (also called a carrier supply layer) 205 is formed, and a shot having a laminated structure of a barrier layer 206 made of undoped InAlAs and an etching stop layer 207 made of undoped InP. A key junction forming layer is formed.

  The etching stop layer 207 made of InP stops etching when a part of the contact layer 208 made of n-InGaAs is removed by recess etching to form an opening before the gate electrode 209 is formed. Thus, it has a function of preventing etching of the directly underlying InAlAs layer 206, and is called a recess etching stop layer.

  Usually, in order to obtain a desired threshold voltage (Vth), the sheet carrier density (Ns) generated in the channel layer 203 is controlled by the Si doping concentration in the planar doped layer 205.

The required doping concentration depends on the thicknesses of the channel layer 203, the spacer layer 204, and the Schottky junction formation layer (stacking of 206 and 207), but as a doping concentration to the general planar doping layer 205, As shown in Non-Patent Document 1, a doping concentration of 1 to 2 × 10 ¹³ cm ⁻² or higher is used.

For example, as an example of a typical device layer structure, the thickness of the buffer layer 202 is 200 nm, the thickness of the channel layer 203 is 15 nm, the thickness of the spacer layer 204 is 3 nm, and the barrier layer 206 constituting the Schottky junction formation layer When the thickness of the etching stopper layer 207 is 6 nm and 5 nm, when trying to obtain about 2-3 × 10 ¹² cm ⁻² as practical Ns, the doping concentration to the planar doped layer 205 is about 6 A Si donor concentration of × 10 ¹² cm ⁻² to 1 × 10 ¹³ cm ⁻² is required.

JP-A-6-120258 H. Ishikawa, H .; Shibata, and M.M. Kamada, Appl. Phys. Lett. Vol. 57 (1990) pp. 461-462. “Delta-doping of semiconductors”, Edited by E.M. F. Schubert, (Cambridge University Press, 1996). H. Yokoyama, H .; Sugiyama, Y .; Oda, K .; Watanabe, and T.W. Kobayashi, Jpn. J. et al. Appl. Phys. Vol. 42 (2003) p. 4909-4912. H. Matsuzaki, J. et al. Osaka, T .; Itoh, K .; Sano, and K.K. Murata, Jpn. J. et al. Appl. Phys. Vo 1.40 (2001) pp. 2186-2190.

  Ideally, the planar doped layer 205 has a thickness within one atomic layer, that is, dopant atoms are present in the crystal lattice plane of one layer. However, as described in Non-Patent Document 2, the dopant atoms of the planar doped layer are actually spread on the substrate side and the crystal surface side due to thermal diffusion and surface segregation during crystal growth. As described in Non-Patent Document 3, when this dopant atom spreads to the substrate side, that is, the channel layer side, electrons traveling in the channel layer are easily scattered by the dopant atom, and the electron mobility of the channel layer is lowered. . Further, when the dopant atoms spread to the crystal surface side, that is, the Schottky junction formation layer side, the gate leakage current increases and the device characteristics are deteriorated. Therefore, in order to obtain good device characteristics, it is necessary to realize a steep doping profile with a narrow distribution width as much as possible.

  Compared to the molecular beam epitaxy method (MBE) method, which does not require decomposition of the source gas on the substrate surface, in the case of the metal organic vapor phase epitaxy method (MOVPE method) that requires crystal growth at a relatively high temperature, the planar doped layer is The influence of thermal history during crystal growth is increased. In particular, when the planar doped layer undergoes a long time and high temperature thermal history to grow other device layers on the HFET structure, the diffusion of Si dopant atoms becomes a non-negligible amount and the electron mobility in the channel layer Decrease or increase in gate leakage current may occur.

  In recent years, development of a monolithic integrated device in which an HFET and a resonant tunneling diode photodiode, a Schottky diode, or the like as in Non-Patent Document 4 are stacked has progressed. In order to manufacture these composite devices, it is indispensable to grow a thick laminated film having another element structure on the upper layer of the HFET layer structure. In this case, the planar doped layer undergoes a thermal history for a long time at a high temperature, so that the influence of diffusion of dopant atoms is inevitable. In order to produce the monolithic integrated device as described above while maintaining the original device characteristics using an HFET having a high-concentration planar doped layer, the thickness of the upper laminated film is reduced in order to reduce the influence of thermal history. The sheath structure is limited, and the degree of freedom in device design is narrowed.

  The present invention has been made in view of the above problems, and the problem to be solved by the present invention is that an Si planar doped layer is grown during crystal growth in an HFET structure and a monolithic integrated device structure formed by stacking an HFET and another device. The purpose is to prevent the deterioration of device characteristics such as a decrease in channel layer electron mobility and an increase in gate leakage current due to the spread of Si doping profile due to the thermal history received.

  That is, an object of the present invention is to maintain a steep potential distribution due to planar doping and to suppress degradation of device characteristics such as a decrease in channel layer electron mobility and an increase in gate leakage current. Is to provide. In particular, a heterostructure modulation-doped field effect transistor manufactured using InAlAs as a carrier supply layer is a suitable application target of the present invention.

In the present invention, in order to achieve the above object, as described in claim 1,
A heterojunction field effect transistor having a compound semiconductor epitaxial multilayer film formed on a semi-insulating substrate as a constituent element, wherein the compound semiconductor epitaxial multilayer film is sequentially formed on the semi-insulating substrate, a buffer layer, A first carrier supply layer, a first spacer layer, a channel layer, a second spacer layer, a second carrier supply layer, and a Schottky junction formation layer are stacked, and a gate electrode is formed on the Schottky junction formation layer The source electrode and the drain electrode are formed, the first and second carrier supply layers are planar doped layers, and the dopant sheet concentration in the planar doped layer is a lower limit capable of supplying carriers to the channel layer. The concentration is not less than the upper limit concentration that does not cause dopant diffusion to the channel layer. Constituting the junction type field effect transistor.

In the present invention, as described in claim 2,
2. The hetero field effect transistor according to claim 1, wherein the semi-insulating substrate is made of InP, and the buffer layer, the first spacer layer, the second spacer layer, and the Schottky junction forming layer are configured. A barrier field layer that is an element and is in contact with the second carrier supply layer is made of InAlAs, and the channel layer is made of InGaAs.

In the present invention, as described in claim 3,
3. The heterojunction field effect transistor according to claim 1, wherein a dopant atom to the carrier supply layer which is the planar doped layer is Si.

In the present invention, as described in claim 4,
4. The hetero field effect transistor according to claim 3, wherein a sheet concentration of Si that is a dopant atom of the carrier supply layer that is the planar doped layer is 1 × 10 ¹² cm ⁻² or more and 5 × 10 ¹² cm ⁻² or less. A heterojunction field effect transistor is provided.

  By implementing the present invention, it is possible to provide a field effect transistor that maintains a steep potential distribution due to planar doping and suppresses deterioration of device characteristics such as a decrease in channel layer electron mobility and an increase in gate leakage current. It becomes possible.

An embodiment of the invention according to claim 1 is shown in FIG. As shown in FIG. 1, the field effect transistor of the present invention includes a buffer layer 102 made of a compound epitaxial film, a first carrier supply layer 103, a first spacer layer 104, a channel, and laminated on a semi-insulating substrate 101. A layer 105, a second spacer layer 106, a second carrier supply layer 107, a Schottky junction formation layer composed of a barrier layer 108 and an etching stop layer 109, a contact layer 110, a predetermined on the Schottky junction formation layer It consists of a gate electrode 111, a source electrode 112, and a drain electrode 113 formed in the part,
Carrier supply layers 103 and 107 exist above and below the channel layer via spacer layers 104 and 106, respectively, and carrier supply layers 103 and 107 are planar doped layers (limited to a narrow range of dopant concentration distribution in the thickness direction). The dopant concentration of the planar doped layer is not less than the lower limit concentration for supplying carriers to the channel layer and not more than the upper limit concentration at which the dopant does not diffuse into the channel layer. The source electrode 112 and the drain electrode 113 are connected to the etching stopper layer 109 via different contact layers 110, respectively.

  In the embodiment of the invention according to claim 2, in FIG. 1, the semi-insulating substrate 101 is made of InP, and includes a buffer layer 102, a first spacer layer 104, a second spacer layer 106, and a barrier layer 108. Is InAlAs, and the channel layer 105 is InGaAs.

  In the embodiment of the invention according to claim 3, the dopant to the first carrier supply layer 103 and the second carrier supply layer 107 is Si.

In the embodiment of the invention according to claim 4, the sheet concentration of Si as a dopant to the first carrier supply layer 103 and the second carrier supply layer 107 is 1 × 10 ¹² cm ⁻² or more, 5 × 10 ¹² cm ⁻² or less.

  In the present invention, in the HFET structure, the carrier supply layer is two planar doped layers formed above and below the channel layer via the spacer layer, and the dopant concentration per layer is a lower limit at which carriers can be supplied to the channel layer. The concentration is equal to or higher than the concentration, and is equal to or lower than the upper limit concentration at which the dopant does not diffuse into the channel layer. As a result, electrons having a sufficient sheet concentration are generated in the channel layer, and at the same time, the influence of the thermal history during crystal growth can be reduced and a steep doping profile can be maintained. Furthermore, it is possible to suppress the deterioration of the electrical characteristics of the HFET when a long and high temperature thermal history is passed to form another device structure on the HFET layer.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 and FIG. 3 show the depth profile of the Si concentration before and after heat treatment at 630 ° C. and 590 ° C. for 2 hours in an arsine atmosphere on a sample obtained by planarly doping Si in InAlAs. FIG. 2 shows a doping profile in a Si-planar-doped sample with a sheet concentration of 1.1 × 10 ¹³ cm ⁻² , and FIG. 3 shows a Si-planar-doped sample with a sheet concentration of 3.3 × 10 ¹² cm ^−2. The doping profile is shown. This heat treatment condition is a typical temperature and time during which the planar doped layer in the HFET layer actually passes when another device layer is formed on the HFET layer by the MOVPE method or the like for the purpose of manufacturing a monolithic integrated device. Is the heat history condition.

  In the sample of FIG. 2, it can be seen that the distribution of Si atoms in the planar doped layer is remarkably expanded by the heat treatment. On the other hand, in the sample of FIG. 3, there is almost no change in the Si doping profile due to the heat treatment. Thus, it can be seen that the lower the doping concentration, the smaller the Si diffusion constant. The doping concentration dependence of the diffusion behavior of planarly doped Si atoms in InAlAs was first clarified experimentally by the present inventors, and the present invention was made based on this new knowledge. It is.

In the HFET structure formed on a commonly used InP substrate, the concentration of Si atoms planarly doped in the carrier supply layer corresponding to 205 in FIG. 6 is 1 to 2 × 10 ¹³ cm ^{−2 as described above.} It is. At this concentration, when a heat treatment temperature of 630 ° C. for 2 hours is applied, the diffusion constant of Si atoms is estimated to be about 1 × 10 ⁻¹⁷ cm ² / s from the analysis of the result of FIG. About 3 nm. This is about the same as the thickness of the spacer layer that is usually used. That is, in such an HFET structure, it is shown that Si atoms in the carrier supply layer diffuse to the channel layer side by the heat treatment under the same conditions, and the mobility can be lowered.

On the other hand, as shown in FIG. 3, if the Si concentration of the planar doped layer is around 3 × 10 ¹² cm ⁻² , there is almost no change in the doping profile, and this is applied to the HFET structure. However, it is considered that the electrical characteristics are not affected. As a result of systematically carrying out the same experiment, the present inventors have confirmed that the doping profile is hardly changed by the heat treatment if the Si sheet concentration is 5 × 10 ¹² cm ⁻² or less.

Next, the buffer layer 202 shown in FIG. 6 has a thickness of 200 nm, the channel layer 203 has a thickness of 15 nm, the spacer layer 204 has a thickness of 3 nm, a barrier layer 206 constituting the Schottky junction formation layer, and an etching stop layer. Samples having an HFET structure with a thickness of 207 of 6 nm and 5 nm were subjected to a heat treatment in an arsine atmosphere similar to the above experiment by changing the heat treatment temperature, and the change in electron mobility in the channel layer due to the heat treatment was observed. It was. The result is shown in FIG. It can be seen that if the Si sheet concentration is 5 × 10 ¹² cm ⁻² or less, the mobility does not decrease due to the heat treatment in the temperature range from 590 ° C. to 630 ° C. In this way, if the sheet doping concentration in the planar doped layer is limited, it is possible to suppress the deterioration of the electrical characteristics of the HFET structure due to the thermal history.

However, when the Si sheet concentration is 5 × 10 ¹² cm ⁻² or less in the layer structure of FIG. 6, the sheet doping concentration itself is low, so that the electron concentration of the channel layer is lowered accordingly. Accordingly, in order to generate a practical concentration of electrons in the channel layer, as shown in FIG. 1, the planarity of the Si sheet is 1 × 10 ¹² cm ⁻² or more and 5 × 10 ¹² cm ⁻² or less. Two carrier supply layers 103 and 107 made of a doped layer are formed. Thus, carriers having a concentration capable of device operation can be generated in the channel layer.

FIG. 5 shows the change in the mobility of electrons in the channel layer before and after the heat treatment in the arsine atmosphere similar to the above experiment. The buffer layer 102 shown in FIG. 1 has a thickness of 200 nm, the first spacer layer 104 has a thickness of 3 nm, the channel layer 105 has a thickness of 15 nm, the second spacer layer 106 has a thickness of 3 nm, and a Schottky junction. HFET having two carrier supply layers composed of a planar doped layer in which the thickness of the barrier layer 108 and the etching stopper layer 109 constituting the formation layer is 6 nm and 5 nm, and the sheet concentration of Si is 5 × 10 ¹² cm ⁻² In the case of the structure, the thickness of the buffer layer 202 shown in FIG. 6 is 200 nm, the thickness of the channel layer 203 is 15 nm, the thickness of the spacer layer 204 is 3 nm, the barrier layer 206 constituting the Schottky junction formation layer, and etching The single layer with stop layer 207 thickness of 6 nm and 5 mn and Si sheet concentration of 1 × 10 ¹³ cm ^−2. An example of the case of an HFET structure having a carrier supply layer composed of a Rena doped layer (same as that in FIG. 4) is shown in comparison. In the former case, no decrease in mobility is observed, but it can be seen that the latter mobility is significantly reduced by heat treatment. As described above, this is probably because the diffusion of Si dopant atoms is suppressed by the application of the carrier supply layer having a low doping concentration.

  In the layer configuration of FIG. 1, it is appropriate that the channel layer 105 has a thickness of 15 nm and the spacer layers 104 and 106 have a thickness of 3 nm in order to ensure good device characteristics. The present inventors have confirmed that the effect of the present invention can be obtained even when the thickness of 105 is 10 nm or more and 30 nm or less and the thickness of the spacer layers 104 and 106 is 1 nm or more and 5 nm or less.

  In order to improve the thermal stability of the HFET structure formed on the InP substrate, a method using InAlP or InP as the material of the carrier supply layer as described in Non-Patent Document 3 can also be mentioned. However, when a P-based material is inserted into the HFET structure, the crystal growth sequence becomes complicated, such as switching of the V group source gas supply during crystal growth. In addition, since the carrier supply layer also acts as an etching stop layer, the mesa formation procedure by etching becomes complicated in manufacturing the device. On the other hand, in the present invention, it is not necessary to switch the group V source gas for forming the carrier supply layer, and it is possible to form a layer structure with a simple crystal growth sequence. In addition, the etching process for device fabrication does not complicate the process.

  Further, in the conventional layer structure, it is necessary to reduce the influence of thermal history in order to produce a monolithic integrated device without degrading the device characteristics of the HFET. In other words, there are limitations such as shortening the growth time or lowering the growth temperature by thinning the element structure formed on the HFET or increasing the growth rate. The thinning of the element structure reduces the design freedom of the structure. Changing the growth rate or growth temperature may cause deterioration of crystal quality. In the present invention, it is possible to eliminate such adverse effects.

  As described above, according to the present invention, in an HFET formed on an InP substrate, diffusion of dopant atoms due to thermal history during crystal growth is achieved by using two carrier supply layers composed of a low-concentration planar doped layer. And the deterioration of the electrical characteristics of the HFET can be prevented. This makes it possible to freely manufacture a monolithic integrated element by stacking an HFET structure and another device structure.

  In the above embodiment, the semi-insulating substrate 101 is made of InP, the buffer layer 102, the first spacer layer 104, the second spacer layer 106 and the barrier layer 108 are made of InAlAs, and the channel layer 105 is made of InGaAs. However, the present invention is not limited to this.

1 is a cross-sectional view of a heterostructure field effect transistor according to the present invention. It is the figure which showed the doping profile of Si before and behind heat processing in the arsine atmosphere of the InAlAs sample which carried out the planar doping of Si with a sheet | seat density | concentration of 1.1 * 10 ^{< 13} > cm ^<-2 >. It is the figure which showed the doping profile of Si before and after heat processing in the arsine atmosphere of the InAlAs sample which carried out the planar doping of Si with a sheet | seat density | concentration of 3.3 * 10 ^{< 12} > cm ^<-2 >. It is the figure which showed the change by the heat treatment in an arsine atmosphere of the channel layer electron mobility in the HFET structure formed on the InP board | substrate which has the carrier supply layer which gave the planar dope with different density | concentration. It is the figure which showed the change by the heat processing in an arsine atmosphere of the channel layer electron mobility of the HFET structure which has one carrier supply layer which gave the planar dope, and the HFET structure which has two carrier supply layers. It is sectional drawing of the conventional common heterojunction field effect transistor.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 101 ... Semi-insulating substrate, 102 ... Buffer layer, 103 ... First carrier supply layer, 104 ... First spacer layer, 105 ... Channel layer, 106 ... Second spacer layer, 107 ... Second carrier supply layer , 108 ... barrier layer, 109 ... etching stop layer, 110 ... contact layer, 111 ... gate electrode, 112 ... source electrode, 113 ... drain electrode, 201 ... InP substrate, 202 ... buffer layer, 203 ... channel layer, 204 ... spacer Layer 205, planar doped layer, 206 barrier layer, 207 etching stop layer, 208 contact layer, 209 gate electrode, 210 source electrode, 211 drain electrode.

Claims (4)

  A heterojunction field effect transistor having a compound semiconductor epitaxial multilayer film formed on a semi-insulating substrate as a constituent element, wherein the compound semiconductor epitaxial multilayer film is sequentially formed on the semi-insulating substrate, a buffer layer, A first carrier supply layer, a first spacer layer, a channel layer, a second spacer layer, a second carrier supply layer, and a Schottky junction formation layer are stacked, and a gate electrode is formed on the Schottky junction formation layer The source electrode and the drain electrode are formed, the first and second carrier supply layers are planar doped layers, and the dopant sheet concentration in the planar doped layer is a lower limit capable of supplying carriers to the channel layer. The concentration is not less than the upper limit concentration that does not cause dopant diffusion to the channel layer. Junction field effect transistor.   2. The hetero field effect transistor according to claim 1, wherein the semi-insulating substrate is made of InP, and the buffer layer, the first spacer layer, the second spacer layer, and the Schottky junction forming layer are configured. A hetero field effect transistor, wherein a barrier layer which is an element and is in contact with the second carrier supply layer is made of InAlAs, and the channel layer is made of InGaAs.   3. The heterojunction field effect transistor according to claim 1, wherein a dopant atom to the carrier supply layer which is the planar doped layer is Si. 4. The hetero field effect transistor according to claim 3, wherein a sheet concentration of Si that is a dopant atom of the carrier supply layer that is the planar doped layer is 1 × 10 ¹² cm ⁻² or more and 5 × 10 ¹² cm ⁻² or less. A heterojunction field effect transistor, characterized in that:

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