JP2005243937A - Designing method of integrated circuit device, data processor implementing its method and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide configuration which responds effectively according to such time as failures occur and to a change in specification or the like, in an integrated circuit device using a FPGA or the like. <P>SOLUTION: The configuration comprises steps of implementing configuration applying one placement and routing information of a plurality of placement and routing information including different restricting conditions according to the occurrence of faults or desired designing conditions, verifying whether it normally operates for a logic circuit obtained from its results, implementing again the configuration applying other placement and routing information when the results are not normal, and repeating implementation of a verifying process for a processor having placement and routing obtained in the above process. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an integrated circuit device design method, a data processing device and a program capable of executing the method, and in particular, by performing configuration including placement and routing processing for realizing a desired logic circuit function after mounting. The present invention relates to a design method of an integrated circuit device capable of changing, adjusting, and the like of a circuit function, a data processing device and a program capable of executing the method.

  In the field of data processing devices such as communication devices and information processing devices that require high reliability, program logic as an integrated circuit device that can implement a self-diagnosis function and can change and adjust the specifications of logic circuits -Arrays, processor arrays, FPGAs, PLDs, etc. are known.

In the application of the integrated circuit device having such a configuration, when a circuit component that has been confirmed to function normally at the time of manufacture of the device is damaged or abnormal after that, or after shipment of the device. When a function change including version upgrade or a circuit change is performed, it is desired to cope with the problem by using a circuit portion that has not been used before. That is, it is desired to avoid malfunction by performing a layout that avoids a problem location when an abnormality occurs, or to perform a desired function change, circuit change, or the like. In addition, if there is any inherent damage or abnormality in the integrated circuit device itself at the time of manufacture of the device, self-diagnosis is performed for the purpose of avoiding malfunction caused by it, and the original function is restored by avoiding the corresponding failure. Therefore, it is desired to improve reliability.
JP 2000-147058 A JP-A-8-292933 JP 11-259328 A JP-A-9-62528 Japanese Patent Laid-Open No. 10-313061 JP-A-5-55374 JP-A-9-64314 JP-A-6-112316 JP-A-8-63493

  For example, Patent Document 1 has a plurality (odd number) of identical processing circuits, and among the outputs from the respective processing circuits, many results are determined to be normal, and one of the plurality of processing circuits having the outputs. A method is disclosed in which a user processing circuit can be realized without applying a processing circuit arranged in a defective part (area) by applying one as a normal circuit. In this configuration, since there are a plurality of processing circuits, only one circuit is actually used. Therefore, the circuit scale (circuit area) used by the user is less than “one / multiple”, and the basic integrated circuit device. There is a problem that the use efficiency of the system deteriorates.

  Further, Patent Document 2 discloses a configuration in which a plurality of circuits are laid out for each function, and a user function is realized by a connection relationship of the functions of each circuit. In this case, when a failure / abnormality is detected in the user function, a defective part (layout area) is specified, and the user function is realized by reconstructing the connection relationship based on the information. In this configuration, although a plurality of circuits are laid out by function, only one circuit is actually used. Therefore, the circuit scale (circuit area) actually used by the user is less than "one / multiple" There is a problem that the utilization efficiency of the integrated circuit device is deteriorated.

  In Patent Document 3, user functions are divided and arranged (mapped) for a plurality of FPGAs and FPIAs, and then normality is determined by a diagnostic program. These series of operations are performed by a plurality of FPGAs. , A method (apparatus) for detecting a failure of a defective portion by performing the combination on the FPIA is disclosed. In this configuration, although a plurality of FPGAs and FPIAs are used for each function, only one set of circuits is actually used. Therefore, the circuit scale used by the user on the PCB is less than “one-multiple”, and the basic integrated circuit There is a problem that the use efficiency of the system deteriorates.

  In Patent Literature 4, an internal memory having a plurality of layout pattern definition information of a user processing circuit in advance, a failure detection unit for determining the normality of a user processing circuit after layout, and a definition processing unit for determining re-layout when a failure is detected are disclosed. A self-healing device is disclosed. In this case, the failure detection unit determines whether there is a failure / abnormality in the user processing circuit after layout, and if it is determined as a failure / abnormality, a layout pattern other than the layout region having the failure / abnormality in the definition processing unit. The definition information is read from the internal memory and re-layout is performed so that the user processing circuit is not laid out in the defective part (area). In this configuration, when a defective part is specified, it can be considered that it takes a considerable processing time to discriminate all the series of basic processing circuits. Further, since the detection result of the defective part is stored in the internal memory, there is a problem that the internal memory area that can be used by the user is compressed.

  In Patent Document 5, information on a defective part at the time of occurrence of an initial failure (manufacturing failure) in an integrated circuit device manufacturing stage (device test stage or the like) is stored in an internal nonvolatile storage means, and the user uses the integrated circuit device. A method for relieving an integrated circuit device having an initial failure by reading the information and constructing and applying a circuit while avoiding a defective portion is disclosed. In this configuration, the following problems can be considered. In other words, the damage and abnormalities after the integrated circuit device manufacturing cannot be dealt with, and the defective part is unique to each integrated circuit device, and the user's placement and wiring information differs for each integrated circuit device, and the location reflecting the defective part information Since it is necessary to prepare the number of products that use the wiring information, the amount of required information increases, and the time for preparing the information also increases accordingly.

  In Patent Document 6, information such as a malfunctioning part due to secular change or the like discovered by measurement at the site of operation of the apparatus is accumulated and read out and written to a storage block inside the integrated circuit apparatus, and then the integrated circuit apparatus A method for increasing the useful life of an integrated circuit device by reading out the information when the diversion is used and applying a layout that avoids a defective portion is disclosed. In this configuration, a malfunctioning part due to secular change or the like discovered by measurement at the operation site is specified, and at the time of diversion, the information is used to re-layout, but the defective part in that case is unique to the integrated circuit device. For this reason, it is necessary to prepare the number of products to be used for the placement and wiring information reflecting the different defect location information for each integrated circuit device. Therefore, the amount of required information becomes large, and the time for preparing it takes much longer.

  The conventional techniques disclosed in Patent Documents 1 to 6 can be broadly divided into the following two problems. As a first problem, when a redundant configuration in which a plurality of identical processing circuits are prepared in an integrated circuit device is adopted, the circuit scale of a user actually used becomes “one / multiple” of the whole and is used. Inefficiency. For example, assuming the circuit configuration shown in FIG. 1, the use state of the integrated circuit device in the layout is as shown in FIG. That is, when the user circuit (0) does not include a defective portion, the circuit is used, and other circuits, that is, the redundant configuration user circuit (1) to user circuit (n) are not used. For this reason, utilization efficiency worsens. In addition, since a plurality of identical processing circuits are provided in the integrated circuit device to provide a redundant configuration, the AC characteristics inside the integrated circuit device are deteriorated. That is, in the case of the layout of FIG. 2, if “Δ” indicates the arrival time of each signal, the following relationship holds.

ΔT0 ≦ ΔT1 ≦ ΔTn
ΔT0 ′ ≦ ΔT1 ′ ≦ ΔTn ′
Here, since the maximum operating speed of the integrated circuit device is determined by 1 / ΔTn or 1 / ΔTn ′, the AC characteristics inside the integrated circuit device are deteriorated by the redundant configuration.

  The techniques disclosed in Patent Documents 1 to 3 are considered to have the first problem.

  A possible second problem is that “failure point information” (see FIG. 3) for identifying a defective part generated at an integrated circuit device manufacturing stage or an integrated circuit device operation site is provided, and the corresponding defective part ( When the layout setting circuit is configured to perform the layout again so as to avoid (see FIG. 4), since the defective portion information differs for each integrated circuit device, the integrated circuit device to be used when the number of shipments becomes large Different placement and routing information for each number is required, and the amount of information is considered to be a considerable amount. In addition, since the user needs to perform layout work in proportion to the number in the layout setting circuit, there is a high possibility that it will be a problem particularly in mass production. A circuit configuration example in that case is shown in FIG. Further, FIG. 4 shows a use state of the integrated circuit device in that case on the layout.

  It is the disclosure techniques of Patent Documents 4 to 6 that are considered to have this second problem.

In order to solve the above-described problems, the present invention obtains a plurality of placement and routing information having predetermined layout constraint conditions each having different contents, and the plurality of placement and routing information in response to occurrence of a failure or a desired design change request. A placement and routing stage for performing placement and routing on a predetermined basic integrated circuit device according to one of the placement and routing information;
A test stage for performing a predetermined function test on the basic integrated circuit device on which the placement and routing has been performed, and if the result of the test is not normal, placement is performed according to other placement and routing information among the plurality of placement and routing information The basic integrated circuit device in which the placement and wiring in which the result of the test stage becomes normal is made by repeating the execution of the test stage again for the basic integrated circuit device in which the placement and wiring is made, by performing wiring And a stage comprising the steps of:

  Further, in the plurality of placement and routing information having predetermined layout constraint conditions having different contents, the predetermined layout constraint conditions having different contents are based on conditions for prohibiting the use of predetermined circuit areas in the basic integrated circuit device. It is desirable that

  Further, it is desirable that the predetermined circuit area to be prohibited from use be set so that it does not overlap each other among the plurality of placement and routing information, or only a part thereof overlaps.

  Here, the placement and routing step is carried out for the purpose of avoiding the failure by obtaining an integrated circuit device having a layout and wiring that avoids the failure location when a failure occurs in the integrated circuit device product, for example.

  As described above, the present invention adopts a configuration in which wiring placement is performed by applying one placement wiring information among a plurality of placement wiring information having different layout constraint conditions, and is common in the same basic integrated circuit device (FPGA or the like). Design using different layouts in sequence while utilizing regions (regions other than placement prohibited regions). Therefore, the redundant configuration of n times is not necessary as compared with the configuration employing the circuit redundant configuration as disclosed in Patent Documents 1 to 3. As a result, it is possible to prevent the deterioration of the utilization efficiency on the layout as shown in FIG. 2 and the deterioration of the AC characteristics due to the increase of the path length such as ΔTn and ΔTn ′, and the above first problem can be solved effectively. .

  Furthermore, the configuration is such that the placement and routing is performed by applying one of the placement and routing information among the plurality of placement and routing information having different layout constraint conditions. Basic integration in which placement and routing is finally performed without repeating malfunction by repeating placement and routing by applying other placement and routing information, and performing tests on the basic integrated circuit on which placement and routing has been performed. By adopting a configuration for obtaining a circuit device, collection of defective portion information for specifying different defective portions for each device as disclosed in Patent Documents 4 to 6, and different layout work for each device based on the information. Implementation becomes unnecessary.

  That is, according to the present invention, for a device having the same model number, for example, a plurality of pieces of placement and routing information having uniform contents are provided between products regardless of the number of shipments, and a re-layout operation with a uniform configuration is performed between products according to the information. Therefore, it is possible to easily obtain a layout for avoiding a defective portion or changing / adding a function, so that it is not necessary to provide an n-fold redundant configuration as in the disclosed technologies of Patent Documents 1 to 3, and As in the technologies disclosed in Patent Documents 4 to 6, there is no need to perform a specific layout work for each product in order to identify and avoid defective parts individually for each product, and an efficient integrated circuit device design can be realized. .

  According to the embodiment of the present invention, the layout wiring information (that is, the wiring prohibition areas of a plurality of different basic circuits on the basic integrated circuit device (ie, the location information) can be avoided without specifying the fault location of the integrated circuit device. “Layout information”, and information on which position a desired logic element is arranged and a route between the logic elements is prepared for a basic integrated circuit device such as an FPGA. A self-diagnosis is performed on an integrated circuit device that has been placed and routed using one place and route information. If the operation is defective, place and route information having different placement prohibited areas is set and placement and route is performed again. The self-diagnosis is performed again on the integrated circuit device thus obtained, and an integrated circuit device having a layout and wiring that finally recovers a desired function is obtained by repeating the self-diagnosis.

  FIG. 5 shows a circuit configuration according to the embodiment of the present invention, FIG. 6 shows a usage situation on the layout in the basic integrated circuit device at that time, and FIG. 7 shows an operation flow thereof. Here, the placement and routing information having a plurality of different placement prohibited areas 15 is prepared outside the integrated circuit device. When a defect occurs or the like (step S1), the placement and routing information having different placement prohibited areas 15 is sequentially selected from the plurality of placement and routing information until the defective portion can be avoided (step S2). Therefore, the placement and routing is performed on the basic integrated circuit device, the verification processing (step S3) is performed on the integrated circuit device on which the placement and routing has been performed, and the series of processing is repeated (the loop of steps S2, S3, and S4). As described above, since there is no provision of a plurality of identical circuits (redundant configuration) inside the integrated circuit device as in Patent Documents 1 to 3, the basic integrated circuit device can be used efficiently, and the use efficiency of the user circuit is improved. Reduction can be minimized.

  For example, when the disclosed technique disclosed in Patent Document 1 is taken as an example, consider the user usage rate in the integrated circuit device. When the number of the same user circuits provided in the integrated circuit device in advance to avoid a defective part is set to 4 (redundant configuration), only one of the circuits is actually installed at the installation site (in operation) of the device. Since it is actually applied as a user circuit, the actual usage rate of the user circuit in the integrated circuit device is 1/4 = 25%. In consideration of maximizing this usage rate, at least two identical user circuits are required. In this case, the circuit usage rate is 1/2 = 50% (upper limit).

  On the other hand, when the same examination is performed on the system according to the embodiment of the present invention, when the number of pieces of placement / wiring information having different placement prohibited areas 15 is four, which placement prohibited areas 15 are different? Even in the placement and routing information, ¼ = 25%. By combining the placement prohibited areas 15 in the four pieces of placement information, the entire area of the basic circuit configuration of the device can be covered. In this case, the usage rate of the actual user circuit in the integrated circuit device is 100% −25% = 75% regardless of which placement and routing information is applied. In consideration of the upper limit when the usage rate is maximized, the number of pieces of placement and routing information having different placement prohibited areas 15 can be increased as much as possible to logically place in the integrated circuit device. It is possible to approximate the user usage rate to 100%.

  From the above, it can be said that the user usage rate in the integrated circuit device according to the embodiment of the present invention is clearly an effective method as compared with the prior art.

  Further, since the setting of the placement prohibition area 15 arbitrarily designates a part of the basic circuit group in the integrated circuit device, the influence on the internal AC characteristics, that is, the occurrence of an increase in delay time, etc. is minimized. Does not hinder the work of creating the placement and routing information. In other words, according to the embodiment of the present invention, a place where the signal arrival time (having a proportional relationship with the distance) such as ΔTn and ΔTn ′ shown in FIG. No.

  In addition, according to the embodiment of the present invention, when a defective part occurs at the integrated circuit device manufacturing stage or operation site, the placement and routing information having a plurality of arbitrary non-overlapping (or partially overlapping) placement prohibited areas 15 Are prepared so that the entire arrangement and wiring possible area of the corresponding basic integrated circuit device is covered by the combination of the arrangement prohibition areas 15 included in each of the arrangement and wiring information (see FIGS. 9 and 10). As a result, the placement prohibition area 15 of any placement and routing information includes a defective part of the basic circuit. Therefore, such a defective part is excluded as the placement prohibition area 15 and is not included in the effective placement and routing range. By selecting the wiring information, the defective part can be avoided. Therefore, it is not necessary to create different layout and wiring information for each product of the integrated circuit device based on the “defect location information” in Patent Documents 4 to 6, and even when the number of shipments is large, the integration including the defect portion is performed. It is not necessary to provide different arrangement and wiring information for the number of circuit devices shipped.

  As described above, according to the embodiment of the present invention, since it is possible to avoid a specific defective portion for each integrated circuit device product even by using several pieces of placement and routing information that satisfy a predetermined condition common to each product, It is possible to prepare the placement and routing information before shipping the product. Accordingly, it is possible to easily estimate the time required to generate the plurality of pieces of placement and routing information before the device is shipped and put into operation. On the other hand, in the above prior art, since the location and wiring information is prepared on the user side after specifying the location of the defective part, when the number of products shipped becomes large, all devices can be operated normally. The time required for this will be the same as the number of integrated circuit device products including defective parts.

  In order to make this point clearer, as an example, a comparison with the technology disclosed in Patent Document 4 is performed.

The time required for putting the apparatus into the operating state according to the prior art of Patent Document 4 can be obtained by the following equation, for example.
(Time required to divide the same user circuit into a plurality of pieces and create a plurality of pieces of placement and routing information with different placement prohibited areas) = T1a (h)
+ (Time required for performing a plurality of layouts for each FPGA corresponding to each divided user circuit and performing a specific test for a defective portion by using the plurality of created placement and routing information = T1b (d)
+ (Time for mapping for each FPGA using the placement and routing information avoiding the defective part obtained by the test) = T1c (s)
On the other hand, the time required for putting the apparatus into the operating state by the method according to the embodiment of the present invention can be obtained by the following equation, for example.
(Time required to create a plurality of pieces of placement and routing information with different placement prohibited areas) = T2a (h)
+
(Time until the mapping is performed with the placement and routing information that does not include the defective portion by sequentially testing using the plurality of placement and routing information) = T2b (s)
To compare the time required for each process of the prior art and the embodiment of the present invention by the above formula, assuming that the same time is required for both the placement and routing information creation, T1a (h) ≈T2a ( h). In this case, control information such as placement prohibited area designation and input / output PIN placement designation is manually created by the user. Depending on the number of pieces of placement and routing information to be created, the required time can be estimated as several hours for both T1a (h) and T2a (h).

  Further, since the process of T1c (s) can be performed automatically without user effort, the required time is estimated to be about several seconds, and T2b (s) is a total even if this process is repeated a plurality of times. It is considered to be several seconds to several minutes, and the total required time is considered as T1c (s) ≈T2b (s).

  Therefore, in the embodiment of the present invention, compared to the prior art, a plurality of layouts are performed for each FPGA by using a plurality of placement and routing information created in the prior art, and a defective portion specific test is performed for each of them. Can be reduced by the time T1b (d) required to perform. This reducible time T1b (d) is to determine an individual defective portion for each FPGA, to associate (type) different placement and routing information for each FPGA, and further to the placement and routing information between the FPGA integrated circuit device and the placement and routing information. When considering the necessity of managing pairs, the time required can be estimated to be several days.

  Further, according to the embodiment of the present invention, a plurality of FPGA products having different defective parts can be configured in the same process (a plurality of placement and routing information having the same contents), whereas in the prior art, Since different placement and routing information is individually selected and configured for different defective parts for each FPGA product, there is a possibility that placement and routing information may be mistaken due to factors such as human error in the process. As a result, there is a possibility of mapping with incorrect placement and routing information. If extra time required in that case is T3 (h), for example, it is estimated to be several hours, the embodiment of the present invention requires T1b (d) + T3 (h) as compared with the prior art. Can be reduced.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 8 is a block diagram of a data processing apparatus according to an embodiment of the present invention. The data processing apparatus 100 in FIG. 1 includes a CPU 110 that controls the entire apparatus, an FPGA (Field Programmable Gate Array) 120 that constitutes an integrated circuit device having a predetermined function, a nonvolatile memory 180, and a CPU bus 140 that connects them. .

  The nonvolatile memory 180 includes an area 180a for storing an operation system (OS) for controlling various processing operations executed by the data processing apparatus 100, an area 180b for storing application programs related to the various processing operations, and a function test of the FPGA 120. The memory FLASH1 having the areas 180c and 180d for storing the test pattern for executing the test and the expected value to be compared with the test result of the functional test, and n pieces of FPGA configuration data including the plurality of placement and routing information And a memory FLASH2 having a storage area 180e.

  The data processing apparatus 100 is connected to the communication network 200 via a LAN interface.

  FIG. 9 shows an example of the placement and routing information having the “placement prohibited area 15” in a plurality of different FPGA 120 placement and routing possible areas. As shown in the figure, the placement prohibited area 15 is placed at different positions between the placement and routing information, and by combining the placement prohibited areas 15, as a result, as shown in FIG. The circuit device (FPGA 120) is arranged so as to be laid all over the area where wiring and wiring are possible.

  Further, as shown in FIG. 11, the self-diagnosis circuit 12 may be included in the integrated circuit device (FPGA 120). As shown in the figure, in this case, the self-diagnosis circuit 12 is arranged without changing the arrangement position between the arrangement and wiring information so that the self-diagnosis circuit 12 does not include a defective portion.

  The operation according to the embodiment of the present invention will be described below. First, when the self-diagnosis circuit 12 is provided in the FPGA 120 as shown in FIG. 11, the memory FLASH1 of the nonvolatile memory 180 has an area for storing an FPGA test test pattern and an expected value to be compared with the test result as described above. The memory FLASH2 of the nonvolatile memory 180 has an area for storing FPGA configuration data. Usually, the memories FLASH1 and 2 have areas 180a and 180b in which software information such as OS and applications are stored, and the data processing apparatus 100 is activated when the CPU 110 reads out the data.

  The self-diagnosis circuit 12 in the FPGA 120 reads configuration data (for example, any placement and routing information in FIG. 11) from the memory FLASH2, and configures the FPGA 120 according to the configuration data. As a result, in the FPGA 120, a predetermined logic circuit is configured in an area avoiding the arrangement prohibition area 15 and the self-diagnostic circuit 12 set in the configuration data (step S2 in FIG. 7). Thereafter, the self-diagnosis circuit 12 in the FPGA 120 reads a test pattern from the memory FLASH 1 via the CPU bus 140 and executes a function test of the logic circuit configured in the FPGA 120. Then, the normality of the logic circuit in the FPGA 120 is determined by comparing the test result output as a result with the expected value stored in the FLASH 1 (step S3).

  If the result of the determination is “logic circuit function failure” (NG in step S3), the next configuration data (placement and routing information) is read from the memory FLASH2, and the configuration data is stored in the FPGA 120 in the same manner as described above. The configuration is performed while avoiding the placement prohibited area 15 set to (step S2). Then, the same determination is made (step S3), and if it is NG, the next configuration data is read and the configuration is performed (step S2). Thereafter, the loop processing of steps S2 to S4 is repeated until the result of the determination by the self-diagnosis circuit 12 becomes “the function of the logic circuit is normal”.

  Thus, the configuration data composed of the placement and routing information as shown in FIG. 11 stored in the area 180e of the memory FLASH2 is sequentially read out, and the FPGA 120 is configured according to the contents thereof, so that it finally meets the requirements. Configuration data including placement and routing information having a defective portion as the “placement prohibited area 15” is applied. In this case, the self-diagnosis result is “normal” (OK in step S3). As a result, the placement and routing based on the configuration of the FPGA 120 at that time is adopted, and the actual operation is performed by applying the FPGA 120 in the state where the placement and routing is performed (step S5).

  Next, a case where the version of the FPGA 120 is upgraded will be described. In this case, configuration data, test patterns, and expected values similar to those described above are downloaded from a predetermined server via the LAN interface via the network 200 in the system of the data processing apparatus 100, and the above-described case is used using these information. Similarly, the FPGA 120 is configured to configure a logic circuit, the test data is applied to the logic circuit, the test is performed, and the placement and wiring by the configuration when the test result is “functional” is adopted. And put it into operation.

  Next, a case where determination is performed by the CPU 110 will be described. In this case, the determination is made by the external CPU 110 instead of the determination by the self-diagnosis circuit 12 in the FPGA 120. The tester pattern, expected value, and configuration data are stored in the non-volatile memory 180 and obtained when a function test is performed using the test pattern after the FPGA 120 is configured, as in the case where the automatic diagnosis circuit is provided in the FPGA 120 described above. The test results are stored in a predetermined memory (whether nonvolatile or volatile) in the system. The CPU 110 makes a determination by comparing the test result with the expected value stored in the memory FLASH2. If the result is NG as described above, the FPGA 120 uses the next configuration data until the result becomes OK. The operation of configuring is repeated.

  Next, a case where configuration data, a test pattern, and an expected value are downloaded via the LAN interface and the determination is performed by the CPU 110 will be described. In this case, configuration data, test patterns, and expected values are downloaded from a predetermined server via the network 200 via the LAN interface. The configuration and testing method is the same as the above case, that is, the configuration and test of the FPGA 120 using the configuration data, the test pattern, and the expected value in the nonvolatile memory 180 and the CPU 110 performs the determination. . If the determination result is NG, the next configuration data is requested to the server via the network 200 and newly downloaded in the same manner. With this configuration, it is possible to execute a function test using an infinite number of test patterns, and to perform a function test with higher accuracy. In this case, since it is not necessary to store configuration data or the like in the nonvolatile memory, a sufficient area for the OS or application can be secured in the storage area of the nonvolatile memory 180 and can be used effectively.

  Next, a configuration using the placement and routing information shown in FIG. 11 will be described in detail. In this case, a part of an arbitrary basic circuit group inside the FPGA 120 is set as the placement prohibition area 15 and the self-diagnosis circuit 12 is provided. About this self-diagnosis circuit 12, a circuit configuration is constructed in the same region even at the time of reconfiguration. Further, a test pattern for failure diagnosis and an expected value are set in the nonvolatile memory inside the FPGA 120 by default at the time of configuration. The self-diagnosis circuit 12 reads the test pattern from the non-volatile memory, performs a function test according to the read test pattern, and notifies the result of comparison between the result and the expected value to the outside. If an error is detected as a result, configuration is performed again with another ROM data (configuration data, that is, “place and route information” or “layout information”) according to the procedure described above with reference to FIG. I do.

  Note that the self-diagnosis process is performed at the time of configuration when the data processing apparatus 100 is turned on, or at the time of non-operation. In any circuit setting, if the expected value does not match, An alarm is generated from the data processing apparatus 100. The internal memory (non-volatile memory 180) stores a test pattern for self-diagnosis and an expected value when the power is turned on, but overwrites the contents after the data processing apparatus 100 shifts to the normal operation mode. It may be used as a normal memory as possible.

  Next, the case where the placement and routing information shown in FIG. 9 is used will be described in detail. In this case, a part of an arbitrary basic circuit group is set as a prohibited area in the FPGA 120, and a desired logic circuit is constructed in an area excluding this area. In this case, a test pattern for failure diagnosis and an expected value are prepared in the non-volatile memory 180 outside the FPGA 120. Then, when an external CPU 110 performs failure diagnosis and an error is detected, configuration is performed with other ROM data (placement and wiring information) according to the procedure described above with reference to FIG. 8, and similar self-diagnosis is performed.

  Also in this case, the self-diagnosis is performed at the time of configuration at the time of power-on or during non-operation, and an alarm is generated from the data processing device 100 when the expected value is not matched in any circuit setting.

  The operation of the embodiment of the present invention will be described more specifically.

  For example, configuration is performed with the layout configuration of the placement and routing information shown in FIG. 11A, a logic circuit is constructed in the FPGA 120, the CPU 120 reads a test pattern from the memory FLASH1 (FIG. 8), and the function of the FPGA 120 according to this Perform the test. The output test result is compared with the expected value of the memory FLASH1 (FIG. 8) to verify whether there is an error. If an error is detected as a result, data having a layout configuration as shown in FIG. 11B is selected from the memory FLASH 2 again, and the FPGA 120 is reconfigured. Then, a function test is performed in the same manner, and when an error is detected again, data having the layout configuration of FIG. 11C is selected from the memory FLASH2, thereby performing reconfiguration, and the FPGA 120 is subjected to reconfiguration. A similar test is performed. Similarly, until no error is detected, data having the layout configuration shown in FIGS. 11D, 11E, and 11F is sequentially applied to repeat the reconfiguration and the function test.

  As described above, according to the embodiment of the present invention, when an error is detected in the function test, a plurality of layout configurations in which the placement prohibited area 15 does not overlap or partially overlaps with the layout configuration of other placement and routing information. Therefore, a configuration that satisfies a desired function can be easily achieved without specifying a defective portion of the FPGA 120 because the functional test is repeated by applying data having a different layout configuration.

  In the case of FIG. 9, the self-diagnosis circuit 12 is not provided in the FPGA 120, and the arrangement prohibition area 15 is provided at an arbitrary position. As in the case of FIG. 11, the CPU 120 reads a test pattern from the memory FLASH1 (FIG. 8) and performs a function test after the configuration by applying the layout configuration of FIG. 9A. The CPU 120 compares the test result output as a result with the expected value of the memory FLASH1 (FIG. 8), verifies the presence or absence of an error, and if an error is detected, the memory FLASH2 again checks the error in FIG. 9B. The data to be the layout configuration is selected, and the FPGA 120 is reconfigured. Then, a function test is performed in the same manner. When an error is detected again, data having the layout configuration shown in FIG. 9C is selected again from the memory FLASH2, and the same test is performed. Similarly, until no error is detected, data having the layout configuration shown in FIGS. 9D, 9E, and 9F is sequentially applied, and the reconfiguration and the function test are repeated.

  As described above, according to the embodiment of the present invention, even when the placement and routing information of FIG. 9 is applied, similarly, when an error is detected in the function test, the placement prohibited area 15 has a different layout configuration. By repeating the function test by applying data that is different from a plurality of layout configurations that do not overlap or partially overlap, and perform the function test, the desired function can be obtained without specifying the defective part of the FPGA 120. A satisfactory configuration can be easily achieved.

  Next, a method for setting the “placement prohibited area 15” as shown in FIGS.

  For example, the techniques disclosed in Patent Documents 7 to 9 can be applied as a method for setting such an “arrangement prohibited area 15”.

  FIG. 12 shows an operation flowchart of an example of the placement prohibited area 15 setting process. The arrangement area setting process can be performed using a well-known FPGA automatic wiring tool. First, in step S21, a net list of logic circuits having a predetermined function is created and input to the automatic wiring tool by a well-known method, and pattern number n is initialized in step S22. In step S 23, “placement prohibited area 15” is set at an arbitrary position in the placeable and routable area of FPGA 120. In step S24, the automatic wiring tool performs a fitting process on the FPGA 120 in accordance with the net list created in step S21 and the position information of the placement prohibited area 15 set in step S23. Thereby, configuration data (that is, “placement / wiring information” or “layout information”) for realizing the logic circuit represented by the netlist to which the corresponding placement prohibited area 15 (pattern n) is applied is completed. The series of processes (steps S23 to S26) are repeatedly executed until a predetermined number n of wiring prohibited area patterns (for example, each pattern of the wiring prohibited areas shown in FIG. 9 or FIG. 11) are completed. As a result, a plurality of pieces of placement / wiring information (configuration data) each having the n prohibited placement areas 15 for n patterns is generated.

  Hereinafter, a specific example of setting the placement prohibited area 15 in the case of an Altera FPGA will be described. In this case, “Create New Logic-Lock Region” is set, and an arrangement area is set. By not assigning a module to this area, an area that cannot be placed is generated, and “placement prohibited area 15” is set. An example of a control card (* .esf) in Quartus II Version 3.0 in that case is shown below.

  In this example, an area (2 × 2) in an arbitrary range is designated for the Logic-Lock Region at arbitrary coordinates of the LAB (X axis = 2, Y axis = 29).

"LOGICLOCK_REGION (Region_0)
{
LL_ORIGIN = LAB_X2_Y29;
LL_HEIGHT = 2;
LL_WIDTH = 2;
LL_STATE = LOCKED;
LL_AUTO_SIZE = OFF;
LL_RESERVED = OFF;
LL_MEMBER_STATE = LOCKED;
LL_SOFT = OFF;
}
Next, the case of a Xilinx FPGA will be described in the same manner. In this case, “Area Group” is set in the Constraint Editor, and unnecessary circuits that are not used are arranged. The useless circuit outputs a signal to any output pin so that it will not disappear when optimized, but the user does not use the useless circuit and useless output pin, so it is necessary for the specified placement area. The circuit is no longer arranged, and as a result, an area that can be viewed as the “placement prohibited area 15” is set. An example of the control card (* .ucf) of ISE Version 6.1.03i in that case is shown below.

  In this example, an area group is specified for any SLICE coordinate (upper left coordinate: X axis = 21, Y axis = 173, lower right coordinate: X axis = 78, Y axis = 114). Show.

“INST“ useless module name not used ”AREA_GROUP =“ Area Group name ”;
AREA_GROUP “Area Group name” RANGE = SLICE_X21Y173: SLICE_X78Y114;

It is a block diagram of the integrated circuit device which has an example of the conventional self-diagnosis function. It is a figure which shows the two-dimensional basic integrated circuit utilization condition in the structure of FIG. It is a block diagram of an integrated circuit device having a layout setting circuit of another conventional example. It is a figure which shows the two-dimensional basic integrated circuit utilization condition in the structure of FIG. 1 is a block diagram of an integrated circuit device according to an embodiment of the present invention. It is a figure which shows the two-dimensional basic integrated circuit utilization condition in the structure of FIG. It is an operation | movement flowchart which shows the process sequence in the structure of FIG. 1 is a block diagram of a data processing apparatus according to an embodiment of the present invention. It is a figure which shows an example of the configuration data as the arrangement | positioning wiring information stored in the non-volatile memory shown in FIG. It is a figure which shows the position which each of the arrangement | positioning prohibition area | region 15 in the configuration data shown in FIG. 9 occupies in the arrangement | positioning wiring possible area | region of FPGA as a basic integrated circuit device. It is a figure which shows the other example of the configuration data as the arrangement | positioning wiring information stored in the non-volatile memory shown in FIG. 12 is an operation flowchart of processing for creating configuration data having an arrangement prohibition area as shown in FIGS.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Integrated circuit apparatus 11 User circuit 12 Self-diagnosis circuit 15 Arrangement prohibition area 100 Data processing apparatus 110 CPU
120 FPGA
140 CPU bus 180 Nonvolatile memory 200 Network

Claims (5)

Obtaining a plurality of placement and routing information including predetermined constraints with different contents,
A placement and routing stage for performing placement and routing on a predetermined basic integrated circuit in accordance with one placement and routing information of the plurality of placement and routing information in response to a failure occurrence or a design change request;
A test stage for performing a predetermined function test on the basic integrated circuit device on which the placement and routing is performed;
When the result of the functional test is not normal, the placement and routing is performed again on the predetermined basic integrated circuit device in accordance with other placement and routing information among the plurality of placement and routing information, and the base on which the placement and routing is made A method of designing an integrated circuit device comprising the step of obtaining a basic integrated circuit device having a placement and routing in which the result of the test step is normal by repeating the execution of the test step on the integrated circuit device again.   2. The plurality of pieces of placement and routing information including predetermined constraint conditions having different contents, wherein the predetermined constraint conditions having different contents are conditions for prohibiting the use of predetermined circuit areas in the basic integrated circuit device. The method described in 1.   3. The method according to claim 2, wherein the predetermined circuit area to be prohibited is set so as not to overlap each other among the plurality of placement and routing information, or to partially overlap.   A data processing apparatus including a configuration for performing the method according to any one of claims 1 to 4, wherein the position wiring stage and the test stage are performed at a predetermined timing. A program comprising instructions for causing a computer to execute the method according to any one of claims 1 to 4.

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