JP2005223627A - Operational amplifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an operational amplifier circuit capable of realizing a voltage buffer which can prevent the occurrence of overshoot or undershoot in an output waveform at the rise of the operational amplifier circuit and at the time of a step input even when the output impedance of a module for generating an input signal to the operational amplifier circuit is high. <P>SOLUTION: A signal input part is of a folded cascade type, a pair of transistors M3, M4 of which the gates and drains are mutually connected are connected between the drains of a differential pair of transistors M1, M2 and a power supply, and when the differential pair of transistors M1, M2 are balanced, operation points are determined so that the pair of transistors M3, M4 of which the gates and drains are mutually connected are put in OFF states. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an operational amplifier circuit, for example, suitable for application to an operational amplifier circuit used as a voltage buffer for the purpose of impedance conversion that requires smooth response characteristics at startup and response characteristics at step input. It is a thing.

When an operational amplifier circuit is used as a voltage buffer, there is a method of forming a voltage follower using the operational amplifier circuit.
FIG. 5 is a circuit diagram showing a configuration of a voltage follower using a conventional operational amplifier circuit.
In FIG. 5, the output terminal of the operational amplifier OP is connected to the inverting input terminal of the operational amplifier OP. The impedance conversion can be performed by inputting the input voltage V _IN to the normal input terminal of the operational amplifier OP and taking out the output voltage V _OUT from the output terminal of the operational amplifier OP.
Here, when configuring a voltage follower using an operational amplifier circuit, a wide input range is often required for the operational amplifier circuit. As an operational amplifier circuit having a wide input range, for example, a folded cascode operational amplifier circuit is well known as disclosed in Non-Patent Document 1.

FIG. 6 is a circuit diagram showing a configuration of a conventional folded cascode operational amplifier circuit.
In FIG. 6, the folded cascode type operational amplifier circuit is provided with a differential pair transistor 21, a cascode type load transistor 22 and a current biasing transistor 23.
Here, the differential pair transistor 21 is provided with N-channel MOS transistors M51 and M52. The sources of the N-channel MOS transistors M51 and M52 are connected to the drain of the N-channel MOS transistor M53 which is a current biasing transistor. The source of the N channel MOS transistor M53 is connected to the ground potential.

  The cascode-type load transistor 22 is provided with N-channel MOS transistors M60 to M63. The N-channel MOS transistors M60 and M62 are connected in series with each other, and the source of the N-channel MOS transistor M62 is connected to the ground potential. ing. The N channel MOS transistors M61 and M63 are connected in series, the source of the N channel MOS transistor M63 is connected to the ground potential, and the gates of the N channel MOS transistors M60 and M61 are connected to each other. The gates of the N channel MOS transistors M62 and M63 are connected to each other, and the gates of the N channel MOS transistors M62 and M63 are connected to the drain of the N channel MOS transistor M60.

  The current bias transistor 23 is provided with P channel MOS transistors M55 to M58. The P channel MOS transistors M55 and M57 are connected in series with each other, and the source of the P channel MOS transistor M55 is connected to the power supply potential. ing. The drain of the P channel MOS transistor M55 is connected to the drain of the N channel MOS transistor M51, and the drain of the P channel MOS transistor M57 is connected to the drain of the N channel MOS transistor M60.

P channel MOS transistors M56 and M58 are connected in series with each other, and the source of P channel MOS transistor M56 is connected to the power supply potential. The drain of the P channel MOS transistor M56 is connected to the drain of the N channel MOS transistor M52, and the drain of the P channel MOS transistor M58 is connected to the drain of the N channel MOS transistor M61.
The gates of the P channel MOS transistors M55 and M56 are connected to each other, and the gates of the P channel MOS transistors M57 and M58 are connected to each other.

  Then, by inputting bias 21 to the N channel MOS transistor M53, it becomes possible to control the operating points of the N channel MOS transistors M51 and M52. Further, by inputting bias 22 to the N channel MOS transistors M60 and M61, the operating point of the N channel MOS transistors M62 and M63 can be controlled. Further, by inputting bias 24 to the N-channel MOS transistors M55 and M56, the overdrive voltage of the P-channel MOS transistors M55 and M56 can be controlled. Further, by inputting bias 23 to N channel MOS transistors M57 and M58, it becomes possible to control the operating points of internal node B3 and internal node C3.

FIG. 7 is a circuit diagram showing a configuration when the folded cascode operational amplifier circuit of FIG. 6 is used as a voltage follower.
In FIG. 7, in order to use the folded cascode operational amplifier circuit of FIG. 6 as a voltage follower, the gate of the N-channel MOS transistor M52 is connected to the drain of the N-channel MOS transistor M61. The gate of the N channel MOS transistor M51 is provided with the normal input terminal P-In of the folded cascode type operational amplifier circuit, and the gate of the N channel MOS transistor M52 is the inverted input of the folded cascode type operational amplifier circuit. The terminal N-In is provided, and the output terminal OUT3 of the folded cascode operational amplifier circuit is provided at the drain of the N-channel MOS transistor M61.

The input signal Vin is input to the normal input terminal P-In of the folded cascode operational amplifier circuit, and VDD is supplied as a power supply voltage, thereby using the folded cascode operational amplifier circuit as a voltage follower. Can do.
FIG. 8 is a diagram showing a transient response of each node at start-up when the folded cascode operational amplifier circuit of FIG. 6 is used as a voltage follower.

  Here, as an initial state, the folded cascode operational amplifier circuit is powered down, and a voltage within a range in which the folded cascode operational amplifier circuit can operate is applied to the normal input terminal P-In, for example, Assume that ½ · VDD is applied. Note that power down refers to a state in which the potential of the output terminal OUT3 is 0V. Here, the case where the folded cascode operational amplifier circuit is powered down means that the power of the folded cascode operational amplifier circuit is not supplied (VDD = 0V), or the folded cascode operational amplifier is operated by an additional circuit. Any of the cases where all paths between VDD and GND in the amplifier circuit are disconnected may be used.

When the folded cascode operational amplifier circuit shifts from the power-down state to the power-up state, the normal input terminal P-In maintains the potential of 1/2 · VDD and the inverting input terminal N-In has 0V. It gradually rises from. At this time, while the potential difference between the non-inverting input terminal P-In and the inverting input terminal N-In is large, the input portion of the folded cascode operational amplifier circuit operates like a comparator, and the internal nodes A3 and B3 are The potential that is relatively close to the GND level is gradually increased. When the output of the folded cascode operational amplifier circuit, that is, the potential of the inverting input terminal N-In approaches the potential of the non-inverting input terminal P-In, negative feedback is activated rapidly, and the potential at the internal node B3 is rapidly increased. And the operation becomes such that it settles to the operating point in the steady state.
In order to obtain a wider input range, for example, as disclosed in Non-Patent Document 2, a rail-to-rail operational amplifier circuit having two differential pairs may be used.

FIG. 9 is a circuit diagram showing a configuration of a conventional rail-to-rail operational amplifier circuit.
In FIG. 9, the rail-to-rail operational amplifier circuit includes a pair of P-receiver and N-receiver differential pairs, and an N-receiver differential pair transistor 31a and a P-receiver differential pair transistor 31b are provided. In addition, a cascode type load transistor 33 and a current bias transistor 32 are provided.

Here, the differential pair transistor 31a is provided with N-channel MOS transistors M71 and M72. The sources of the N-channel MOS transistors M71 and M72 are connected to the drain of the N-channel MOS transistor M79. The source is connected to ground potential.
The differential pair transistor 31b is provided with P-channel MOS transistors M73 and M74, the sources of the P-channel MOS transistors M73 and M74 are connected to the drain of the P-channel MOS transistor M84, and the source of the P-channel MOS transistor M84. Are connected to the power supply potential. The P channel MOS transistor M84 and the N channel MOS transistor M79 are current bias transistors.

  The current bias transistor 32 includes N-channel MOS transistors M80 to M83. The N-channel MOS transistors M80 and M82 are connected in series with each other, and the source of the N-channel MOS transistor M82 is connected to the ground potential. ing. The N channel MOS transistors M81 and M83 are connected in series with each other, and the source of the N channel MOS transistor M83 is connected to the ground potential. The gates of N-channel MOS transistors M80 and M81 are connected to each other, and the gates of N-channel MOS transistors M79, M82 and M83 are connected to each other. The drain of the N channel MOS transistor M82 is connected to the drain of the P channel MOS transistor M74, and the drain of the N channel MOS transistor M83 is connected to the drain of the P channel MOS transistor M73.

  The cascode-type load transistor 33 is provided with P-channel MOS transistors M75 to M78. The P-channel MOS transistors M75 and M77 are connected in series with each other, and the source of the P-channel MOS transistor M75 is connected to the power supply potential. ing. The drain of the P channel MOS transistor M75 is connected to the drain of the N channel MOS transistor M71, and the drain of the P channel MOS transistor M77 is connected to the drain of the N channel MOS transistor M80.

The P channel MOS transistors M76 and M78 are connected in series with each other, and the source of the P channel MOS transistor M76 is connected to the power supply potential. The drain of the P channel MOS transistor M76 is connected to the drain of the N channel MOS transistor M72, and the drain of the P channel MOS transistor M78 is connected to the drain of the N channel MOS transistor M81.
The gates of the P-channel MOS transistors M75 and M76 are connected to each other and to the drain of the P-channel MOS transistor M77, and the gates of the P-channel MOS transistors M77 and M78 are connected to each other.

  Then, by inputting bias 51 to the N-channel MOS transistor M79, it becomes possible to control the operating points of the N-channel MOS transistors M71 and M72. Further, by inputting bias 54 to the N-channel MOS transistor M84, it becomes possible to control the operating points of the N-channel MOS transistors M73 and M74. Further, by inputting bias 52 to the N-channel MOS transistors M80 and M81, the operating points of the internal nodes C4 and D4 can be controlled. Further, by inputting the bias 53 to the N-channel MOS transistors M77 and M78, the operating points of the internal nodes A4 and B4 can be controlled.

  In order to use the rail-to-rail operational amplifier circuit of FIG. 9 as a voltage follower, the gates of the N channel MOS transistor M71 and the P channel MOS transistor M74 can be connected to the drain of the N channel MOS transistor M81. . The gates of the N-channel MOS transistor M71 and the P-channel MOS transistor M74 are provided with the normal input terminal P-In of the rail-to-rail type operational amplifier circuit, and the N-channel MOS transistor M72 and the P-channel MOS transistor M73. Is provided with an inverting input terminal N-In of the rail-to-rail operational amplifier circuit, and an output terminal OUT4 of the rail-to-rail operational amplifier circuit is provided at the drain of the N-channel MOS transistor M81. Yes. The rail-to-rail operational amplifier circuit can be used as a voltage follower by inputting an input signal to the normal input terminal P-In of the rail-to-rail operational amplifier circuit.

Here, in the rail-to-rail operational amplifier circuit, when the input voltage is near GND, the N receiving differential pair transistor 31a is in the OFF state, and only the P receiving differential pair transistor 31b operates. Conversely, when the input voltage is near VDD, the P-receiving differential pair transistor 31b is in an OFF state, and only the N-receiving differential pair transistor 31a operates.
Further, when the input voltage is near 1/2 · VDD, both differential pair transistors 31a and 31b operate. Therefore, when a rail-to-rail operational amplifier circuit is used as a voltage follower, even when the operational amplifier circuit has already been started up, it is about 1 / 2.VDD from near GND, or 1 / minute from near VDD. In the operation when a step input that makes a transition to the vicinity of 2 · VDD is given, one of the differential pair transistors 31a and 31b rises from the power-down state.
By Rubik Gregorian, “Analog MOS Integrated Circuits for Signal Processing” (USA), JOHN WILEY & SONS, Inc. 1986, p. 251-255 Ron Hogervorst, et. al. , A Compact Power-Efficient 3V CMOS Rail-to-Rail Input / Output Operational Amplifier for VLSI Cell Libraries, IEEE J.A. Solid State Circuits, VOL. 29, no. 12, December 1994, pp 1505-1513.

However, in the folded cascode operational amplifier circuit of FIG. 6, a parasitic capacitance C _gd exists between the gate and drain of the N-channel MOS transistor M51, and a parasitic capacitance C _gs exists between the gate and source of the N-channel MOS transistor M51. Exists. The change in potential at the internal node A point and the internal node B point is transmitted to the normal input terminal P-In via these parasitic capacitances C _gd and C _gs .

Therefore, if the output impedance R _{f of the} module that generates the input signal Vin to the folded cascode operational amplifier circuit is sufficiently small, the potential of the normal input terminal P-In hardly changes, but the output impedance R _f is If it is larger, the potential of the normal rotation input terminal P-In fluctuates, and the fluctuation appears as an overshoot in the output of the folded cascode type operational amplifier circuit as shown in FIG.

Further, when the rail-to-rail operational amplifier circuit of FIG. 9 is used as a voltage follower, its characteristics are the same as those at the time of startup of a normal folded cascode operational amplifier circuit, and in particular, a module that generates an input signal. When the output impedance is large, overshoot and undershoot similar to those of the folded cascode operational amplifier circuit occur in the output waveform. Depending on the application, such overshoot or undershoot may cause a fatal problem.
Therefore, an object of the present invention is to smooth the response characteristics when the operational amplifier circuit is started up and when the step is input even when the output impedance of the module that generates the input signal to the operational amplifier circuit is high. An operational amplifier circuit is provided.

  In order to solve the above-described problem, according to the operational amplifier circuit of the first aspect, a pair of differential pair transistors, a folded cascode type load transistor, and a current biasing transistor disposed in the signal input unit are provided. A folded cascode operational amplifier circuit; and an additional circuit for controlling a fluctuation range of the drain potential of the differential pair transistor.

  Thus, even when a voltage follower is configured using an operational amplifier circuit, the output of the voltage follower can be raised after raising the drain potential of the differential pair transistor to which the input signal is inputted. For this reason, even when the potential on the input side varies with the variation in the drain potential of the differential pair transistor, the variation in the output of the voltage follower can be suppressed. As a result, even when the output impedance of the module that generates the input signal to the operational amplifier circuit is high, overshoot and undershoot of the output waveform at startup and step input can be suppressed, and the response of the voltage follower The characteristics can be smoothed.

The operational amplifier circuit according to claim 2 is characterized in that the additional circuit is a transistor pair connected in series to the drain of the differential pair transistor and having a gate and a drain connected.
As a result, even when the potential difference between the normal input terminal and the inverting input terminal of the operational amplifier circuit is large, the transistor connected to the drain of the differential pair transistor can be turned on, and the potential of the drain of the differential pair transistor can be turned on. Can be launched quickly. For this reason, even when a voltage follower is configured using an operational amplifier circuit, the output of the voltage follower can be raised after the drain potential of the differential pair transistor to which the input signal is input is raised. It is possible to suppress overshoot and undershoot of the output waveform during raising and step input.

According to the operational amplifier circuit of claim 3, when the differential pair transistors are balanced, the bias of the current bias transistor is set so that the transistor pair of the additional circuit is turned off. It is characterized by being.
This makes it possible to control the fluctuation range of the drain potential of the differential pair transistor, and in the state where the operational amplifier circuit operates as a voltage buffer due to the negative feedback, the characteristics are hardly adversely affected. Can be.

According to the operational amplifier circuit of claim 4, a rail-to-rail in which another differential pair transistor having a different polarity from the differential pair transistor of the folded cascode operational amplifier circuit is added to the signal input section. A differential operational amplifier circuit and an additional circuit for controlling a fluctuation range of the drain potential of the differential pair transistor.
As a result, even when the potential on the input side fluctuates with the fluctuation of the drain potential of the differential pair transistor, fluctuations in the output of the voltage follower can be suppressed, and a wide input range can be obtained, It is possible to suppress overshoot and undershoot of the output waveform at start-up and step input.

The operational amplifier circuit according to claim 5 is characterized in that the additional circuit is a transistor pair connected in series to the drains of the differential pair transistors and having a gate and a drain connected.
This suppresses the drop in the drain potential of the differential pair transistor and enables a wide input range, while suppressing overshoot and undershoot of the output waveform at startup and step input. Can do.

  As described above, according to the present invention, when a voltage follower is formed and used as a voltage buffer, even when the output impedance of a module that generates an input signal to the operational amplifier circuit is high, Further, it is possible to suppress the occurrence of overshoot or undershoot in the output waveform at the time of step input, and smooth response characteristics can be obtained.

Hereinafter, an operational amplifier circuit according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a circuit diagram showing a configuration of an operational amplifier circuit according to the first embodiment of the present invention. In the first embodiment, the additional circuit 4 for controlling the fluctuation range of the drain potential is added to the folded cascode type arithmetic circuit shown in FIG. 6 and used as a voltage follower.
In FIG. 1, in the first embodiment, a differential pair transistor 1, a cascode load transistor 2, a current biasing transistor 3 and an additional circuit 4 are provided.
Here, the differential pair transistor 1 is provided with N-channel MOS transistors M1 and M2. The sources of the N-channel MOS transistors M1 and M2 are connected to the drain of the N-channel MOS transistor M9. The source is connected to ground potential.

  The differential pair transistor 1 is connected to an additional circuit 4 that controls the fluctuation range of the drain potential of the N-channel MOS transistor M1. Here, the additional circuit 4 is provided with P-channel MOS transistors M3 and M4. The P-channel MOS transistors M3 and M4 are respectively diode-connected and connected in series with the N-channel MOS transistors M1 and M2. That is, the sources of the P-channel MOS transistors M3 and M4 are connected to the power supply potential, and the drains of the P-channel MOS transistors M3 and M4 are connected to the drains of the N-channel MOS transistors M1 and M2, respectively. The gate of M4 is connected to the drains of P-channel MOS transistors M3 and M4, respectively.

The P transistor M4 is not necessary for controlling the fluctuation range of the drain potential of the N-channel MOS transistor M1, but is preferably added to maintain the operational balance as a differential amplifier circuit.
The cascode-type load transistor 2 is provided with N-channel MOS transistors M10 to M13. The N-channel MOS transistors M10 and M12 are connected in series with each other, and the source of the N-channel MOS transistor M12 is connected to the ground potential. ing. The N channel MOS transistors M11 and M13 are connected in series with each other, the source of the N channel MOS transistor M13 is connected to the ground potential, and the gates of the N channel MOS transistors M10 and M11 are connected to each other. The gates of the N channel MOS transistors M12 and M13 are connected to each other, and the gates of the N channel MOS transistors M12 and M13 are connected to the drain of the N channel MOS transistor M10.

  The current bias transistor 3 is provided with P-channel MOS transistors M5 to M8. The P-channel MOS transistors M5 and M7 are connected in series with each other, and the source of the P-channel MOS transistor M5 is connected to the power supply potential. ing. The drain of the P channel MOS transistor M5 is connected to the drain of the N channel MOS transistor M1, and the drain of the P channel MOS transistor M7 is connected to the drain of the N channel MOS transistor M10.

  The P channel MOS transistors M6 and M8 are connected in series with each other, and the source of the P channel MOS transistor M6 is connected to the power supply potential. The drain of the P channel MOS transistor M6 is connected to the drain of the N channel MOS transistor M2, and the drain of the P channel MOS transistor M8 is connected to the drain of the N channel MOS transistor M11.

  In order to use the operational amplifier circuit of FIG. 1 as a voltage follower, the gate of the N-channel MOS transistor M2 is connected to the drain of the N-channel MOS transistor M11. The gate of the N channel MOS transistor M1 is provided with the normal input terminal P-In of the operational amplifier circuit, and the gate of the N channel MOS transistor M2 is provided with the inverted input terminal N-In of the operational amplifier circuit. The output terminal OUT1 of the operational amplifier circuit is provided at the drain of the N-channel MOS transistor M11. Then, by inputting the input signal Vin to the normal input terminal P-In of the operational amplifier circuit and supplying VDD as the power supply voltage, the operational amplifier circuit of FIG. 1 can be used as a voltage follower.

FIG. 2 is a diagram showing a transient response of each node at start-up when the operational amplifier circuit of FIG. 1 is used as a voltage follower.
Here, the operational amplifier circuit is powered down as an initial state, and ½ · VDD, for example, is applied to the normal input terminal P-In as a voltage within a range in which the operational amplifier circuit can operate. Assuming that When the operational amplifier circuit shifts from the power-down state to the power-up state, the normal input terminal P-In maintains the potential of 1/2 · VDD and the inverting input terminal N-In gradually increases from the GND level. Rise. At this time, while the potential difference between the non-inverting input terminal P-In and the inverting input terminal N-In is large, the input part of the operational amplifier circuit operates like a comparator, and the potential of the internal node B1 is initially GND. Although it is near the level, since the diode-connected P-channel MOS transistor M3 is turned on, the potential of the internal node B1 immediately rises to near VDD-Vtp (Vtp is the absolute value of the threshold value of the P-channel MOS transistor M3).

Here, a parasitic capacitance C _gd exists between the gate and the drain of the N-channel MOS transistor M1, and a parasitic capacitance C _gs exists between the gate and the source of the N-channel MOS transistor M1. The change in potential at the internal node A point and the internal node B point is transmitted to the normal input terminal P-In via the parasitic capacitances C _gd and C _gs . For this reason, when the output impedance _Rf is large, the potential of the normal input terminal P-In varies, and an overshoot occurs in the potential of the normal input terminal P-In. However, at this time, the potential of the inverting input terminal N-In gradually rises in a state close to the GND level, so that an overshoot can be prevented from occurring in the output of the operational amplifier circuit.

Thereafter, when the output of the operational amplifier circuit, that is, the potential of the inverting input terminal N-In approaches the potential of the non-inverting input terminal P-In, negative feedback is rapidly activated, and the potential at the internal node B increases. However, since the amount of change in potential at the internal node B is small, even when the output impedance _Rf is large, the fluctuation of the normal input terminal P-In can be reduced. For this reason, even when the operational amplifier circuit is used as a voltage follower, it is possible to suppress the overshoot of the output of the operational amplifier circuit, and the transient response characteristic of the operational amplifier circuit can be smoothed.

The P-channel MOS transistors M3 and M4 have the above-described great effect in a state where the operational amplifier circuit operates as a comparator, while the negative feedback works and the operational amplifier circuit operates as a voltage buffer. In such a state, it is possible to set the operating point so as not to adversely affect the characteristics.
That is, when the transistor is operated in the saturation region, it is normal to take a certain potential as the overdrive voltage Vov (gate-source voltage Vgs−threshold Vth), but if the overdrive voltage Vov is taken unnecessarily, Since the operation range becomes narrow, there is no particular problem with setting Vov <Vth. Since the overdrive voltage (Vov _5,6 = VDD−V _bias4 −Vth) of the P-channel MOS transistors M5 and M6 can be controlled by the potential of bias4, it is easy to satisfy Vov _5,6 <Vth. .

Since the operating points of the internal node B1 and the internal node C1 can be controlled by the current flowing through the P-channel MOS transistors M7 and M8 and the potential of bias3, Vov _5,6 <(VDD−V _B ) = ( It is easy to set VDD−V _C ) <Vth (V _B and V _C are the potentials of the internal nodes B1 and C1, respectively).
If the bias condition is set so as to be such an operating point, almost no current flows because the gate voltages of the P-channel MOS transistors M3 and M4 do not exceed the threshold when operating as a voltage buffer. For this reason, it is possible to prevent the operating point inside the operational amplifier circuit from changing compared to the case where the P channel MOS transistors M3 and M4 are not provided, and even when the P channel MOS transistors M3 and M4 are added, the operational amplifier circuit. It is possible to make it hardly affect the characteristics of the. In addition, the time required for the startup of the operational amplifier circuit can be kept unchanged.

FIG. 3 is a circuit diagram showing a configuration of an operational amplifier circuit according to the second embodiment of the present invention. In the second embodiment, additional circuits 14a and 14b for controlling the fluctuation range of the drain potential are added to a two-stage rail-to-rail operational amplifier circuit to be used as a voltage follower. is there.
3, in the second embodiment, two pairs of differential transistors 11a and 11b, a cascode-type load transistor 12, a current biasing transistor 13, additional circuits 14a and 14b, and an output circuit 15 are provided. .

Here, the differential pair transistor 11a is provided with N-channel MOS transistors M21 and M22. The sources of the N-channel MOS transistors M21 and M22 are connected to the drain of the N-channel MOS transistor M42. The source is connected to ground potential.
The differential pair transistor 11a is connected to an additional circuit 14a that controls the fluctuation range of the drain potential of the N-channel MOS transistor M21. Here, the additional circuit 14a is provided with P-channel MOS transistors M23 and M24. The P-channel MOS transistors M23 and M24 are respectively diode-connected and connected in series with the N-channel MOS transistors M21 and M22. That is, the sources of the P-channel MOS transistors M23 and M24 are connected to the power supply potential, and the drains of the P-channel MOS transistors M23 and M24 are connected to the drains of the N-channel MOS transistors M21 and M22, respectively. The gate of M24 is connected to the drains of P-channel MOS transistors M23 and M24, respectively.

The differential pair transistor 11b is provided with P-channel MOS transistors M25 and M26. The sources of the P-channel MOS transistors M25 and M26 are connected to the drain of the P-channel MOS transistor M43, and the source of the P-channel MOS transistor M43. Are connected to the power supply potential.
The differential pair transistor 11b is connected to an additional circuit 14b for controlling the fluctuation range of the drain potential of the P-channel MOS transistor M26. Here, the additional circuit 14b is provided with P-channel MOS transistors M27 and M28. The N-channel MOS transistors M27 and M28 are respectively diode-connected and connected in series with the P-channel MOS transistors M25 and M26. That is, the sources of N-channel MOS transistors M27 and M28 are connected to the power supply potential, and the drains of N-channel MOS transistors M27 and M28 are connected to the drains of P-channel MOS transistors M25 and M26, respectively. The gate of M28 is connected to the drains of N-channel MOS transistors M27 and M28, respectively.

  The cascode-type load transistor 12 is provided with N-channel MOS transistors M34 to M37. The N-channel MOS transistors M34 and M36 are connected in series with each other, and the source of the N-channel MOS transistor M36 is connected to the ground potential. ing. The N channel MOS transistors M35 and M37 are connected in series with each other, and the source of the N channel MOS transistor M37 is connected to the ground potential. The gates of the N channel MOS transistors M34 and M35 are connected to each other, and the gates of the N channel MOS transistors M36 and M37 are connected to each other. The drain of the N channel MOS transistor M36 is connected to the drain of the P channel MOS transistor M26, and the drain of the N channel MOS transistor M37 is connected to the drain of the P channel MOS transistor M25.

  The current bias transistor 13 is provided with P-channel MOS transistors M30 to M33. The P-channel MOS transistors M30 and M32 are connected in series, and the source of the P-channel MOS transistor M30 is connected to the power supply potential. ing. The drain of the P channel MOS transistor M30 is connected to the drain of the N channel MOS transistor M21, and the drain of the P channel MOS transistor M32 is connected to the drain of the N channel MOS transistor M34.

The P channel MOS transistors M31 and M33 are connected in series, and the source of the P channel MOS transistor M31 is connected to the power supply potential. The drain of the P channel MOS transistor M31 is connected to the drain of the N channel MOS transistor M22.
The gates of the P-channel MOS transistors M30 and M31 are connected to each other and are connected to the drain of the P-channel MOS transistor M32. The gates of the P-channel MOS transistors M32 and M33 are connected to each other.

  The output circuit 15 is provided with P-channel MOS transistors M38 and M40, N-channel MOS transistors M39 and M41, resistors R1 and R2, and capacitors C1 and C2. P channel MOS transistor M38 and N channel MOS transistor M39 can be used as output transistors. The P channel MOS transistor M40 and the N channel MOS transistor M41 can be used for bias setting of the P channel MOS transistor M38 and the N channel MOS transistor M39. The resistors R1 and R2 and the capacitors C1 and C2 can be used for phase compensation.

  Here, the P channel MOS transistor M38 and the N channel MOS transistor M39 are connected in series, the source of the P channel MOS transistor M38 is connected to the power supply potential, and the source of the N channel MOS transistor M39 is connected to the ground potential. ing. A resistor R1 and a capacitor C1 connected in series with each other are connected between the gate and drain of the P-channel MOS transistor M38, and between the gate and drain of the N-channel MOS transistor M39. A connected resistor R2 and capacitor C2 are connected.

  The P channel MOS transistor M40 and the N channel MOS transistor M41 are connected in parallel to each other. The drain of the N-channel MOS transistor M41 is connected to the drain of the P-channel MOS transistor M33 and to the gate of the P-channel MOS transistor M38. The source of the N channel MOS transistor M41 is connected to the drain of the N channel MOS transistor M35 and to the gate of the N channel MOS transistor M39.

  In order to use the operational amplifier circuit of FIG. 3 as a voltage follower, the gates of the N channel MOS transistor M21 and the P channel MOS transistor M26 are connected to the drain of the N channel MOS transistor M39. The gates of the N channel MOS transistor M22 and the P channel MOS transistor M25 are provided with the normal input terminal P-In of the operational amplifier circuit, and the gates of the N channel MOS transistor M21 and the P channel MOS transistor M26 are operated and amplified. An inverting input terminal N-In of the circuit is provided, and an output terminal OUT2 of the operational amplifier circuit is provided at the drain of the N-channel MOS transistor M39. Then, by inputting the input signal Vin to the normal rotation input terminal P-In of the operational amplifier circuit and supplying VDD as the power supply voltage, the operational amplifier circuit of FIG. 3 can be used as a voltage follower.

In the operational amplifier circuit of FIG. 3, the gate of the N-channel MOS transistor M22 - between the drain there is a parasitic capacitance C _gdn, the gate of the P-channel MOS transistor M25 - between the drain there is a parasitic capacitance C _gdp.
Here, the operating points of the internal nodes A2, B2, C2, and D2 when the differential pair transistors 11a and 11b are balanced are that the P-channel MOS transistors M23 and M24 and the N-channel MOS transistors M27 and M28 are in the off state. Can be set to such a potential. When the potential of the input signal Vin is in the vicinity of GND, the N-channel MOS transistors M21 and M22 are in an off state, so that the P-channel MOS transistors M25 and M26 operate as an operational amplifier circuit having a differential pair. Negative input is applied so that the inverting input terminal P-In and the inverting input terminal N-In have substantially the same potential. At this time, the P-channel MOS transistors M23 and M24 and the N-channel MOS transistors M27 and M28 are also in the off state, and no current flows.

Next, when the input voltage Vin increases stepwise to around ½ · VDD, the voltage applied to the N-channel MOS transistors M21 and M22 in the process of increasing the potential of the inverting input terminal N-In. Since the difference is large, the potential of the internal node B2 tends to decrease to near GND. However, when the potential of the internal node B2 becomes equal to or lower than VDD−Vth, the P-channel MOS transistor M24 is turned on and current starts to flow, so that the potential drop stops when the current determined by the bias 11 is balanced. This potential can be adjusted by the size of the P-channel MOS transistor M24. For this reason, the fluctuation of the internal node B2 when the potential of the inverting input terminal N-In is almost equal to the normal input terminal P-In and negative feedback is applied can be suppressed, and the output impedance _Rf is large (for example, Even in the case of several tens of kΩ or more), it is possible to reduce the influence on the non-inverting input terminal P-In via the parasitic capacitance C _gdn and to obtain a step response without accompanying overshoot. The above operation is basically the same as that at the start-up of the circuit shown in FIG.

FIG. 4 is a diagram showing a transient response of each node at the start-up when the operational amplifier circuit of FIG. 3 is used as a voltage follower in comparison with the conventional example of FIG.
In FIG. 4A, when the output impedance _Rf is large, an input that changes stepwise from the vicinity of GND to about ½ · VDD is given as the input voltage Vin. At this time, in the rail-to-rail operational amplifier circuit of FIG. 9, since the potential fluctuation of the internal node B4 is large, the fluctuation is transmitted to the normal input terminal P-In, and an overshoot occurs at the OUT4 terminal.

On the other hand, as shown in FIG. 4B, in the operational amplifier circuit in which the additional circuit 14a of FIG. 3 is added to the differential pair transistor 11a, the potential drop of the internal node B2 can be suppressed, and the output of the OUT2 terminal It can be seen that there is no overshoot. Conversely, even when an input that changes from near VDD to about 1/2 · VDD is given, by adding the additional circuit 14b of FIG. 3 to the differential pair transistor 11b, the N-channel MOS transistor M27 The rise of the internal node C2 can be suppressed. For this reason, it is possible to reduce the influence on the normal input terminal P-In via the parasitic capacitance C _gdp and to prevent the occurrence of undershoot.
In any case, in the state where the differential pair transistors are balanced, the operational amplification in that state is achieved by designing the operating point so that almost no current flows in the newly added MOS transistor. Various characteristics of the circuit can be maintained.

  The operational amplifier circuit of the present invention can be used as a voltage buffer for impedance conversion, and can smooth the response characteristic at the time of startup and the response characteristic at the time of step input.

1 is a circuit diagram showing a configuration of an operational amplifier circuit according to a first embodiment of the present invention. It is a figure which shows the transient response of each node at the time of start-up at the time of using the operational amplifier circuit of FIG. 1 as a voltage follower. It is a circuit diagram which shows the structure of the operational amplifier circuit which concerns on 2nd Embodiment of this invention. FIG. 10 is a diagram showing a transient response of each node at start-up when the operational amplifier circuit of FIG. 3 is used as a voltage follower in comparison with the conventional example of FIG. 9. It is a circuit diagram which shows the structure of the voltage follower using the conventional operational amplifier circuit. It is a circuit diagram which shows the structure of the conventional folded cascode type | mold operational amplifier circuit. FIG. 7 is a circuit diagram showing a configuration when the folded cascode operational amplifier circuit of FIG. 6 is used as a voltage follower. It is a figure which shows the transient response of each node at the time of start-up at the time of using the folded cascode type | mold operational amplifier circuit of FIG. 6 as a voltage follower. It is a circuit diagram which shows the structure of the conventional rail-to-rail type operational amplifier circuit.

Explanation of symbols

1, 11a, 11b Differential pair transistor 2, 12 Cascode-type load transistor 3, 13 Current bias transistor 4, 14a, 14b Additional circuit M1, M2, M9 to M13, M21, M22, M27, M28, M34 to M37, M39, M41, M42, M51 to M53, M60 to M63, M71, M72, M79, M80 to M83 N-channel MOS transistors M3, M4, M5 to M8, M23 to M26, M30 to M33, M38, M40, M43 , M55 to M58, M73, M74, M75 to M78, M84 P-channel MOS transistor R _f Output impedance C _gd , C _gs parasitic capacitance R1, R2 Resistor C1, C2 Capacitor OP operational amplifier 15 Output circuit

Claims (5)

A folded cascode operational amplifier circuit provided with a pair of differential pair transistors, a folded cascode load transistor, and a current bias transistor disposed in the signal input unit;
And an additional circuit for controlling a fluctuation range of the drain potential of the differential pair transistor.   2. The operational amplifier circuit according to claim 1, wherein the additional circuit is a transistor pair connected in series to the drains of the differential pair transistors and having a gate and a drain connected to each other.   3. The operational amplifier circuit according to claim 2, wherein when the differential pair transistor is balanced, the bias of the current bias transistor is set so that the transistor pair of the additional circuit is turned off. . A rail-to-rail operational amplifier circuit in which another differential pair transistor having a different polarity from the differential pair transistor of the folded cascode operational amplifier circuit is added to the signal input unit,
And an additional circuit for controlling a fluctuation range of the drain potential of the differential pair transistor.   5. The operational amplifier circuit according to claim 4, wherein the additional circuit is a transistor pair connected in series to the drains of the differential pair transistors and having a gate and a drain connected to each other.

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