JP2005197890A - Contactless ic responder - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely synchronize a plurality of IC responders even when they are located close to each other. <P>SOLUTION: An IC card 111 is provided with a resonance circuit including a coil 112 and a capacitance control resonance capacitor 113 whose capacitance is variably controlled to have a prescribed capacitance. The capacitance control resonance capacitor 113 includes: a PMOS transistor 121 whose base level can be variably set; and a base level control circuit 122 for controlling the base level. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a non-contact type IC responder referred to as a non-contact type IC card or IC tag that performs non-contact data communication with an interrogator such as a reader / writer via electromagnetic waves, It belongs to the technology related to adjustment of resonance frequency.

  In recent years, the use of non-contact type IC responders such as non-contact type IC cards and IC tags that transmit and receive data without contact is rapidly progressing, and standardization of communication methods and the like is also progressing rapidly (for example, communication distance). Is ISO 14443 for the proximity type having a communication distance of about 10 cm, and ISO 15693 for the proximity type having a communication distance of about 70 cm.

  This type of IC card, for example, can be read in a non-contact manner by using a reader / writer to read information about the article recorded on the IC card or the like by adding it to the article instead of a barcode. Its application to high article management systems is attracting attention.

  The card system using the non-contact type IC card as described above has a configuration as shown in FIG. 20, for example. In the figure, a reader / writer 901 includes a transmission unit 902, a reception unit 903, a coil 904, and a resonance capacitor 905. The IC card 911 includes a resonance circuit having a coil 912 and a resonance capacitor 913, a rectifying diode 914, and a main body of the IC card 911 shown in FIG. .

  In the IC card system configured as described above, electric power and signals are transmitted and received between the reader / writer 901 and the IC card 911 by electromagnetic induction using electromagnetic waves. More specifically, when an electromagnetic wave in which a data signal is superimposed on a carrier wave having a predetermined frequency is transmitted from the reader / writer 901, in the IC card 911, a voltage due to electromagnetic induction is induced at both ends of the coil 912 constituting the resonance circuit. The This voltage is rectified and used as a power supply voltage, and a data signal is extracted and various processes are performed.

  As shown in FIG. 21, the voltage induced across the coil 912 changes according to the frequency of the received electromagnetic wave, and becomes highest when the carrier frequency is equal to the resonance frequency f0 of the resonance circuit. The resonance frequency f0 is expressed as follows.

f0 = 1 / {2 × π × √ (L × C)}
here,
L: inductance of the coil 912 C: capacitance of the resonance capacitor 913

  Therefore, the inductance of the coil 912 and the capacitance of the resonance capacitor 913 are set when the IC card 911 is manufactured so that the resonance frequency f0 is equal to the carrier frequency.

  In the IC card system as described above, unlike the case of using a barcode, it is conceivable to read data from a plurality of IC cards 911 in a batch. However, in reality, when a plurality of IC cards are stacked and the resonance frequency shifts, the above-described conventional IC card system cannot reliably read data.

  That is, when the coils 912 of a plurality of IC cards are close to each other, the resonance frequency is lowered by the mutual inductance M due to the coupling relationship as shown in FIG. Specifically, the resonance frequency f1 is as follows.

f1 = 1 / [2 × π × √ {(L + M) × C}]
here,
L: Inductance of coil 912 C: Capacitance of resonance capacitor 913 M: Mutual inductance.

  Therefore, the voltage induced in the coil 912 is as shown by the broken line in FIG. 21, and the voltage when the electromagnetic wave having the carrier frequency equal to the resonance frequency f0 when one card is received is lowered. Become. Such a decrease in induced voltage becomes more prominent as the number of adjacent IC cards increases and as a plurality of IC cards come closer to each other. When the IC card 911 falls below the minimum voltage Vo at which the IC card 911 can operate, communication with the reader / writer 901 becomes impossible.

In general, as a technique for tuning the resonance frequency to the carrier frequency, a technique of providing a plurality of capacitive elements and selectively switching them is known (see, for example, Patent Documents 1 and 2).
Japanese Patent Laid-Open No. 10-84304 Japanese National Patent Publication No. 9-511887

  However, in the conventional IC card system, as described above, when a plurality of IC cards are used in an overlapping manner, reliable data reading cannot be performed.

  In addition, as shown in Patent Documents 1 and 2, when a plurality of capacitive elements are provided, the area occupied by the capacitive elements becomes large, resulting in a significant increase in circuit scale.

  In view of the above problems, the present invention can appropriately set the resonance frequency even when a plurality of IC responders are close to each other without causing a significant increase in circuit scale, and reliably tunes to the carrier frequency. It is a problem to be able to make it.

In view of the above points, the invention of claim 1
A non-contact IC responder that performs data communication with an interrogator via electromagnetic waves,
A resonant circuit having a MOS element that forms a capacitive element between the gate and the source and drain connected to each other and has a variable substrate potential;
A control circuit for controlling the substrate potential of the MOS transistor;
It is provided with.

The invention of claim 2
The non-contact IC responder according to claim 1, wherein
The resonance circuit further includes a variable resistor connected in series with the MOS transistor and having a resistance value controlled according to a given potential.
The control circuit is further configured to control a resistance value of the variable resistor.

  As a result, the substrate potential of the MOS transistor is controlled, whereby the capacitance between the gate and the source and drain connected to each other changes, and the resonance frequency is controlled. it can. Furthermore, by controlling the resistance value of the variable resistor connected in series with the MOS transistor, the resonance frequency can be controlled and tuned more flexibly.

The invention of claim 3
A non-contact type IC responder according to any one of claims 1 and 2,
The control circuit is
A non-volatile memory that outputs a control signal for controlling at least one of the substrate potential of the MOS transistor and the resistance value of the variable resistor;
In accordance with the control signal, a potential setting circuit that selects any one of a plurality of predetermined potentials and applies the selected potential to the substrate of the MOS transistor or the variable resistor;
It is provided with.

  Thus, by storing predetermined data in the nonvolatile memory, the potential applied to the substrate can be easily set with respect to the voltage generated by the resonance circuit, and therefore, the resonance frequency can be easily set.

The invention of claim 4
A non-contact type IC responder according to any one of claims 1 and 2,
The control circuit is
A demodulation circuit that demodulates the signal received by the resonance circuit and outputs a demodulated signal;
A potential setting circuit that selects any one of a plurality of predetermined potentials according to the demodulated signal, and applies the selected potential to at least one of the substrate of the MOS transistor and the variable resistor;
It is provided with.

  As a result, the substrate potential or the like, and thus the resonance frequency, is set according to the demodulated signal, and therefore it is easy to set the resonance frequency from the outside of the non-contact type IC responder at the time of reception.

The invention of claim 5
A non-contact IC responder according to any one of claims 3 and 4,
The predetermined plural types of potentials are each one or more corresponding to the potential corresponding to one non-contact type IC responder and the number of one or more types of non-contact type IC responders that are close to each other in a predetermined proximity state. The potential is two or more of the potentials.

  Thereby, it is possible to easily set the resonance frequency appropriately for a single non-contact IC responder or a plurality of non-contact IC responders close to each other.

The invention of claim 6
A non-contact type IC responder according to any one of claims 1 and 2,
The control circuit is
In accordance with a voltage generated by the resonance circuit, at least one of the substrate potential of the MOS transistor and the variable resistance is controlled.

  Thereby, since the substrate potential and the like are controlled according to the voltage generated by the resonance circuit, the resonance frequency can be automatically adjusted.

The invention of claim 7
The non-contact IC responder according to claim 6, wherein
In accordance with a voltage generated by the resonance circuit in a state where a predetermined potential is applied to at least one of the substrate of the MOS transistor and the variable resistor, the control circuit is configured such that the substrate of the MOS transistor or It is configured to switch the potential applied to the variable resistor.

The invention of claim 8
The non-contact IC responder according to claim 7, wherein
The control circuit is configured to sequentially switch a potential applied to the substrate or the variable resistor of the MOS transistor when a voltage generated by the resonance circuit is equal to or lower than a predetermined voltage.

  As a result, it is possible to automatically adjust the resonance frequency by controlling the substrate potential or the like only by simply detecting whether or not the voltage generated by the resonance circuit is equal to or lower than a predetermined voltage.

The invention of claim 9
The non-contact IC responder according to claim 6, wherein
The control circuit is configured to control a potential applied to at least one of the substrate and the variable resistor in accordance with a change in voltage generated by the resonance circuit before and after a predetermined time elapses. It is characterized by that.

The invention of claim 10 provides
The contactless IC transponder of claim 9, wherein
The control circuit is
A detection circuit for detecting a temporal change in voltage generated by the resonance circuit;
A charge pump circuit that boosts the voltage generated by the resonant circuit and applies the boosted voltage to the substrate;
The charge pump circuit is configured to operate when the voltage generated by the resonance circuit is rising.

  Accordingly, the substrate potential and the like are controlled so that the voltage generated by the resonance circuit is maximized by setting the substrate potential and the like in accordance with the increase and decrease of the voltage generated by the resonance circuit. That is, the resonance frequency can be easily adjusted automatically and appropriately.

The invention of claim 11
The non-contact IC responder according to claim 1, wherein
The MOS transistor is a PMOS transistor further formed on an n-type well formed on at least a p-type semiconductor wafer, or an NMOS transistor further formed on a p-type well formed on at least an n-type semiconductor wafer. It is characterized by being.

  Thereby, by applying a potential to the substrate (well) so as to be a reverse voltage of the pn junction between the p-type semiconductor wafer and the n-type well or between the n-type semiconductor wafer and the p-type well. The operation of other NMOS and PMOS transistors on the same substrate can be easily prevented from being affected. Note that the n-type well and the p-type well are not limited to one layer, and may be formed in multiple layers or as a twin well.

  According to the present invention, since the resonance frequency is set by controlling the substrate potential of the MOS transistor, the resonance frequency can be set even when a plurality of IC responders are close without causing a significant increase in circuit scale. It can be easily set appropriately and can be reliably tuned to the carrier frequency.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

Embodiment 1 of the Invention
FIG. 1 is a circuit diagram showing a schematic configuration of a card system using an IC card which is a non-contact type IC responder according to Embodiment 1 of the present invention. In FIG. 1, a reader / writer 101 includes a transmission unit 102, a reception unit 103, a coil 104 (loop antenna), and a resonance capacitor 105. The IC card 111 also includes a resonance circuit having a coil 112 and a capacitance control resonance capacitor 113 that is variably controlled to a predetermined capacitance, a rectifier diode 114, a smoothing capacitor 115, and an LSI load resistor 116. And a main body portion of the IC card 111 shown. Specifically, as shown in FIG. 2, the capacitance control resonance capacitor 113 includes a PMOS transistor 121 capable of variably setting the substrate potential and a substrate potential control circuit 122 for controlling the substrate potential. Has been. Here, the substrate potential control circuit 122 has a power supply voltage lower than the power supply voltage at which the main body of the IC card 111 can operate, that is, as described later, for example, because the IC card 111 is used in an overlapping manner, the resonance frequency is shifted. It is configured to operate even with a power supply voltage obtained when Specifically, for example, the threshold value of the transistor constituting the substrate potential control circuit 122 is set lower than that of the main body.

(Structure and characteristics of PMOS transistor 121)
For example, as shown in FIG. 3, the PMOS transistor 121 is disposed on an n-type well 132 formed on a p-type silicon wafer 131 via a p-type region 133 serving as a source or a drain and a metal oxide film 134. The gate electrode 135 and the n-type region 136 to which the substrate potential control terminal B for controlling the potential of the n-type well 132 is connected are formed.

  A capacitance is generated between the gate and the source and drain connected to each other, and the potential is controlled variably by changing the potential of the n-type well 132 through the n-type region 136. It has become. More specifically, as shown in FIG. 4, the characteristics in which the source-gate capacitance C (vertical axis) changes according to the gate voltage (Vg−Vs) (horizontal axis) and the substrate voltage (Vb−Vs). Have. That is, for example, when the substrate voltage (Vb−Vs) = 0 (broken line in FIG. 4), when the gate voltage (Vg−Vs) becomes lower than the predetermined threshold value Vtp1, a channel is formed immediately below the gate, and the capacitance C becomes larger as the gate voltage (Vg−Vs) becomes lower, and eventually becomes C1 and becomes saturated. When the substrate voltage (Vb−Vs)> 0 (solid line in FIG. 4), the threshold value Vtp1 is shifted to Vtp2, and similarly, the gate voltage (Vg−Vs) is lower than the threshold value Vtp2. Along with this, the capacity C increases. Therefore, for example, assuming that the gate voltage (Vg−Vs) is Vgs1 shown in the figure, the source voltage is changed from the substrate voltage (Vb−Vs) = 0 state to the substrate voltage (Vb−Vs)> 0 state. The capacity C between them can be reduced from C1 to C2. To be precise, the gate voltage (Vg−Vs) is a voltage that changes positively and negatively at the carrier frequency generated at both ends of the coil 112, but on average, the capacitance at a predetermined gate voltage (Vg−Vs). Can be controlled as described above.

  Here, the n-type well 132 is not necessarily provided in order to control the capacitance between the source and the gate, but the PMOS transistor 121 is formed on the n-type well 132 as shown in FIG. When the substrate voltage (Vb−Vs)> 0, that is, for example, the p-type silicon wafer 131 of FIG. 3 is fixed to the GND (ground) potential, and a positive voltage is applied to the n-type region 136. In this case, a reverse voltage is applied between the n-type well 132 and the p-type silicon wafer 131, which affects other NMOS transistors 141 and the like formed on the p-type silicon wafer 131. Without this (without changing the threshold value), a stable operation can be performed.

(Detailed Configuration of Substrate Potential Control Circuit 122)
For example, as shown in FIG. 5, the substrate potential control circuit 122 includes a nonvolatile memory 123, a substrate potential generation circuit 124, and a selector 125.

  The nonvolatile memory 123 is configured to output predetermined data as selection signals φ1 to φ3 when an activation signal is input. Specifically, the selection signal φ3, in advance, depending on the usage mode of whether the IC card 111 is used alone, two are used in an overlapping manner, or three are used in an overlapping manner. Data in which only φ2 or φ1 is set to H (High) level is written. As the nonvolatile memory 123, for example, a charge storage type or a fuse cut type programmable memory is used.

  The substrate potential generating circuit 124 is configured to increase or decrease the voltage rectified by the rectifying diode 114 by, for example, a charge pump circuit or the like to generate predetermined control voltages V1 to V3 in a plurality of stages. The predetermined control voltages V1 to V3 are set such that when applied to the substrate of the PMOS transistor 121, a resonance frequency corresponding to the number of IC cards 111 used is obtained.

  The selector 125 selectively switches the control voltages V1 to V3 output from the substrate potential generation circuit 124 according to the selection signals φ1 to φ3 output from the nonvolatile memory 123, and sets the substrate potential of the PMOS transistor 121. It is supposed to be. The selector 125 and the substrate potential generation circuit 124 constitute a substrate potential setting circuit. Note that the control voltage to be selected is not limited to the three stages V1 to V3, but may be two stages or more stages.

(Operation of IC card 111)
In the IC card system configured as described above, power and signals are transmitted and received between the reader / writer 101 and the IC card 111 by an electromagnetic induction method using electromagnetic waves. More specifically, when an electromagnetic wave in which a data signal is superimposed on a carrier wave having a predetermined frequency is transmitted from the reader / writer 101, in the IC card 111, a voltage due to electromagnetic induction is induced at both ends of the coil 112 constituting the resonance circuit. The This voltage is rectified and used as a power supply voltage, and a data signal is extracted and various processes are performed.

  Here, when a plurality of IC cards 111 are stacked and the coils 112 of the IC cards 111 are close to each other, the resonance frequency is reduced by the mutual inductance M due to the coupling relationship of the coils 112, and the coils 112 The induced voltage will decrease. Therefore, in the IC card 111 of this embodiment, depending on whether the IC card 111 is used in advance, for example, only one IC card 111 is used or a predetermined number of IC cards 111 are used in a stacked manner. By storing predetermined data in the nonvolatile memory 123, the capacitance between the source and gate of the PMOS transistor 121 is set, and the resonance frequency is kept constant.

  Hereinafter, a specific operation when the substrate voltage (Vb−Vs) is controlled by the substrate potential control circuit 122 will be described. FIG. 6 is a timing chart showing voltages at various parts of the IC card 111. When an electromagnetic wave emitted from the reader / writer 101 is received by the IC card 111, a coil reception wave Vcoil is generated at both ends of the coil 112. When this is rectified by the rectifying diode 114 and smoothed by the smoothing capacitor 115, the power supply voltage VDD is obtained. More specifically, after the start of reception, the power supply voltage VDD gradually increases until the accumulated charge in the smoothing capacitor 115 reaches a steady state. As the power supply voltage VDD increases, the control voltages V1 to V3 output from the substrate potential generation circuit 124 also gradually increase, and eventually become constant voltages set in advance. (In FIG. 6, the voltages V3 to V1 are drawn so as to reach a steady state in order, but this does not necessarily change depending on the voltage step-up / step-down method. The substrate voltage (Vb−Vs) is assumed to be VDD−about 0.7V (p) if none of the voltages V1 to V3 is selected by the selector 125, for example. Voltage drop due to -n junction).

  For example, when the power supply voltage VDD reaches a predetermined level, or when a predetermined time elapses after the power supply voltage VDD reaches the predetermined level, a memory activation signal is input to the nonvolatile memory 123 from a timer circuit (not shown), The non-volatile memory 123 outputs data in which the selection signal φ1 stored in advance becomes H level in the case of three, for example, in accordance with the number of IC cards 111 used in an overlapping manner. As a result, the voltage V1 is applied to the substrate of the PMOS transistor 121, and the resonance frequency is maintained at a constant frequency that is tuned to the carrier frequency. That is, when three IC cards 111 are used in an overlapping manner, the inductance component increases due to the mutual inductance M compared to a case where only one IC card 111 is used, while a predetermined voltage V1 higher than the voltage V3 is a PMOS. When applied to the substrate of transistor 121, the capacitance of PMOS transistor 121 is reduced and tuned appropriately.

  As described above, the data corresponding to the number of IC cards 111 to be used in an overlapping manner is stored in the nonvolatile memory 123 in advance, so that the resonance capacitance according to the influence of the mutual inductance M when the power is turned on (at the start of reception). And a sufficient power supply voltage can be obtained by reliably tuning to the carrier frequency, and the data signal can be extracted and processed appropriately. Further, the configuration for controlling the resonance frequency by controlling the substrate voltage of the MOS transistor as described above is suitable for a non-contact type IC responder such as the IC card 111 in that the control power can be suppressed to a very small level. Yes.

  In the above example, the PMOS transistor 121 is used as the resonance capacitor. However, the present invention is not limited to this. For example, an NMOS transistor 151 as shown in FIG. 7 may be used. That is, for example, as shown in FIG. 8, on a p-type well 162 formed on an n-type silicon wafer 161, an n-type region 163 serving as a source or drain and a gate electrode disposed via a metal oxide film 164 An NMOS transistor 151 in which a 165 and a p-type region 166 to which a substrate potential control terminal B for controlling the potential of the p-type well 162 is connected can be used. In this case, as shown in FIG. 9, when the substrate voltage (Vb−Vs) <0, even when the gate voltage Vgs2 is the same, the source-gate is higher than the substrate voltage (Vb−Vs) = 0. The capacity C in between decreases from C1 to C2. Therefore, by generating a voltage obtained by reversing the polarity of the power supply voltage VDD in the substrate potential generation circuit 124, the resonance frequency can be controlled by changing the potential of the p-type well 162 as in the above case. A stable operation can be performed without affecting other PMOS transistors 171 and the like formed on the n-type silicon wafer 161 (without changing the threshold value). The n-type well 132 and the p-type well 162 are not limited to being formed in a single layer, but may be formed in multiple layers.

<< Embodiment 2 of the Invention >>
FIG. 10 is a circuit diagram showing a configuration of the substrate potential control circuit 222 in the IC card 211 according to the second embodiment of the present invention. In the following embodiments, components having the same functions as those of the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  The substrate potential control circuit 222 is different from the substrate potential control circuit 122 of the first embodiment (FIG. 5) in that it includes a demodulation circuit 223 and a control register 224 instead of the nonvolatile memory 123. .

  The demodulating circuit 223 extracts a data signal transmitted from the reader / writer 101 and outputs the substrate potential setting data RX to the control register 224 when the substrate potential setting data RX is received. Yes.

  The control register 224 holds the substrate potential setting data RX and outputs it to the selector 125 as selection signals φ1 to φ3.

  In the IC card 211 configured in this way, as shown in FIG. 11, the substrate potential setting data RX is superimposed on a carrier wave and transmitted from the reader / writer 101 according to a predetermined protocol, as in the first embodiment. In addition, the resonance frequency can be controlled by setting the substrate potential of the PMOS transistor 121 to V1 to V3. In other words, the reader / writer 101 can control the resonance frequency and transmit / receive appropriately without setting the IC card 211 according to the usage pattern (the number of stacked sheets) as in the first embodiment. You can make it. In addition, the resonance frequency can be changed by changing the substrate potential any number of times in the communication state. Further, the IC card 211 detects the power supply voltage VDD and transmits it to the reader / writer 101, or the reader / writer 101 detects the degree of tuning according to the degree of electromagnetic induction coupling to control the resonance frequency, It is also possible to automatically obtain an appropriate tuning state.

<< Embodiment 3 of the Invention >>
FIG. 12 is a circuit diagram showing a configuration of the substrate potential control circuit 322 in the IC card 311 according to the third embodiment of the present invention. The substrate potential control circuit 322 differs from the substrate potential control circuit 122 of the first embodiment (FIG. 5) in that it includes a voltage detection circuit 323 and a latch circuit 324 instead of the nonvolatile memory 123. Yes.

  The voltage detection circuit 323 detects the power supply voltage VDD, and outputs a detection signal indicating which level is a plurality of levels.

  The latch circuit 324 outputs, for example, a signal at which the selection signal φ3 becomes H level to the selector 125 at the start of reception, and the latch signal is input when a predetermined time elapses after the power supply voltage VDD reaches a predetermined level. Then, the detection signal output from the voltage detection circuit 323 is held, and a signal in which only one of the selection signals φ1 to φ3 becomes H level according to the detection signal is output. As a result, any one of the control voltages V1 to V3 is applied to the substrate of the PMOS transistor 121, and the resonance frequency is tuned to the carrier frequency.

  That is, for example, the voltage V3 is selected by the selector 125 at the start of reception and applied to the substrate of the PMOS transistor 121, and in this state, the coil 112 of the single IC card 311 and the PMOS transistor 121 are used. When the IC card 311 is placed at a certain distance from the reader / writer 101 having a certain transmission output, the resonance frequency according to the capacity of the card is set to coincide with the carrier frequency. A constant voltage is obtained as the power supply voltage VDD. However, when a plurality of IC cards 311 are placed close to each other, the resonance frequency is reduced by the mutual inductance M as described above, so that the power supply voltage VDD becomes lower than the constant voltage. Therefore, according to the lowered power supply voltage VDD, predetermined voltages V1 and V2 higher than the voltage V3 are applied to the substrate of the PMOS transistor 121, whereby the capacitance of the PMOS transistor 121 is reduced and the resonance frequency is increased. Therefore, tuning is appropriately performed, a sufficient power supply voltage is obtained, and data signals are extracted and processed appropriately.

  Note that the voltage applied to the substrate of the PMOS transistor 121 at the start of reception is not limited to the voltage V3, but may be a constant voltage. The substrate potential depends on the resonance frequency determined by the voltage and the power supply voltage VDD. The voltage generated by the generation circuit 124 may be set.

  As described above, even when a plurality of IC cards 311 overlap, the mutual arrangement relationship (distance etc.) between the reader / writer 101 and the IC card 311 is determined, and the output of the reader / writer 101 is In the case of a predetermined constant value, since the influence of the mutual inductance M can be detected by the power supply voltage VDD, the resonance capacitance cancels the influence of the mutual inductance M when the power is turned on (at the start of reception). Can be set to automatically obtain an appropriate tuning state.

<< Embodiment 4 of the Invention >>
FIG. 13 is a circuit diagram showing a configuration of the substrate potential control circuit 422 in the IC card 411 according to the fourth embodiment of the present invention. The substrate potential control circuit 422 includes a voltage detection circuit 423, an AND circuit 424, and a shift register 425 instead of the nonvolatile memory 123, as compared with the substrate potential control circuit 122 of the first embodiment (FIG. 5). Is different.

The voltage detection circuit 423 outputs an H level detection signal when the power supply voltage VDD is lower than a predetermined reference voltage, that is, a voltage at which the main body of the IC card 411 operates appropriately. (Note that the substrate potential control circuit 422 itself including the voltage detection circuit 423 is configured to operate even at a voltage lower than the voltage at which the main body of the IC card 411 operates appropriately as described in the first embodiment. Yes.)
The AND circuit 424 outputs a clock signal when an H level detection signal is output from the voltage detection circuit 423.

  Each time the clock signal is input from the AND circuit 424, the shift register 425 sequentially sets any one of the selection signals φ1 to φ3 to the H level. Note that the selection signal that becomes H level at the start of reception may not be determined in particular. However, for example, if it is set so as to correspond to the number of IC cards 411 that are used most frequently, transmission / reception starts quickly. The possibility of being made can be increased.

  In the IC card 411 configured as described above, the control voltages V1 to V3 applied to the substrate of the PMOS transistor 121 at a certain point in time do not correspond to the number of IC cards 411 that are actually used in an overlapping manner. When the frequency is shifted and the obtained power supply voltage VDD is lower than a predetermined reference voltage, other control voltages V1 to V3 are sequentially switched and applied to the substrate of the PMOS transistor 121. When the power supply voltage VDD becomes equal to or higher than a predetermined reference voltage, the detection signal output from the voltage detection circuit 423 becomes the L (Low) level, and the shift register 425 outputs the current output state (selection signal φ1 to φ3 is any of the selection signals φ1 to φ3). Is maintained at the H level), the control voltages V1 to V3 applied to the substrate are also maintained, and the tuning state according to the control voltages V1 to V3 is maintained. That is, even when the distance between the reader / writer 101 and the IC card 411 is not constant, or even when the output of the reader / writer 101 does not appear at a predetermined constant value, at least one of the control voltages V1 to V3 is used. If the voltage VDD is obtained, appropriate transmission / reception is automatically performed.

  In the control as described above, accurate tuning is not always performed (the level of the power supply voltage VDD is not necessarily maximized), but the power supply that can operate the main body by any of the control voltages V1 to V3. As long as the voltage VDD is obtained, transmission and reception can be performed appropriately. Further, when the desired power supply voltage VDD cannot be obtained by any of the control voltages V1 to V3 because the distance between the reader / writer 101 and the IC card 411 is too large, for example, from the reader / writer 101 It is only necessary to appropriately transmit / receive by issuing an alarm sound and prompting the IC card 411 to be brought closer to the reader / writer 101 again. Further, when the transmission / reception cannot be performed, it may be simply processed as transmission / reception impossible. Is possible. Therefore, it is possible to automatically tune and transmit / receive with the simple configuration as described above.

<< Embodiment 5 of the Invention >>
An example of an IC card that can automatically tune the resonance frequency almost accurately regardless of the number of IC cards used will be described.

  As shown in FIG. 14, the IC card 511 of the fifth embodiment replaces the substrate potential control circuit 122 of the first embodiment (FIG. 5) with a voltage detection circuit 512, a charge pump circuit 513, and a voltage drop circuit 514. And.

  The voltage detection circuit 512 includes a timing signal generation circuit 512a, capacitive elements 512b and 512c, PMOS transistors 512d to 512f, and an offset comparator 512g. The PMOS transistors 512d to 512f are turned on / off according to the timing signals Vc1 and Vc2 output from the timing signal generation circuit 512a to cause the capacitor 512c to hold the power supply voltage Vd2 at a predetermined time, while the capacitor 512b Thereafter, the power supply voltage Vd1 after a predetermined time has elapsed is held. The offset comparator 512g detects the detection signal when the voltage Vd1 held in the capacitor 512b is higher than the voltage Vd2 held in the capacitor 512c, that is, when the power supply voltage VDD rises with time. While Vn1 is set to L level, in other cases, it is set to H level.

  The charge pump circuit 513 includes a NOT circuit 513a, an AND circuit 513b, a NOT circuit 513c, capacitive elements 513d and 513e, NMOS transistors 513f to 513h, a diode 513i, and a capacitive element 513j, and a voltage obtained by gradually boosting the power supply voltage VDD Is output as the substrate voltage Vb of the PMOS transistor 121. More specifically, the NOT circuit 513a outputs a signal that alternately repeats the H and L levels in accordance with the received signal (before rectification). The AND circuit 513b outputs a signal that alternately repeats the H and L levels according to the output of the NOT circuit 513a when the timing signal Vc2 is at the H level and the detection signal Vn1 of the offset comparator 512g is at the L level. 513c outputs a signal Vp1 obtained by inverting the output of the AND circuit 513b. Therefore, the NMOS transistors 513g and 513h are alternately turned ON / OFF, whereby the voltage boosted by the charge accumulated in the capacitor 513e is held in the capacitor 513j via the diode 513i and output.

  The voltage reduction circuit 514 includes an NMOS transistor 514a, a pull-up resistor 514b, a PMOS transistor 514c, and a current limiting circuit 514d. When the detection signal Vn1 output from the offset comparator 512g is at the H level, the voltage reduction circuit 514 discharges the charge accumulated in the capacitor 513j by turning on the NMOS transistor 514a and the PMOS transistor 514c. The substrate voltage Vb is gradually reduced.

  FIG. 15 is a timing chart showing signals at various parts of the IC card 511 configured as described above. At timing A shown in the figure, the timing signals Vc1 and Vc2 are both at the H level, and the PMOS transistors 512d to 512f are turned off, so that the power supply voltage VDD immediately before is held in the capacitive elements 512b and 512c. During the period of timing B to C, the timing signal Vc1 becomes L level, and only the PMOS transistor 512d is turned on, and the power supply voltage Vd1 at each time point is applied to the capacitor 512b. Therefore, if the voltage Vd1 is higher than the voltage Vd2, the detection signal Vn1 output from the offset comparator 512g becomes L level, and the signal Vp1 output from the NOT circuit 513c alternately repeats H and L levels, and the substrate The voltage Vb gradually increases. On the other hand, if the voltage Vd1 is equal to or lower than the voltage Vd2, the detection signal Vn1 output from the offset comparator 512g becomes H level, the NMOS transistor 514a and the PMOS transistor 514c are turned on, and the substrate voltage Vb gradually decreases.

  As described above, when the power supply voltage VDD is increasing, the substrate voltage is gradually increased by the charge pump circuit 513, while when the power supply voltage VDD is not changing or decreasing, the substrate voltage is gradually increased. Can be controlled so that the power supply voltage VDD becomes almost maximum regardless of the number of IC cards 511 used (theoretically, the power supply voltage VDD is held in the capacitor elements 512b and 512c). If the time difference is reduced indefinitely, the substrate voltage Vb can be continuously changed to accurately maximize the power supply voltage VDD.) Such an IC card 511 has a slightly larger circuit scale than the IC card 411 of the fourth embodiment, but it is sufficient to be tuned to such an extent that the necessary power supply voltage VDD can be obtained. High tuning accuracy and response performance are not required. Therefore, it is possible to easily perform necessary and sufficient tuning control with a relatively simple circuit.

  If a sufficiently high voltage is applied to the substrate in the initial state, when the power supply voltage VDD is decreasing, the substrate voltage is gradually increased by the charge pump circuit 513 while the power supply voltage VDD does not change. When the voltage is increasing, the substrate voltage may be gradually decreased. However, normally, if no voltage is applied to the substrate from the outside, the substrate voltage becomes VDD−about 0.7V. It is easier to configure to increase the substrate voltage when the voltage VDD is increasing.

Embodiment 6 of the Invention
FIG. 16 is a circuit diagram showing a configuration of an IC card 611 according to Embodiment 3 of the present invention. The IC card 611 includes a variable resistance 621 and a resistance value control circuit 622 connected in series with the PMOS transistor 121 in place of the capacitance control resonance capacitor 113 in the IC card 111 of the first embodiment. A resonance capacitor 613 is provided. Specifically, the variable resistor 621 is, for example, a p-type or n-type MOS transistor whose resistance value R changes when a gate voltage as a control voltage is controlled by a resistance value control circuit 622. Further, the resistance value control circuit 622 has the same configuration as the substrate potential control circuit 122 or the substrate potential control circuit 222 in the second embodiment (FIG. 10), etc., and is supplied from the power supply voltage VDD or the reader / writer 101. A predetermined control voltage is applied to the variable resistor 621 based on the setting data. The variable resistor 621 may be connected in parallel with the PMOS transistor 121, but the power consumption can be reduced by connecting in series as described above.

  As described above, when the substrate voltage (Vb−Vs) of the PMOS transistor 121 is controlled and the resistance value R of the variable resistor 621 is controlled, the combined capacitance of the PMOS transistor 121 and the variable resistor 621 is controlled. Is as shown in FIG.

  That is, for example, when the resistance value R of the variable resistor 621 is 0 and the substrate voltage (Vb−Vs) = 0 (broken line in FIG. 17), as described in the first embodiment (FIG. 4), As the gate voltage (Vg−Vs) decreases, the capacitance C changes (increases) from 0 to C1. In contrast, when the resistance value R of the variable resistor 621 increases to a predetermined resistance value and the substrate voltage (Vb−Vs)> 0 (solid line in FIG. 17), the threshold value Vtp1 shifts to Vtp3, and the gate voltage As (Vg−Vs) becomes lower than the threshold value Vtp3, the capacitance C increases with a gentler slope as the resistance value R increases. Therefore, for example, assuming that the gate voltage (Vg−Vs) is Vgs3 shown in the figure, the substrate voltage (Vb−Vs) = 0 is changed to the substrate voltage (Vb−Vs)> 0 and the resistance value R is increased. As a result, the source-gate capacitance C can be reduced from C1 to C3. Therefore, as in the case of the first embodiment, when a plurality of IC cards 611 are close to each other and the resonance frequency is lowered, the resonance voltage is controlled by controlling the substrate voltage (Vb−Vs) and the resistance value R. By making it small, the resonance capacity can be finely adjusted stepwise or continuously, and can be tuned to the carrier frequency to obtain a stable power and data signal.

  In the sixth embodiment, an NMOS transistor 151 as shown in FIG. 18 is used in place of the PMOS transistor 121, and the resonance frequency is controlled by utilizing the characteristic that the capacitance changes as shown in FIG. You may do it.

  In the non-contact type IC responder according to the present invention, since the resonance frequency is set by controlling the substrate potential of the MOS transistor, a plurality of IC responders are arranged close to each other without causing a significant increase in circuit scale. The resonance frequency can be set appropriately even when the signal is received, and it has the effect of being able to be surely tuned to the carrier wave frequency. The present invention relates to a non-contact type IC responder called a non-contact type IC card or IC tag that performs data communication in a non-contact manner, and is particularly useful as a technique for adjusting a resonance frequency.

It is a circuit diagram which shows schematic structure of the card system using the IC card of Embodiment 1. FIG. 2 is a circuit diagram showing a specific configuration of a capacitance control resonance capacitor 113. FIG. 2 is a sectional view showing the structure of a PMOS transistor 121. FIG. 4 is a graph showing the characteristics of a PMOS transistor 121. FIG. 2 is a circuit diagram showing a detailed configuration of the substrate potential control circuit 122. FIG. 3 is a timing chart showing voltages of respective parts of the IC card 111. FIG. 6 is an explanatory diagram illustrating an NMOS transistor 151 according to a modification of the first embodiment. FIG. 2 is a sectional view showing the structure of an NMOS transistor 151. FIG. 3 is a graph showing characteristics of the NMOS transistor 151. FIG. It is a circuit diagram which shows the structure of the IC card 211 of Embodiment 2. 3 is a timing chart showing voltages of respective parts of the IC card 211. FIG. 6 is a circuit diagram showing a configuration of an IC card 311 of Embodiment 3. FIG. FIG. 6 is a circuit diagram illustrating a configuration of an IC card 411 according to a fourth embodiment. FIG. 10 is a circuit diagram illustrating a configuration of an IC card 511 according to a fifth embodiment. 3 is a timing chart showing signals of respective units. FIG. 10 is a circuit diagram illustrating a configuration of an IC card 611 according to a sixth embodiment. 4 is a graph showing the characteristics of a PMOS transistor 121 and a variable resistor 621. 10 is an explanatory diagram illustrating an NMOS transistor 151 and a variable resistor 621 according to a modification of the third embodiment. 4 is a graph showing characteristics of an NMOS transistor 151 and a variable resistor 621. FIG. It is a circuit diagram which shows schematic structure of the card system using the conventional IC card. It is a graph which shows the relationship between a receiving frequency and the voltage of both ends of a coil. It is a circuit diagram which shows the state where several IC card is adjoining.

Explanation of symbols

101 Reader / Writer 102 Transmitter 103 Receiver 104 Coil 105 Resonance Capacitor 111 IC Card 112 Coil 113 Capacitance Control Resonance Capacitor 114 Rectifier Diode 115 Smoothing Capacitor 116 LSI Load Resistor 121 PMOS Transistor 122 Substrate Potential Control Circuit 123 Nonvolatile Memory 124 substrate potential generation circuit 125 selector 131 p-type silicon wafer 132 n-type well 133 p-type region 134 metal oxide film 135 gate electrode 136 n-type region 141 NMOS transistor 151 NMOS transistor 161 n-type silicon wafer 162 p-type well 163 n-type region 164 Metal oxide film 165 Gate electrode 166 P-type region 171 PMOS transistor 211 IC card 222 Substrate potential control circuit 223 Demodulation circuit 22 Control register 311 IC card 322 Substrate potential control circuit 323 Voltage detection circuit 324 Latch circuit 411 IC card 422 Substrate potential control circuit 423 Voltage detection circuit 424 AND circuit 425 Shift register 511 IC card 512 Voltage detection circuit 512a Timing signal generation circuit 512b / 512c Capacitance elements 512d to 512f PMOS transistor 512g Offset comparator 513 Charge pump circuit 513a NOT circuit 513b AND circuit 513c NOT circuit 513d and 513e Capacitance elements 513f to 513h NMOS transistor 513i Diode 513j Capacitance element 514c Voltage drop circuit 514b PMOS transistor 514d current limiting circuit 11 IC card 613 capacity control resonant capacitor 621 a variable resistor 622 resistance control circuit

Claims (11)

A non-contact IC responder that performs data communication with an interrogator via electromagnetic waves,
A resonant circuit having a MOS element that forms a capacitive element between the gate and the source and drain connected to each other and has a variable substrate potential;
A control circuit for controlling the substrate potential of the MOS transistor;
A non-contact type IC transponder comprising: The non-contact IC responder according to claim 1, wherein
The resonance circuit further includes a variable resistor connected in series with the MOS transistor and having a resistance value controlled according to a given potential.
The non-contact type IC responder, wherein the control circuit is further configured to control a resistance value of the variable resistor. A non-contact type IC responder according to any one of claims 1 and 2,
The control circuit is
A non-volatile memory that outputs a control signal for controlling at least one of the substrate potential of the MOS transistor and the resistance value of the variable resistor;
In accordance with the control signal, a potential setting circuit that selects any one of a plurality of predetermined potentials and applies the selected potential to the substrate of the MOS transistor or the variable resistor;
A non-contact type IC transponder comprising: A non-contact type IC responder according to any one of claims 1 and 2,
The control circuit is
A demodulation circuit that demodulates the signal received by the resonance circuit and outputs a demodulated signal;
A potential setting circuit that selects any one of a plurality of predetermined potentials according to the demodulated signal, and applies the selected potential to at least one of the substrate of the MOS transistor and the variable resistor;
A non-contact type IC transponder comprising: A non-contact IC responder according to any one of claims 3 and 4,
The predetermined plural types of potentials are each one or more corresponding to the potential corresponding to one non-contact type IC responder and the number of one or more types of non-contact type IC responders that are close to each other in a predetermined proximity state. A non-contact type IC transponder characterized by being two or more of the potentials. A non-contact type IC responder according to any one of claims 1 and 2,
The control circuit is
A non-contact type IC transponder configured to control at least one of a substrate potential of the MOS transistor and the variable resistance in accordance with a voltage generated by the resonance circuit. The non-contact IC responder according to claim 6, wherein
In accordance with a voltage generated by the resonance circuit in a state where a predetermined potential is applied to at least one of the substrate of the MOS transistor and the variable resistor, the control circuit is configured such that the substrate of the MOS transistor or A non-contact type IC transponder configured to switch a potential applied to the variable resistor. The non-contact IC responder according to claim 7, wherein
The control circuit is configured to sequentially switch a potential applied to the substrate or the variable resistor of the MOS transistor when a voltage generated by the resonance circuit is equal to or lower than a predetermined voltage. Contact IC transponder. The non-contact IC responder according to claim 6, wherein
The control circuit is configured to control a potential applied to at least one of the substrate and the variable resistor in accordance with a change in voltage generated by the resonance circuit before and after a predetermined time elapses. A non-contact IC responder characterized by the above. The contactless IC transponder of claim 9, wherein
The control circuit is
A detection circuit for detecting a temporal change in voltage generated by the resonance circuit;
A charge pump circuit that boosts the voltage generated by the resonant circuit and applies the boosted voltage to the substrate;
A non-contact IC responder configured to operate the charge pump circuit when a voltage generated by the resonance circuit is increased. The non-contact IC responder according to claim 1, wherein
The MOS transistor is a PMOS transistor further formed on an n-type well formed on at least a p-type semiconductor wafer, or an NMOS transistor further formed on a p-type well formed on at least an n-type semiconductor wafer. There is a non-contact type IC responder characterized by being.

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