JP2005191437A - Semiconductor device, manufacturing method therefor, and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having an organic semiconductor layer which suppresses gate leak currents to show a large ON/OFF ratio. <P>SOLUTION: The semiconductor device comprises an insulating board 11, a gate electrode 12 that is formed selectively on the insulating board 11, a gate insulating film 13 that covers the surface of the insulating board 11 and the gate electrode 12, one source electrode 15 and one drain electrode 15 which are arranged on the gate insulating film 13 to be separated from each other across a prescribed channel length in the length direction of the gate, and the organic semiconductor layer 16 that covers the source/drain electrodes 15, 15. The gate insulating film 13 is made of a porous material layer with a number of pores which has a basic substance of a metal oxide. The area of the interface between the gate insulating film 13 and the organic semiconductor layer 16 is increased to increase the virtual gate capacity of the semiconductor device. In manufacturing the porous material layer, a film is formed first, using a sol solution dispersed with an interface activator, and then the activator is eliminated by heating or the like to form pores on the film. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device including a semiconductor layer made of an organic material, a manufacturing method thereof, and a display device.

  In recent years, research has been actively conducted to form an organic transistor using an organic semiconductor material as a channel generation layer on a substrate by an inexpensive process such as a printing method, and to realize a lightweight, flexible, thin, and inexpensive electronic device using the organic transistor. It has become. For example, Durli et al. Fabricated an organic transistor using organic materials for the gate insulating film, semiconductor layer, and electrode on a polymer film (CJ Drury, CMJ Mutsaers, CM Hart, M. Matters). , DM de Leeuw, Appl. Phys. Lett. Vol.73, p108 (1998).). Bao et al. Screen-printed a gate insulating film made of low-temperature fired polyimide, a polymer semiconductor channel layer made of polythiophene, and an electrode layer made of conductive ink on a polyethylene terephthalate substrate on which an ITO electrode was formed. An organic transistor is formed (Z. Bao, Y. Feng, A. Dodabalapur, VR Raju, AJ Lovinger, Chem. Mater., Vol. 9, p1299 (1997)).

  In recent years, studies have been made to apply organic transistors to switching elements such as liquid crystal elements, organic electroluminescent elements (organic EL elements), and electrophoretic elements. In this case, the on / off ratio of the drain current is high, that is, the off-current (current flowing between the source and the drain when the gate voltage is 0 V) is small, and the on-current (the source when the voltage is applied to the gate electrode). -A large current between the drains) is required for improving the contrast ratio and speeding up the response.

The drain current on / off ratio is the ratio of the drain on current (Ion) that flows between the source and the drain when the gate voltage is applied to the drain on current (Ioff) that flows when the gate voltage is 0V. As a guide when using as. Brown et al (AR Brown, CP Jarrett, DM de Leeuw, M. Matters, Synthetic Metals, VOL88, p37 (1997)) , the estimated carrier concentration N _A caused by doping, field effect mobility from the value for the on / off ratio The relationship between the degree μ and the conductivity σ of the organic semiconductor layer was investigated. According to this, in an organic transistor having a high doping level, it is represented by the following formula (1):
Ion / Ioff = 1 + (μC ₀ V _G / 2dσ) (1)
An organic semiconductor having a low doping level is represented by the following formula (2).
^{_{Ion / Ioff = μC 0 2 V}} G 2 / qN A d 2 σ ... (2)
Here, C ₀ is the capacitance per unit area of the gate insulating film, V _G is the gate voltage, q is the carrier charge, and d is the thickness of the organic semiconductor layer.

In order to obtain a large on / off ratio in the organic transistor from the formulas (1) and (2), 1. Use a material with high mobility. Suppressing the carrier concentration N _A, 3. 3. Use a gate insulating film having a high gate capacitance C ₀ per unit area. It is expected that methods such as reducing the thickness of the organic semiconductor layer are effective.

Here, since there is the following relational expression (3) that the gate capacitance C ₀ per unit area is proportional to the relative dielectric constant ε _r of the insulating film, C ₀ can be obtained by using a material having a large relative dielectric constant ε _r. An approach to improve
C ₀ ∝ε _r ε ₀ S (3)
Here, ε ₀ is the dielectric constant of vacuum, and S is the surface area of the electrode.

  Examples using this approach include: By depositing barium zirconate titanate, which is an inorganic material, on the gate insulating film by sputtering, a gate insulating film having a relative dielectric constant of 17.3 is formed, and an organic transistor having a gate voltage of about 5 V is formed ( (Refer nonpatent literature 1.). On the other hand, a gate insulating film having a relative dielectric constant of 16 is formed by forming a barium strontium titanate film by a sol-gel method using hydrolysis of alcoholate as a low-temperature fabrication process without using a sputtering method. An organic transistor having a gate voltage of about 5 V is manufactured (see Non-Patent Document 2). However, high-temperature annealing exceeding 400 ° C. is required to form a high-dielectric-constant composite oxide thin film with good crystallinity by the sol-gel method, which causes thermal damage to organic semiconductor materials and plastic substrates. There's a problem.

On the other hand, it has been proposed to use an organic material having a relatively large dielectric constant for the insulating film. For example, an organic transistor using an insulating polymer having a cyano group in a gate insulating film, cyanoethyl pullulan (relative permittivity 18.5), polyvinyl alcohol (relative permittivity 7.8), or the like has been proposed (Patent Literature). See 1 and 2.). In addition, a method of dispersing high dielectric constant inorganic compound particles in an organic amorphous insulator has been proposed (see Patent Document 3).
JP-A-8-191162 Japanese National Patent Publication No. 5-508745 JP 2002-110999 A JP-A-4-199638 CD Dimitrakopoulos, S. Purushothaman, J. Kymissis, AC allegari, JM Shaw, Science, vol.283, p822 (1999) CD Dimitrakopoulos, I. Kymissis, S. Purushothaman, DA Neumayer, PR Duncombe, RB Laibowitz, Adv. Mater., Vol.11, p1372 (1999))

  However, when a gate insulating film is formed using an organic material having a high dielectric constant alone, there is a problem that the gate leakage current is large, and as a result, the on / off ratio of the drain current cannot be increased. Here, the reason why the gate leakage current is increased is considered to be due to the high conductivity of the gate insulating film because a material having a large relative dielectric constant is used for the gate insulating film.

  It is generally known that there is a proportional relationship between the dielectric constant and conductivity of an insulating material (Sho Saito, Polymer, Vol. 17, p672 (1968)). That is, a material having a large relative dielectric constant has a high conductivity and can easily pass a current. Here, such a relationship is considered to be due to ionic impurities contained in the material. The work required to create an ionic substance from a pair of molecules bonded by Coulomb force is related to the relative dielectric constant of the medium that affects the Coulomb force. That is, in a medium having a large relative dielectric constant, the Coulomb force is small, and thermal dissociation easily occurs easily, resulting in an increase in conductivity.

  In organic materials, particularly polymer materials, it is very difficult to remove ionic impurities during the synthesis process. Sources of main ionic impurities include impurities in the raw material monomers, mixed catalyst residues in the polymerization and condensation polymerization processes, various compounding agents in the heat molding process, moisture absorption, polymer decomposition and dissociation, and the like.

  Therefore, in the approach of increasing the relative dielectric constant of the gate insulating film, as described above, the conductivity increases, and accordingly, the gate leakage current increases, and as a result, it is difficult to increase the on / off ratio. There is a problem that it is.

  Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device including an organic semiconductor layer that suppresses gate leakage current and has a large on / off ratio, a manufacturing method thereof, and an electronic device. Is to provide a device.

  The gate electrode, the organic semiconductor layer, the gate insulating film formed between the gate electrode and the semiconductor layer, and the gate electrode opposite to the gate electrode through the gate insulating film There is provided a semiconductor device comprising two source / drain electrodes spaced apart on the side, wherein the gate insulating film is composed of a porous layer in which pores are formed.

  According to the first aspect of the present invention, since the gate insulating film is made of the porous layer, the contact area between the gate insulating film and the semiconductor layer made of an organic material is significantly increased as compared with the case where the gate insulating film is a continuous body. Therefore, the gate capacitance can be increased, and the number of carriers stored at the gate insulating film / semiconductor layer interface can be increased with a lower gate voltage than in the prior art. In addition, since the gate insulating film / semiconductor layer interface has a curved shape, the effective gate length increases, the total number of fixed charges is small because the number of molecules contained in the porous body layer is small, and Effects such as improvement of insulation by air in the material layer work synergistically, and gate leakage current and source-drain leakage current can be suppressed. As a result, the drain-on current value (Ion) flowing between the source and the drain is increased and the drain-off current is suppressed, so that a semiconductor device having a large on / off ratio can be realized.

  According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the gate insulating film is formed on the porous body layer formed on the semiconductor layer side, and on the gate electrode side. The insulating film is made of a material different from the material.

  According to the invention described in claim 2, the gate insulating film is made of a laminate of an insulating film and a porous body layer made of a material different from the porous body layer, so that the effect of the porous body layer / semiconductor layer interface can be reduced. In addition, by using, for example, a material having a high relative dielectric constant for the insulating film, the relative dielectric constant of the entire gate insulating film can be improved and gate leakage current can be suppressed. In addition, adhesion can be improved by providing an insulating film between the gate electrode and the porous body layer.

  According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the source / drain electrodes may be formed on the surface of the gate insulating film on the semiconductor layer side and covered with the semiconductor layer. As described in 4, the source / drain electrodes may be formed on the surface of the semiconductor layer opposite to the gate insulating film.

  As described in claim 5, in the semiconductor device according to any one of claims 1 to 4, the porous body layer is made of a metal oxide in which a large number of the pores are formed.

  According to the invention described in claim 5, since the porous body layer is formed of a metal oxide, it is excellent in chemical resistance, oxidation resistance, and mechanical strength as compared with, for example, a polymer compound.

  As described in claim 6, in the semiconductor device according to claim 5, the metal oxide is silicon oxide.

  According to the invention described in claim 6, silicon oxide is excellent in chemical stability and can improve the long-term reliability of the semiconductor device.

  As described in claim 7, in the semiconductor device according to any one of claims 1 to 6, the average pore diameter of the pores is set in a range of 1 nm to 100 nm.

  According to the invention described in claim 7, by setting the average pore diameter within this range, both the mechanical strength and the controllability of the number average pore diameter of the pores can be achieved.

  As described in claim 8, in the semiconductor device according to any one of claims 1 to 7, the volume ratio of pores in the porous body layer is based on the volume of the porous body layer. It is set in the range of 20% or more and less than 80%.

  According to the eighth aspect of the invention, by setting the volume ratio of the pores within this range, it is possible to have an appropriate mechanical strength and further increase the on / off ratio.

  As described in claim 9, in the semiconductor device according to any one of claims 1 to 8, the thickness of the porous body layer is set in a range of 1 nm to 1000 nm.

  According to the invention described in claim 9, by setting the thickness of the porous body layer within this range, the thickness of the carrier formed in the vicinity of the porous body layer of the semiconductor layer is effectively included. be able to.

  As described in claim 10, in the semiconductor device according to any one of claims 1 to 9, the surface of the pore is covered with a hydrophobic material.

  According to the invention described in claim 10, by covering the surface of the pores with a hydrophobic material such as 1,1,1,3,3,3-hexamethyldisilazane, the porous body layer The occurrence of cracks can be prevented, and the homogeneity of the porous body layer and the macroscopic flatness of the surface can be improved.

  The semiconductor device according to any one of claims 1 to 10, wherein the insulating substrate, a gate electrode formed on the insulating substrate, and the gate electrode are covered. A gate insulating film; two source / drain electrodes formed on the gate insulating film apart from each other; and a semiconductor layer made of an organic material covering the surface of the gate insulating film and the two source / drain electrodes.

  According to the eleventh aspect of the present invention, since the semiconductor layer made of an organic substance is located at the uppermost part, either a dry process or a wet process is used for patterning the gate electrode, the source / drain electrode, and the gate insulating film. However, since the semiconductor layer is not exposed to the ions, radicals, or solvent used, deterioration of the semiconductor layer can be prevented.

  The semiconductor device according to any one of claims 1 to 10, wherein the insulating substrate, a gate electrode formed on the insulating substrate, and the gate electrode are covered. A gate insulating film; a semiconductor layer made of an organic material covering the gate insulating film; and two source / drain electrodes formed separately on the semiconductor layer.

  According to the twelfth aspect of the invention, since the source / drain electrodes are formed on the semiconductor layer, the semiconductor layer can be formed uniformly without being disturbed by the uneven shape of the source / drain electrodes.

  The semiconductor device according to any one of claims 1 to 10, wherein the insulating substrate and two source / drain electrodes formed on the insulating substrate are separated from each other. A semiconductor layer made of an organic material covering the two source / drain electrodes, the gate insulating film covering the semiconductor layer, and a gate electrode formed on the gate insulating film.

  According to the thirteenth aspect of the present invention, since the semiconductor layer made of an organic material is formed on the source / drain electrode, and the semiconductor layer is covered with the gate insulating film, the source / drain electrode and the gate electrode are patterned. Since the semiconductor layer is not exposed to the solvent used at the time, deterioration of the semiconductor layer can be prevented.

  The semiconductor device according to any one of claims 1 to 10, wherein the insulating substrate, the semiconductor layer formed on the insulating substrate, and the semiconductor layer are spaced apart from each other. Two source / drain electrodes formed in this manner, the gate insulating film covering the semiconductor layer and the two source / drain electrodes, and a gate electrode formed on the gate insulating film.

  According to the fourteenth aspect of the present invention, since the source / drain electrodes are formed on the semiconductor layer, the semiconductor layer can be formed uniformly without being disturbed by the uneven shape of the source / drain electrodes.

  According to a fifteenth aspect of the present invention, an image element unit and the semiconductor device according to any one of the first to fourteenth aspects are arranged, and the semiconductor device is selectively turned on or off to be in the element unit. There is provided a display device including an image element unit driving unit that applies an electric field or injects carriers into the element unit to control optical properties of the image element unit.

  According to the invention described in claim 15, since the semiconductor device according to any one of claims 1 to 13 has a large on / off ratio and high durability, the display device has high display performance. Contrast ratio and long-term reliability.

  17. A method of manufacturing a field effect type semiconductor device comprising a semiconductor layer made of an organic substance as claimed in claim 16, comprising a step of forming a gate insulating film made of a porous layer, wherein the gate insulating film forming step Preparing a porous precursor solution containing a surfactant, applying the porous precursor solution, drying to form a porous precursor film, and heating the porous precursor film And removing the surfactant. A method for manufacturing a semiconductor device is provided.

  According to the invention described in claim 16, the surfactant is dispersed in the porous precursor solution to form micelles, and the surfactant is removed after the porous precursor film is formed, so that the shape and the pore diameter can be reduced. A porous gate insulating film having uniform pores can be formed.

  17. The method of manufacturing a semiconductor device according to claim 16, wherein the step of preparing the porous precursor solution includes hydrolyzing the metal alkoxide to which the surfactant is added under an acidic condition. Turn into.

  According to the invention described in claim 17, the metal alkoxide is hydrolyzed under acidic conditions to form a sol solution, and micelles having good uniformity in the shape and diameter of the surfactant are formed in the sol solution. be able to.

  According to claim 18, in the method of manufacturing a semiconductor device according to claim 16 or 17, the step of removing the surfactant is performed at a temperature selected from a range of 200 ° C to 700 ° C.

  According to the eighteenth aspect of the present invention, the surfactant can be efficiently decomposed and removed by setting to such a heating temperature range.

  According to a nineteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the sixteenth or seventeenth aspect, the step of removing the surfactant includes a process of eluting and removing the porous precursor film with a solvent.

  According to the invention described in claim 19, since the surfactant can be removed by a low temperature process, the porous body layer itself, the electrode or the semiconductor constituting the semiconductor device formed before the porous body layer Thermal damage to the layer or the like can be suppressed.

  20. The method of manufacturing a semiconductor device according to claim 16, wherein the step of removing the surfactant from the porous precursor film is performed by removing the porous precursor film from an ozone or oxygen atmosphere. Including performing a plasma treatment therein.

  According to the twentieth aspect of the present invention, it is possible to efficiently remove the surfactant while suppressing thermal damage to the porous body layer itself.

  The method of manufacturing a semiconductor device according to any one of claims 16 to 20, wherein the step of preparing the porous precursor solution includes a metal alkoxide to which the surfactant is added. Further, a hydrophobizing agent is added.

  According to a twenty-second aspect of the present invention, in the semiconductor device manufacturing method according to any one of the sixteenth to twentieth aspects, the method further includes a step of performing a hydrophobizing treatment after the step of removing the surfactant.

  According to the invention described in claims 21 and 22, a hydrophobic treatment agent is added to the porous precursor solution, or cracks are prevented from being generated in the porous body layer due to the hydrophobic treatment of the pores. The homogeneity of the material layer and the macroscopic flatness of the surface can be improved.

  According to the present invention, by making the gate insulating film a porous body layer, the contact area between the gate insulating film and the semiconductor layer made of an organic material is increased to increase the gate capacitance, and as a result, flows between the source and the drain. The drain on-current value increases. Further, the gate leakage current and the source / drain leakage current can be suppressed and the drain-off current can be suppressed by the effect of improving the insulating property of the gate insulating film. As a result, it is possible to realize a semiconductor device that suppresses gate leakage current and has a large on / off ratio.

  Embodiments will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view of a semiconductor device according to the first embodiment of the present invention. Referring to FIG. 1, a semiconductor device 10 according to the present embodiment includes an insulating substrate 11, a gate electrode 12 selectively formed on the insulating substrate 11, a surface of the insulating substrate 11, and the gate electrode 12. A gate insulating film 13 made of a porous layer covering; two source / drain electrodes 15 arranged on the gate insulating film 13 with a predetermined distance apart in the gate length direction; and a surface of the gate insulating film 13 And an organic semiconductor layer 16 covering the source / drain electrode 15. In this embodiment, since the gate insulating film 13 is composed of a porous layer, the same reference numeral (13) is used for the gate insulating film and the porous layer.

  In the semiconductor device 10, since the gate insulating film 13 is composed of a porous body layer in which a large number of pores are formed, the area of the interface 13 a between the gate insulating film 13 and the organic semiconductor layer 16 increases, and a substantial gate is formed. Capacity increases. Therefore, the drain-on current flowing between the two source / drain electrodes 15 with a low gate voltage can be increased. On the other hand, the interface 13a of the gate insulating film 13 / organic semiconductor layer 16 has a curved surface shape, the effective gate length increases, and the total number of fixed charges is small because the number of molecules contained in the porous body layer 13 is small. The gate leakage current and the leakage current between the source and the drain are suppressed by a synergistic effect that the insulating property is improved by the air in the porous body layer 13. Accordingly, the drain-off current is suppressed. As a result, the gate leakage current is suppressed, the drain current is increased, and the on / off ratio is increased. Hereinafter, the semiconductor device 10 will be specifically described.

  The insulating substrate 11 is not particularly limited, such as an insulating plastic substrate, a glass substrate, a semiconductor substrate, and a ceramic substrate. However, in the case of providing flexibility to an electronic device to which the semiconductor device 10 of the present embodiment is applied. A plastic substrate is preferable, and a polyimide substrate is particularly preferable from the viewpoint of heat resistance and moisture resistance.

  For example, the gate electrode 12 has a length of 1 μm to 1000 μm in the gate length direction, a length of 5 μm to 4000 μm in the gate width direction, and a film thickness of 10 nm to 200 nm. The source / drain electrodes 15 have, for example, a length of 1 μm to 1000 μm in the gate length direction, a length of 5 μm to 4000 μm in the gate width direction, and a thickness of 10 nm to 200 nm so as to face the gate electrode 12 on the gate insulating film 13. . The gap in the gate length direction of the two source / drain electrodes 15 is set in the range of 0.01 μm to 1000 μm.

  The material of the gate electrode 12 and the source / drain electrode 15 is not particularly limited as long as it is a conductive material. For example, platinum, gold, silver, nickel, chromium, copper, iron, tin, antimony, lead, tantalum, indium, Palladium, tellurium, rhenium, iridium, aluminum, ruthenium, germanium, molybdenum, tungsten, tin / antimony oxide, indium / tin oxide (ITO), indium / zinc oxide (IZO), fluorine-doped zinc oxide, zinc, carbon, graphite Glassy carbon, silver paste and carbon paste, lithium, beryllium, sodium, magnesium, potassium, calcium, scandium, titanium, manganese, zirconium, gallium, niobium, sodium, sodium-potassium alloy, magnesium Lithium, magnesium / copper mixture, a magnesium / silver mixture, a magnesium / aluminum mixture, magnesium / indium mixture, aluminum / aluminum oxide mixture, can be used lithium / aluminum mixture, or a laminated body. Of these, platinum, gold, silver, copper, aluminum, indium, ITO, IZO, and carbon are preferable in terms of stability in the air.

  In addition, known conductive polymers whose conductivity has been improved by doping, such as conductive polyaniline, conductive polypyrrole, conductive polythiophene, and a complex of polyethylenedioxythiophene and polystyrene sulfonic acid are conductive and stable in the atmosphere. From the viewpoint of the properties, two or more of these materials may be used in combination. Furthermore, carbon materials such as conductive carbon black, carbon nanotube, and fullerene (C60, C70) can be used.

  Further, a heat-fused body of conductive fine particles can be used. Examples of the conductive fine particles include fine metal particles such as platinum, gold, silver, copper, cobalt, chromium, iridium, nickel, palladium, molybdenum, and tungsten having an average particle diameter (diameter) of 1 to 50 nm, preferably 1 to 10 nm. It is done.

  In order to reduce the energy barrier at the interface between the source / drain electrode 15 and the organic semiconductor layer 16, it is preferable to use a material capable of forming an ohmic contact as the material of the source / drain electrode 15. In order to form an ohmic contact, when a p-type semiconductor whose carriers are holes is used for the organic semiconductor layer 16, it is preferable that the work function of the source / drain electrode 15 is larger than the work function of the organic semiconductor layer 16. . For example, the material of the source / drain electrode 15 may be polyaniline when poly (3-hexylthiophene) is used for the organic semiconductor layer 16, and gold when pentacene is used.

  In addition, when an n-type semiconductor whose carriers are electrons is used for the organic semiconductor layer 16, it is preferable that the work function of the organic semiconductor layer 16 is smaller. For example, the material of the source / drain electrode 15 may be aluminum when fluorinated copper phthalocyanine is used for the organic semiconductor layer 16, and lithium fluoride when C60 is used.

  It should be noted that the combination of the source / drain electrode 15 material and the organic semiconductor layer 16 material is specifically determined by examining current-voltage characteristics to determine whether or not the electrical resistance becomes smaller at the contact surface with the organic semiconductor layer 16. The

  As a method for forming the gate electrode 12 and the source / drain electrode 15, a pattern of these electrodes is formed using a known photolithography method or a lift-off method, and the conductive material is patterned by a vapor deposition method or a sputtering method. An electrode may be formed by a method of forming a conductive film, or by forming a resist pattern on a metal foil such as aluminum or copper by thermal transfer or ink jet. Alternatively, the electrode may be formed by directly jetting a solution or dispersion of a conductive polymer or a conductive fine particle dispersion with an ink jet apparatus, or a conductive ink or conductive material containing carbon black, a conductive polymer, or conductive fine particles. A coating film coated with a paste or the like may be formed by patterning using a lithography method or a laser ablation method, and the conductive ink or conductive paste is patterned by a printing method such as relief printing, intaglio printing, planographic printing, or screen printing. An electrode may be formed.

  The thickness of the organic semiconductor layer 16 is not particularly limited, but the characteristics of the transistor are often greatly influenced by the thickness of the active layer formed in the organic semiconductor layer 16. Is set to be larger than the film thickness of the active layer. The film thickness of the organic semiconductor layer 16 varies depending on the organic semiconductor material, but is preferably 1 μm or less, and particularly preferably 5 nm to 300 nm.

  As a material of the organic semiconductor layer 16, a π-electron conjugated aromatic compound, a chain compound, an organic pigment, an organic silicon compound, or the like can be used. Specifically, polypyrroles such as polypyrrole, poly (N-substituted pyrrole), poly (3-substituted pyrrole), poly (3,4-disubstituted pyrrole), polythiophene, poly (3-substituted thiophene), poly ( 3,4-disubstituted thiophene), polythiophenes such as polybenzothiophene, polyisothianaphthenes such as polyisothianaphthene, polychenylene vinylenes such as polychenylene vinylene, poly (p-phenylene vinylene), etc. Poly (p-phenylene vinylene) s, polyaniline, poly (N-substituted aniline), poly (3-substituted aniline), poly (aniline) such as poly (2,3-substituted aniline), polyacetylenes such as polyacetylene, polydiacetylene, etc. Of polydiacetylenes, polyazulenes such as polyazulene, polypyrene Which polypyrenes, polycarbazoles such as polycarbazole and poly (N-substituted carbazole), polyselenophenes such as polyselenophene, polyfurans such as polyfuran and polybenzofuran, poly (p-phenylene) such as poly (p-phenylene) -Phenylene), polyindoles such as polyindole, polypyridazines such as polypyridazine, naphthacene, pentacene, hexacene, heptacene, dibenzopentacene, tetrabenzopentacene, pyrene, dibenzopyrene, chrysene, perylene, coronene, terylene, ovalene , Derivatives of polyacenes such as quaterylene and circumanthracene, and polyacenes substituted with a functional group such as an atom such as N, S or O, or a carbonyl group (triphenodioxazine, triphenodithia Emissions, hexacene-6,15-quinone, etc.), polyvinylcarbazole, polyphenylene sulfide, or the like can be used polycyclic condensate described in the polymer and JP-11-195790 discloses such polyvinylene sulfide. Further, α-seccithiophene α, ω-dihexyl-α-sexithiophene, α, ω-dihexyl-α-kinkethiophene, α, ω-bis (α, which is a thiophene hexamer having the same repeating unit as these polymers, for example. Oligomers such as 3-butoxypropyl) -α-sexithiophene and styrylbenzene derivatives can also be preferably used.

  Furthermore, metal phthalocyanines such as copper phthalocyanine and fluorine-substituted copper phthalocyanine described in JP-A-11-251601, naphthalene 1,4,5,8-tetracarboxylic acid diimide, N, N′-bis (4-trifluoromethyl) Benzyl) naphthalene 1,4,5,8-tetracarboxylic acid diimide, N, N′-bis (1H, 1H-perfluorooctyl), N, N′-bis (1H, 1H-perfluorobutyl) and N, N '-Dioctylnaphthalene 1,4,5,8-tetracarboxylic acid diimide derivative, naphthalene 2,3,6,7 tetracarboxylic acid diimide and other naphthalene tetracarboxylic acid diimides, and anthracene 2,3,6,7-tetra Condensed ring tet such as anthracene tetracarboxylic acid diimides such as carboxylic acid diimide Carboxylic acid diimides, C60, C70, C76, C78, fullerenes, etc. C84, SWNT (single-walled carbon nanotube), carbon nanotubes, merocyanine dyes, and the like pigments such hemicyanine dyes.

  Other materials include tetrathiafulvalene (TTF) -tetracyanoquinodimethane (TCNQ) complex, bisethylenetetrathiafulvalene (BEDTTTTF) -perchloric acid complex, BEDTTTTF-iodine complex, TCNQ-iodine complex, etc. The organic molecular complex can also be used. Furthermore, σ conjugated polymers such as polysilane and polygerman, and organic / inorganic hybrid materials can also be used. Note that at least one organic semiconductor material selected from these materials may be used, or a plurality of materials may be used.

  Further, the organic semiconductor layer 16 may be made of, for example, a material having a functional group such as acryloyl group, acetamide group, dimethylamino group, cyano group, carboxyl group, nitro group, benzoquinone derivative, tetracyanoethylene and tetracyanoquinodimethane, Materials that serve as acceptors that accept electrons such as derivatives thereof, materials having functional groups such as amino groups, triphenyl groups, alkyl groups, hydroxyl groups, alkoxy groups, and phenyl groups, substitutions such as phenylenediamine So-called doping containing materials that serve as donors as electron donors, such as amines, anthracene, benzoanthracene, substituted benzoanthracenes, pyrene, substituted pyrene, carbazole and its derivatives, tetrathiafulvalene and its derivatives Processing Good.

The doping treatment means introducing an electron-donating molecule (acceptor) or an electron-donating molecule (donor) into the thin film as a dopant. Therefore, the doped thin film is a thin film containing the condensed polycyclic aromatic compound and the dopant. Either an acceptor or a donor can be used as the dopant. Acceptors include halogens such as Cl ₂ , Br ₂ , I ₂ , ICl, ICl ₃ , IBr and IF, Lewis acids such as PF ₅ , AsF ₅ , SbF ₅ , BF ₃ , BCl ₃ , BBr ₃ and SO ₃ , Protic acids such as HF, HCl, HNO ₃ , H ₂ SO ₄ , HClO ₄ , FSO ₃ H, ClSO ₃ H, CF ₃ SO ₃ H, organic acids such as acetic acid, formic acid, amino acids, FeCl ₃ , FeOCl, TiCl ₄ , ZrCl ₄ , HfCl ₄ , NbF ₅ , NbCl ₅ , TaCl ₅ , MoCl ₅ , WF ₅ , WCl ₆ , UF ₆ , LnCl ₃ (Ln = La, Ce, Nd, and lanthanoids such as Pr) , Cl ⁻ , Br ⁻ , I ⁻ , ClO ₄ ⁻ , PF ₆ ⁻ , AsF ₅ ⁻ , SbF ₆ ⁻ , BF ₄ ⁻ , electrolyte anions such as sulfonate anions, and the like. As donors, alkali metals such as Li, Na, K, Rb, and Cs, alkaline earth metals such as Ca, Sr, and Ba, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, and Dy , Ho, Er, Yb and other rare earth metals, ammonium ions, R ₄ P ⁺ , R ₄ As ⁺ , R ₃ S ⁺ , and acetylcholine.

  As a doping method of these dopants, there is a method in which the organic semiconductor layer 16 is formed in advance and the dopant is introduced into the organic semiconductor layer 16. Specifically, gas phase doping using a gas state dopant, liquid phase doping in which a solution or liquid dopant is brought into contact with the surface of the organic semiconductor layer, and solid state dopant in contact with the surface of the organic semiconductor layer. A solid phase doping method in which a dopant is diffusely doped can be mentioned. In liquid phase doping, the doping efficiency can be adjusted by applying an electric field.

  In addition, as another doping method, there is a method of introducing a dopant when forming the organic semiconductor layer 16. Specifically, a mixed solution of an organic semiconductor compound and a dopant may be prepared and applied, or a dispersion of an organic semiconductor compound and a dopant may be prepared separately, and applied and dried at the same time. Moreover, when using a vacuum evaporation method, a dopant can be introduce | transduced by co-evaporating a dopant with an organic-semiconductor compound. In the case of using a sputtering method, the dopant can be introduced into the thin film by sputtering using a binary target of an organic semiconductor compound and a dopant. Still other methods include electrochemical doping, chemical doping such as photo-initiated doping, and ion implantation methods described, for example, in the publication ("Industrial Materials", Vol. 34, No. 4, p. 55, 1986). Any physical doping such as can be used.

  The organic semiconductor layer 16 can be fabricated by vacuum deposition, molecular beam epitaxial growth, ion cluster beam method, low energy ion beam method, ion plating method, CVD method, sputtering method, plasma polymerization method, electrolytic polymerization method, chemical method. Examples include a polymerization method, a spray coating method, a spin coating method, a blade coating method, a dip coating method, a casting method, a roll coating method, a bar coating method, a die coating method, and an LB method, which can be used depending on the material.

  The gate insulating film 13 is formed of a porous metal oxide formed from a precursor solution containing a surfactant as a hole forming material and a metal alkoxide, or a porous metal oxide by an anodic oxidation method. . The gate insulating film 13 made of such a material has a large number of pores formed in the film. The shape of the hollow portion of the pore may be spherical or columnar. The pore diameter may be any size in the micro, meso, or macro region. The micro, meso, or macro region is based on the classification by the pore size of the porous material defined by The International Union of Pure and Applied Chemistry (IUPAC). The micro region is 2 nm or less, and the meso region is 2 To 50 nm, a macro region means a pore diameter of 50 nm or more.

The number average pore diameter of the pores in the porous body layer 13 is set in the range of 1 nm to 100 nm, and preferably 1 nm to 50 nm. If it exceeds 100 nm, the mechanical strength of the porous body layer is lowered, and it is difficult to form pores of less than 1 nm with good controllability. Moreover, 50 nm or less is preferable in that the mechanical strength is further improved. Here, the number average pore diameter of the pores is determined by measuring the triaxial average diameter of each pore for the entire porous body layer having a predetermined volume. Specifically, the triaxial average diameter can be obtained from a cross-sectional scanning electron microscope image or a cross-sectional transmission electron microscope image. In addition, in the case of these samples for which it is difficult to measure the electron microscope image, for example, when it is difficult to approximate the shape of the pore to be spherical, the pore size distribution is measured by the X-ray small angle scattering method, The maximum diameter of the distribution may be the triaxial average diameter. In addition, when measuring a triaxial average diameter from the said electron microscope image, it expands to total magnification 10 < ⁶ > -10 < ⁷ > time, for example, 20 samples are calculated | required and an average value is calculated | required.

  The proportion of the volume occupied by the pores in the porous body layer 13 is preferably 20% or more and less than 80%, and particularly preferably 30% to 50%. The drain-on current can be increased by increasing the contact area between the organic semiconductor layer 16 and the porous body layer 13. Moreover, since the pores in the porous body layer 13 are filled with air having excellent electrical insulation, the gate leakage current of the porous body layer 13 can be suppressed. Here, the upper limit is set to less than 80% because the pore density is about 80% when spherical pores of the same size are closely packed.

  Here, the volume occupied by the pores is determined by measuring the triaxial average diameter of the individual pores by the method described above, and calculating the volume of the pores on the assumption that the pores are spherical having the triaxial average diameter. This is obtained by carrying out this operation on the entire porous body layer having a predetermined volume. For the same reason as described above, the volume density of the pores may be obtained by measuring the pore size distribution by the X-ray small angle scattering method.

Further, assuming that the triaxial average diameter of the pore diameter is r (m) and the ratio of the volume occupied by the pores in the porous body layer 13 of the unit volume, that is, the volume density of the pores is N, the N / r value is It is preferably 0.02 (nm ⁻¹ ) or more. From Example 2 described later, the on / off ratio of the semiconductor device can be increased by about 100 times or more. The upper limit of the N / r value is less than 0.8 (nm ⁻¹ ) because the volume density N of the pores is less than 80% and the triaxial average diameter r is preferably 1 nm or more. It is preferable that

This can also be confirmed by the following simplified theoretical calculation. The volume density N of the pores and the total surface area of the pores per unit volume, S (m ⁻¹ ) can be expressed by the following formulas (6) and (7), respectively.
N = 4/3 · πr ³ · n (6)
S = 4πr ² · n (7)
Here, the number of pores per unit volume is n (pieces / m ³ ), and the average pore diameter is r (m). From Equation (6) and Equation (7),
S = 3N / r (8)
Holds. From equation (8), it can be seen that the total surface area S of the pores per unit volume is proportional to the volume density N of the pores, inversely proportional to the average value r of the pore diameters, and proportional to the N / r value. From this, in order to increase the contact area at the interface between the organic semiconductor layer 16 and the porous body layer 13, the volume density N of the pores is increased, the average value r of the pore diameters is decreased, and further, N / r It can be seen that the value should be increased.

  The film thickness of the porous body layer 13 as the gate insulating film 13 is set to 1 nm to 1000 nm. The reason why the film thickness is 1 nm or more is that the contact area at the interface between the organic semiconductor layer 16 and the porous body layer 13 is because the thickness of carriers accumulated in the vicinity of the interface between the organic semiconductor layer 16 and the porous body layer 13 is 1 nm or more. Becomes large enough, and as a result, it is possible to collect many carriers.

  On the other hand, regarding the upper limit of the film thickness of the porous body layer 13, it has been clarified that the accumulated thickness of carriers in the vicinity of the interface between the organic semiconductor layer 16 and the porous body layer 13 when a gate voltage is applied is about the Debye length. Tsuna (Adachi, Chiba et al. “Device characteristics of organic TFTs in the ultra-thin film region” 50th Japan Society of Applied Physics, 27-30 March 2003 (Kanagawa University), Gilles Horowitz et al., “Gate voltage dependent mobility of oligothiophene field-effect transistors ”, J. Appl. Phys. Vol. 85, No. 6 (1999), Jiyoul Lee et al., Appl. Phys. Let. Vol. 82, No. 23 (2003)) . Considering the Debye length, the thickness of the porous body layer 13 is set to 1000 nm or less, preferably 500 nm or less.

  Here, the film thickness of the porous body layer 13 is the distance between the surface of the gate electrode 12 and the roughness average surface of the surface of the porous body layer 13 at the interface between the organic semiconductor layer 16 and the porous body layer 13. Here, the roughness average surface is obtained by extending the roughness average line in the cross section of the organic semiconductor layer 16 / porous body layer 13 or the like into a two-dimensional plane. The roughness average line can be obtained by measuring the cross-sectional shape with a scanning electron microscope, a transmission electron microscope, a scanning probe microscope, or the like.

  A method of forming such a porous body layer 13 will be specifically described below with reference to FIG.

  FIG. 2 is a flowchart showing a porous body layer forming step. First, the metal alkoxide is hydrolyzed under acidic conditions in the presence of a surfactant to prepare a porous body precursor solution (sol solution) (S102). The surfactant forms spherical micelles in the sol solution. The micelle is formed with the hydrophobic group portion facing inward and the hydrophilic group portion facing outward, and the micelle shape and diameter are formed with good uniformity. The shape formed by these micelles finally becomes the pores of the porous body layer.

  Surfactants include cationic surfactants, anionic surfactants, or nonionic surfactants such as polyethylene oxide (PEO) and polypropylene oxide (PPO), and their copolymers and block copolymers. Either an agent or a triblock copolymer may be used. A compound such as mesitylene may be added to increase the volume of the hollow pores.

The cationic surfactant is not particularly limited, and examples thereof include a quaternary ammonium salt or an alkylamine salt. Examples of the quaternary ammonium salt include quaternary ammonium salts represented by the following general formula (4).
[R ¹ _n (CH ₃ ) _4-n N] ⁺ [X] ⁻ (4)
(In the formula, R ¹ represents a linear alkyl group, n represents an integer of 1 to 3, and X represents a halogen atom or a hydroxyl group.)
In particular, a quaternary alkyltrimethylammonium halide or hydroxide represented by the general formula [R ¹ (CH ₃ ) ₃ N] ⁺ [X] ^{— wherein} the substitution number n in the general formula (4) is 1 Is preferable because it is easy to form micelles.

In the general formula (4), 8 to 24 is preferable as the number of carbon atoms of the linear alkyl group R ^1, especially preferably 8 to 17 in terms of solubility. If the number of carbon atoms is 25 or more, it is insoluble in water and difficult to handle, and if it is less than 8, micelles are difficult to form. Moreover, as a halogen atom of X, a chlorine atom and a bromine atom are preferable. Specific examples of the quaternary alkyltrimethylammonium salt include octyltrimethylammonium chloride, octyltrimethylammonium bromide, octyltrimethylammonium hydroxide, decyltrimethylammonium chloride, decyltrimethylammonium bromide, decyltrimethylammonium hydroxide, Dodecyltrimethylammonium chloride, dodecyltrimethylammonium bromide, dodecyltrimethylammonium hydroxide, hexadecyltrimethylammonium chloride, hexadecyltrimethylammonium bromide, hexadecyltrimethylammonium hydroxide, octadecyltrimethylammonium chloride, octadecyltrimethylammonium bromide, hydroxy acid Octadecyl trimethyl ammonium, and the like. Two or more of these ammonium salts may be combined.

Moreover, as an alkylamine salt, the alkylamine salt represented by following General formula (5) is mentioned.
[R ² NH ₃ ] ⁺ [X] ⁻ (5)
(In the formula, R ² represents a linear alkyl group, and X represents a halogen atom or a hydroxyl group.)
In the general formula (5), 8 to 24 is preferable as the number of carbon atoms of the linear alkyl group R ^2, and particularly preferably 8 to 17 in terms of solubility. If the carbon number is 25 or more, it is insoluble and difficult to handle, and if it is less than 8, it is difficult to form micelles. Moreover, as a halogen atom of X, a chlorine atom and a bromine atom are mentioned by the point which is easy to acquire.

  As the surfactant solvent, water, ethanol, methanol, isopropyl alcohol, or the like can be used.

  The addition amount of each of the surfactant and a solvent such as water and ethanol is appropriately determined depending on the type of the surfactant, and is specifically set to an addition amount for forming a micelle.

  There are many types of metal alkoxides used in the present embodiment depending on the combination of a metal and an alkoxy group. Examples of the metal include lithium, sodium, potassium, magnesium, calcium, strontium, barium, aluminum, indium, and germanium. Bismuth, iron, copper, yttrium, titanium, zirconium, tantalum, silicon and the like. In particular, aluminum, titanium, zirconium, and silicon are preferable in terms of low cost and multivalent ions.

  Examples of the silicon alkoxide include tetramethoxysilane (TMOS), tetraethoxysilane (TEOS), tetrapropoxysilane, tetrabutoxysilane, methyltrimethoxysilane, methyltriethoxysilane, dimethyldimethoxysilane, dimethyldiethoxysilane, Dimethyldimethoxysilane, phenyltrimethoxysilane, diphenyldimethoxysilane, tetraethoxysilane, methyltriethoxysilane, dimethyldiethoxysilane, phenyltriethoxysilane, diphenyldiethoxysilane, hexyltrimethoxysilane, hexyltriethoxysilane, decyltrimethoxy Silane, decyltrimethoxysilane, trifluoropropyltrimethoxysilane, and heptadecatrifluorodecyltrimethoxy Run, and the like. Further, fumed silica, colloidal silica, water glass, or the like can be used instead of silicon alkoxide.

  The acidic conditions for the hydrolysis are preferably in the range of pH 1 to pH 2 in terms of dissociation of the silane group, and hydrochloric acid, sulfuric acid, nitric acid and the like are added.

  Next, a sol solution is applied and dried to form a surfactant-dispersed metal oxide film having a predetermined thickness (S104). The surfactant-dispersed metal oxide film obtained by drying has a structure in which the surfactant forms micelles such as spheres or rods, and the hydrolysis product of the metal alkoxide surrounds it. The structure is fixed by drying.

  The coating method of the sol solution can be various coating methods and is not particularly limited, but preferred methods include spin casting, dip coating, screen printing, and casting, and the film thickness can be easily controlled. The spin casting method and the dip coating method are particularly preferable in that a relatively large area can be applied.

  Next, the surfactant-dispersed metal oxide film is heated (S106). A metal oxide is produced from the hydrolysis product of the metal alkoxide, the surfactant is decomposed and removed, and a porous body layer in which the portion from which the micelles of the surfactant are removed becomes pores is formed.

  The heat treatment is performed in the air or in a nitrogen atmosphere, and the heating temperature is appropriately selected depending on the surfactant to be used, but is set in the range of 200 ° C. to 700 ° C. and is 200 in terms of thermal influence on the organic semiconductor layer. The range of ° C to 400 ° C is preferable, and 200 ° C to 300 ° C is particularly preferable. The heating temperature is preferably in the range of 200 ° C to 400 ° C in that a metal oxide is produced from a hydrolysis product of a metal alkoxide.

  As other treatments for decomposing and removing the surfactant in the surfactant-dispersed metal oxide film, (i) the surfactant-dispersed metal oxide film with a solvent is washed and the surfactant is eluted and removed. Examples include a treatment for forming pores, (ii) a treatment for oxidizing and removing a surfactant in an ozone atmosphere, and (iii) a treatment for removing and oxidizing a surfactant in an oxygen plasma atmosphere. The treatments (i) to (iii) are preferable in that they do not involve high temperature heating. Even if a material having low heat resistance is present in the semiconductor device, the metal oxide porous layer can be formed.

  The solvent (i) is not particularly limited, but methanol, ethanol, water, tetrahydrofuran, and the like are preferable because they are highly polar and easily elute the active agent. In addition, when the pores are hydrophobized as described later, solvents with low polarity are effective, and hydrocarbon solvents such as petroleum ether, hexane, and octane and aromatic hydrocarbons such as benzene, toluene, and xylene are used. A solvent is effective. These heated polar and nonpolar solvents are more preferred because the solubility of the active agent is increased.

  Next, the porous body layer is hydrophobized (S108). In the hydrophobization treatment, the porous body layer is immersed in 1,1,1,3,3,3-hexamethyldisilazane or a solution of chlorosilane having an alkyl group, or exposed to these vapors and dried. Hydrophobic treatment prevents the formation of cracks in the porous body layer by forming a coating such as 1,1,1,3,3,3-hexamethyldisilazane, which is a hydrophobic material, on the pore surface. can do.

  Note that a silicon compound having a hydrophobic portion may be added instead of the hydrophobic treatment when preparing the sol solution. The silicon compound having a hydrophobized portion can be achieved by a method of adding an alkoxysilane having an alkyl group or a vinyl group or a method of adding a chlorosilane having an alkyl group. Specific materials include monoalkyltrialkoxysilane, dialkyldialkoxysilane, and trialkylalkoxysilane. Examples of the alkyl group include a methyl group, an ethyl group, a propyl group, a butyl group, and a phenyl group. The alkoxy group of the alkoxysilane includes, for example, a methoxy group, an ethoxy group, a propoxy group, and a butoxy group. Groups.

  As described above, the gate insulating film of the porous body layer subjected to the hydrophobic treatment is formed. In addition, you may laminate | stack the porous body layer of a different material from the materials mentioned above for a porous body layer. Moreover, you may laminate | stack the porous body layer which consists of the same material or different material which formed different pore diameters, for example, a number average pore diameter.

  In addition, the porous body layer may be formed with irregularities on the surface by etching the surface in contact with the semiconductor layer with oxygen plasma using a polymer material film such as polyethylene or polyimide. It can also be produced by an anodic oxidation method. In this case, a metal film made of aluminum, titanium, zirconia, niobium, hafnia, zinc, tantalum, or the like is used, and a recess is formed on the surface as a starting point of the pores. Can be formed.

  Next, a semiconductor device according to a first modification of the present embodiment will be described. The semiconductor device according to this modification is configured in the same manner as the semiconductor device of the first embodiment except that the organic semiconductor layer and the source / drain electrodes are different.

  FIG. 3 is a cross-sectional view of a semiconductor device according to a first modification of the present embodiment. In the figure, portions corresponding to the portions described above are denoted by the same reference numerals, and description thereof is omitted.

  Referring to FIG. 3, the semiconductor device 20 according to the present modification covers the insulating substrate 11, the gate electrode 12 selectively formed on the insulating substrate 11, and the surface of the insulating substrate 11 and the gate electrode 12. A gate insulating film 13 made of a porous layer, an organic semiconductor layer 16 covering the gate insulating film 13, and two source / drain electrodes 15 disposed on the organic semiconductor layer 16 so as to be spaced apart in the gate length direction. ing.

The semiconductor device 20 of this modification is formed in the same manner as in the first embodiment except that the organic semiconductor layer 16 is formed first and then the source / drain electrodes 15 are formed. Since the source / drain electrode 15 is formed after the organic semiconductor layer 16 is formed on the gate insulating film 13, the surface of the porous body layer 13 of the gate insulating film 13 is contaminated by the cleaning process of the source / drain electrode 15 or the like. Generation of damage due to the etching process can be avoided, and a clean and homogeneous porous layer 13 / organic semiconductor layer 16 interface can be formed. As a result, a semiconductor device with excellent stability of element characteristics can be realized. Next, a semiconductor device according to a second modification of the present embodiment will be described. The semiconductor device according to this modification is configured in the same manner as the semiconductor device of the first embodiment except that an insulating film is provided as a gate insulating film in addition to the porous layer.

  FIG. 4 is a cross-sectional view of a semiconductor device according to a second modification of the present embodiment. In the figure, portions corresponding to the portions described above are denoted by the same reference numerals, and description thereof is omitted.

  Referring to FIG. 4, the semiconductor device 30 according to the present modification covers the insulating substrate 11, the gate electrode 12 selectively formed on the insulating substrate 11, and the surface of the insulating substrate 11 and the gate electrode 12. In this way, the gate insulating film 33 in which the insulating film 31 and the porous body layer 32 are formed in this order, and two pieces of the porous body layer 32 that are spaced apart from each other with a predetermined channel length in the gate length direction. A source / drain electrode 15 and an organic semiconductor layer 16 covering the source / drain electrode 15 are formed. The gate insulating film 33 is composed of a stacked body of the insulating film 31 and the porous body layer 32, and the porous body layer 32 is in contact with the organic semiconductor layer 16. The porous body layer 32 is the same as the porous body layer 13 of the first embodiment shown in FIG.

  The insulating film 31 has a film thickness of, for example, 10 nm to 1000 nm (preferably 100 nm to 1000 nm). Any insulating material can be used as long as it is an insulating material. For example, polychloropyrene, polyethylene terephthalate, polyoxymethylene, polyvinyl chloride, polyvinylidene fluoride, cyanoethyl pullulan, polymethyl methacrylate, polysulfone, polycarbonate, polyimide, polyethylene, polyester, polyvinyl phenol, melamine resin, phenol resin, fluorine resin, polyphenylene sulfide Organic materials such as polyparaxylene and polyacrylonitrile, inorganic materials such as silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium oxide, and silicon nitride oxide, various insulating Langmuir-Blodgett films, and the like can be used. . Of course, the materials are not limited to these, and two or more of these materials may be used, or two or more insulating films made of different materials may be stacked.

  Of these materials, silicon nitride, aluminum oxide, aluminum nitride, titanium oxide, and silicon nitrogen oxide are preferable in terms of relative dielectric constant. The relative dielectric constant of the entire gate insulating film can be improved and the gate leakage current can be further suppressed. In addition, an insulating film material for improving the adhesive strength between the gate electrode 12 and the porous body layer can be appropriately selected.

  A method for forming the insulating film 31 is not particularly limited, and examples thereof include a CVD method, a plasma CVD method, a plasma polymerization method, a vapor deposition method, a spin coating method, a dipping method, a cluster ion beam vapor deposition method, and a Langmuir-Blodgett method. Can also be used.

  In the semiconductor device 30 of this modification, in addition to the effect of the porous layer / organic semiconductor layer 16 of the semiconductor device of the first embodiment, a material having a high relative dielectric constant is used for the insulating film 31 to obtain a gate capacitance. Can be increased. As a result, the on / off ratio of the drain current can be improved.

  Next, a semiconductor device according to a third modification of the present embodiment will be described. The semiconductor device according to this modification is configured in the same manner as the semiconductor device according to the first modification of the first embodiment, except that an insulating film is provided as a gate insulating film in addition to the porous layer.

  FIG. 5 is a cross-sectional view of a semiconductor device according to a third modification of the present embodiment. In the figure, portions corresponding to the portions described above are denoted by the same reference numerals, and description thereof is omitted.

  Referring to FIG. 5, the semiconductor device 40 according to the present modification covers the insulating substrate 11, the gate electrode 12 selectively formed on the insulating substrate 11, and the surface of the insulating substrate 11 and the gate electrode 12. As described above, the gate insulating film 33 in which the insulating film 31 and the porous body layer 32 are formed in this order, the organic semiconductor layer 16 covering the porous body layer 32, and the organic semiconductor layer 16 are spaced apart in the gate length direction. The two source / drain electrodes 15 are formed.

  Since the semiconductor device 40 of the present modification is a combination of the configurations of the semiconductor device according to the first modification and the semiconductor device according to the second modification, the effects of those semiconductor devices are combined. . Therefore, the stability of the device characteristics and the on / off ratio of the drain current can be improved.

  Next, a semiconductor device according to a fourth modification of the present embodiment will be described. In the semiconductor device according to this modification, an organic semiconductor layer is first formed on an insulating substrate, and then a gate insulating film is formed.

  FIG. 6 is a cross-sectional view of a semiconductor device according to a fourth modification of the present embodiment. In the figure, portions corresponding to the portions described above are denoted by the same reference numerals, and description thereof is omitted.

  Referring to FIG. 6, a semiconductor device 50 according to the present modification covers an insulating substrate 11, two source / drain electrodes 15 formed on the insulating substrate 11 at a distance, and the source / drain electrode 15. An organic semiconductor layer 16, a gate insulating film 13 made of a porous layer covering the organic semiconductor layer 16, and a gate electrode selectively formed on the gate insulating film 13 substantially above the center of the two source / drain electrodes 15 12 is comprised.

  Since the organic semiconductor layer 16 is covered with the gate insulating film 13, the semiconductor device 50 of this modification is not exposed to the external atmosphere. Therefore, since it does not come into direct contact with moisture or oxygen that degrades the electrical characteristics of the organic semiconductor layer 16, the durability of the semiconductor device can be improved. In addition, a clean and harmless homogeneous organic semiconductor layer 16 / gate insulating film 13 interface is formed, and the on / off ratio of the drain current can be improved. In addition, since the source / drain electrodes 15 are formed on the insulating substrate 11 which is a base having a good flatness, the source / drain electrodes 15 can be arranged with high accuracy and can be easily formed.

  Note that a water-impermeable film such as a silicon nitride film or a polyimide film covering the surface of the gate insulating film 13 and the surface of the gate electrode 12 may be formed. It is possible to prevent moisture from reaching the organic semiconductor layer 16 through the gate insulating film 13 of the porous body layer.

  Next, a semiconductor device according to a fifth modification of the present embodiment will be described. This modification has a configuration in which the organic semiconductor layer is prevented from being directly exposed to the outside atmosphere as in the fourth modification described above.

  FIG. 7 is a cross-sectional view of a semiconductor device according to a fifth modification of the present embodiment. In the figure, portions corresponding to the portions described above are denoted by the same reference numerals, and description thereof is omitted.

  Referring to FIG. 7, a semiconductor device 60 according to this modification is formed on an insulating substrate 11, an organic semiconductor layer 16 selectively formed on the insulating substrate 11, and a space on the organic semiconductor layer 16. The two source / drain electrodes 15, the gate insulating film 13 made of a porous layer covering the source / drain electrodes 15, and the gate insulating film 13 substantially above the center of the two source / drain electrodes 15 are selectively formed. It is comprised from the gate electrode 12 formed in this.

  In the semiconductor device 60 of this modification, the organic semiconductor layer 16 is covered with the source / drain electrodes 15 and the gate insulating film 13 and is not exposed to the external atmosphere. Therefore, since it does not come into direct contact with moisture or oxygen that degrades the electrical characteristics of the organic semiconductor layer 16, the durability of the semiconductor device can be improved. Similar to the fourth modification, a water-impermeable film such as a silicon nitride film or a polyimide film covering the surface of the gate insulating film 13 and the surface of the gate electrode 12 may be formed.

  Although the description of the manufacturing method of the semiconductor device according to the first to fifth modifications has been omitted, it can be manufactured using the same method as the manufacturing method described in the first embodiment. Next, examples according to the present embodiment and comparative examples not according to the present invention will be described.

[Example 1]
In this example, a transistor having a structure similar to that of the first embodiment shown in FIG. 1 was manufactured. After a metal mask having a gate electrode-shaped opening was placed on the surface of a glass substrate having a size of 30 mm × 30 mm × 1.1 mm, an aluminum electrode having a thickness of 70 nm was formed by vacuum deposition, and a gate electrode (gate length 50 μm, A gate width of 250 μm) was produced. At this time, the degree of vacuum is 6.7 × 10 ⁻⁴ Pa (5 × 10 ⁻⁶ Torr), the film formation rate is 0.3 to 0.5 nm / second, the substrate temperature is not particularly controlled, and is room temperature (25 ° C.). The film thickness was monitored by a crystal resonator of a vacuum deposition apparatus.

  Next, a sol solution of the precursor solution of the porous layer of the gate insulating film was prepared. Specifically, a mixed solution of tetraethoxysilane (TEOS): water: ethanol: concentrated hydrochloric acid at a molar ratio of 1: 5: 5: 0.03 was heated to 70 ° C. and stirred for 4 hours. After adding an ethanol solution of Pluronic L64 (manufactured by BASF) which is a polyethylene oxide-polypropylene oxide-polyethylene oxide block copolymer (EO-b-PO-b-EO) as a surfactant to this mixed solution and stirring for 5 hours. The sol solution was obtained by allowing the silicon alkoxide to hydrolyze under acidic conditions in the presence of a surfactant.

  The sol solution thus prepared was spin-cast while rotating at 1500 RPM so as to cover the gate electrode, and then dried at 110 ° C. in a nitrogen atmosphere using an oven to form a surfactant-dispersed silica film. The surfactant was removed by heating the surfactant-dispersed silica membrane in air (300 ° C., 60 minutes).

  Subsequently, the porous body layer was formed by immersing in hexamethyldisilazane (HMDS) and vacuum-drying (110 degreeC, 5 minutes) (henceforth "HMDS process"). The film thickness of the porous body layer was about 0.5 μm.

  FIG. 8 is a transmission electron microscope (TEM) image of the surface of the porous body layer. As shown in FIG. 8, it is understood that the porous body layer has spherical pores having a substantially uniform size with a number average pore diameter (radius) of 2 nm.

Next, after arranging a metal mask on the porous body layer, a source electrode and a drain electrode were formed by an Au film by an evaporation method. The shape of the source electrode and the drain electrode was a rectangle of 1 mm × 10 mm, and the film thickness was 50 nm. The degree of vacuum during vapor deposition is 6.7 × 10 ⁻⁴ Pa (5 × 10 ⁻⁶ Torr), the film formation rate is 0.2 to 0.3 nm / second, and the substrate temperature is not particularly controlled, and is room temperature (25 ° C.). It was. When this film was observed with a reflective optical microscope, the distance between the source electrode and the drain electrode (channel length) was 10 μm, and the electrode length (channel width) was 10 mm.

  Subsequently, a chloroform solution of regioregular poly (3-hexylthiophene) was spin-coated on the porous layer, the source electrode, and the drain electrode to form an organic semiconductor layer having a thickness of 100 nm. Thus, the transistor of this example was completed.

FIG. 9 is a diagram showing the characteristics of the transistor of Example 1. When a source-drain voltage is applied from 0 V to −30 with respect to a gate voltage V _{G of} 2 V from 0 V to −20 V, the voltage between the source and drain is shown. It is the figure which showed the drain current which flows. The horizontal axis represents the source-drain voltage, and the vertical axis represents the drain current value.

  Referring to FIG. 9, it can be seen that the drain current is changed by the gate voltage at the source-drain voltage of -30 V, that is, the gate modulation is performed. A large drain current of about 0.1 mA is obtained at the maximum. The on / off ratio at a source-drain voltage of -30 V was about 300. The measurement was performed using a semiconductor parameter analyzer (model: 4145B, manufactured by Hewlett-Packard Company) in a nitrogen atmosphere.

[Comparative Example 1]
As the transistor of this comparative example, a transistor having the same configuration as that of Example 1 was manufactured except that the surfactant-dispersed silica film of Example 1 was used as the gate insulating film. Specifically, the transistor of this comparative example is obtained by omitting the heat treatment in air after the production of the surfactant-dispersed silica film of Example 1, and the surfactant-dispersed silica film is a surfactant. Since it is not removed, the porous body layer is not formed.

  The current-voltage characteristics of the transistor of this comparative example thus obtained were measured in the same manner as in Example 1. As a result, the on / off ratio at the source-drain electrode voltage of -30 V was about 10.

[Example 2]
In this example, a transistor having the same structure as that of the fourth modification example of the first embodiment shown in FIG. 6 was produced.

  First, in the same manner as in Example 1, a gate electrode made of an aluminum film having a thickness of 70 nm was formed on the surface of a glass substrate having a size of 30 mm × 30 mm × 1.1 mm.

A silicon oxide film having a thickness of 300 nm was formed by electron beam evaporation so as to cover the gate electrode. The degree of vacuum was 1.1 × 10 ⁻³ Pa (8 × 10 ⁻⁶ Torr), and the film formation rate was 100 nm / min. The acceleration voltage was set to 4.5 kV and the emission current was set to 30 mA. The silicon oxide film was not patterned.

  Next, a sol solution prepared in the same manner as in Example 1 so as to cover the silicon oxide film is spin-cast in the same manner as in Example 1 to form a film, which is then dried at 110 ° C. in a nitrogen atmosphere using an oven and subjected to surface activity. An agent-dispersed silica film was prepared.

  Next, the surfactant-dispersed silica film was exposed in an ozone atmosphere at different times from 0 minutes to 120 minutes to form various samples with different average pore diameters and volume densities. The same HMDS treatment was performed to obtain a porous body layer.

  Next, as in Example 1, source / drain electrodes and a semiconductor layer were formed. The current-voltage characteristics of the transistor thus obtained were measured with a semiconductor parameter analyzer (supra) in the same manner as in Example 1.

  FIG. 10 is a diagram illustrating the relationship between the on / off ratio and the N / r value of the transistor of Example 2. The vertical axis represents the on / off ratio, the horizontal axis represents the N / r value, where N is the pore volume density and r is the number average pore diameter (radius).

Referring to FIG. 10, the on / off ratio increases as the N / r value increases. The on / off ratio is 100 when the N / r value is 0.02 (nm ⁻¹ ). Therefore, it can be seen that it is preferable to set the N / r value to 0.02 (nm ⁻¹ ) or more.

Here, N was measured using a molecular ellipsometry method, and r was an average value of 20 measured values arbitrarily selected by cross-sectional transmission electron microscope (10 ⁶ to 10 ⁷ times magnified on photographic paper).

[Example 3]
In this example, a transistor having the same structure as that of the second modification of the first embodiment shown in FIG. 4 was produced.

First, after arranging a metal mask having source electrode and drain electrode-shaped openings on the surface of a glass substrate having a size of 30 mm × 30 mm × 1.1 mm, a chromium film having a thickness of 10 nm is formed as a contact metal, and then a thickness of 70 nm. A source electrode and a drain electrode were formed by evaporating an Au film. The shape of the source electrode and the drain electrode was a rectangle of 1 mm × 10 mm. The degree of vacuum during vapor deposition was 6.7 × 10 ⁻⁴ Pa (5 × 10 ⁻⁶ Torr), and the film formation rate was 0.2 to 0.3 nm / second. The substrate temperature was not particularly controlled and was set to room temperature (25 ° C.). When this film was observed with a reflective optical microscope, the distance between the source electrode and the drain electrode (channel length) was 10 μm, and the electrode length (channel width) was 10 mm.

  Next, an organic semiconductor layer (thickness: 100 nm) covering the substrate surface, the source electrode, and the drain electrode was formed in the same manner as in Example 1. Next, a sol solution of the precursor solution of the porous layer of the gate insulating film was similarly prepared except that polyethylene oxide was used instead of the surfactant EO-b-PO-b-EO of Example 1. A solution was prepared.

The sol solution thus prepared was spin cast on the organic semiconductor layer while rotating at 1500 RPM, dried at 110 ° C., and then dried at 110 ° C. in a nitrogen atmosphere using an oven, and the surfactant-dispersed silica A membrane was prepared. The surfactant was then removed by exposure to O ₂ plasma for 3 minutes. Subsequently, the porous body layer was obtained by performing the HMDS process similar to Example 1. FIG.

  Next, a gate electrode made of an aluminum film having a thickness of 70 nm was formed on the porous layer by vacuum vapor deposition in the same manner as in Example 1. Thus, the transistor of this example was completed.

  The current-voltage characteristics of the transistor thus obtained were measured with a semiconductor parameter analyzer (supra) in the same manner as in Example 1. The on / off ratio at a source-drain voltage of −20 V was about 200.

[Comparative Example 2]
In this comparative example, a transistor having the same structure as in Example 3 was produced except that the surfactant-dispersed silica film in Example 3 was not subjected to O ₂ plasma treatment.

  The current-voltage characteristics of the transistors thus obtained were measured with a semiconductor parameter analyzer (supra). The on / off ratio at a source-drain voltage of -20 V was about 10.

(Second Embodiment)
FIG. 11 is a cross-sectional view of a main part of a liquid crystal display device according to the second embodiment of the present invention. Referring to FIG. 11, in the liquid crystal display device 70 of the present embodiment, a TFT array unit 72, a liquid crystal element unit 73, a transparent electrode unit 74, and a transparent substrate 75 are sequentially stacked on the transparent substrate 71 and the transparent substrate 71. It has been configured.

  As the transparent substrates 71 and 75, a glass substrate or a plastic substrate such as polyester, polycarbonate, polyarylate, or polyether sulfone can be used. The transparent electrode portion 74 can be made of a transparent conductive oxide material such as an ITO film or a ZTO film.

  The liquid crystal element unit 73 is composed of an alignment film / liquid crystal / alignment film, and the liquid crystal is, for example, a twisted nematic (TN) method, a super twisted nematic (STN) method, a guest host liquid crystal, a polymer dispersed liquid crystal ( A known display method such as PDLC can be used. The reflective liquid crystal display device is preferably PDLC in that a bright white display can be obtained.

  The TFT array unit 72 is electrically connected to a gate electrode 80 and a transistor 76 arranged in a matrix on the transparent substrate 71, a pixel electrode 79 electrically connected to the drain electrode 78 of the transistor 76, and a gate. A gate bus line (not shown) for supplying a voltage and a source bus line (not shown) for supplying a driving voltage to the source electrode 81 are configured. The transistor 76 includes a gate electrode 80 formed on the transparent substrate 71, a gate insulating film 82 covering the surface of the transparent substrate 71 and the gate electrode 80, and a source electrode 81 and a drain electrode 78 formed separately on the gate insulating film 82. The organic semiconductor layer 83 covers the surface of the gate insulating film 82 and the source electrode 81 and the drain electrode 78.

  In the liquid crystal display device 70, when a signal is supplied via the gate bus line and the source bus line, the transistor 76 is selectively turned on, and the drive voltage is supplied to the pixel electrode 79 via the drain electrode 78. By applying an electric field to the liquid crystal of the liquid crystal element unit 73 between the transparent electrode unit 74 and the transparent electrode unit 74, switching of transmission or blocking of the backlight light incident from the back side of the transparent substrate 71 is performed. An image is displayed by the light emitted from.

  The liquid crystal display device 70 of the present embodiment is characterized by the transistor 76 of the TFT array unit 72. For the transistor 76, the semiconductor device of the first embodiment and any one of the semiconductor devices of the first to fifth modifications are used. Since the transistor 76 has a large on / off ratio and high durability as described above, the liquid crystal display device 70 has a high contrast ratio, excellent visibility, and long-term reliability as display performance. . In addition, it is good also as a color liquid crystal display device by forming a well-known color filter on a transparent substrate.

  As the display device, an organic EL (electroluminescence) element portion and an electrophoretic element portion are used in place of the liquid crystal element portion 73 of the liquid crystal display device 70 described above, thereby providing an organic EL display device and an electrophoretic display device, respectively. Also good.

  The organic EL display device includes, for example, a hole transport layer / a light emitting layer / an electron transport layer as the organic EL element portion, and a known material can be used for each layer. The holes and electrons injected by the TFT array unit 72 described above recombine in the light emitting layer to emit light spontaneously, and color display can be performed by selecting the dopant of the light emitting layer. Since the organic EL layer is a very thin organic thin film, a flexible display device can be realized by combining with the semiconductor device of the first embodiment formed on a plastic substrate.

  In addition, the electrophoretic display device uses an electrophoretic particle and a microcapsule containing a color dispersion medium in which a colorant is dispersed in a dispersion medium, or both color and electrical characteristics as an electrophoretic element unit. The thing using the microcapsule which included the rotating particle which consists of two different hemispheres with the insulating liquid, etc. can be used.

  In the former type of electrophoretic element section, the electrophoretic particles are white, for example, the colored dispersion medium is black, for example, and the electrophoretic particles charged in the colored dispersion medium are applied with an electric field by the TFT array section described above. As a result, the position in the colored dispersion medium is changed. Information can be displayed by the arrangement of the electrophoretic particles.

  Titanium oxide is particularly preferably used as the white electrophoretic particles, and surface treatment or compounding with other materials is performed as necessary.

  Dispersion media include aromatic hydrocarbons such as benzene, toluene, xylene, naphthenic hydrocarbons, aliphatic hydrocarbons such as hexane, cyclohexane, kerosene, paraffinic hydrocarbons, trichloroethylene, tetrachloroethylene, trichlorofluoroethylene, odor It is preferable to use an organic solvent having high resistivity, such as halogenated carbons or hydrocarbons such as ethyl halide, fluorine-containing ether compounds, fluorine-containing ester compounds, and silicone oil. As the colorant, oil-soluble dyes such as anthraquinones and azo compounds having desired light absorption characteristics are used. A surfactant or the like may be added to the dispersion for stabilization of dispersion.

  The microcapsule is made of, for example, a polymer film and can be formed by a known method such as a coacervation method, an In-Situ polymerization method, or an interfacial polymerization method.

  In addition, the latter type of electrophoretic element unit includes rotating particles in which hemispheres made of resins containing dyes or pigments of different colors are combined with an insulating liquid such as silicone oil in the above-described polymer microcapsule. It is included. When an electric field is applied, the rotating particles rotate due to the difference in charging polarity of the respective hemispheres and exhibit any color.

  In this display method, a bright and wide viewing angle can be displayed, and once the electrophoretic particles or rotating particles are placed, the display does not change even when the electric field is turned off. It is preferable.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the present invention described in the claims. It can be changed.

  For example, the semiconductor device according to the first embodiment or its modification shown in FIGS. 1 and 3 to 7 shows an example in which both sides in the gate length direction are tapered, but instead of the tapered shape. A curved surface may be used, or both sides of each layer may form end faces, for example, the end faces may be regulated by an insulating film. Furthermore, the surface of the semiconductor device may be covered with an insulating film.

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. It is a flowchart which shows the formation process of a porous body layer. It is sectional drawing of the semiconductor device which concerns on the 1st modification of 1st Embodiment. It is sectional drawing of the semiconductor device which concerns on the 2nd modification of 1st Embodiment. It is sectional drawing of the semiconductor device which concerns on the 3rd modification of 1st Embodiment. It is sectional drawing of the semiconductor device which concerns on the 4th modification of 1st Embodiment. It is sectional drawing of the semiconductor device which concerns on the 5th modification of 1st Embodiment. It is a transmission electron microscope image of the surface of a porous body layer. FIG. 4 is a diagram illustrating the characteristics of the transistor of Example 1. It is a figure which shows the relationship between the on / off ratio of the transistor of Example 2, and N / r value. It is principal part sectional drawing of the liquid crystal display device which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

10, 20, 30, 40, 50, 60 Semiconductor device 11 Insulating substrate 12, 80 Gate electrode 13 Gate insulating film, porous layer 15 Source / drain electrode 16, 83 Organic semiconductor layer 31 Insulating film 32 Porous layer 70 Liquid crystal display device 71, 75 Transparent substrate 72 TFT array portion 73 Liquid crystal element portion 74 Transparent electrode portion 76 Transistor 78 Drain electrode 79 Pixel electrode 81 Source electrode 82 Gate insulating film

Claims (22)

A gate electrode;
A semiconductor layer made of organic matter;
A gate insulating film formed between the gate electrode and the semiconductor layer;
Two source / drain electrodes formed on the opposite side of the gate electrode through a gate insulating film,
The semiconductor device according to claim 1, wherein the gate insulating film comprises a porous body layer having pores formed therein.   The said gate insulating film consists of the said porous body layer formed in the semiconductor layer side, and the insulating film of the material which is formed in the gate electrode side and is different from the said porous body layer. Semiconductor device.   3. The semiconductor device according to claim 1, wherein the source / drain electrodes are formed on the surface of the gate insulating film on the semiconductor layer side and are covered with the semiconductor layer.   3. The semiconductor device according to claim 1, wherein the source / drain electrodes are formed on the surface of the semiconductor layer opposite to the gate insulating film.   The semiconductor device according to claim 1, wherein the porous body layer is made of a metal oxide in which a large number of the pores are formed.   6. The semiconductor device according to claim 5, wherein the metal oxide is a silicon oxide.   The semiconductor device according to claim 1, wherein an average radius of the pores is set in a range of 1 nm to 100 nm.   The volume ratio of the pores occupying the porous body layer is set in a range of 20% or more and less than 80% based on the volume of the porous body layer. A semiconductor device according to claim 1.   9. The semiconductor device according to claim 1, wherein a thickness of the porous body layer is set in a range of 1 nm to 1000 nm.   The semiconductor device according to claim 1, wherein a surface of the pore is covered with a hydrophobic material. An insulating substrate;
A gate electrode formed on the insulating substrate;
The gate insulating film covering the gate electrode;
Two source / drain electrodes separately formed on the gate insulating layer;
The semiconductor device according to claim 1, further comprising: a semiconductor layer made of an organic material that covers the surface of the gate insulating film and the two source / drain electrodes. An insulating substrate;
A gate electrode formed on the insulating substrate;
The gate insulating film covering the gate electrode;
A semiconductor layer made of an organic material covering the gate insulating film;
The semiconductor device according to claim 1, further comprising two source / drain electrodes formed on the semiconductor layer so as to be separated from each other. An insulating substrate;
Two source / drain electrodes formed separately on the insulating substrate;
A semiconductor layer made of an organic material covering the two source / drain electrodes;
The gate insulating film covering the semiconductor layer;
The semiconductor device according to claim 1, further comprising a gate electrode formed on the gate insulating film. An insulating substrate;
A semiconductor layer formed on the insulating substrate;
Two source / drain electrodes formed apart from each other on the semiconductor layer;
The gate insulating film covering the semiconductor layer and the two source / drain electrodes;
The semiconductor device according to claim 1, further comprising a gate electrode formed on the gate insulating film. An image element unit;
15. The semiconductor device according to claim 1, wherein the semiconductor device is selectively turned on or off, an electric field is applied to the element portion, or carriers are injected into the element portion. And an image element unit driving means for controlling the optical properties of the image element unit. A method of manufacturing a field effect type semiconductor device including a semiconductor layer made of an organic substance,
Including a step of forming a gate insulating film comprising a porous body layer,
The gate insulating film forming step includes
Preparing a porous precursor solution comprising a surfactant;
Applying the porous precursor solution and drying to form a porous precursor film; and
Heating the porous precursor film to remove the surfactant. A method for manufacturing a semiconductor device, comprising:   17. The method of manufacturing a semiconductor device according to claim 16, wherein the step of preparing the porous precursor solution hydrolyzes the metal alkoxide to which the surfactant is added under an acidic condition to form a sol.   18. The method of manufacturing a semiconductor device according to claim 16, wherein the step of removing the surfactant is performed by heating at a temperature selected from a range of 200 ° C. to 700 ° C. 18.   18. The method of manufacturing a semiconductor device according to claim 16, wherein the step of removing the surfactant includes a process of eluting and removing the porous precursor film with a solvent.   18. The method of manufacturing a semiconductor device according to claim 16, wherein the step of removing the surfactant includes performing a plasma treatment on the porous precursor film in an ozone or oxygen atmosphere.   21. The semiconductor according to claim 16, wherein the step of preparing the porous precursor solution further comprises adding a hydrophobizing agent to the metal alkoxide to which the surfactant is added. Device manufacturing method. After the step of removing the surfactant,
21. The method of manufacturing a semiconductor device according to claim 16, further comprising a step of performing a hydrophobic treatment.