JP2005191229A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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Abstract
【解決手段】 基板10に、フリップチップ接続した半導体素子が後工程の処理で必要とする強度を保持する分量で、かつワイヤボンディング用のパッド14を覆うことがない分量のアンダーフィル樹脂20を供給する工程と、前記アンダーフィル樹脂20が供給された基板10に1段目の半導体素子18をフリップチップ接続し、前記アンダーフィル樹脂を20硬化させる工程と、2段目以降の半導体素子22を前記フリップチップ接続された半導体素子18にダイボンディングし、2段目以降の半導体素子22と前記パッド14とをワイヤボンディングする工程と、ワイヤボンディング後に、前記1段目の半導体素子18と基板10との間を、アンダーフィル樹脂20によって完全に充填する工程と、基板10の半導体素子18、22が搭載された面を樹脂封止する工程とを備える。
【選択図】 図1
Description
図2(a)は、半導体素子を搭載する基板10を示す。基板10の半導体素子搭載面には、フリップチップ接続用の接続電極12とワイヤボンディング接続用のパッド14とが設けられている。この例ではフリップチップ接続用の半導体素子18として金バンプ16を備えたものを使用するから、接続電極12の表面には、あらかじめはんだ13を被覆した基板10を使用している。
図2(c)は、次に、半導体素子18と基板10との間をアンダーフィル樹脂20によりアンダーフィルし、アンダーフィル樹脂20を硬化させた状態を示す。アンダーフィルは、半導体素子18と接続電極12との接合部が熱応力等によって剥離したりしないように、半導体素子18を確実に基板10に保持することを目的とするものである。
図2(d)は、フリップチップ接続した半導体素子18の上に、ダイボンディング材24を用いて、2段目の半導体素子22をダイ付けした状態である。
すなわち、半導体素子を基板上に複数枚積み重ねて搭載した半導体装置であって、1段目の半導体素子をフリップチップ接続によって搭載し、2段目以降の半導体素子をワイヤボンディング接続によって搭載する半導体装置の製造方法において、前記基板に、フリップチップ接続した半導体素子が後工程の処理で必要とする強度を保持する分量で、かつワイヤボンディング用のパッドを覆うことがない分量のアンダーフィル樹脂を供給する工程と、前記アンダーフィル樹脂が供給された基板に1段目の半導体素子をフリップチップ接続し、前記アンダーフィル樹脂を硬化させる工程と、2段目以降の半導体素子を前記フリップチップ接続された半導体素子にダイボンディングし、2段目以降の半導体素子と前記パッドとをワイヤボンディングする工程と、ワイヤボンディング後に、前記1段目の半導体素子と基板との間を、アンダーフィル樹脂によって完全に充填する工程と、基板の半導体素子が搭載された面を樹脂封止する工程とを備えることを特徴とする。
また、前記半導体素子をフリップチップ接続する際に基板に供給するアンダーフィル樹脂の分量を、基板に形成されたフリップチップ接続用の接続電極によって囲まれた領域を超えてアンダーフィル樹脂が漏出しない分量とすることを特徴とする。
図1は、本発明に係る半導体装置の製造方法の一実施形態を示す説明図である。なお、実際の半導体装置の製造工程においてワークとして使用する基板は、一枚で複数個の半導体装置を製造する基板として形成されているものであり、基板上にマトリクス状に半導体素子を搭載して製品とするが、図1では、説明上、単一の半導体装置を製造する単位ブロック部分について示している。
図1(b)は、基板10に1段目の半導体素子18をフリップチップ接続するため、基板10の半導体素子搭載面にアンダーフィル樹脂20を供給した状態を示す。アンダーフィル樹脂20は図のように1段目の半導体素子18を搭載する位置、すなわち半導体素子18の平面領域内にポッティングして供給する。
実際にはフリップチップボンダーで半導体素子18を支持し、ボンダーにより半導体素子18を加熱しながら基板10に押圧し、そのまま6〜10秒間程度保持することによって、はんだ13を溶融し、アンダーフィル樹脂20を熱硬化させる。
なお、半導体素子をフリップチップ接続によって搭載する方法として、電極端子にはんだバンプを設けた半導体素子を搭載する方法もある。この場合にも、本実施形態と同様にして半導体素子をフリップチップ接続によって搭載することができる。
図1(e)は、2段目の半導体素子22とパッド14との間をワイヤボンディングした状態を示す。26がボンディングワイヤである。本実施形態の製造方法においては、パッド14がアンダーフィル樹脂20によって覆われるといったことがなく、したがって半導体素子22とパッド14とのワイヤボンディング接続を確実に行うことができる。このワイヤボンディング工程では、2段目の半導体素子22とパッド14とは技術的な意味でワイヤボンディングが可能な最短距離にパッド14を配置してワイヤボンディングすることを可能にするものであり、パッド14を半導体素子22に最大限近づけてワイヤボンディングすることが可能である。
なお、2次的にアンダーフィルする際に使用するアンダーフィル樹脂20は先のアンダーフィル工程で使用したアンダーフィル樹脂20と同じ樹脂が望ましい。アンダーフィル樹脂20を注入した後、加熱炉内でアンダーフィル樹脂20を硬化させる。
なお、本実施形態の半導体装置では、基板10上に2枚の半導体素子18、22を搭載したが、半導体素子を3枚以上搭載する場合は、2段目の半導体素子22の上にさらに半導体素子をダイボンディングし、これらと基板10に設けたパッドとの間をワイヤボンディング接続するようにすればよい。
12 接続電極
14 パッド
16 金バンプ
18、22 半導体素子
20、20a アンダーフィル樹脂
24 ダイボンディング材
26 ボンディングワイヤ
28 樹脂
Claims (3)
- 半導体素子を基板上に複数枚積み重ねて搭載した半導体装置であって、1段目の半導体素子をフリップチップ接続によって搭載し、2段目以降の半導体素子をワイヤボンディング接続によって搭載する半導体装置の製造方法において、
前記基板に、フリップチップ接続した半導体素子が後工程の処理で必要とする強度を保持する分量で、かつワイヤボンディング用のパッドを覆うことがない分量のアンダーフィル樹脂を供給する工程と、
前記アンダーフィル樹脂が供給された基板に1段目の半導体素子をフリップチップ接続し、前記アンダーフィル樹脂を硬化させる工程と、
2段目以降の半導体素子を前記フリップチップ接続された半導体素子にダイボンディングし、2段目以降の半導体素子と前記パッドとをワイヤボンディングする工程と、
ワイヤボンディング後に、前記1段目の半導体素子と基板との間を、アンダーフィル樹脂によって完全に充填する工程と、
基板の半導体素子が搭載された面を樹脂封止する工程とを備えることを特徴とする半導体装置の製造方法。 - 半導体素子をフリップチップ接続する際に基板に供給するアンダーフィル樹脂の分量を、フリップチップ接続される半導体素子の平面領域を超えてアンダーフィル樹脂が漏出しない分量とすることを特徴とする請求項1記載の半導体装置の製造方法。
- 半導体素子をフリップチップ接続する際に基板に供給するアンダーフィル樹脂の分量を、基板に形成されたフリップチップ接続用の接続電極によって囲まれた領域を超えてアンダーフィル樹脂が漏出しない分量とすることを特徴とする請求項1記載の半導体装置の製造方法。
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---|---|---|---|---|
US9515057B2 (en) | 2013-11-14 | 2016-12-06 | Samsung Electronics Co., Ltd. | Semiconductor package and method of manufacturing the semiconductor package |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11168122A (ja) * | 1997-10-02 | 1999-06-22 | Matsushita Electric Ind Co Ltd | 回路基板への半導体素子の装着方法、及び半導体装置 |
JPH11219984A (ja) * | 1997-11-06 | 1999-08-10 | Sharp Corp | 半導体装置パッケージおよびその製造方法ならびにそのための回路基板 |
WO2001018864A1 (fr) * | 1999-09-03 | 2001-03-15 | Seiko Epson Corporation | Dispositif a semi-conducteurs, son procede de fabrication, carte de circuit et dispositif electronique |
JP2002237566A (ja) * | 2001-02-09 | 2002-08-23 | Matsushita Electric Ind Co Ltd | 半導体装置の3次元実装構造体とその製造方法 |
-
2003
- 2003-12-25 JP JP2003429862A patent/JP2005191229A/ja active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11168122A (ja) * | 1997-10-02 | 1999-06-22 | Matsushita Electric Ind Co Ltd | 回路基板への半導体素子の装着方法、及び半導体装置 |
JPH11219984A (ja) * | 1997-11-06 | 1999-08-10 | Sharp Corp | 半導体装置パッケージおよびその製造方法ならびにそのための回路基板 |
WO2001018864A1 (fr) * | 1999-09-03 | 2001-03-15 | Seiko Epson Corporation | Dispositif a semi-conducteurs, son procede de fabrication, carte de circuit et dispositif electronique |
JP2002237566A (ja) * | 2001-02-09 | 2002-08-23 | Matsushita Electric Ind Co Ltd | 半導体装置の3次元実装構造体とその製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9515057B2 (en) | 2013-11-14 | 2016-12-06 | Samsung Electronics Co., Ltd. | Semiconductor package and method of manufacturing the semiconductor package |
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