JP2005183689A - Support substrate, conveying body, semiconductor device, method for manufacturing the same, circuit board and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a support substrate which is used by being pasted to a processing substrate in a process of manufacturing a semiconductor device, and is suitable for the stabilization of conveyance. <P>SOLUTION: The support substrate 50 is used by being pasted to the processing substrate 10 in the process of manufacturing the semiconductor device. A light detecting film is formed on a face 50a on the opposite side of a side pasted to the processing substrate 10 in the support substrate 50. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a support substrate, a carrier, a method for manufacturing a semiconductor device, a semiconductor device, a circuit board, and an electronic device.

  Portable electronic devices such as mobile phones, notebook personal computers, and PDAs (Personal Data Assistance) are required to be smaller and lighter. Along with this, the mounting space of the semiconductor chip in the electronic device described above is also limited, and high-density mounting of the semiconductor chip has become a problem. Therefore, a three-dimensional mounting technique has been proposed in which semiconductor chips are stacked and the semiconductor chips are interconnected to achieve high-density mounting of the semiconductor chips (see, for example, Patent Document 1).

For example, there is a technique in which another substrate (support substrate) is temporarily mounted on the processed substrate in order to reinforce the processed substrate in the manufacturing process of the semiconductor chip applied to the above-described three-dimensional mounting technology. As a technique for mounting the reinforcing support substrate, for example, there is a technique in which a processed substrate and a support substrate are bonded together with a bonding material (see, for example, Patent Document 2).
JP 2002-25948 A Japanese Patent Laid-Open No. 2002-338771

  In the technique of bonding a processed substrate and a support substrate through a bonding material, the support substrate is often made of glass that transmits light for the purpose of irradiating the bonding material with light. In addition, the light irradiation with respect to the bonding material described above is used, for example, to impart energy for urging the bonding material to peel when the support substrate is peeled from the processed substrate.

  However, the detection of the glass member is unstable in a light detection sensor that is widely used in a substrate transport system. For this reason, when a processed substrate on which a support substrate made of glass is mounted is transported, the position of the processed substrate cannot be accurately detected, which may cause a transport failure.

  Further, in recent years, a suction system using electrostatic force is often used in a transport system used in the manufacturing process of a semiconductor device. However, the glass as an insulator is difficult to be electrostatically adsorbed, and there is a problem that it is difficult to stably convey a processed substrate on which a supporting substrate made of glass is mounted in a conveyance system using electrostatic adsorption technology.

This invention is made | formed in view of the said situation, and it aims at providing the support body suitable for stabilization of conveyance, and the conveyance body provided with this support substrate.
Another object of the present invention is to provide a method of manufacturing a semiconductor device using the support substrate, and a semiconductor device, a circuit board, and an electronic device manufactured using the manufacturing method.

In order to achieve the above object, the present invention employs the following configuration.
The first support substrate of the present invention is a support substrate that is used by being bonded to a processed substrate in the process of manufacturing a semiconductor device, and is provided on a surface opposite to the side bonded to the processed substrate, for light detection. This film is formed.
In the above support substrate, examples of the film include a conductor film or a semiconductor film.
In this case, it is desirable that the film is formed on the entire surface or the peripheral portion of the surface.

The second support substrate of the present invention is a support substrate that is used by being bonded to a processed substrate in the process of manufacturing a semiconductor device, and is characterized in that a process capable of electrostatic attraction is performed.
In the above support substrate, a conductor film or a semiconductor film may be formed on the surface opposite to the surface bonded to the processed substrate.
Alternatively, the support substrate may be made of glass containing impurities.

The third support substrate of the present invention is a support substrate that is used by being bonded to a processed substrate in the process of manufacturing a semiconductor device, and has a surface on the side opposite to the surface to be bonded to the processed substrate. A film for electrostatic attraction is formed.
In the above support substrate, examples of the film include a conductor film or a semiconductor film.
In this case, it is desirable that the film is formed on the entire surface or the peripheral portion of the surface.

The transport body of the present invention includes a processed substrate used in the manufacturing process of a semiconductor device, the transport support described above, and a resin layer for bonding the processed substrate and the transport support. It is characterized by that.
In this case, the resin layer is preferably made of a material having high dry etching resistance.
Alternatively, the resin layer is preferably made of a material having high thermal conductivity.

The manufacturing method of the semiconductor manufacturing apparatus of this invention has the process of performing a predetermined process with respect to a process board | substrate using the conveyance body mentioned above.
The predetermined process includes, for example, at least one of a process of mechanically polishing one surface of the processed substrate and a process of dry etching one surface of the processed substrate.
The manufacturing method including these processing steps is applied to, for example, manufacturing a semiconductor device having a semiconductor substrate on which an integrated circuit is formed and an electrode penetrating the semiconductor substrate.

The semiconductor device of the present invention is manufactured using the above-described method for manufacturing a semiconductor device.
The circuit board of the present invention is characterized in that the above-described semiconductor device is mounted.
In addition, an electronic apparatus according to the present invention includes the above-described semiconductor device.

Here, as described above, the support substrate used by being bonded to the processed substrate in the process of manufacturing the semiconductor device is often made of glass that is a transparent body and an insulator.
Even if the support substrate is a transparent body such as glass, the photodetection film is formed on the surface opposite to the side to be bonded to the processed substrate, so that the position of the support substrate is detected. It becomes possible. As a result, it is possible to detect with high accuracy the position of the transport body on which the processed substrate and the support substrate are bonded together, and to transport the transport body stably based on the detection result.

  This technique is also preferably applied to a case where the size of the support substrate is the same or larger than that of the processed substrate and the processed substrate is hidden from the detection sensor. That is, even when the size of the support substrate is the same or larger than that of the processed substrate, the position of the processed substrate can be detected well by detecting the photodetection film. In addition, since the size of the support substrate is larger than that of the processed substrate, the edge of the processed substrate is reliably prevented from protruding from the support substrate, and the processed substrate comes into contact with other objects and causes problems such as cracking. Is prevented.

  In the above support substrate, for example, when the film is a conductor film made of Al or the like, or a semiconductor film made of polysilicon (Poly-Si) or the like, good light detection can be performed.

  In this case, for example, by forming the film on the entire surface or the peripheral portion of the surface, it becomes possible to detect the position of the edge (edge) of the support substrate. It becomes possible to detect well.

  On the other hand, even when the support substrate is made of an insulator such as glass, the support substrate can be transported using an electrostatic adsorption technique because the support substrate is subjected to a process that enables electrostatic adsorption. The electrostatic adsorption technique has an advantage that it is easy to achieve stabilization of conveyance, enlargement of a processed substrate, reduction of particles, and the like.

For example, a conductive film made of Al or the like or a semiconductor film made of polysilicon (Poly-Si) or the like is formed on the surface opposite to the surface to be bonded to the processed substrate, so that the supporting substrate can be electrostatically attracted. It becomes.
Alternatively, the support substrate can be electrostatically attracted by being made of glass containing impurities.

Here, the technique of forming a conductor film made of Al or the like or a semiconductor film made of polysilicon (Poly-Si) or the like on the support substrate makes it possible to realize both light detection and electrostatic adsorption.
That is, even when the support substrate is a transparent body such as glass and is an insulator, the conductor film or the semiconductor film is formed on the surface opposite to the surface bonded to the processed substrate. Both the detection of the position of the supporting substrate and electrostatic adsorption can be performed. As a result, with this support substrate, it is possible to obtain both the advantages of light detection and the advantages of electrostatic adsorption.

  Moreover, the said support substrate is used as a conveyance body bonded together with the process board | substrate through the resin layer, for example.

  In the transport body described above, since the resin layer is made of a material having high dry etching resistance, destruction of the resin layer is suppressed in the dry etching process, and transport failures are prevented from occurring.

  Moreover, in said conveyance body, when a resin layer consists of material with high heat conductivity, the heat conductivity of the whole conveyance body improves and the improvement of the efficiency of the process accompanying the heat with respect to a process board | substrate is achieved. For example, it is possible to obtain stable etching characteristics by improving the thermal conductivity of the entire carrier in the dry etching process.

  Moreover, since the manufacturing method of the semiconductor manufacturing apparatus which uses said conveyance body can convey a conveyance body stably, stabilization of a process is achieved.

  Examples of the process using the carrier include a process of mechanically polishing one surface of the processed substrate and a process of dry-etching one surface of the processed substrate, and a manufacturing process including these processing steps is performed. Thus, for example, a semiconductor device having a semiconductor substrate on which an integrated circuit is formed and an electrode penetrating the semiconductor substrate can be manufactured.

A semiconductor device manufactured using the method for manufacturing a semiconductor device can obtain stable quality.
Similarly, the circuit board on which the semiconductor device is mounted can obtain stable quality.
Similarly, an electronic device including the semiconductor device can obtain stable quality.

Embodiments of the present invention will be described below with reference to the drawings.
Here, FIG. 1 is a perspective view schematically showing the support substrate and the transport body according to the present invention, FIG. 2 is a plan view of the transport body of FIG. 1 viewed from the back side, and FIG. FIG. 4 is a plan view showing another embodiment of the support substrate and the carrier and the carrier shown in FIG. 1 as seen from the back side, and FIG. 5 is an electrode portion of the semiconductor chip. 6 to 10 are explanatory views of a semiconductor chip manufacturing method, FIG. 11 is an explanatory view of a stacked state of a semiconductor device, FIGS. 12 and 13 are explanatory views of rewiring, and FIG. FIG. 15 is a perspective view of a mobile phone which is an example of an electronic device.
In each drawing used for the following description, the scale of each member is appropriately changed in order to make each member a recognizable size.

(Transport support and transport body)
First, an embodiment of a support substrate and a carrier according to the present invention will be described with reference to FIGS.
The support substrate 50 is formed on the semiconductor substrate 10 as a processed substrate for the purpose of reinforcing or protecting the semiconductor substrate 10 in a predetermined processing step (a polishing step and a dry etching processing step described later) in a semiconductor device manufacturing method described later. They are pasted together and used in the form of the conveyance body 55.

  The transport body 55 has a configuration in which the support substrate 50 and the semiconductor substrate 10 are integrally joined via a resin layer 52 and a release layer 53. The resin layer 52 is used to absorb unevenness on the surface of the semiconductor substrate 10 and to bond the semiconductor substrate 10 and the support substrate 50. The release layer 53 is formed from the semiconductor substrate 10 after the predetermined processing step. It is used for peeling the support substrate 50.

  In this example, glass that is a transmissive member that transmits light is used as a material for forming the support substrate 50. The reason why the glass as the transmissive member is used is to ensure that the light having the peeling energy irradiated to the back surface 50a of the support substrate 50 reaches the release layer 53 when the support substrate 50 is peeled from the semiconductor substrate 10. is there.

  The planar shape of the support substrate 50 is determined according to the semiconductor substrate 10. In this example, the planar shapes of the semiconductor substrate 10 and the support substrate 50 are both substantially circular, and the outer diameter of the support substrate 50 is larger than that of the semiconductor substrate 10. The outer diameter of the support substrate 50 is larger than that of the semiconductor substrate 10 even when the semiconductor substrate 10 and the support substrate 50 are bonded to each other, even when the center positions of both are slightly shifted. This is to prevent the edge of the protrusion from protruding. As described above, in this example, the edge of the semiconductor substrate 10 is prevented from protruding, so that, for example, the edge of the semiconductor substrate 10 is another object when the carrier 55 is transported or when the semiconductor substrate 10 is subjected to predetermined processing. Occurrence of problems such as damage due to contact with the

As shown in the plan view of FIG. 2, a film 56 that can be detected by a detection sensor used in a transfer device or a processing device is formed on the back surface 50 a of the support substrate 50. In this example, the film 56 is formed on the periphery of the back surface 50 a of the support substrate 50.
More specifically, the film 56 is formed in an annular region from the outer edge of the support substrate 50 to the outer edge of the semiconductor substrate 10 on the back surface 50 a of the support substrate 50. The formation region of the film 56 is configured in this manner, so that the position of the edge portion (edge) of the support substrate 50 can be detected, and light having peeling energy can be reliably transmitted to the entire peeling layer 53. It is to make it reach. In addition, since the position of the edge (edge) of the support substrate 50 can be detected, the position of the support substrate 50 (and the transport body 55) can be detected well.

  Here, as the film 56 for light detection, those having optical characteristics such as reflectance and light transmittance that are significantly different from those of the back surface 50a of the support substrate 50 are preferable. As an example, the transmittance is low and the reflectance is low. Examples thereof include a high conductor film such as an Al film. The conductor film can be formed using, for example, a PVD (Phisical Vapor Deposition) method such as vacuum deposition, sputtering, or ion plating, a CVD method, an IMP (ion metal plasma) method, an electroless plating method, or the like. Note that a semiconductor film made of polysilicon (Poly-Si) or the like may be used as the light detection film 56. Even if it is a film | membrane which permeate | transmits light, it should just be detectable based on the difference of the optical characteristic between the support substrates 50. The timing for forming the light detection film 56 may be before or after the semiconductor substrate 10 and the support substrate 50 are bonded to each other.

  Furthermore, the support substrate 50 of the present example can be electrostatically attracted by the formation of the light detection film 56. FIG. 3 shows a substrate holding device (electrostatic chuck) 57 using an electrostatic adsorption technique. As shown in FIG. 3, even if the support substrate 50 is an insulator, the film 56 formed on the back surface 50a of the support substrate 50 is charged, so that the support substrate 50 (and It becomes possible to electrostatically attract the carrier 55). The above-described conductor film made of Al or the like, or a semiconductor film made of polysilicon (Poly-Si) or the like can be preferably applied to such an electrostatic adsorption technique. The electrostatic adsorption technique has an advantage that it is easy to achieve stabilization of conveyance, enlargement of a processed substrate, reduction of particles, and the like.

Here, the form of the light detection film 56 is not limited to that shown in FIG.
For example, as shown in FIG. 4, the photodetection film 56 may be formed on the entire back surface 50 a of the support substrate 50. Also in this embodiment, since the position of the edge (edge) of the support substrate 50 can be detected, the position of the support substrate 50 (and the transport body 55) can be detected well. In addition, this embodiment has an advantage that the region where the film 56 is formed is wide and electrostatic adsorption is easy. In this case, if the light transmittance of the film 56 is low, the light for peeling may be blocked by the film 56. Therefore, as the light detecting film 56, polysilicon (Poly-Si) or the like is used. It is preferable to use a film that transmits light to some extent, such as a semiconductor film made of copper.

  Returning to FIG. 1, for example, a curable adhesive such as a thermosetting adhesive or a photocurable adhesive is used for the resin layer 52. The resin layer 52 is preferably made of a material having high dry etching resistance. The purpose of this is to suppress the breakage of the resin layer 52 in the dry etching process described later, and to prevent the occurrence of a conveyance failure associated therewith. Furthermore, the resin layer 52 is preferably made of a material having high thermal conductivity. This is for the purpose of improving the thermal conductivity of the entire carrier 55 and stabilizing the etching characteristics in the dry etching process described later.

  As a method for arranging the resin layer 52, various known techniques such as an inkjet method, a powder jet method, a squeezing method, a spin coating method, a spray coating method, and a roll coating method are used in addition to various printing methods. . The resin layer 52 is removed by being dissolved by a solvent or the like after the support substrate 50 is peeled from the semiconductor substrate 10.

  The peeling layer 53 is made of a material that causes peeling (also referred to as “in-layer peeling” or “interfacial peeling”) in the layer or at the interface by irradiation light such as laser light. That is, by irradiating with a certain intensity of light, the bonding force between atoms or molecules in the atoms or molecules constituting the constituent material disappears or decreases, causing ablation or the like and causing separation. is there. Further, when the component contained in the release layer 53 is released as a gas due to the irradiation of the irradiation light and is separated, the release layer 53 absorbs the light and becomes a gas, and the vapor is released and separated. May lead to.

  As a composition of the peeling layer 53, for example, amorphous silicon (a-Si) is adopted, and hydrogen (H) may be contained in the amorphous silicon. It is preferable that hydrogen is contained because hydrogen is released by light irradiation to generate an internal pressure in the peeling layer 53, which promotes peeling. In this case, the hydrogen content is preferably about 2 at% or more, more preferably 2 to 20% at%. The hydrogen content should be set appropriately for film formation conditions, such as the gas composition, gas pressure, gas atmosphere, gas flow rate, gas temperature, substrate temperature, and power to be applied when using the CVD method. Adjust by. Other release layer materials include silicon oxide or silicate compounds, nitride ceramics such as silicon nitride, aluminum nitride, and titanium nitride, organic polymer materials (those whose interatomic bonds are broken by light irradiation), A metal, for example, Al, Li, Ti, Mn, In, Sn, Y, La, Ce, Nd, Pr, Gd, or Sm, or an alloy containing at least one of them can be given.

  The formation method of the peeling layer 53 should just be a method which can form the peeling layer 53 with uniform thickness, and can be suitably selected according to various conditions, such as a composition and thickness of the peeling layer 53. FIG. For example, various vapor deposition methods such as CVD (including MOCCVD, low pressure CVD, ECR-CVD), vapor deposition, molecular beam vapor deposition (MB), sputtering, ion doping, PVD, electroplating, immersion plating (dipping) ), Various plating methods such as electroless plating method, Langmuir ProJet (LB) method, spin coating method, spray coating method, roll coating method and other coating methods, various printing methods, transfer method, ink jet method, powder jet method Applicable to etc. Of these, two or more methods may be combined.

  In particular, when the composition of the release layer 53 is amorphous silicon (a-Si), it is preferable to form a film by a CVD method, particularly low-pressure CVD or plasma CVD. Further, when the release layer 53 is formed by using a ceramic by a sol-gel method or is formed of an organic polymer material, it is preferably formed by a coating method, particularly by spin coating.

  As described above, according to the transport body 55 configured as described above, the film 56 for light detection and electrostatic attraction is formed on the back surface 50a of the support substrate 50, and thus the transport and processing are stabilized. It has been.

  In the transport body 55 described above, the resin layer 52 and the release layer 53 are separate layers, but they may be combined into one layer. That is, as a layer for joining the semiconductor substrate 10 and the support substrate 50, a layer having an adhesive force and an effect of causing peeling by light, heat energy, or the like may be used. In this case, it is preferable to apply the technique described in JP-A-2002-338771 described above.

  Further, soda glass may be used as a material for forming the support substrate 50. Since soda glass contains many impurities such as Al and Fe, it can be electrostatically adsorbed without forming a conductor film or a semiconductor film.

(Semiconductor device)
Next, a semiconductor chip which is an embodiment of the semiconductor device according to the present invention will be described with reference to FIG.
FIG. 5 is a side sectional view of the electrode portion of the semiconductor chip according to the present embodiment. The semiconductor chip 2 according to the present embodiment includes a first insulating material in a semiconductor substrate 10 on which an integrated circuit is formed and a through hole H4 formed from the active surface 10a of the semiconductor substrate 10 to the back surface 10b of the semiconductor substrate 10. And an electrode 34 formed through an insulating film 22 as a layer.

  In the semiconductor chip 2 shown in FIG. 5, an integrated circuit (not shown) made of transistors, memory elements, and other electronic elements is formed on the surface 10a of the semiconductor substrate 10 made of Si (silicon) or the like. On the active surface 10a of the semiconductor substrate 10, an insulating film 12 made of SiO2 (silicon oxide) or the like is formed. Further, an interlayer insulating film 14 made of borophosphosilicate glass (hereinafter referred to as BPSG) or the like is formed on the surface of the insulating film 12.

  An electrode pad 16 is formed on a predetermined portion of the surface of the interlayer insulating film 14. The electrode pad 16 includes a first layer 16a made of Ti (titanium) or the like, a second layer 16b made of TiN (titanium nitride) or the like, a third layer 16c made of AlCu (aluminum / copper) or the like, and TiN or the like. The fourth layer (cap layer) 16d is formed by sequentially stacking. Note that the constituent material of the electrode pad 16 may be appropriately changed according to the electrical characteristics, physical characteristics, and chemical characteristics required for the electrode pad 16. That is, the electrode pad 16 may be formed using only Al generally used as an electrode of the integrated circuit, or the electrode pad 16 may be formed using only Cu having a low electric resistance.

  The electrode pads 16 are formed side by side in the periphery of the semiconductor chip 2 in plan view. The electrode pad 16 may be formed side by side in the periphery of the semiconductor chip 2 or may be formed side by side in the center. When formed in the peripheral portion, the semiconductor chip 2 is formed side by side along at least one side (in many cases, two or four sides). Each electrode pad 16 is electrically connected to the integrated circuit described above at a location not shown. Note that no integrated circuit is formed below the electrode pad 16.

  A passivation film 18 is formed on the surface of the interlayer insulating film 14 so as to cover the electrode pad 16. The passivation film 18 is made of SiO2 (silicon oxide), SiN (silicon nitride), polyimide resin, or the like, and has a thickness of, for example, about 1 μm.

  An opening H1 of the passivation film 18 and an opening H2 of the electrode pad 16 are formed at the center of the electrode pad 16. The diameter of the opening H2 is smaller than the diameter of the opening H1, and is set to about 60 μm, for example. The fourth layer 16d in the electrode pad 16 is opened with the same diameter as the opening H1. On the other hand, an insulating film 20 made of SiO2 (silicon oxide) or the like is formed on the surface of the passivation film 18 and the inner surfaces of the opening H1 and the opening H2.

  A hole H3 penetrating the insulating film 20, the interlayer insulating film 14, the insulating film 12, and the semiconductor substrate 10 is formed in the central portion of the electrode pad 16. The diameter of the hole H3 is smaller than the diameter of the opening H2, for example, about 30 μm. The hole H3 is not limited to a circular shape in plan view, and may be formed in a rectangular shape in plan view. The opening H1, the opening H2, and the hole H3 form a through hole H4 that penetrates from the active surface to the back surface of the semiconductor substrate.

  An insulating film 22 as a first insulating layer is formed on the inner surface of the through hole H4 and the surface of the insulating film 20. The insulating film 22 prevents current leakage, erosion due to oxygen, moisture, and the like, and is formed to a thickness of about 1 μm. The insulating film 22 is formed so as to protrude from the back surface 10 b of the semiconductor substrate 10. On the other hand, the insulating film 20 and the insulating film 22 formed on the surface of the third layer 16c of the electrode pad 16 are partially removed along the periphery of the opening H2.

  A base film 24 is formed on the exposed surface of the third layer 16 c of the electrode pad 16 and the remaining surface of the insulating film 22. The base film 24 includes a barrier layer (barrier metal) formed on the surface of the insulating film 22 and the like, and a seed layer (seed electrode) formed on the surface of the barrier layer. The barrier layer prevents the constituent material of the electrode 34 described later from diffusing into the substrate 10 and is made of TiW (titanium tungsten), TiN (titanium nitride), TaN (tantalum nitride), or the like. On the other hand, the seed layer serves as an electrode when an electrode 34 described later is formed by plating, and is made of Cu, Au, Ag, or the like.

  An electrode 34 is formed inside the base film 24. The electrode 34 is made of a conductive material having a low electrical resistance such as Cu or W. Note that if the electrode 34 is formed of a conductive material in which poly-Si (polysilicon) is doped with impurities such as B and P, it is not necessary to prevent diffusion to the substrate 10, so that the barrier layer described above becomes unnecessary. . And the plug part 36 of the electrode 34 is formed by forming the electrode 34 in the through-hole H4. Note that the plug portion 36 and the electrode pad 16 are electrically connected via the base film 24 at the P portion in FIG. Further, the lower end surface of the plug portion 36 is exposed to the outside. On the other hand, the post part 35 of the electrode 34 is formed by extending the electrode 34 above the passivation film 18 and also at the peripheral part of the opening H1. The post portion 35 is not limited to a circular shape in plan view, and may be formed in a rectangular shape in plan view.

  In the present embodiment, the tip end surface of the plug portion 36 of the electrode 34 on the back side of the substrate 10 is formed so as to protrude from the back surface 10 b of the semiconductor substrate 10. The protruding height of the plug part 36 is, for example, about 10 μm to 20 μm. Thereby, when laminating a plurality of semiconductor chips, a space between the semiconductor chips can be ensured, so that the gaps between the semiconductor chips can be easily filled with underfill or the like. Note that by adjusting the protruding height of the plug portion 36, the interval between the stacked semiconductor chips can be adjusted. Further, instead of filling underfill or the like after the lamination, even when a thermosetting resin or the like is applied to the back surface 10b of the semiconductor chip 2 before the lamination, the thermosetting resin or the like is applied while avoiding the protruding plug portion 36. Therefore, the semiconductor chip wiring connection can be reliably performed.

  On the other hand, a solder layer 40 is formed on the upper surface of the post portion 35 of the electrode 34. The solder layer 40 may be formed of a general PbSn alloy or the like, but is preferably formed of a lead-free solder material such as an AgSn alloy from the viewpoint of the environment. Instead of the solder layer 40 which is a soft wax material, a hard wax material (molten metal) layer made of SnAg alloy or the like, or a metal paste layer made of Ag paste or the like may be formed. It is preferable from the viewpoint of the environment and the like that the hard wax material layer and the metal paste layer are also formed of a lead-free material. The semiconductor chip 2 according to the present embodiment is configured as described above.

(Method for manufacturing semiconductor device)
Next, the semiconductor chip manufacturing method according to the present embodiment will be described with reference to FIGS. 6 to 10 are explanatory diagrams of the semiconductor chip manufacturing method according to the present embodiment. In the following, a case where a plurality of semiconductor chip formation regions in a semiconductor substrate are simultaneously processed will be described as an example. However, the following processing may be performed on each semiconductor chip.

  First, as shown in FIG. 6A, the insulating film 12 and the interlayer insulating film 14 are formed on the surface of the semiconductor substrate 10. Then, an electrode pad 16 is formed on the surface of the interlayer insulating film 14. Specifically, first, the first to fourth layers of the electrode pad 16 are sequentially formed on the entire surface of the interlayer insulating film 14. Each film is formed by sputtering or the like. Next, a resist or the like is applied to the surface. Further, the final shape of the electrode pad 16 is patterned on the resist by photolithography. Then, etching is performed using the patterned resist as a mask to form electrode pads in a predetermined shape (for example, a rectangular shape). Thereafter, a passivation film 18 is formed on the surface of the electrode pad 16.

  Next, an opening H <b> 1 is formed in the passivation film 18. Specifically, a resist or the like is first applied to the entire surface of the passivation film. The resist may be a photoresist, an electron beam resist, an X-ray resist, or the like, and may be either a positive type or a negative type. The resist is applied by spin coating, dipping, spray coating, or the like. Note that pre-baking is performed after the resist is applied. Then, the resist is exposed using a mask in which the pattern of the opening H1 is formed, and further developed to pattern the shape of the opening H1 in the resist. Note that post-baking is performed after resist patterning.

  Then, the passivation film 18 is etched using the patterned resist as a mask. In the present embodiment, the fourth layer of the electrode pad 16 is also etched together with the passivation film 18. For etching, wet etching can be employed, but dry etching is preferably employed. The dry etching may be reactive ion etching (RIE). Note that after the opening H1 is formed in the passivation film 18, the resist on the passivation film 18 is stripped with a stripping solution. As described above, as shown in FIG. 6A, the opening H1 is formed in the passivation film 18, and the electrode pad 16 is exposed.

  Next, as illustrated in FIG. 6B, an opening H <b> 2 is formed in the electrode pad 16. Specifically, a resist or the like is applied to the entire exposed electrode pad 16 and passivation film 18 to pattern the shape of the opening H2. Next, the electrode pad 16 is dry-etched using the patterned resist as a mask. Note that RIE can be used for dry etching. Thereafter, when the resist is peeled off, an opening H2 is formed in the electrode pad 16 as shown in FIG.

  Next, as illustrated in FIG. 6C, an insulating film 20 is formed on the entire upper surface of the substrate 10. The insulating film 20 functions as a mask when the hole H3 is drilled in the substrate 10 by dry etching. The film thickness of the insulating film 20 is set to about 2 μm, for example, depending on the depth of the hole H3 drilled in the substrate 10. In this embodiment, SiO2 is used as the insulating film 20, but a photoresist may be used as long as the selection ratio with Si can be obtained. The insulating film 20 is made of tetraethyl orthosilicate (Si (OC2H5) 4: hereinafter referred to as TEOS), that is, PE-TEOS, or ozone formed by PECVD (Plasma Enhanced Chemical Vapor Deposition). It is possible to use O3-TEOS which is the thermal CVD used, or silicon oxide formed using CVD.

  Next, the shape of the hole H3 is patterned in the insulating film 20. Specifically, a resist or the like is first applied to the entire surface of the insulating film 20, and the shape of the hole H3 is patterned. Next, the insulating film 20, the interlayer insulating film 14, and the insulating film 12 are dry-etched using the patterned resist as a mask. Thereafter, if the resist is peeled off, the shape of the hole H3 is patterned in the insulating film 20 and the like, and the substrate 10 is exposed.

  Next, the hole H3 is drilled in the substrate 10 by high-speed dry etching. Note that RIE or ICP (Inductively Coupled Plasma) can be used as dry etching. At this time, as described above, the insulating film 20 (SiO2) is used as a mask, but a resist may be used as a mask instead of the insulating film 20. The depth of the hole H3 is appropriately set according to the thickness of the semiconductor chip to be finally formed. That is, the depth of the hole H3 is set so that the tip of the electrode formed inside the hole H3 can be exposed on the back surface of the substrate 10 after the semiconductor chip is etched to the final thickness. As a result, the hole H3 is formed in the substrate 10 as shown in FIG. A recess H0 is formed from the active surface of the substrate 10 to the inside by the opening H1, the opening H2, and the hole H3.

  Next, as illustrated in FIG. 7A, an insulating film 22 that is a first insulating layer is formed on the inner surface of the recess H <b> 0 and the surface of the insulating film 20. The insulating film 22 is made of, for example, PE-TEOS or O3-TEOS, and is formed to have a surface film thickness of about 1 μm by, for example, plasma TEOS.

  Next, anisotropic etching is performed on the insulating film 22 and the insulating film 20 to expose a part of the electrode pad 16. In the present embodiment, a part of the surface of the electrode pad 16 is exposed along the periphery of the opening H2. Specifically, a resist or the like is first applied to the entire surface of the insulating film 22, and the exposed portion is patterned. Next, the insulating film 22 and the insulating film 20 are anisotropically etched using the patterned resist as a mask. For this anisotropic etching, it is preferable to use dry etching such as RIE. As a result, the state shown in FIG.

  Next, as shown in FIG. 7B, a base film 24 is formed on the exposed surface of the electrode pad 16 and the remaining surface of the insulating film 22. As the base film 24, a barrier layer is first formed, and a seed layer is formed thereon. The barrier layer and the seed layer are formed using, for example, a PVD (Phisical Vapor Deposition) method such as vacuum deposition, sputtering, or ion plating, a CVD method, an IMP (ion metal plasma) method, an electroless plating method, or the like.

  Next, as shown in FIG. 8A, the electrode 34 is formed. Specifically, a resist 32 is first applied on the entire upper surface of the substrate 10. As the resist 32, a liquid resist for plating or a dry film can be employed. In addition, although it is possible to use a resist used when etching an Al electrode generally provided in a semiconductor device or an insulating resin resist, it has resistance to a plating solution and an etching solution used in a process described later. That is the premise.

  The resist 32 is applied by a spin coating method, a dipping method, a spray coating method, or the like. Here, the thickness of the resist 32 is set to be approximately the same as the height of the post portion 35 of the electrode 34 to be formed plus the thickness of the solder layer 40. Note that pre-baking is performed after the resist 32 is applied.

  Next, the resist 32 is patterned according to the planar shape of the post portion 35 of the electrode 34 to be formed. Specifically, the resist 32 is patterned by performing exposure processing and development processing using a mask on which a predetermined pattern is formed. Here, if the post portion 35 has a rectangular planar shape, a rectangular opening is patterned in the resist 32. The size of the opening is set according to the pitch of the electrodes 34 in the semiconductor chip, and is formed to have a size of 120 μm square or 80 μm square, for example. Further, the size of the opening is set so that the resist 32 does not fall after patterning.

  The method for forming the resist 32 so as to surround the post portion 35 of the electrode 34 has been described above. However, the resist 32 is not necessarily formed so as to surround the entire circumference of the post portion 35. For example, when the electrodes 34 are formed adjacent to each other only in the left-right direction of the paper surface of FIG. 8A, the resist 32 need not be formed in the depth direction of the paper surface. As described above, the resist 32 is formed along at least a part of the outer shape of the post portion 35.

  In addition, the method for forming the resist 32 using the photolithography technique has been described above. However, when the resist 32 is formed by this method, when the resist is applied to the entire surface, a part of the resist may enter the hole H3 and remain as a residue in the hole H3 even if development processing is performed. Therefore, it is preferable to form the resist 32 in a patterned state by using, for example, a dry film or a printing method such as screen printing. Alternatively, the resist 32 may be formed in a patterned state by discharging a droplet of a resist only to a position where the resist 32 is formed using a droplet discharge device such as an inkjet device. Thereby, the resist 32 can be formed without entering the hole H3.

  Next, using this resist 32 as a mask, the electrode material is filled into the recess H0 to form the electrode. The electrode material is filled by a plating process, a CVD method, or the like. For the plating process, for example, an electrochemical plating (ECP) method is used. Note that a seed layer constituting the base film 24 is used as an electrode in the plating process. Moreover, a cup type plating apparatus is used as the plating apparatus. The cup-type plating apparatus is an apparatus that performs plating by ejecting a plating solution from a cup-shaped container. Thereby, the electrode material is filled in the recess H0, and the plug portion 36 is formed. Further, the opening formed in the resist 32 is also filled with the electrode material, and the post portion 35 is formed.

  Next, a solder layer 40 is formed on the upper surface of the electrode 34. The solder layer 40 is formed by a solder plating method or a printing method such as screen printing. A seed layer constituting the base film 24 can be used as an electrode for solder plating. Moreover, a cup type plating apparatus can be used as the plating apparatus. On the other hand, a hard wax material layer made of SnAg or the like may be formed instead of the solder layer 40. The hard wax material layer can also be formed by a plating method or a printing method. As a result, the state shown in FIG.

  Next, as shown in FIG. 8B, the resist 32 is stripped (removed) using a stripping solution or the like. Note that ozone water or the like can be used as the stripping solution. Subsequently, the base film 24 exposed above the substrate 10 is removed. Specifically, a resist or the like is first applied to the entire upper surface of the substrate 10 and the shape of the post portion 35 of the electrode 34 is patterned. Next, the base film 24 is dry-etched using the patterned resist as a mask. When a hard wax material layer is formed instead of the solder layer 40, the base film 24 can be etched using the hard wax material layer as a mask. In this case, since photolithography is not required, the manufacturing process can be simplified.

  Next, as shown in FIG. 9A, the substrate 10 is turned upside down and the support substrate 50 described above is mounted below the substrate 10. That is, the release layer 53 described above is formed in advance on the support substrate 50 and bonded to the substrate 10 via the resin layer 52 described above. That is, the resin layer 52 firmly bonds the substrate 10 and the support substrate 50 while absorbing irregularities on the active surface 10 a of the substrate 10. By adopting the form of the transport body 55 in which the support substrate 50 is mounted on the substrate 10, when the substrate 10 is transported or when the back surface 10 b of the substrate 10 is processed, the substrate 10 is cracked due to contact with other objects. Can be prevented.

  Next, as shown in FIG. 9B, the back surface 10b of the substrate 10 is mechanically polished to reduce the thickness of the substrate 10. Thereafter, the entire surface of the back surface 10 b of the substrate 10 is etched to expose the tip of the insulating film 22, and the tip of the electrode 34 is disposed outside the back surface 10 b of the substrate 10. For this etching, either wet etching or dry etching may be used, but in this example, dry etching is used.

  Here, in the dry etching process, the support substrate 50 is bonded to the substrate 10, so that the cooling rate tends to decrease, and as a result, the etching characteristics such as the etching rate may become unstable. In this example, since the resin layer 52 is made of a material having high thermal conductivity, the thermal conductivity of the entire transport body 55 is improved, and stable etching characteristics can be obtained. In addition, since the resin layer 52 is made of a material having high dry etching resistance, the resin layer 52 is prevented from being damaged by etching and the occurrence of a conveyance failure is prevented. Note that the insulating film 22 and the base film 24 may be etched and removed simultaneously with the etching of the substrate 10.

  Next, as shown in FIG. 10, the tip of the electrode 34 is exposed. Specifically, the insulating film 22 and the base film 24 covering the tip of the electrode 34 are removed, and the tip of the electrode 34 is exposed. The insulating film 22 and the base film 24 are removed by CMP (Chemical and Mechanical Polishing) polishing or the like. In CMP, the substrate is polished by a balance between mechanical polishing of the substrate by a polishing cloth and chemical action by a polishing liquid supplied thereto. Note that the tip of the electrode 34 may be polished when the insulating film 22 and the base film 24 are removed by polishing. In this case, since the base film 24 is completely removed, it is possible to prevent poor conduction between the electrodes when the semiconductor chips are stacked.

  Then, the light for peeling is irradiated from the back surface 10b of the board | substrate 10, and the board | substrate 10 and the support substrate 50 are isolate | separated. Further, the resin layer 52 is removed from the substrate 10 by dissolution using a solvent or the like. Next, a dicing tape (not shown) is attached to the back surface 10b of the substrate 10, and then the substrate 10 is diced to be separated into individual semiconductor chips. Note that the substrate 10 may be cut by irradiation with CO2 laser or YAG laser. Thus, the state shown in FIG. 5 is obtained, and the semiconductor chip 2 according to the present embodiment is completed.

(Laminated structure)
The semiconductor chips 2 formed as described above are stacked to form a three-dimensionally mounted semiconductor device. FIG. 11 is a side cross-sectional view showing a state in which the semiconductor chips according to the present embodiment are stacked. Each of the semiconductor chips 2a and 2b is arranged so that the lower end surface of the plug portion of the electrode 34 in the upper semiconductor chip 2a is positioned on the upper surface of the post portion of the electrode 34 in the lower semiconductor chip 2b. Then, the electrodes 34 in the respective semiconductor chips 2a and 2b are joined to each other through the solder layer 40. Specifically, the semiconductor chips 2a and 2b are pressed against each other while the solder layer 40 is dissolved by reflow. As a result, a solder alloy is formed at the joint between the solder layer 40 and the electrode 34, and both are mechanically and electrically joined. Thus, the semiconductor chips 2a and 2b are connected by wiring. If necessary, an underfill is filled in the gaps between the stacked semiconductor chips.

(Relocation wiring)
In order to mount the semiconductor device stacked as described above on the circuit board, it is desirable to perform rewiring. First, rewiring will be briefly described. FIG. 12 is an explanatory diagram of the rewiring of the semiconductor chip. Since a plurality of electrodes 62 are formed along the opposite side of the surface of the semiconductor chip 61 shown in FIG. 12A, the pitch between adjacent electrodes is narrowed. When such a semiconductor chip 61 is mounted on a circuit board, adjacent electrodes may be short-circuited. Therefore, in order to widen the pitch between the electrodes, rewiring is performed to draw out the plurality of electrodes 62 formed along the opposite sides of the semiconductor chip 61 to the center.

  FIG. 12B is a plan view of the semiconductor chip on which rewiring has been performed. A plurality of circular electrode pads 63 are arranged on the matrix at the center of the surface of the semiconductor chip 61. Each electrode pad 63 is connected to one or a plurality of electrodes 62 by rewiring 64. As a result, the narrow-pitch electrodes 62 are drawn out to the central portion, and the pitch is increased.

  FIG. 13 is a side cross-sectional view taken along line AA in FIG. A solder resist 65 is formed at the center of the bottom surface of the semiconductor chip 61 that is the lowermost layer by inverting the stacked semiconductor device as described above. A rewiring 64 is formed from the post portion of the electrode 62 to the surface of the solder resist 65. An electrode pad 63 is formed at the end of the rewiring 64 on the solder resist 65 side, and a bump 78 is formed on the surface of the electrode pad. The bump 78 is, for example, a solder bump and is formed by a printing method or the like. A reinforcing resin 66 and the like are molded on the entire bottom surface of the semiconductor chip 61.

(Circuit board)
FIG. 14 is a perspective view of a circuit board. In FIG. 14, the semiconductor device 1 formed by stacking semiconductor chips is mounted on a circuit board 1000. Specifically, bumps formed on the lowermost semiconductor chip in the semiconductor device 1 are mounted by performing reflow, FCB (Flip Chip Bonding), or the like on the electrode pads formed on the surface of the circuit board 1000. Has been. The semiconductor device 1 may be mounted with an anisotropic conductive film or the like sandwiched between the circuit board.

(Electronics)
Next, an example of an electronic device including the above-described semiconductor device is described with reference to FIGS. FIG. 15 is a perspective view of a mobile phone. The semiconductor device described above is arranged inside the housing of the mobile phone 300.

  Note that the semiconductor device described above can be applied to various electronic devices other than mobile phones. For example, LCD projectors, multimedia-compatible personal computers (PCs) and engineering workstations (EWS), pagers, word processors, TVs, viewfinder type or monitor direct view type video tape recorders, electronic notebooks, electronic desk calculators, car navigation systems The present invention can be applied to electronic devices such as a device, a POS terminal, and a device provided with a touch panel.

  It should be noted that an electronic component can be manufactured by replacing the “semiconductor chip” in the above-described embodiment with an “electronic element”. Examples of electronic components manufactured using such electronic elements include optical elements, resistors, capacitors, coils, oscillators, filters, temperature sensors, thermistors, varistors, volumes, and fuses.

  The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, but it goes without saying that the present invention is not limited to such examples. Various shapes, combinations, and the like of the constituent members shown in the above-described examples are examples, and various modifications can be made based on design requirements and the like without departing from the gist of the present invention.

The perspective view which shows typically the support substrate and conveyance body which concern on this invention. The top view which looked at the conveyance body of FIG. 1 from the back surface side. The figure which shows the board | substrate holding | maintenance apparatus using an electrostatic adsorption technique. The top view which showed the other example of the support substrate and the conveyance body, and looked at the conveyance body of FIG. 1 from the back surface side. Side surface sectional drawing of the electrode part of a semiconductor chip. Explanatory drawing of the manufacturing method of a semiconductor chip. Explanatory drawing of the manufacturing method of a semiconductor chip. Explanatory drawing of the manufacturing method of a semiconductor chip. Explanatory drawing of the manufacturing method of a semiconductor chip. Explanatory drawing of the manufacturing method of a semiconductor chip. 3 is an explanatory diagram of a stacked state of a semiconductor device. Explanatory drawing of rewiring. Explanatory drawing of rewiring. An explanatory view of a circuit board. The perspective view of the mobile telephone which is an example of an electronic device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 2 ... Semiconductor chip, 10 ... Semiconductor substrate (processed substrate), 34 ... Electrode, 50 ... Support substrate, 50a ... Back surface (surface), 52 ... Resin layer, 53 ... Release layer, 55 ... Carrier, 56 ... Film.

Claims (18)

A support substrate used by being bonded to a processed substrate in the process of manufacturing a semiconductor device,
A support substrate, wherein a film for light detection is formed on a surface opposite to a side to be bonded to the processed substrate.   The support substrate according to claim 1, wherein the film is a conductor film or a semiconductor film.   The support substrate according to claim 1, wherein the film is formed on an entire surface or a peripheral portion of the surface. A support substrate used by being bonded to a processed substrate in the process of manufacturing a semiconductor device,
A support substrate that has been subjected to a process capable of electrostatic attraction.   The support substrate according to claim 4, wherein a conductor film or a semiconductor film is formed on a surface opposite to a surface to be bonded to the processed substrate.   The support substrate according to claim 4, wherein the support substrate is made of glass containing impurities. A support substrate used by being bonded to a processed substrate in the process of manufacturing a semiconductor device,
A support substrate, wherein a film for light detection and electrostatic attraction is formed on a surface opposite to a surface to be bonded to the processed substrate.   The support substrate according to claim 7, wherein the film is a conductor film or a semiconductor film.   The support substrate according to claim 7, wherein the film is formed on the entire surface or a peripheral portion of the surface.   A processed substrate used in a manufacturing process of a semiconductor device, a transport support according to any one of claims 1 to 9, and a resin layer for bonding the processed substrate and the transport support. A carrier characterized by comprising a carrier.   The transport body according to claim 10, wherein the resin layer is made of a material having high dry etching resistance.   The transport body according to claim 10 or 11, wherein the resin layer is made of a material having high thermal conductivity.   A method for manufacturing a semiconductor manufacturing apparatus, comprising a step of performing a predetermined process on a processed substrate using the carrier according to claim 10.   The semiconductor device according to claim 13, wherein the predetermined process includes at least one of a process of mechanically polishing one surface of the processed substrate and a process of dry-etching one surface of the processed substrate. Production method.   15. The method of manufacturing a semiconductor device according to claim 14, wherein a semiconductor device having a semiconductor substrate on which an integrated circuit is formed and an electrode penetrating the semiconductor substrate is manufactured. A semiconductor device manufactured using the method for manufacturing a semiconductor device according to claim 13. A circuit board on which the semiconductor device according to claim 16 is mounted. An electronic apparatus comprising the semiconductor device according to claim 16.

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