JP2005182337A - Signal processor and recording/reproducing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal processor for safely and efficiently executing the data transfer of a digital signal whose copyright should be protected. <P>SOLUTION: This signal processor is provided with first and second encrypting/decrypting parts (109, 110) for encrypting/decoding a digital signal to be inputted/outputted, a memory (104) for temporarily storing the digital signal and an arbiter (adjusting part) (103) for arbitrating the digital signal, and for processing it in time-division manner. The arbiter is configured to execute in parallel the encryption processing and the decryption processing in the first and second encrypting/decrypting parts in time-division manner. The recording/reproducing parts (200, 300) record/reproduce the encrypted signal, and the encrypted signal is transmitted on a PCI bus (410). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a signal processing device that performs encryption / decryption processing of input / output digital signals and a recording / reproducing device using the same.

  In recent years, instead of home video tape recorders, so-called HDD recorders using a hard disk as a recording medium are rapidly spreading. In particular, there is a great demand for an integrated recorder that can perform recording and reproduction on a recording optical disk such as a DVD-RAM (Digital Versatile Disc Random Access Memory). When a hard disk and a recordable optical disk are combined, the received program is temporarily recorded on the hard disk, and the favorite program among them is copied or moved for storage, and the data on the hard disk is deleted. Usability is improved.

  A device for recording and reproducing such a digital signal can record a large amount of digitized content, so that a video signal or the like can be easily copied and has no deterioration. Is essential.

  A technology that can be used for copyright protection is content encryption. As an example of copyright protection, Patent Document 1 discloses a PCI bus by encrypting a portion of a stream that requires copyright protection in order to prevent a stream transferred over a computer bus from being illegally copied. Techniques for transferring the above are disclosed.

JP 2001-86481 A

  In the digital recorder combining the hard disk and the recordable optical disc, the content on the data bus in the apparatus needs to be encrypted in addition to the content on the medium for copyright protection. When recording and reproducing content between two media, encryption / decryption processing must be performed efficiently.

  An object of the present invention is to solve the above-described problems and to provide an apparatus that efficiently performs data transfer of a digital signal to be copyright protected.

  In order to solve such problems, the present invention provides an input unit to which a digital signal is input, an output unit to which a digital signal is output, an input / output bus unit to which digital signals and control signals are input and output, and the input A first and second encryption / decryption unit for encrypting and decrypting the digital signal input / output through the output unit and the input / output bus unit, a memory for temporarily storing the digital signal, and the input unit The output unit, the input / output bus unit, the first and second encryption / decryption units, and an arbitration unit that arbitrates a digital signal between the memory and the time division processing, and is input to the input / output bus unit. And a control unit that controls the first and second encryption / decryption units, the arbitration unit, the input unit, the output unit, and the input / output bus unit. The arbitration unit performs the time-division parallel processing of encryption processing and decryption processing in the first and second encryption / decryption units.

  According to the present invention, it is possible to provide an apparatus that suitably performs data transfer of a digital signal to be copyright protected.

  Embodiments of a signal processing apparatus according to the present invention and a recording / reproducing apparatus using the same will be described below.

  FIG. 1 is a block diagram showing an embodiment of a signal processing apparatus according to the present invention. 100 is a signal processing device, 101 is an input terminal for inputting a digital signal, and 102 is an output terminal for outputting a digital signal. Reference numeral 111 denotes an input / output bus terminal for inputting / outputting digital signals and control signals. A memory 104 temporarily stores digital signals. Reference numeral 103 denotes an arbiter (arbitration unit) that processes writing to and reading from the memory 104 in a time-sharing manner. An input interface unit 105 receives a digital signal input from the input terminal 101 and passes it to the arbiter 103, and an output interface unit 106 outputs the digital signal received from the arbiter 103 to the output terminal 102. An input / output bus interface unit 107 inputs / outputs digital signals between the arbiter 103 and the input / output bus terminal 111, and inputs a control signal from a host (not shown) to the control unit 108. For example, a peripheral component (PCI) (Peripheral Component) An Interconnect bus is used. Reference numerals 109 and 110 denote encryption / decryption units that perform digital signal encryption / decryption processing, and 108 controls the input interface unit 105, the output interface 106, the arbiter 103, the encryption / decryption unit 109, the encryption / decryption unit 110, and the input / output bus interface unit 107. In particular, it is a controller.

  Here, an operation of outputting a digital signal input from the input terminal 101 to the input / output bus terminal 111 will be described. As described above, the control signal from the host is supplied from the input / output bus interface unit 107 to the control unit 108 via the input / output bus terminal 111. The control unit 108 analyzes and controls the received control signal.

  First, a digital signal input from the input interface unit 105 via the input terminal 101 is stored in the memory 104 via the arbiter 103. Here, when the received control signal instructs encryption by the encryption / decryption unit 109, the digital signal stored in the memory 104 is once read by the arbiter 103, encrypted by the encryption / decryption unit 109, and again. Stored in the memory 104. Subsequently, the arbiter 103 supplies the digital signal encrypted by the encryption / decryption unit 109 and stored in the memory 104 to the input / output bus interface unit 107, and the digital signal is output from the input / output bus terminal 111.

  When the received control signal instructs encryption by the encryption / decryption unit 110, the digital signal stored in the memory 104 is once read by the arbiter 103, encrypted by the encryption / decryption unit 110, and again. Stored in the memory 104. Subsequently, the arbiter 103 supplies the digital signal encrypted by the encryption / decryption unit 110 and stored in the memory 104 to the input / output bus interface unit 107, and the digital signal is output from the input / output bus terminal 111.

  Further, when the received control signal does not instruct encryption, the digital signal input from the input interface unit 105 and stored in the memory 104 is read from the arbiter 103 and supplied to the input / output bus interface unit 107. A digital signal is output from the input / output bus terminal 111.

  Next, an operation of outputting a digital signal input from the input / output bus terminal 111 to the output terminal 102 will be described. As described above, the control signal from the host is supplied from the input / output bus interface unit 107 to the control unit 108 via the input / output bus terminal 111. The control unit 108 analyzes and controls the received control signal.

  First, a digital signal input from the input / output bus interface unit 107 via the input / output bus terminal 111 is stored in the memory 104 via the arbiter 103. Here, when the received control signal instructs the decryption by the encryption / decryption unit 109, the digital signal stored in the memory 104 is once read by the arbiter 103, decrypted by the encryption / decryption unit 109, and again. Stored in the memory 104. Subsequently, the arbiter 103 supplies the digital signal decrypted by the encryption / decryption unit 109 and stored in the memory 104 to the output interface unit 106, and the digital signal is output from the output terminal 102.

  Further, when the received control signal instructs the decryption by the encryption / decryption unit 110, the digital signal stored in the memory 104 is once read by the arbiter 103, decrypted by the encryption / decryption unit 110, and again. Stored in the memory 104. Subsequently, the arbiter 103 supplies the digital signal decrypted by the encryption / decryption unit 110 and stored in the memory 104 to the output interface unit 106, and the digital signal is output from the output terminal 102.

  Further, when the received control signal does not instruct decoding, a digital signal input from the input / output bus interface unit 107 and stored in the memory 104 is read from the arbiter 103 and supplied to the output interface 102. A digital signal is output from the output terminal 102.

  Next, an operation of decrypting and encrypting a digital signal input from the input / output bus terminal 111 and outputting it again to the input / output bus terminal 111 will be described. As described above, the control signal from the host is supplied from the input / output bus interface unit 107 to the control unit 108 via the input / output bus terminal 111. The control unit 108 analyzes and controls the received control signal.

  First, a digital signal input from the input / output bus interface unit 107 via the input / output bus terminal 111 is stored in the memory 104 via the arbiter 103. Here, the digital signal stored in the memory 104 is once read by the arbiter 103, decrypted by the encryption / decryption unit 109, and stored in the memory 104 again. Further, the digital signal decrypted and stored by the encryption / decryption unit 109 is read, encrypted by the encryption / decryption unit 110 and stored again in the memory 104. Subsequently, the arbiter 103 supplies the digital signal encrypted by the encryption / decryption unit 110 and stored in the memory 104 to the input / output bus interface unit 107, and the digital signal is output from the input / output bus terminal 111.

  A case will be described in which the above-described operations are processed in parallel in a time-sharing manner. A control signal from the host is supplied from the input / output bus interface unit 107 to the control unit 108 via the input / output bus terminal 111. By supplying another control signal from the host, a plurality of processes are processed in parallel. Is possible.

  For example, a case will be described in which the control signal instructing the encryption by the encryption / decryption unit 109 and the control signal instructing the decryption by the encryption / decryption unit 110 are received in an overlapping manner. A digital signal (hereinafter referred to as a first signal) input from the input interface unit 105 via the input terminal 101 is stored in the memory 104 via the arbiter 103, and input / output bus via the input / output bus terminal 111. A digital signal (hereinafter referred to as a second signal) input from the interface unit 107 is stored in the memory 104 via the arbiter 103. In this case, the arbiter 103 stores the first and second signals input from the respective interface units to the memory 104 in different areas in a time division manner.

  Next, the arbiter 103 reads the digital signal stored in the memory 104, supplies the first signal to the encryption / decryption unit 109, and stores the first signal encrypted in the encryption / decryption unit 109 in the memory 104 again. . The second signal is supplied to the encryption / decryption unit 110, and the second signal decrypted by the encryption / decryption unit 110 is stored in the memory 104 again. Also in this case, the data is stored in a time division in a different area from the above.

  Further, the arbiter 103 supplies the first signal encrypted by the encryption / decryption unit 109 from the memory 104 to the input / output bus interface unit 107, and outputs the second signal decrypted by the encryption / decryption unit 110 to the output interface unit. 106. Also in this case, reading is performed in a time division manner.

  As described above, a plurality of parallel processes of encryption and decryption can be realized by the arbiter 103 of this embodiment. In addition, for example, the digital signal input from the input / output bus terminal 111 is encrypted while the digital signal input from the input / output bus terminal 111 is decrypted and encrypted and output to the input / output bus terminal 111 again. Decoding by the decoding unit 109 and parallel processing such as output from the output terminal 102 via the output interface unit 106 can be similarly performed.

  FIG. 2 shows an embodiment in which the signal processing apparatus 100 is applied to a digital recorder. 400 is a digital recorder, 401 is a video signal input terminal, 402 is an audio signal input terminal, 403 is a video signal A / D converter, 404 is an audio signal A / D converter, 405 is a copy restriction information detection circuit, and 407 is a video signal compression. Circuit, 408 is an audio signal compression circuit, 409 is a system encoder, 100 is the above-described signal processing device, 410 is a PCI bus, 411 is a bus interface, so-called south bridge, 200 is a recording / playback unit such as a hard disk drive, and 300 is For example, a recording / playback unit such as an optical disk drive, 413 is a CPU interface, so-called north bridge, 412 is a memory, 421 is a control circuit, so-called CPU, 414 is a system decoder, 415 is a video signal expansion circuit, and 416 is an audio signal expansion circuit. 417 Image signal D / A converter, 418 audio signal D / A converter, 419 denotes a video signal output terminal, 420 is an audio signal output terminal.

  First, recording and reproducing operations in the recording / reproducing unit 200 and the recording / reproducing unit 300 will be described. The video signal input from the video signal input terminal 401 is converted into a digital signal by the video signal A / D converter 403, input to the copy restriction information detection circuit 405, and input to the video signal compression circuit 407. The copy restriction information detection circuit 405 detects, for example, copy restriction information superimposed on the vertical blanking interval of the video signal. The copy restriction information is information having the meanings of copy permission, one-generation copy permission, and copy prohibition. In the case of copy prohibition, the following operations are not performed.

  The video signal compression circuit 407 generates, for example, compression-encoded data that conforms to the ISO / IEC13818-2 (commonly called MPEG2 Video) MP @ ML (Main Profile @ Main Level) standard as a video compression encoding method. The video compression encoding method is not limited to this, and may be a JPEG standard method. The generated compressed encoded video data is input to the system encoder 409.

  The audio signal input from the audio signal input terminal 402 is subjected to analog / digital conversion at a predetermined sampling rate in the audio signal A / D converter 404. The audio signal converted into the digital signal is input to the audio signal compression circuit 408. The audio signal compression circuit 408 generates, for example, compression encoded data that conforms to the ISO / IEC13818-1 (commonly called MPEG2Audio) standard as an audio compression encoding method. The voice compression coding method is not particularly limited. The generated compression-encoded audio data is input to the system encoder 409.

  The compressed encoded video data and compressed encoded audio data input to the system encoder 409 are packetized and multiplexed, converted into a single system stream, and then input to the signal processing apparatus 100. As additional information, the size and aspect ratio of the original video, the bit rate of the compressed encoded video data and the compressed encoded audio data in the system stream, copy restriction information, and the like are added to the system stream. Here, when the copy restriction information detection circuit 405 detects that one-generation copying is possible, for example, the copy restriction information added to the system stream is changed to copy prohibition information and added.

  The control circuit 421 issues a control signal to the signal processing apparatus 100 via the input / output bus terminal 111 based on the detection result of the copy restriction information detection circuit 405. When it is detected that one-generation copying is possible, an encryption processing instruction is issued.

  The system stream input to the signal processing device 100 is processed in accordance with the control signal received from the control circuit 421, and is temporarily stored in the memory 412 via the bus interface 411 and the CPU interface 413 from the input / output bus terminal 111 via the PCI bus 410. Is recorded in the recording / reproducing unit 200 or the recording / reproducing unit 300 via the CPU interface 413 and the bus interface 411.

  At this time, for example, when recording is performed by the recording / reproducing unit 200, encryption is performed by the encryption / decryption unit 109 of FIG. 1, and when recording is performed by the recording / reproducing unit 300, encryption is performed by the encryption / decryption unit 110 of FIG. . The operation of the signal processing apparatus 100 is as described above.

  Note that the unique information held by the control circuit 421 may be used as key information for generating the encryption / decryption key supplied to the encryption / decryption unit 109 and the encryption / decryption unit 110 inside the signal processing apparatus 100. In addition to the above, unique information possessed by the optical disc of the recording / reproducing unit 300 may be used as key information for generating the encryption / decryption key supplied to the encryption / decryption unit 110.

  Here, the system stream is encrypted in the encryption / decryption unit (109, 110) when the copy restriction information detection circuit 405 detects, for example, information that allows one-generation copying. May not be encrypted.

  On the other hand, a system stream reproduced by the recording / reproducing unit 200 or the recording / reproducing unit 300 is stored in the memory 412 via the bus interface 411 and the CPU interface 413. The system stream stored in the memory 412 is input from the input / output bus terminal 111 to the signal processing apparatus 100 via the PCI bus 410 via the CPU interface 413 and the bus interface 411.

  The system stream input to the signal processing device 100 is processed according to the control signal received from the control circuit 421 and input to the system decoder 414 via the output terminal 102. The operation of the signal processing apparatus 100 is as described above, and the encryption / decryption key supplied to the encryption / decryption unit 109 or the encryption / decryption unit 110 is the same as that during recording.

  The system stream input to the system decoder 414 is separated into packets of compressed encoded video data and compressed encoded audio data, and the compressed encoded video data extracted from each packet is sent to the video signal decompression circuit 415 and The compression-encoded audio data is input to the audio signal expansion circuit 416. The expanded video signal is input to the video signal D / A converter 417, and the audio signal is input to the audio signal D / A converter 418, converted into an analog signal, and output from the video signal output terminal 419 and the audio signal output terminal 420. Is done.

  As described above, the signal processing apparatus 100 performs encryption and decryption processing according to the recording medium based on the copy restriction information of the video / audio signal to be recorded, and the encrypted system stream is stored on the recording medium. Since it is recorded, the copyright on the recording medium can be protected. Further, since the encrypted system stream is also transmitted on the PCI bus 410, data transfer can be performed safely.

  Next, a dubbing operation from the recording / reproducing unit 200 to the recording / reproducing unit 300 will be described. A system stream reproduced from the recording / reproducing unit 200 is stored in the memory 412 via the bus interface 411 and the CPU interface 413. The system stream stored in the memory 412 is input from the input / output bus terminal 111 to the signal processing apparatus 100 via the PCI bus 410 via the CPU interface 413 and the bus interface 411.

  The system stream input to the signal processing device 100 is subjected to decryption processing and encryption processing according to the control signal received from the control circuit 421, and is output from the input / output bus terminal 111. The operation of the signal processing apparatus 100 is as described above. The output system stream is temporarily stored in the memory 412 via the bus interface 411 and the CPU interface 413 from the input / output bus terminal 111 via the PCI bus 410, and then recorded and reproduced via the CPU interface 413 and the bus interface 411. Recorded by the unit 300.

  As described above, also in the dubbing operation between recording media, the signal processing apparatus 100 performs encryption and decryption processing according to the recording medium, and the encrypted system stream is recorded on the recording medium. Therefore, the copyright on the recording medium can be protected. Further, since the encrypted system stream is also transmitted on the PCI bus 410, data transfer can be performed safely.

  It is also possible to perform a reproduction operation while performing a recording operation. For example, a case where reproduction from the recording / reproducing unit 300 is performed while recording by the recording / reproducing unit 200 will be described. The system stream from the system encoder 409 input to the signal processing apparatus 100 is recorded by the recording / reproducing unit 200 from the input / output bus terminal 111 via the PCI bus 410 according to the control signal received from the control circuit 421. At the same time, in accordance with the control signal received from the control circuit 421, the system stream reproduced from the recording / reproducing unit 300 is input from the input / output bus terminal 111 via the PCI bus 410 and supplied to the system decoder 414. Thereby, independent of the recording operation in the recording / reproducing unit 200, the reproducing operation in the recording / reproducing unit 300 can be realized.

Alternatively, during the dubbing operation from the recording / playback unit 200 to the recording / playback unit 300, for example, a system stream playback operation different from the system stream dubbed from the recording / playback unit 200 can be performed.
These operations are based on the parallel processing in the signal processing apparatus 100 described above.

  FIG. 3 shows another embodiment in which the signal processing apparatus 100 is applied to a digital recorder. Reference numeral 422 denotes a video signal changeover switch, and 423 denotes an audio signal changeover switch. As described above, in the case of recording by the recording / reproducing units 200 and 300, the video signal converted into a digital signal by the video signal A / D converter 403 is input to the video signal compression circuit 407 via the video signal selector switch 422. Is done. The audio signal converted into a digital signal by the audio signal A / D converter 404 is input to the audio signal compression circuit 408 via the audio signal changeover switch 423. Subsequent processing is as described above.

  A system stream reproduced from the recording / reproducing unit 200 is stored in the memory 412 via the bus interface 411 and the CPU interface 413. The system stream stored in the memory 412 is input from the input / output bus terminal 111 to the signal processing apparatus 100 via the PCI bus 410 via the CPU interface 413 and the bus interface 411.

  The system stream input to the signal processing device 100 is decoded according to the control signal received from the control circuit 421, output from the output terminal 102, and input to the system decoder 414. The system stream input to the system decoder 414 is separated into packets of compressed encoded video data and compressed encoded audio data, and the compressed encoded video data extracted from each packet is sent to the video signal decompression circuit 415 and The compression-encoded audio data is input to the audio signal expansion circuit 416. The expanded video signal is input to the video signal changeover switch 422, and the audio signal is input to the audio signal changeover switch 423, which are input to the video signal compression circuit 407 and the audio signal compression circuit 408, respectively. In the video signal compression circuit 407 and the audio signal compression circuit 408, compression encoding processing is performed again at a lower bit rate than the compression encoded video data and compression encoded audio data of the system stream reproduced from the recording / reproducing unit 200. Input to the encoder 409. The compressed encoded video data and compressed encoded audio data input to the system encoder 409 are packetized and multiplexed, converted into a single system stream, and then input to the signal processing apparatus 100.

  The system stream input to the signal processing apparatus 100 is subjected to encryption processing and output from the input / output bus terminal 111. The operation of the signal processing apparatus 100 is as described above. The output system stream is temporarily stored in the memory 412 via the bus interface 411 and the CPU interface 413 from the input / output bus terminal 111 via the PCI bus 410, and then recorded and reproduced via the CPU interface 413 and the bus interface 411. Recorded by the unit 300.

  As described above, also in the dubbing operation between the recording media while converting the recording rate, the signal processing apparatus 100 performs encryption and decryption processing according to the recording medium, and the encryption is performed on the recording medium. Since the system stream is recorded, the copyright on the recording medium can be protected. Further, since the encrypted system stream is also transmitted on the PCI bus 410, data transfer can be performed safely.

It is a figure which shows the block configuration of one Example of the signal processing apparatus which concerns on this invention. It is a figure which shows the block configuration of one Example of the digital recorder which concerns on this invention. It is a figure which shows the block configuration of the other Example of the digital recorder which concerns on this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Signal processing apparatus, 101 ... Input terminal, 102 ... Output terminal, 103 ... Arbiter (arbitration part) circuit, 104 ... Memory, 105 ... Input interface part, 106 ... Output interface part, 107 ... I / O bus interface part, 108 ... Control unit 109, 110 ... Encryption / decryption unit 111 ... Input / output bus terminal, 200,300 ... Recording / playback unit, 400 ... Digital recorder, 403, 404 ... A / D converter, 405 ... Copy restriction information detection circuit, 407 ... Video signal compression circuit, 408 ... Audio signal compression circuit, 409 ... System encoder, 410 ... PCI bus, 411 ... Bus interface, 412 ... Memory, 413 ... CPU interface, 414 ... System decoder, 415 ... Video signal decompression circuit, 416 ... Audio signal expansion circuit, 417, 418 ... D / A Converter, 421 ... control circuit.

Claims (9)

An input unit for inputting a digital signal;
An output unit for outputting a digital signal;
An input / output bus unit for inputting / outputting digital signals and control signals;
First and second encryption / decryption units for encrypting and decrypting the digital signal input / output at the input unit, the output unit, and the input / output bus unit;
A memory for temporarily storing the digital signal;
An arbitration unit that arbitrates a digital signal between the input unit, the output unit, the input / output bus unit, the first and second encryption / decryption units, and the memory;
Based on the control signal input to the input / output bus unit, the first and second encryption / decryption unit, the arbitration unit, the input unit, the output unit, and a control unit for controlling the input / output bus unit,
A signal processing apparatus comprising: The signal processing device according to claim 1,
The arbitration unit and the control unit perform parallel processing of encryption and decryption operations in the first and second encryption / decryption units based on a plurality of control signals input to the input / output bus unit. A signal processing device. The signal processing device according to claim 1 or 2,
Based on the control signal input to the input / output bus unit, the digital signal input to the input unit is designated as one of the first encryption / decryption unit or the second encryption / decryption unit. A signal processing apparatus characterized in that the data is encrypted and output to the input / output bus unit. The signal processing device according to claim 1 or 2,
Based on the control signal input to the input / output bus unit, the digital signal input to the input / output bus unit is decrypted by the first encryption / decryption unit or the second encryption / decryption unit, and the output unit A signal processing device that outputs to The signal processing device according to claim 1 or 2,
Based on the control signal input to the input / output bus unit, the digital signal input to the input / output bus unit is converted into one of the designated encryption units of the first encryption / decryption unit or the second encryption / decryption unit. A signal processing device, wherein the signal processing device is decrypted by a decryption unit, further encrypted by the other encryption / decryption unit, and output to the input / output bus unit. The signal processing device according to any one of claims 1 to 5,
The signal processing apparatus, wherein the first and second encryption / decryption units perform encryption and decryption using different encryption algorithms. The signal processing device according to claim 1,
The input unit, the output unit, the input / output bus unit, the first and second encryption / decryption units, the arbitration unit, the memory, and the control unit are mounted on one integrated circuit. Signal processing device. An encryption part for encrypting the digital signal;
A decoding unit for decoding the digital signal;
A memory for temporarily storing digital signals;
An arbitration unit that arbitrates a digital signal between the encryption unit, the decryption unit, and the memory, and processes in a time-sharing manner;
The arbitration unit performs parallel processing of encryption and decryption operations in the encryption unit and the decryption unit. A recording / reproducing apparatus including the signal processing apparatus according to claim 1,
Digital signals for recording and reproduction are input to and output from the input unit and the output unit,
A recording / reproducing apparatus, wherein a recording / reproducing unit that performs recording / reproducing on a recording medium is connected to the input / output bus unit via a bus interface.

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