JP2005159596A - Digital camera - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital camera capable of photographing a moving picture that decreases the number of memories so as to reduce the manufacturing cost and the power consumption. <P>SOLUTION: A memory 5 is connected to a main processing circuit 3 via an MIU 304. In the case of photographing a moving picture, image data received from a sensor 2 are transferred to a moving picture processing circuit 4 from a YUVU interface via an SPU 301 and an RPU 302. An encoder decoder unit 401 of the moving picture processing circuit 4 executes compression processing. In the case of executing the compression processing, a DMAC 406 transmits a DMA control signal to the main processing circuit 3 via a DMA interface 407. A DMA interface 307 of the main processing circuit 3 accesses the memory 5 via the MIU 304. In the case of applying compression processing to the moving picture, the memory 5 of the main processing circuit 3 is used for a buffer in this way. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a digital camera capable of capturing moving images.

  There are digital cameras that can shoot moving images. Image data continuously output from the CCD sensor is compressed and recorded as compressed moving image data. In order to perform such compression processing, many digital cameras include a dedicated LSI chip for moving image compression processing.

  In order to perform moving image compression processing such as MPEG, it is necessary to execute processing in units of blocks of 8 × 8 pixels, and a memory having a frame area for storing such block images is required. Therefore, a dedicated LSI chip for moving image processing includes a memory such as an SDRAM for use as a buffer area during compression processing. Furthermore, a memory is also required for a circuit for performing overall control of the digital camera. Therefore, in the conventional digital camera, both the main processing circuit and the moving image processing are each provided with a memory.

  In order to reduce the cost of the digital camera, the following techniques exist. Japanese Patent Application Laid-Open No. 2004-228561 discloses a technique that uses a line memory during compression processing. Thereby, the cost is reduced as compared with the case of using the frame memory. Patent Document 2 below discloses a technique for reducing the number of pins of a memory controller by using both a data signal line of SDRAM and an address signal line of FlashROM.

JP-A-5-252522 JP 2001-92714 A

  The configuration in which both the main processing circuit and the moving image processing circuit as described above include memories such as SDRAM has a problem of high cost. In addition, since a plurality of memories such as SDRAM are driven, there is a problem that power consumption is large.

  In the technique of the above-mentioned patent document 1, a certain amount of cost can be reduced by using a line memory, but a memory different from the memory connected to the main processing circuit is also required. Further, the technique of Patent Document 2 still requires a plurality of memories.

  In view of the above problems, an object of the present invention is to reduce the number of memories in a digital camera capable of capturing moving images, thereby realizing cost reduction and power consumption reduction.

  In order to solve the above-mentioned problem, the invention described in claim 1 is a digital camera capable of capturing a moving image, and includes a main processing circuit, a memory connected to the main processing circuit, and a moving image processing circuit. The main processing circuit includes a first interface for outputting image data input from a sensor to the moving image processing circuit, and a first DMA interface, and the moving image processing circuit outputs image data output from the main processing circuit. A second DMA interface connected to the first DMA interface, an image compression circuit for compressing image data input via the second interface to generate moving image data, a DMA controller, And transferred to the moving image processing circuit via the first and second interfaces. When over data is compressed in the image compression circuit, the DMA controller, by accessing the memory via the first and second 2DMA interface, characterized by using said memory as a buffer.

  The invention according to claim 2 is a digital camera capable of capturing a moving image, and includes a main processing circuit, a memory connected to the main processing circuit, and a moving image processing circuit. A first interface for outputting image data input from a sensor to the moving image processing circuit; and a memory emulation circuit; the moving image processing circuit; a second interface for inputting image data output from the main processing circuit; An image compression circuit for compressing image data input via the second interface to generate moving image data, and a memory controller connected to the memory emulation circuit, wherein the first and second interfaces are provided. When image data transferred to the moving image processing circuit via the image compression circuit is compressed by the image compression circuit The memory controller, by accessing the memory via the memory emulation circuit, characterized by using said memory as a buffer.

  The invention according to claim 3 is a digital camera capable of capturing a moving image, and includes a main processing circuit, a memory connected to the main processing circuit, and a moving image processing circuit. A first interface for outputting image data input from a sensor to the moving image processing circuit; and a selector; the moving image processing circuit; a second interface for inputting image data output from the main processing circuit; An image compression circuit for compressing image data input via the second interface to generate moving image data; and a memory controller connected to the selector. Access to the memory from the moving picture processing circuit and via a memory bus in the main processing circuit. A circuit that selectively permits access to the memory, and the memory controller when the image data transferred to the moving image processing circuit via the first and second interfaces is compressed by the image compression circuit. However, the memory is used as a buffer by accessing the memory via the selector.

  According to a fourth aspect of the present invention, in the digital camera according to any one of the first to third aspects, the main processing circuit includes: an image processing circuit that performs predetermined image processing on image data input from the sensor; A display processing circuit that executes an image display process on the display device, and a plurality of line memories interposed between the image processing circuit and the display processing circuit, wherein the moving image processing circuit stores the memory When executing compression processing using the image processing circuit, the image data output in units of one horizontal line from the image processing circuit is displayed via the plurality of line memories without using the memory bus of the main processing circuit. By transferring to the processing circuit, the image continuously output from the sensor is displayed on the display device in parallel with the compression processing.

  According to a fifth aspect of the present invention, in the digital camera according to the fourth aspect, the image data output from the image processing circuit to the line memory is data whose resolution has been converted in accordance with the display size of the display device. It is characterized by that.

  According to a sixth aspect of the present invention, in the digital camera according to the fourth aspect of the present invention, the digital camera further includes a circuit for converting the resolution of image data output from the plurality of line memories.

  According to a seventh aspect of the present invention, in the digital camera according to any one of the fourth to sixth aspects, the display cycle of one frame of the display device is made to coincide with the one-frame output cycle of the sensor. And

  According to an eighth aspect of the present invention, in the digital camera according to any one of the fourth to seventh aspects, when the display device is an LCD (liquid crystal display device), any one of the fourth to seventh aspects. An image is displayed on the LCD according to the procedure described in the above, and when the display device is a television, the image is displayed on the television using the memory as a buffer.

  The invention according to claim 9 is a digital camera, wherein an image processing circuit that performs predetermined image processing on image data input from a sensor, a display processing circuit that executes image display processing on a display device, and the image A plurality of line memories interposed between a processing circuit and the display processing circuit, a memory interface, and a memory bus for transferring a memory control signal to the memory interface, and using the memory bus Without transferring the image data output in units of one horizontal line from the image processing circuit to the display processing circuit via the plurality of line memories, the image continuously output from the sensor is displayed on the display device. It is characterized by displaying.

  According to the first to third aspects of the invention, since the memory of the main processing circuit is used as a buffer at the time of moving image processing, the main processing circuit and the moving image processing circuit can share the memory, and the cost is reduced. Reduction and power consumption can be reduced.

  According to the invention described in claims 4 to 8, the main processing circuit and the moving image processing circuit can share the memory, and the use band of the memory bus by the image display processing is reduced. Therefore, the image display process can be executed in parallel with the moving image compression process.

  According to the ninth aspect of the present invention, it is possible to perform image display processing while reducing the use band of the memory bus.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

{First embodiment}
FIG. 1 is a block diagram of a digital camera 1 according to the first embodiment. The digital camera 1 is a digital still camera that can capture a moving image. The digital camera 1 includes a sensor 2, a main processing circuit 3, a moving image processing circuit 4, a memory 5, an LCD 6, and a TV output interface 7.

  The main processing circuit 3 and the moving image processing circuit 4 are configured as LSIs, and these LSIs are mounted on a substrate. The main processing circuit 3 includes a CPU 303 that performs overall control of the digital camera 1, and has a function of controlling the sensor 2 to input an image and performing various image processing on the input image. The moving image processing circuit 4 includes a function for compressing moving images and the like, and is a dedicated LSI for processing moving images.

  The sensor 2 is a CCD image sensor, receives light from a subject that has passed through an optical mechanism, performs photoelectric conversion, and outputs an analog image signal. A CMOS image sensor may be employed instead of the CCD image sensor. The memory 5 is used as a buffer area in various processes, and is used for storing still images and moving images. The LCD 6 is provided on the back side of the main body of the digital camera 1, for example, for displaying a still image or a moving image stored in the memory 5, and for LiveView for continuously displaying images output from the sensor 2 in real time. Is also used. Further, by connecting the television output interface 7 to a television, it is possible to display still images and moving images stored in the memory 5 on the television screen and to perform LiveView.

  The analog image signal output from the sensor 2 passes through an analog signal processing circuit (not shown) that performs gain adjustment and the like, and then is A / D at a predetermined quantization level in an A / D conversion circuit (not shown). It is converted and output to the main processing circuit 3 as a digital image signal (original image data; Raw Image Data).

  The original image data output to the main processing circuit 3 is input to an SPU (Signal Processing Unit) 301 included in the main processing circuit 3. The SPU 301 performs preprocessing such as defective pixel correction on the digital image signal, and then outputs the digital image signal to a bus 300 or an RPU (Real Time Processing Unit) 302. The RPU 302 has a function of executing various digital image processing such as shading correction processing, pixel interpolation processing, gamma correction processing, color space conversion processing, contour enhancement processing, and resolution conversion processing in real time on the image signal input from the SPU 301. have. A signal output from the SPU 301 or RPU 302 to the bus 300 can be stored in the memory 5 through an MIU (Memory Interface Unit) 304 under the control of the CPU 303, for example, in the case of still image shooting processing. Note that data transfer via the bus 300 may be performed by a DMAC (DMA controller) 306 instead of the CPU 303. The MIU converts an internal memory control signal sent from the DMA or CPU onto the memory bus into a signal for accessing an externally connected memory and outputs the signal.

  On the other hand, when shooting a moving image, image data continuously output to the bus 300 via the SPU 301 or RPU 302 is sequentially transferred from the YUV interface 305 to the moving image processing circuit 4. In this embodiment, the original image data output from the sensor 2 and input to the main processing circuit 3 is RGB image data, but the RGB image data is an YUV image by color space conversion processing in the RPU 302. This YUV image data is output from the YUV interface 305.

  In the moving image processing circuit 4, the YUV interface 405 receives sequentially transferred image data. Then, the YUV image data is transferred to the encoder / decoder unit 401 and compression processing is executed. When this compression processing is executed, a memory is required as a buffer for compression images, a buffer for data in the middle of compression processing (work memory area), or a buffer for data after completion of compression. The present invention uses a memory 5 connected to the main processing circuit 3 for these purposes.

  In order to use the memory 5, the DMAC 406 transmits a control signal to the memory 5. This control signal includes an address signal and a data signal. This control signal is directly transferred to the DMA interface 307 of the main processing circuit 3 via the DMA interface 407. The DMA interface 307 gains control over the bus 300 and then accesses the memory 5 via an MIU (Memory Interface Unit). In this way, the moving image processing circuit 4 can use the memory 5 as a buffer during compression processing.

  An encoder / decoder unit 401. When compression processing is executed using the memory 5 as a buffer and compressed moving image data is generated, the microsequencer 402 performs sequence processing. That is, the sequence processing of the compressed moving image data and the compressed audio data input from the PCM audio codec interface 404 is performed, and moving image data with audio is generated. Note that the microsequencer 402 executes sequence processing using the local memory 403.

  As described above, according to the present embodiment, when moving image compression processing is performed in the encoder / decoder unit 401, the memory 5 connected to the main processing circuit 3 is used as a buffer. 4 does not need to have a memory such as an SDRAM. The moving image processing circuit 4 in the present embodiment includes a local memory 403 used by the microsequencer 402, but this memory is sufficient as a small-capacity memory compared to a buffer memory for moving image compression processing. That is, by sharing the memory 5 such as SDRAM between the main processing circuit 3 and the moving image processing circuit 4, the number of systems can be reduced and the manufacturing cost can be reduced. Further, it is possible to reduce power consumption by reducing the number of memories 5 such as SDRAM.

  Next, LiveView will be described. The digital camera 1 according to the present embodiment can display a moving image on the LCD 6 in real time while executing the moving image compression process as described above. However, since the moving image processing circuit 4 accesses the memory 5 while executing the compression processing, data flows on the bus 300 by accessing the memory 5. Therefore, the main processing circuit 3 performs the following processing so as not to flow data to the bus 300 as much as possible when performing LiveView.

  As described in the compression process, the original image data output from the sensor 2 is input to the RPU 302 via the SPU 301 and various image processes are executed. Next, the RPU 302 outputs image data with reduced resolution for display. For example, when the sensor 2 is a 5 million pixel class CCD image sensor with 2560 dots in the horizontal direction and 1920 lines in the vertical direction, and the LCD 6 is a QVGA (Quarter VGA) LCD with 320 dots in the horizontal direction and 240 lines in the vertical direction. The RPU 302 reduces the image data of 2560 × 1920 pixels to image data of 320 × 240 pixels for display. In addition, the RPU 302 outputs the resolution-converted image data line by line in the horizontal direction. That is, image data that has undergone predetermined image processing in the RPU 302 is transferred to the moving image processing circuit 4 via the YUV interface 405 on the one hand as image data of 2560 × 1920 pixels, and after the resolution conversion on the other hand. , One horizontal line is output at a time.

  Image data of one horizontal line output from the RPU 302 is first input to the line memory 311 via the selector 313. Then, at the next clock, image data for the next horizontal line is output from the RPU 302, the image data is input to the line memory 312 via the selector 313, and the horizontal 1 stored in the line memory 311 is also displayed. The line image data is output to the selector 315 via the selector 314. In the LiveView mode for the LCD 6, the selector 315 outputs an input signal from the selector 314. Accordingly, the image data of one horizontal line output from the line memory 311 is input to an IDU (Image Display Unit) 308.

  Such processing is repeated, and image data of one horizontal line sequentially output from the RPU 302 is alternately input to the line memory 311 and the line memory 312. At the timing when the image data is input to the line memory 311, the line memory 312 At the timing when the image data is output from the line memory 312 and the image data is input to the line memory 312, the image data for display output from the RPU 302 passes through the bus 300 by being output from the image data from the line memory 311. Without being transferred to the IDU 308. The IDU 308 displays an image on the LCD 6.

  As described above, in this embodiment, the main processing circuit 3 and the moving image processing circuit 4 share the memory 5, thereby reducing the system cost and performing LiveView. By reducing the amount of data flowing through the memory bus, LiveView can be performed smoothly even during moving image compression processing.

  Here, in order to perform LiveView on the LCD 6 using the line memories 311 and 312 as described above, it is a condition that one frame period of the sensor 2 and one frame period of the LCD 6 match. In the present invention, when the frame periods of the sensor 2 and the LCD 6 are different, the drive frequency of the LCD 6 is changed to match the frame period with the frame period of the sensor 2.

  Furthermore, in order to perform LiveView using the two line memories 311 and 312 as described above, in addition to having the same frame period, the horizontal line period of the sensor 2 and the LCD 6 must also match. There is.

  However, in the above embodiment, the image data output from the RPU 302 to the line memories 311 and 312 is data whose resolution has been converted in accordance with the display size of the LCD 6. Therefore, in the above embodiment in which the RPU 302 performs resolution conversion, this condition is satisfied by matching the timing at which the RPU 302 outputs image data of one horizontal line with the horizontal line period of the LCD 6.

  On the other hand, when the RPU 302 does not perform resolution conversion, that is, when the RPU 302 outputs image data as it is with the output image data size of the sensor 2, an implementation method for performing LiveView using a line memory is shown in FIG. The description will be given with reference.

  As shown in FIG. 2, in this realization method, N line memories 311-1, 311-2,... 311-N and N line memories 312-1, 312-2,. Use -N. Also, a resolution conversion unit 316 that converts the resolution of data output from each line memory is provided. Other configurations of the digital camera 1 are the same as those shown in FIG.

  For example, it is assumed that the number of horizontal lines of the output image of the sensor 2 is a × N (a and N are integers), and the number of horizontal lines of the LCD 6 is a × M (M is an integer). In this case, it is necessary to thin out the number of lines to M / N.

  Therefore, first, the image data of the first N horizontal lines output from the RPU 302 are input to the line memories 311-1, 311-2,. At the next clock, the image data of the next N horizontal lines is input to the line memories 312-1, 312-2,... 312-N and the line memories 311-1, 311-2,. The image data of the first N horizontal lines that have been input to 311 -N are input to the resolution conversion unit 316. Therefore, the conversion process is performed so that the number of horizontal lines is M. This conversion processing is not particularly limited, but for example, bilinear processing may be executed. In addition, the number of pixels in one horizontal line is also thinned out by bilinear processing or the like, and processing is performed to match the number of pixels in one line of the LCD 6.

  The above processing is performed alternately using N line memories 311-1, 311-2,... 311-N and N line memories 312-1, 312-2,. In this way, image data of M lines is alternately output to the IDU 308. Accordingly, even when the RPU 302 does not perform resolution conversion, LiveView can be performed using the line memory without using the bus 300.

  Next, the case of television output will be described. When outputting to a television screen, unlike the LCD, the display frequency of the television cannot be changed. Further, although one horizontal line period of a television is 63.5 μs, there is actually no sensor having such a high speed one horizontal period. For this reason, it is not realistic to perform resolution conversion using a line memory and perform LiveView on the television as in the above embodiment (of course, it operates at the same frame period as the television and the same one horizontal). If there is a sensor that operates in a line cycle, the same processing as LiveView for the LCD described above may be performed on the television output. Therefore, in the present embodiment, when LiveView is performed on a television, the memory 5 is used as a buffer area as shown in FIG.

  As shown in FIG. 3, the image data output from the RPU 302 is stored in the buffer 81 of the memory 5. Next, the image data output from the RPU 302 is stored in the buffer 82 of the memory 5, and the image data stored in the buffer 81 is transferred to the IDU 308 via the selector 315. In the television output mode, the selector 315 outputs data input from the bus 300 to the IDU 308.

  Further, at the next timing, the image data output from the RPU 302 is stored again in the buffer 81 of the memory 5, and the image data stored in the buffer 82 is transferred to the IDU 308 via the selector 315. By repeating such processing, the image data is sequentially transferred to the IDU 308. The data transferred to the IDU 308 is then converted into image data of the NTSC system or the like by the TV encoder 309, converted to an analog signal by the DAC 310, and then output to the television via the television output interface 7. is there.

  In this way, when outputting to the television, the image data for display uses the bus 300. Generally, when shooting a moving image, a cable is connected to the television and LiveView is performed on the television screen. This is not likely to be done. That is, since it is considered rare that LiveView data and moving image processing data flow on the bus 300, the configuration has few practical problems.

  As shown in the figure, since the moving image processing circuit 4 includes the MIU 408 and the memory interface port 409, an external memory can be connected to the moving image processing circuit 4. Yes.

{Second Embodiment}
Next, a second embodiment of the present invention will be described with reference to FIG. In the second embodiment, the description of the same configuration and processing as in the first embodiment is omitted, and only the characteristic part is described. In FIG. 4, the same reference numerals are given to the same components as those in the first embodiment.

  In the digital camera 1 according to the second embodiment, the main processing circuit 3 includes a memory emulation circuit 317. For example, when the memory 5 is an SDRAM, an SDRAM emulation circuit is used. The output line from the MIU 408 of the moving image processing circuit 4 branches, and the branched line is connected to the memory emulation circuit 317. The main processing circuit 3 and the moving image processing circuit 4 do not include a DMA interface.

  When the image data is transferred to the moving image processing circuit 4 by the same process as in the first embodiment, the encoder / decoder unit 401 executes the compression process. Here, when the DMAC 406 sends a control signal to the memory 5, this control signal is transferred to the MIU 408. This control signal includes an address signal and a data signal. Then, the MIU 408 outputs a control signal for the memory 5.

  The control signal output from the MIU 408 is input to the memory emulation circuit 317. The memory emulation circuit 317 performs the same operation as the memory 5 on the MIU 408. As a result, the MIU 408 executes the same processing as accessing the memory 5. On the other hand, the memory emulation circuit 317 performs a process of writing data to the memory 5 and a process of reading data from the memory 5 after obtaining the control right of the bus 300.

  Thus, when the encoder / decoder unit 401 executes the compression process, the memory 5 is accessed and the memory 5 is used as a buffer. As described above, in the second embodiment as well, the main processing circuit 3 and the moving image processing circuit 4 can share the memory 5. In addition, LiveView for the LCD 6 is also performed by the same processing as in the first embodiment, and the bandwidth of the bus 300 is secured.

{Third embodiment}
Next, a third embodiment of the present invention will be described with reference to FIG. In the third embodiment, the description of the same configuration and processing as in the first embodiment is omitted, and only the characteristic part is described. In FIG. 5, the same reference numerals are given to the same configurations as those in the first embodiment.

  In the digital camera 1 according to the third embodiment, the main processing circuit 3 includes a selector 318 that inputs the output data of the MIU 304. Further, an output line from the MIU 408 of the moving image processing circuit 4 is branched, and this branched line is also connected to the selector 318. That is, the selector 318 can selectively connect the MIUs 304 and 408 to the memory 5. The main processing circuit 3 and the moving image processing circuit 4 do not include a DMA interface.

  When the image data is transferred to the moving image processing circuit 4 by the same process as in the first embodiment, the encoder / decoder unit 401 executes the compression process. Here, when the DMAC 406 sends a control signal to the memory 5, this control signal is transferred to the MIU 408. This control signal includes an address signal and a data signal. Then, the MIU 408 outputs a control signal for the memory 5.

  The control signal output from the MIU 408 is input to the selector 318. The selector 318 has a function of arbitrating access between the MIU 304 and the MIU 408 to the memory 5. As a result, the DMAC 406 can access the memory 5 via the MIU 408. When the encoder / decoder unit 401 executes the compression process, the DMAC 406 accesses the memory 5 and uses the memory 5 as a buffer. As described above, in the second embodiment as well, the main processing circuit 3 and the moving image processing circuit 4 can share the memory 5. In addition, LiveView for the LCD 6 is also performed by the same processing as in the first embodiment, and the bandwidth of the bus 300 is secured.

1 is a block diagram of a digital camera according to a first embodiment. It is another Example figure which performs LiveView using a line memory. It is a figure which shows the operation | movement at the time of performing television output. It is a block diagram of the digital camera concerning 2nd Embodiment. It is a block diagram of the digital camera concerning 3rd Embodiment.

Explanation of symbols

1 Digital Camera 2 Sensor 3 Main Processing Circuit 4 Movie Processing Circuit 5 Memory 6 LCD
7 TV output line

Claims (9)

A digital camera capable of shooting moving images,
A main processing circuit;
A memory connected to the main processing circuit;
A video processing circuit;
With
The main processing circuit includes:
A first interface for outputting image data input from a sensor to the moving image processing circuit;
A first DMA interface;
With
The moving image processing circuit includes:
A second interface for inputting image data output from the main processing circuit;
A second DMA interface connected to the first DMA interface;
An image compression circuit for compressing image data input via the second interface to generate moving image data;
A DMA controller;
With
When the image data transferred to the moving image processing circuit via the first and second interfaces is compressed by the image compression circuit, the DMA controller stores data in the memory via the first and second DMA interfaces. A digital camera using the memory as a buffer by accessing. A digital camera capable of shooting moving images,
A main processing circuit;
A memory connected to the main processing circuit;
A video processing circuit;
With
The main processing circuit includes:
A first interface for outputting image data input from a sensor to the moving image processing circuit;
A memory emulation circuit;
With
The moving image processing circuit includes:
A second interface for inputting image data output from the main processing circuit;
An image compression circuit for compressing image data input via the second interface to generate moving image data;
A memory controller connected to the memory emulation circuit;
With
When the image data transferred to the moving image processing circuit via the first and second interfaces is compressed by the image compression circuit, the memory controller accesses the memory via the memory emulation circuit. According to the digital camera, the memory is used as a buffer. A digital camera capable of shooting moving images,
A main processing circuit;
A memory connected to the main processing circuit;
A video processing circuit;
With
The main processing circuit includes:
A first interface for outputting image data input from a sensor to the moving image processing circuit;
A selector,
With
The moving image processing circuit includes:
A second interface for inputting image data output from the main processing circuit;
An image compression circuit for compressing image data input via the second interface to generate moving image data;
A memory controller connected to the selector;
With
The selector selectively permits an access to the memory from the moving image processing circuit performed via the memory controller and an access to the memory performed via a memory bus in the main processing circuit. A memory controller that accesses the memory via the selector when image data transferred to the moving image processing circuit via the first and second interfaces is compressed by the image compression circuit. Thus, a digital camera using the memory as a buffer. The digital camera according to any one of claims 1 to 3,
The main processing circuit includes:
An image processing circuit for performing predetermined image processing on the image data input from the sensor;
A display processing circuit for performing image display processing on the display device;
A plurality of line memories interposed between the image processing circuit and the display processing circuit;
With
When the moving image processing circuit executes the compression process using the memory, the image data output in units of one horizontal line is output from the image processing circuit without using the memory bus of the main processing circuit. A digital camera characterized in that an image continuously output from the sensor is displayed on the display device in parallel with the compression processing by being transferred to the display processing circuit via a plurality of line memories. The digital camera according to claim 4, wherein
The digital camera, wherein the image data output from the image processing circuit to the line memory is data whose resolution has been converted according to the display size of the display device. 5. The digital camera according to claim 4, further comprising:
A circuit for converting the resolution of the image data output from the plurality of line memories;
A digital camera comprising: The digital camera according to any one of claims 4 to 6,
A digital camera characterized in that a display cycle of one frame of the display device is matched with a one-frame output cycle of the sensor. The digital camera according to any one of claims 4 to 7,
When the display device is an LCD (liquid crystal display device), an image is displayed on the LCD according to the procedure according to any one of claims 4 to 7, and when the display device is a television, the memory is stored. A digital camera that uses a buffer to display an image on a television. A digital camera,
An image processing circuit for performing predetermined image processing on the image data input from the sensor;
A display processing circuit for performing image display processing on the display device;
A plurality of line memories interposed between the image processing circuit and the display processing circuit;
A memory interface;
A memory bus for transferring a memory control signal to the memory interface;
With
Without using the memory bus, image data output in units of one horizontal line from the image processing circuit is transferred to the display processing circuit via the plurality of line memories, thereby being continuously output from the sensor. An image is displayed on the display device.

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