JP2005117773A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor which mounts a boosting circuit taking an optimum action, according to load capacity. <P>SOLUTION: The time constant of the waveform at a rise in boosted potential VPP is monitored at real time by measuring a time when boosted potential VPP reaches a specified reference potential by means of a system clock CLKS. When the measured time is shorter than the time recorded in advance in a ROM66, a control unit 68 adjusts the driving force of a boosting circuit 50 by lessening the amplitude of a clock ϕ. Hereby, even in case that the relative relation between driving force and load changes by power voltage, load capacity, and other factors, the driving force can be optimized. That is, even if information such a power voltage, the number of selected bit lines, etc. are not given from outside, the driving force is adjusted autonomously, and current consumption and improvement of ripple quantity are achieved. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a booster circuit, and more particularly to a booster circuit used for a flash memory.

In Japanese Patent No. 3403006 (Patent Document 1), a semiconductor integrated circuit including a substrate bias charge pump is arranged in parallel for the purpose of reducing the chip area as much as possible without reducing the maximum voltage. A configuration is disclosed in which a plurality of charge pump circuits connected to each other are switched and used.
Japanese Patent No. 3403006

  FIG. 18 is a circuit diagram showing the configuration of the potential generation circuit 500.

  Referring to FIG. 18, signal OSC generated by oscillator 512 is converted to complementary clocks φ and / φ by NAND circuit 514 and inverters 516 to 520, and is boosted by the complementary clocks φ and / φ. 502 performs a boosting operation. The booster circuit supplies the boosted potential VPP to the load circuit 506. The comparator 510 compares the reference potential Vref with the divided potential DIV obtained by dividing the potential VPP by the voltage dividing circuit 504. When the potential DIV exceeds the potential Vref generated by the reference potential generation circuit 508, the comparator inactivates the boost activation signal VPPEN to L level.

  As a result, the clock signals φ, / φ are disabled, and the boosting operation is stopped. After that, when the level of the potential VPP decreases due to leakage or the like and the potential DIV becomes lower than the potential Vref, the comparator activates the signal VPPEN to the H level again. Then, the clock signals φ and / φ are enabled, and the booster circuit 502 resumes the boosting operation.

  FIG. 19 is a waveform diagram for explaining the operation of the potential generation circuit 500.

  Referring to FIGS. 18 and 19, when booster circuit 502 repeats the boost stop and boost restart operations, potential VPP is stabilized within the range of ΔVPP with the potential VPP0 as the center. VPP0 is represented by the following formula (1).

VPP0 = (R1 + R2) / R2 * Vref (1)
As described above, when the driving power of the booster circuit is not so large with respect to the capacity of the load circuit, the potential VPP is controlled to a constant value of VPP0.

  However, when the driving power of the booster circuit 502 is larger than the capacity of the load circuit 506, the amount of charge supplied to the load circuit 506 via the booster capacitor C in one clock-up operation becomes excessive. The comparator 510 detects that the potential VPP has reached the potential VPP0 and stops the boosting operation. However, since the comparator requires a predetermined response time to respond, a time difference is required to stop the boosting operation. Will occur. Since the boosting operation is performed during this time, the potential VPP is boosted to a potential that exceeds the potential VPP0 by a certain amount.

  In addition, after the boosting operation is stopped by the comparator 510, the potential VPP decreases due to the leakage current of the output node of the boosting circuit 502, for example, the consumption current of the load circuit 506 or the voltage dividing circuit 504. At this time, when the potential VPP drops to the potential VPP0, the comparator 510 should detect it and immediately restart the boosting operation, but it still takes the response time Td. Therefore, the boosting operation is resumed only after the potential VPP falls below the potential VPP0 to some extent.

  For this reason, as shown in FIG. 19, the potential VPP has a sawtooth waveform even in a steady state.

  In the flash memory, such a boosted potential is used for the bit line potential at the time of writing. The bit line potential needs to be stabilized at a constant value, and if a saw-tooth ripple as shown in FIG. 19 occurs, problems such as over programming occur. For this reason, it is often performed to stabilize the potential VPP by adding a decoupling capacitor Cd so that the load capacitance does not decrease with respect to the driving force of the booster circuit 502.

  The driving force of the booster circuit 502 varies depending on the clock amplitude and the like. The clock amplitude is usually equal to the power supply voltage. When the power supply voltage is high, the driving power of the booster circuit 502 is large. Conversely, when the power supply voltage is low, the driving power of the booster circuit 502 is small.

  The boosted potential VPP needs to be boosted to the target potential VPP0 within a certain time. If the driving power of the booster circuit 502 is optimized with respect to the load when the booster circuit 502 has high driving power, that is, the power supply voltage is high, if the power supply voltage is low, it takes too much time for boosting. Therefore, the booster circuit 502 is optimized when the power supply voltage is low.

  However, when the power supply voltage increases and the driving power increases, the booster circuit 502 is clearly overpowered with respect to the load circuit 506, and the ripple increases. If the driving power of the booster circuit 502 is set high, the power consumption of the booster circuit 502 itself increases.

  In particular, in a flash memory, the number of bit lines selected at the time of writing differs depending on the data pattern to be written. For example, only one bit line may be boosted, and several thousand bit lines may be boosted. Thus, not only the driving force changes, but also the load capacity changes. A change in the load capacitance also causes a potential ripple, which causes a problem.

  In order to suppress such an increase in ripple, a sufficient decoupling capacity may be added. However, if the load capacity is increased too much, the driving force is insufficient when the power supply voltage is low. In order to compensate for this deficiency in driving force, it is necessary to increase the driving force of the booster circuit. As a result, problems such as an increase in the area of the booster circuit and an increase in power consumption in the booster circuit occur. If a large decoupling capacity is provided, the area occupied by the decoupling capacity cannot be ignored.

  An object of the present invention is to provide a semiconductor device including a booster circuit with reduced current consumption and improved ripple amount.

  In summary, the present invention relates to a semiconductor device, an internal circuit, a potential generation circuit that generates an internal potential for use in the internal circuit, and a time constant of a change in the internal potential. And a control circuit that controls the potential generation circuit so that the time constant is equivalent to a predetermined value when the value is smaller or larger than the value.

  Therefore, the main advantage of the present invention is that even when the relative relationship between the driving force and the load varies depending on the power supply voltage, the load capacity, and other factors, the operation is optimized, and the ripple and power consumption can be reduced. That is.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

[Embodiment 1]
FIG. 1 is a block diagram showing a configuration of a semiconductor device 1 of the present invention. In this specification, a flash memory is described as an example of a semiconductor device including a booster circuit.

Referring to FIG. 1, a semiconductor device 1 uses a ROM therein, and a write & erase control unit 2 that controls write and erase based on a program code held in the ROM, and write & erase control signals VDCCONT and activation signal VPPEN from the control unit 2, the output potential VPP in response to these receives a reset signal RSTE, Vout-, a voltage generator 3 which generates and outputs V _WL, the address signal ADR from the outside An address buffer 16 that receives the internal address signal from the address buffer 16 and a potential supplied from the voltage generating unit 3 to receive potentials from the select gate line SGL, word lines WL0 and WL1, source line SL, and well. And an input / output buffer 22 for transmitting / receiving the data input / output signal DIO, and an address from the address buffer 16 It includes a Y decoder 20 for decoding received the item, and a Y-system control circuit 24 for applying a high voltage corresponding to the data input and output signals to the main bit line MBL in accordance with the output of the Y decoder 20.

The voltage generation unit 3 receives a control signal VDCCONT, an activation signal VPTEN, and a reset signal RSTE from the write & erase control unit 2 and generates an output potential VPP in response thereto, and a control signal VDCCONT, Controlled by a negative voltage generation circuit 8 that generates an output potential Vout− in response to a reset signal RSTE and a charge pump activation signal NPUMPE, a WL boost circuit 12 that generates a word line potential V _WL , and a write & erase control unit 2 Distributor 14 that receives output potentials VPP, Vout− and word line potential V _WL and distributes them to each internal circuit.

  Although not shown, the X decoder includes a WL decoder for selecting a word line, an SG decoder for selecting a select gate, a WELL decoder for selecting a well region corresponding to the selected memory block, and a source line. And an SL decoder for selection.

  The Y-system control circuit 24 selects a column at the time of reading and applies a high potential to the main bit line MBL at the time of writing based on the YG & sense amplifier and the latch circuit that perform the reading operation by the sense amplifier and the latched data. Page buffer to determine whether or not.

  The WL boost circuit 12 is a circuit that generates a boosted potential to be applied to the word line WL selected at the time of reading and the selected select gate SG in order to realize high-speed access.

  Semiconductor device 1 further includes a memory array 26. The memory array 26 includes memory blocks BLOCK0 to BLOCKn that are formed in wells that are separated from each other.

  Memory block BLOCK 0 includes memory cells 30 and 32 and a select gate 28. In the memory block BLOCK0, memory cells corresponding to the select gate line SGL, word lines WL0, WL1 and source line SL selected by the X decoder 18 are selected, and a signal corresponding to data is received from the main bit line MBL and data is held. Is done. FIG. 1 representatively shows select gate 28 and memory cells 30 and 32 corresponding to selected select gate line SGL, word lines WL0 and WL1, and source line SL.

  FIG. 2 is a circuit diagram showing the configuration of write / erase control unit 2 and positive voltage generation circuit 4 in FIG.

  Referring to FIG. 2, positive voltage generating circuit 4 includes a boosting circuit 50 that performs a boosting operation in response to clock signals φ and / φ, resistors R1 and R2 that divide the potential of the output node of boosting circuit 50, and a reference. A reference potential generation circuit 76 that generates the potentials Vref1 to Vref3 and a comparator 74 that compares the potential DIV1 divided by the resistors R1 and R2 with the reference potential Vref1 and outputs a signal VPPE.

  The positive voltage generation circuit 4 further includes a boosting oscillator 54 that outputs a boosting clock signal CLKP, a NAND circuit 56 that receives the clock signal CLKP and the signal VPPEN, an output that is inverted from the NAND circuit 56, and an inverted clock signal. An inverter 58 that outputs φ, an inverter 60 that receives the output of NAND circuit 56, and an inverter 62 that receives and inverts the output of inverter 60 and outputs clock signal / φ are included.

  Positive voltage generation circuit 4 further includes a VDC 52 that drops power supply potential VCC in accordance with control signal VDCCONT and outputs power supply potential VCCL. Power supply potential VCCL is applied to inverters 58 and 62 as an operating power supply potential. Therefore, the amplitudes of clock signals φ and / φ become power supply potential VCCL.

  Note that a load capacitor CL is connected to the output node of the booster circuit 50. For example, in the case of a flash memory, the load capacitance CL changes in accordance with the number of selected bit lines determined by the write data pattern.

  The write & erase control unit 2 includes a voltage detection circuit 69. The voltage detection circuit 69 compares the resistors R3 and R4 connected in series for dividing the potential VPP output from the booster circuit 50, the potential DIV2 divided by the resistors R3 and R4, and the reference potential Vref2. The comparator 70 that outputs the signal CP01, the resistors R5 and R6 connected in series for dividing the potential VPP, the potential DIV3 divided by the resistors R5 and R6, and the reference potential Vref3 are compared, and the signal CP02 is obtained. And a comparator 72 for outputting.

  The write & erase control unit 2 further includes a system clock oscillator 64 that generates a system clock CLKS, which is a time reference for observing the time constant, and a read only memory (ROM) for storing information corresponding to a predetermined time constant. ) 66 and a booster control circuit 68 that outputs a control signal VDCCONT for controlling the VDC 52 based on the clock signal CLKS, the signals CP01 and CP02, and the information stored in the ROM 66.

  FIG. 3 is a circuit diagram showing a configuration of the booster circuit 50.

  Referring to FIG. 3, booster circuit 50 includes an N-channel MOS transistor 82 diode-connected in the direction from the power supply node to node N1, and a capacitor 84 having one end connected to node N1 and receiving clock signal φ at the other end. N-channel MOS transistor 86 diode-connected so that the direction from node N1 to node N2 is the forward direction, and capacitor 88 having one end connected to node N2 and the other end coupled to clock signal / φ including.

  Boost circuit 50 further includes an N-channel MOS transistor 90 diode-connected so that the direction from node N2 to node N3 is the forward direction, and a capacitor connected at one end to node N3 and receiving clock signal φ at the other end. 92, an N-channel MOS transistor 94 connected so that the direction from node N3 to node N4 is the forward direction, capacitor 96 having one end connected to node N4 and receiving clock signal φ at the other end, and node N4 To N node MOS transistor 98 connected so that the direction from node N5 toward node N5 is the forward direction.

  Boosted potential VPP is output from node N5.

  FIG. 4 is a block diagram showing a specific configuration of booster control circuit 68 in FIG.

  Referring to FIG. 4, booster control circuit 68 compares count circuit CN that outputs count number CN according to clock signal CLKS, and the specified system clock number information N provided from count number CN and ROM 66. The comparison circuit 404, the comparison circuit 406 for comparing the count number CN and the prescribed system clock number information M given from the ROM 66, and the control signal VDCCONT according to the signals CP01 and CP02 and the outputs of the comparison circuits 404 and 406 Determination logic 408 to be output.

  As the voltage starts to rise, the system clock oscillator 64 of FIG. 2 starts oscillating and the count circuit 402 counts. The count circuit 402 outputs the count number CN to the comparison circuit 404.

  On the other hand, the specified system clock number information N from the ROM 66 is input to the comparison circuit 404, and a different logic signal OUT1 is output depending on whether the count number CN is less than N or more than N.

  When the control signal CP01 changes from the L level to the H level and the logic signal OUT1 indicates less than N, the determination logic 408 outputs the instruction signal VDCCONT for reducing the driving force of the charge pump.

  On the other hand, when the control signal CP01 changes from the L level to the H level and the logic signal OUT1 indicates N or more, the determination logic 408 outputs the instruction signal VDCCONT so as not to change the driving force of the charge pump.

  Similarly, the comparison circuit 406 changes the logic signal OUT2 depending on whether the count number CN is greater than or equal to M or less than M. When the control signal CP02 changes from the L level to the H level and the logic signal OUT2 indicates less than M when the control signal CP02 changes from the L level, the determination logic 408 changes the instruction signal VDCCONT so as to reduce the driving force of the charge pump.

  On the other hand, when the control signal CP02 changes from the L level to the H level and the logic signal OUT2 indicates M or more, the determination logic 408 outputs the instruction signal VDCCONT so as not to change the driving force of the charge pump.

  FIG. 5 is an operation waveform diagram for explaining the operation of the positive voltage generating circuit according to the first embodiment.

2 and 5, boosting oscillator 54 generates clock signal CLKP, and boost enable signal VPPEN is at the H level at time t0. Then, complementary clock signals φ, / φ are output from inverters 58 and 62. The H level of the complementary clock signals φ, / φ is given by the potential VCCL obtained by stepping down the power supply potential VCC given from the outside by the step-down circuit VDC52. The reference potential generation circuit 76 generates three types of reference potentials Vref1 to Vref3. It should be noted that the magnitudes of the three reference potentials are Vref1>Vref3> Vref2 (2)
There is a relationship.

  The comparators 70, 72, and 74 compare the potentials DIV1 to DIV3 divided from the boosted potential VPP with the reference potentials Vref1 to Vref3, respectively, to observe the boosted potential VPP.

  The booster control circuit 68 receives the system clock CLKS and the outputs of the comparators 70 and 72, and outputs a VDC control signal VDCCONT based on information previously acquired from the ROM 66. The ROM 66 retains information on how many clocks the system clock CLKS is and what the outputs of the comparators 70 and 72 should be inverted. Booster control circuit 68 controls potential VCCL which is the H level of complementary clock signals φ, / φ by signal VDCCONT.

  When the booster circuit 50 starts the boosting operation at time t0 to t1, the boosted potential VPP starts to rise at a speed corresponding to the time constant τ1. At time t1, the potential VPP reaches the potential VPP1. The potential VPP1 is expressed by the following formula (3).

VPP1 = (R5 + R6) / R6 * Vref2 (3)
At this time, the comparator 70 detects this, and the signal CP01 is inverted from the L level to the H level. The booster control circuit 68 has acquired a predetermined number N of clocks from the ROM 66. Then, the booster control circuit 68 compares the clock number X and the clock number N when the signal CP01 is inverted.

  When the clock number X is smaller than the clock number N, the booster control circuit 68 determines that the driving power of the booster circuit 50 is large and outputs a control signal VDCCONT to the VDC 52 to increase the time constant. The potential VCCL is decreased from the potential VCCL0 to the potential VCCL1. As a result, the driving force of the booster circuit 50 is reduced.

  From time t1 to t2, the booster circuit 50 continues the boosting operation in a state where the driving force is reduced by one step, and the time constant of the rise of the boosted potential VPP increases to τ2. Here, τ1 <τ2.

  At time t2, the potential VPP reaches the potential VPP2. The potential VPP2 is expressed by the following formula (4).

VPP2 = (R3 + R4) / R4 * Vref3 (4)
At this time, the comparator 72 detects this, and the signal CP02 is inverted from the L level to the H level.

  The booster control circuit 68 compares the predetermined clock number M acquired from the ROM 66 with the clock number Y when the signal CP02 is inverted. When the clock number Y is smaller than the clock number M, the booster control circuit 68 determines that the driving power of the booster circuit is still large. In order to increase the time constant, the booster control circuit 68 outputs a control signal VDCCONT to the VDC 52 and lowers the level of the potential VCCL from the potential VCCL1 to the potential VCCL2. As a result, the driving force of the booster circuit 50 is further reduced.

  The booster circuit continues the boosting operation in this state from time t2 to t3, and at this time, the time constant when the boosted potential rises becomes τ3. Note that τ2 <τ3.

  Thus, since the driving force of the booster circuit 50 is optimized, the power consumption in the booster circuit 50 is reduced. In this state, the potential VPP reaches the target reached potential VPP0 at time t3. VPP0 is expressed by the following equation (5).

VPP0 = (R1 + R2) / R2 * Vref1 (5)
After time t3, the comparator 74 compares the potential DIV1 obtained by dividing the potential VPP with the reference potential Vref1, and when the potential DIV1 exceeds the reference potential Vref1, the output VPPEN is inverted from the H level to the L level. As a result, the complementary clock signals φ, / φ are not supplied to the booster circuit 50 and the boosting operation is stopped.

  Thereafter, the comparator 74 monitors the potential VPP, and when the potential drop occurs, the comparator inverting the output VPPE from the L level to the H level and restarts the boosting operation again. When the boosting operation is resumed, the potential VPP increases. Subsequent operations are the same as in the conventional example, but the amplitude of the clock signals φ and / φ is optimized so that the driving power of the booster circuit 50 is not too large. Become smaller. Even during the regulation operation after time t3, the power consumption of the booster circuit 50 is smaller than that of the conventional example.

  FIG. 6 is a flowchart showing the operation of the booster control circuit 68 in FIG.

  Referring to FIGS. 2 and 6, when the step-up operation is started in step S1, first, in step S2, step-up unit control circuit 68 acquires information N and M on the number of clocks corresponding to the target time constant from ROM 66. To do.

  In step S3, it is determined whether or not the clock number X when the signal CP01 output from the comparator 70 changes to H level is smaller than the clock number N read from the ROM 66. If the clock number X is not smaller than the clock number N, the process directly proceeds to step S7. On the other hand, when the clock number X is smaller than the clock number N, the process proceeds to step S4, and the driving force of the booster circuit 50 is decreased by a predetermined amount. Then, the process proceeds to step S5.

  In step S5, the clock number X when the signal CP02 output from the comparator 72 becomes H level is compared with the clock number M read from the ROM. If the clock number X is not smaller than the clock number M, the process proceeds directly to step S7. On the other hand, if the clock number X is smaller than the clock number M, the process proceeds to step S6 and the driving force of the booster circuit 50 is decreased by a predetermined amount. Then, the process proceeds to step S7.

  In step S7, the boosting and regulating operations are continued, and the boosting operation is finished in step S8.

  In steps S3 and S5, if it takes a time longer than the prescribed number of clocks to invert the signals CP01 and CP02, there is no need to reduce the driving force, so no measures for reducing the driving force are taken. Proceed directly to step S7.

  In this way, the time constant at the time of rising is monitored in real time while the boosted potential is rising, and the driving force is adjusted. Although the case where both signals CP01 and CP02 are used is shown, the driving force may be adjusted using only one of signals CP01 and CP02.

  The rise time constant of the boosted potential is a factor representing the relative relationship between the driving force of the booster circuit and the load capacity. When the driving force is large with respect to the load capacity, the time constant becomes small. Conversely, when the driving force is small relative to the load capacity of the booster circuit, the time constant increases. The change in the time constant is monitored in real time by measuring the time to reach a predetermined reference potential using the system clock. Thus, the driving force can be optimized even when the relative relationship between the driving force and the load varies due to the power supply voltage, the load capacity, and other factors.

  In other words, the driving force is adjusted autonomously without external information such as the power supply voltage and the number of selected bit lines. As a result, current consumption can be reduced and the amount of ripple can be improved.

[Embodiment 2]
FIG. 7 is a circuit diagram showing the configuration of the write & erase control unit and positive voltage generation circuit of the second embodiment.

  Referring to FIG. 7, positive voltage generating circuit 104 has a constant operating power supply voltage for inverters 58 and 62 in the configuration of positive voltage generating circuit 4 described in FIG. 2, and boosts instead of boosting oscillator 54. VCO 110 for use is included. Since the other configuration of positive voltage generating circuit 104 is the same as that of positive voltage generating circuit 4 in FIG. 2, description thereof will not be repeated.

  Write & erase control unit 102 includes boosting unit control circuit 106 and ROM 108 in place of boosting unit control circuit 68 and ROM 66 in the configuration of write & erase control unit 2 in the figure. The other configuration of write & erase control unit 2 is the same as that of write & erase control unit 2, and therefore description thereof will not be repeated.

  In the first embodiment, the amplitudes of the complementary clock signals φ and / φ are reduced as means for reducing the driving force. In the second embodiment, instead of changing the amplitudes of the complementary clock signals φ and / φ, the same effect as in the first embodiment is obtained by reducing the frequency f of the complementary clock signals φ and / φ.

  A voltage-controlled oscillator (VCO) is used as a source for generating a boosting clock. Upon receiving a control signal VCOCONT output from the booster control circuit 106, the boosting VCO 110 sets the frequency of the clock signal CLKP. Lower. When the frequency of the clock signal CLKP changes, the frequencies of the clock signals φ and / φ also change accordingly.

  FIG. 8 is a circuit diagram showing a specific configuration of boosting VCO 110 in FIG.

  Referring to FIG. 8, boosting VCO 110 includes an oscillation control voltage selection signal generation circuit 410, an oscillation control voltage generation circuit 412, and a ring oscillator 414.

  The oscillation control voltage selection signal generation circuit 410 receives an inverter 416 that receives and inverts the control signal VCONT1, an inverter 418 that receives and inverts the control signal VCONT2, and a NAND circuit that receives the control signals VCONT1 and VCOCONT2 and outputs a selection signal A 420, a NAND circuit 422 that receives the output of the inverter 416 and the control signal VCOCONT2, and outputs a selection signal B; a NAND circuit 424 that receives the output of the control signal VCOCONT1 and the inverter 418 and outputs a selection signal C; A NAND circuit 426 that receives the outputs of 416 and 418 and outputs a selection signal D.

  The oscillation control voltage generation circuit 412 includes a resistor 432 connected between the node N31 and the node N32, an NPN transistor 428 having a base and a collector connected to the node N32 and an emitter connected to the ground node, and a node N31 and a node A resistor 434 connected to N33, a resistor 436 connected between node N33 and node N34, and an NPN transistor 430 having a base and a collector connected to node N34 and an emitter connected to the ground node. Including. The size of the NPN transistor 430 is N times the size of the NPN transistor 428.

  The oscillation control voltage generation circuit 412 further includes a comparison circuit 438 in which a positive input node is connected to the node N32, a negative input node is connected to the node N33, and an output is connected to the node N31, and between the node N31 and the node N35. A resistor 440 to be connected, a resistor 442 connected between the node N35 and the node N36, a resistor 444 connected between the node N36 and the node N37, and a node N37 connected to the ground node. And a resistor 446.

  The resistance values of the resistors 440 to 446 are set so that the potentials of the nodes N35, N36, and N37 are 0.9V, 0.6V, and 0.3V, respectively, when the node N31 is 1.2V, for example. Selected.

  Oscillation control voltage generation circuit 412 is further connected between node N31 and node N38, and has an N channel MOS transistor 448 that receives control signal D at its gate, and is connected between nodes N35 and N38 and has a control signal at its gate. N channel MOS transistor 450 receiving C, N channel MOS transistor 452 connected between nodes N36 and N38 and receiving control signal B at the gate, and connected between nodes N37 and N38 and connected to the control signal at the gate N channel MOS transistor 454 receiving A.

  The ring oscillator 414 includes three stages of differential inverting amplifiers 456, 458, and 460 that are activated in response to the control signal ACT and connected in a ring shape whose delay time changes in accordance with the control voltage VCONT output from the node N38. Including.

  Differential inverting amplifier 456 is connected between a power supply node and node N39 and receives a control voltage VCONT at its gate, and is connected between the power supply node and node N40 and receives a control voltage VCONT at its gate. P-channel MOS transistor 464, an N-channel MOS transistor 466 connected between nodes N39 and N41 and receiving one output of differential inverting amplifier 460 at its gate, and a gate connected between nodes N40 and N41 N channel MOS transistor 468 receiving the other output of differential inverting amplifier 460, and N channel MOS transistor 470 connected between node N41 and the ground node and receiving control signal ACT at its gate.

  Since the configuration of differential inverting amplifiers 458 and 460 is similar to that of differential inverting amplifier 456, description thereof will not be repeated. A clock signal CLKP is output from one output of the differential inverting amplifier 460.

  The ring oscillator 414 includes three stages of differential inverting amplifiers 456, 458, and 460, and the oscillation period is determined depending on the delay time of each stage. As the level of the control signal VCONT changes according to the control signals VCONT1 and VCOCONT2, the oscillation cycle becomes variable. When the level of control voltage VCONT increases, the impedances of P channel MOS transistors 462 and 464 constituting the differential inverting amplifier increase, and the oscillation period of clock signal CLKP increases. The control signals VCONT1 and VCONCON2 are signals generated based on the control signals CP01 and CP02 in FIG. 6, respectively.

  FIG. 9 is an operation waveform diagram for explaining the operation of the circuit shown in FIG.

  7 and 9, boosting VCO 110 generates clock signal CLKP, and boost enable signal VPPEN is at the H level at time t0. Then, complementary clock signals φ, / φ are output from inverters 58 and 62. The reference potential generation circuit 76 generates three types of reference potentials Vref1 to Vref3. Note that the magnitudes of the three reference potentials have the relationship of Equation (2) described above.

  The comparators 70, 72, and 74 compare the potentials DIV1 to DIV3 divided from the boosted potential VPP with the reference potentials Vref1 to Vref3, respectively, to observe the boosted potential VPP.

  The booster control circuit 106 receives the system clock CLKS and the outputs of the comparators 70 and 72, and outputs a VDC control signal VDCCONT based on information acquired from the ROM 108 in advance. The ROM 108 holds information indicating how many clocks the system clock CLKS is and what the outputs of the comparators 70 and 72 should be inverted. The booster control circuit 106 controls the frequency of the clock signal CLKP generated by the booster VCO 110 according to the signal VCOCONT.

  At time t0 to t1, when the frequency of the clock signal CLKP is f0 and the booster circuit 50 starts the boosting operation, the boosted potential VPP starts to rise at a speed corresponding to the time constant τ1. At time t1, the potential VPP reaches the potential VPP1. Note that the potential VPP1 is expressed by Equation (3) described above.

  At this time, the comparator 70 detects this, and the signal CP01 is inverted from the L level to the H level. The booster control circuit 106 has acquired a predetermined number of clocks N from the ROM 108. The booster control circuit 106 compares the clock number X and the clock number N corresponding to the time required until the signal CP01 is inverted.

  When the clock number X is smaller than the clock number N, the booster control circuit 106 determines that the driving power of the booster circuit 50 is large, and outputs a control signal VCOCONT to the VCO 110 to increase the time constant. The frequency of the clock signal CLKP is lowered from f0 to f1. As a result, the driving force of the booster circuit 50 is reduced by one step.

  From time t1 to t2, the booster circuit 50 continues the boosting operation in a state where the driving force is reduced by one step, and the time constant of the rise of the boosted potential VPP increases to τ2. Here, τ1 <τ2.

  At time t2, the potential VPP reaches the potential VPP2. Note that the potential VPP2 is expressed by the equation (4) described above.

  At this time, the comparator 72 detects this, and the signal CP02 is inverted from the L level to the H level.

  The booster control circuit 106 compares the predetermined clock number M acquired from the ROM 108 with the clock number Y corresponding to the time required until the signal CP02 is inverted. When the clock number Y is smaller than the clock number M, the booster control circuit 106 determines that the driving power of the booster circuit is still large. The booster control circuit 106 determines that the driving power of the booster circuit 50 is large, outputs a control signal VCOCONT to the VCO 110 in order to increase the time constant, and lowers the frequency of the clock signal CLKP from f1 to f2. As a result, the driving force of the booster circuit 50 is further reduced by one step.

  The booster circuit continues the boosting operation in this state from time t2 to t3, and at this time, the time constant when the boosted potential rises becomes τ3. Note that τ2 <τ3.

  Thus, since the driving force of the booster circuit 50 is optimized, the power consumption in the booster circuit 50 is reduced. In this state, the potential VPP reaches the target reached potential VPP0 at time t3. VPP0 is expressed by the above-described equation (5).

  After time t3, the comparator 74 compares the potential DIV1 obtained by dividing the potential VPP with the reference potential Vref1, and when the potential DIV1 exceeds the reference potential Vref1, the output VPPEN is inverted from the H level to the L level. As a result, the complementary clock signals φ, / φ are not supplied to the booster circuit 50 and the boosting operation is stopped.

  Thereafter, the comparator 74 monitors the potential VPP, and when the potential drop occurs, the comparator inverting the output VPPE from the L level to the H level and restarts the boosting operation again. When the boosting operation is resumed, the potential VPP increases. The subsequent operation is the same as in the conventional example, but the frequency of the clock signal CLKP is optimized so that the driving power of the booster circuit 50 is not too large, so that the ripple amount of the potential VPP is smaller than that in the conventional example. . Even during the regulation operation after time t3, the power consumption of the booster circuit 50 is smaller than that of the conventional example.

  Also in the second embodiment, the time constant of the waveform is monitored in real time while the boosted potential is rising, and the driving force of the booster circuit is adjusted. Thereby, even when the relative relationship between the driving force and the load varies due to the power supply voltage, the load capacity, and other factors, the driving force of the booster circuit can be optimized.

[Embodiment 3]
FIG. 10 is a circuit diagram showing the configuration of the positive voltage generation circuit and the write & erase control unit used in the third embodiment.

  Referring to FIG. 10, positive voltage generation circuit 204 has a configuration in which the power supply voltage of inverters 58 and 62 is constant in the configuration of positive voltage generation circuit 4 described with reference to FIG. 210. The response speed of the comparator 210 changes according to the control signal CPCONT. Since the configuration of other parts of positive voltage generation circuit 204 is the same as that of positive voltage generation circuit 4 described in FIG. 2, description thereof will not be repeated.

  The write & erase control unit 202 is the same as the write & erase control unit 2 described in FIG. 2 except that the comparator 72, resistors R3 and R4 are removed, and the booster control circuit 68 and the ROM 66 are replaced. A booster control circuit 206 and a ROM 208 are included. Since the configuration of other parts of write & erase control unit 202 is the same as that of write & erase control unit 2, description thereof will not be repeated.

  FIG. 11 is a circuit diagram showing a configuration of comparator 210 in FIG.

  Referring to FIG. 11, comparator 210 is connected between a power supply node and node N11 and has a gate connected to node N11 and a P-channel MOS transistor 212 connected between node N11 and a node connected between node N11 and node N13. N-channel MOS transistor 216 receiving reference potential Vref1, P-channel MOS transistor 214 connected between the power supply node and node N12 and having the gate connected to node N11, and connected between nodes N12 and N13 and the gate N channel MOS transistor 218 to which divided potential DIV is coupled.

  Comparator 210 further includes an N channel MOS transistor 211 connected between node N13 and the ground node and receiving a signal CPEN at the gate, and an N channel connected between node N13 and the ground node and receiving a control signal CPCONT at the gate. MOS transistor 212. The signal CPEN is a signal for activating the comparator 210.

  Referring to FIG. 10 again, in the first and second embodiments, the driving force is reduced when the driving force of the booster circuit is larger than the load. In the third embodiment, the response of the comparator 210 is improved instead. For this purpose, the bias current is increased by the transistor 212.

  FIG. 12 is a first operation waveform diagram for explaining the operation of the third embodiment.

  FIG. 13 is a second operation waveform diagram for explaining the operation of the third embodiment.

  In FIG. 11, when the transistor 212 of the comparator 210 is in a non-conducting state, the ripple Vr1 of the potential VPP in the steady state is determined according to the response time td1 of the comparator 210 as shown in FIG. In this case, the ripple amount is the same as in the case of the prior art.

  On the other hand, when the transistor 212 is turned on, the amount of ripple is reduced. As shown in FIG. 13, when the signal CP01 rises from the L level to the H level at time t1, the period from time t0 to t1 is measured by the system clock CLKS, and the specified clock number N stored in the ROM 208 is To be compared. When the output signal CP01 of the comparator 70 is inverted from the L level to the H level within the specified number of clocks N, the booster control circuit 206 activates the control signal CPCONT from the L level to the H level.

  Then, although only the transistor 211 was initially a bias current supply source, the transistor 212 is also added as a bias current supply source. As a result, the sum of the bias currents of the comparators increases, so that the response of the comparators improves. Accordingly, the response time of the comparator is shortened from td1 in FIG. 12 to td2 in FIG. As a result, the ripple amount decreases from Vr1 to Vr2.

  On the other hand, when the output of the comparator 70 is inverted after a time corresponding to the specified number of clocks N, the bias current of the comparator is kept small as in the conventional case, so that the consumption current of the comparator is reduced.

  FIG. 14 is a flowchart for explaining the operation of the booster control circuit according to the third embodiment.

  Referring to FIG. 14, the boosting operation is started in step S11. In step S12, the booster control circuit 206 acquires information representing the target time constant τ from the ROM 208, that is, the clock number N.

  In step S13, the input number X of the system clock CLKS when the signal CP01 changes from the L level to the H level is compared with the clock number N acquired from the ROM. If the number of clocks X <N, the process proceeds to step S14, and the booster control circuit 206 activates a control signal CPCONT for increasing the bias current of the comparator. Then, the process proceeds to step S15.

  On the other hand, if the number of clocks X <N is not satisfied in step S13, the process proceeds directly to step S15.

  In step S15, the boosting and regulating operations are continued. In step S16, the control during the boosting operation ends.

  Also in the third embodiment, the time constant of the waveform is monitored in real time while the boosted potential is rising, and the response speed of the comparator is adjusted. Thus, even when the relative relationship between the driving force and the load varies due to the power supply voltage, the load capacity, and other factors, the response speed of the comparator can be optimized, which is effective in reducing ripple and power consumption.

[Embodiment 4]
FIG. 15 is a circuit diagram showing the configuration of the write & erase control unit and positive voltage generation circuit of the fourth embodiment.

  Referring to FIG. 15, positive voltage generation circuit 304 has the same configuration as that of positive voltage generation circuit 4 described with reference to FIG. 2, and the power supply voltages of inverters 58 and 62 are constant, and instead of booster circuit 50. A booster circuit 310 is included. Since other structures of positive voltage generating circuit 304 are the same as those of positive voltage generating circuit 4, description thereof will not be repeated.

  The write & erase control unit 302 includes a boost unit control circuit 306 and a ROM 308 in place of the boost unit control circuit 68 and the ROM 66 in the configuration of the write & erase control unit 2 described with reference to FIG. The other configuration of write & erase control unit 302 is the same as that of write & erase control unit 2, and therefore description thereof will not be repeated.

  The booster control circuit 306 supplies signals CAPCONT1 and CAPCONT2 for controlling the capacity of the charge pump in the booster circuit to the booster circuit 310.

  FIG. 16 is a circuit diagram showing a configuration of booster circuit 310 in FIG.

  Referring to FIG. 16, booster circuit 310 has an N-channel MOS transistor 322 whose gate and drain are connected to the power supply node and whose source is connected to node N11, and one end connected to node N11 and is supplied with clock signal φ. A variable capacitance circuit 312 having the other end connected to node N21, an N-channel MOS transistor 324 having a gate and drain connected to node N11 and a source connected to node N12, and one end connected to node N12 and a clock signal / A variable capacitance circuit 314 having the other end connected to node N22 to which φ is applied, and an N channel MOS transistor 326 having a gate and drain connected to node N12 and a source connected to node N13 are included.

  Boost circuit 310 further includes a variable capacitance circuit 316 having one end connected to node N14 and the other end connected to node N24 to which clock signal φ is applied, a gate and a drain connected to node N14, and a source connected to node N15. N channel MOS transistor 328 connected. Boosted potential VPP is output from node N15.

  Booster circuit 310 further includes a level shift circuit 320 that shifts the respective H levels of control signals CAPCONT1 and CAPCONT2 to boosted potential VPP and outputs control signals HCAPCONT1 and HCAPCONT2. N channel MOS transistors 322 to 328 are diode-connected and perform an equivalent function to diode elements connected in series.

  The variable capacitance circuit 312 includes a capacitor 332 connected between the node N11 and the node N21, a P-channel MOS transistor 342 and a capacitor 352 connected in series between the node N11 and the node N21, and the node N11 and the node P channel MOS transistor 362 and capacitor 372 connected in series with N21. A control signal HCAPCONT1 is applied to the gate of the P-channel MOS transistor 342. Control signal HCAPCONT2 is applied to the gate of P-channel MOS transistor 362.

  The variable capacitance circuit 314 includes a capacitor 336 connected between the node N12 and the node N22, a P-channel MOS transistor 344 and a capacitor 354 connected in series between the node N12 and the node N22, and the node N12 and the node P channel MOS transistor 364 and capacitor 374 connected in series with N22. Control signal HCAPCONT1 is applied to the gate of P channel MOS transistor 344. A control signal HCAPCONT2 is applied to the gate of P channel MOS transistor 364.

  Variable capacitance circuit 316 includes a capacitor 338 connected between node N14 and node N24, a P-channel MOS transistor 346 and capacitor 356 connected in series between node N14 and node N24, and node N14 and a node P channel MOS transistor 366 and capacitor 376 connected in series with N24. Control signal HCAPCONT1 is applied to the gate of P-channel MOS transistor 346. A control signal HCAPCONT2 is applied to the gate of P channel MOS transistor 366.

  FIG. 17 is an operation waveform diagram for explaining the operation of the fourth embodiment.

  Referring to FIG. 17, at time t0 at the beginning of the boost operation, boost circuit 310 operates in a state where variable capacitance circuits 312, 314, and 316 have the maximum capacitance value. That is, signals CAPCONT1 and CAPCONT2 are both at L level, and in response, signals HCAPCONT1 and HCAPCONT2 are both at L level, and P-channel MOS transistors 342 to 346 and 362 to 366 are in a conductive state. At this time, the total capacitance value of the variable capacitance circuit 312 is the sum of the capacitance values of the capacitors 332, 352, and 372. In the variable capacitance circuits 314 and 316, the capacitance value is the sum of the three capacitance values.

  The booster circuit 310 operates between times t0 and t1, and at this time, the potential VPP is increased with the time constant τ1.

  When the potential VPP reaches the potential VPP1 at time t1, the comparator 70 inverts the signal CP01. When the time required up to this time is within the prescribed number N of clocks registered in the ROM 208 in advance, the capacity control signal CAPCONT1 for controlling the capacity values of the variable capacity circuits 312 to 316 is changed from the L level. Activated to H level. This signal is level-converted via the level shift circuit 320 to become a signal HCAPCONT1.

  As a result, P channel MOS transistors 342 to 346 are turned off, and capacitors 352 to 356 are excluded from the boosting capacity of the charge pump. As a result, the capacitance value of the variable capacitance circuit 312 is the sum of the capacitance values of the capacitors 332 and 372. Similarly, in the variable capacitance circuits 314 and 316, each capacitance value is the sum of two capacitors.

  As a result, the driving force of the booster circuit is reduced from time t1 to time t2, and the potential VPP continues to rise with the time constant τ2.

  When the potential VPP reaches the potential VPP2 at time t2, the comparator 72 detects this and changes the control signal CP02 from the L level to the H level. The elapsed time up to this time is measured by the booster control circuit 306 with reference to the clock signal CLKS. Then, the result is compared with a predetermined clock number M registered in advance in the ROM 308.

  When the elapsed time is shorter than the time corresponding to the prescribed number of clocks M, the booster control circuit 306 changes the control signal CAPCONT2 from the L level to the H level. This signal is level-converted through the level shift circuit 320 so that the potential VPP becomes H level, and a signal HCAPCONT2 is output. When signal HCAPCONT2 becomes H level, P channel MOS transistors 362, 364, and 366 are both rendered non-conductive, and capacitors 372, 374, and 376 are excluded from the boost capacitance.

  As a result, the capacitance value of the variable capacitance circuit 312 becomes equal to the capacitance value of the capacitor 332. Similarly, the capacitance values of the variable capacitance circuits 314 and 316 are the capacitance values of one capacitor. As a result, the booster circuit 310 further reduces the driving force, and the potential VPP continues to rise with the time constant τ3 from time t2 to t3. The operation of booster control circuit 306 performs the same control as in the flowchart shown in FIG. 14, and therefore description thereof will not be repeated.

  Also in the fourth embodiment, the time constant of the waveform is monitored in real time while the boosted potential is rising, and the driving force of the booster circuit is adjusted. As a result, even when the relative relationship between the driving force and the load varies due to the power supply voltage, the load capacity, and other factors, the driving force of the booster circuit is optimized, and ripple and power consumption can be reduced.

  In the above embodiment, the example in which the driving force is adjusted so that the time constant approaches the predetermined value when the observed time constant is smaller than the predetermined value has been described. Further, when the observed time constant is larger than a predetermined value, the present invention can also be applied when adjusting the driving force so that the time constant approaches the predetermined value.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is the block diagram which showed the structure of the semiconductor device 1 of this invention. FIG. 2 is a circuit diagram showing configurations of a write & erase control unit 2 and a positive voltage generation circuit 4 in FIG. 1. 3 is a circuit diagram showing a configuration of a booster circuit 50. FIG. FIG. 3 is a block diagram showing a specific configuration of a booster control circuit 68 in FIG. 2. FIG. 6 is an operation waveform diagram for illustrating the operation of the positive voltage generation circuit according to the first embodiment. 3 is a flowchart showing the operation of a booster control circuit 68 in FIG. FIG. 6 is a circuit diagram showing a configuration of a write & erase control unit and a positive voltage generation circuit according to a second embodiment. FIG. 8 is a circuit diagram showing a specific configuration of the boosting VCO 110 in FIG. 7. FIG. 8 is an operation waveform diagram for explaining the operation of the circuit shown in FIG. 7. FIG. 10 is a circuit diagram showing a configuration of a positive voltage generation circuit and a write & erase control unit used in the third embodiment. FIG. 11 is a circuit diagram illustrating a configuration of a comparator 210 in FIG. 10. FIG. 10 is a first operation waveform diagram for illustrating the operation of the third embodiment. FIG. 11 is a second operation waveform diagram for illustrating the operation of the third embodiment. 10 is a flowchart for explaining an operation of the booster control circuit according to the third embodiment. FIG. 10 is a circuit diagram showing configurations of a write & erase control unit and a positive voltage generation circuit according to a fourth embodiment. FIG. 16 is a circuit diagram showing a configuration of a booster circuit 310 in FIG. 15. FIG. 10 is an operation waveform diagram for illustrating the operation of the fourth embodiment. 3 is a circuit diagram showing a configuration of a potential generation circuit 500. FIG. 6 is a waveform diagram for explaining the operation of the potential generation circuit 500. FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor device, 2,102,202,302 Write & erase control part, 3 Voltage generation part, 4,104,204,304 Positive voltage generation circuit, 8 Negative voltage generation circuit, 12 Boost circuit, 14 Distributor, 16 address Buffer, 18, 20 Decoder, 22 Input / output buffer, 24 Y system control circuit, 26 Memory array, 28 Select gate, 30, 32 Memory cell, 50, 310 Booster circuit, 52 VDC, 54 Booster oscillator, 64 System clock oscillator , 66, 108, 208 ROM, 68, 106, 206, 306 Booster control circuit, 70, 72, 74, 210 Comparator, 76 Reference potential generation circuit, 82, 86, 90, 94, 98, 322 to 328, 342 346, 362-366, 211-218 transistor, 84 , 88, 92, 96, 332-338, 352-356, 372-376 Capacitor, 110 Boost VCO, 312-316 Variable capacity circuit, 320 Level shift circuit, BLOCK0-BLOCKn Memory block, CL load capacity, Cd decouple capacity MBL main bit line, R1-R6 resistors, SG select gate, SGL select gate line, SL source line, WL, WL0, WL1 word lines.

Claims (11)

Internal circuitry,
A potential generating circuit for generating an internal potential for use in the internal circuit;
A control circuit that observes the time constant of the change in the internal potential and controls the potential generation circuit so that the time constant is equivalent to the predetermined value when the time constant is smaller or larger than a predetermined value. A semiconductor device comprising: The control circuit includes:
A voltage detection circuit that detects the second potential when the internal potential sequentially rises or falls from the first potential to the third potential through the second potential, and outputs a voltage detection signal;
A system clock generation circuit for generating a system clock signal serving as a reference for observing the time constant;
Based on the voltage detection signal and the system clock signal, it is determined whether or not the predetermined time constant is the predetermined time constant based on whether or not the time from the first potential to the second potential is a predetermined time. The semiconductor device according to claim 1, further comprising: a booster control circuit that generates a control signal for controlling the potential generation circuit in response to the signal. The booster control circuit includes:
A count circuit for counting the system clock signal;
A comparison circuit that compares the count number output by the count circuit with a predetermined count number corresponding to the predetermined time;
The semiconductor device according to claim 2, further comprising: a determination logic circuit that determines the magnitude of the time constant based on the detection signal and an output signal of the comparison circuit and generates the control signal. The potential generation circuit includes:
A clock generator for generating a clock signal;
A booster circuit that boosts and outputs a power supply potential according to the clock signal,
2. The semiconductor device according to claim 1, wherein the control circuit instructs the clock generation unit to decrease the amplitude of the clock signal when the time constant is smaller than a predetermined value. The clock generator
An oscillator,
A clock buffer for outputting the clock signal according to the output of the oscillator;
The semiconductor device according to claim 4, further comprising: a power supply potential supply circuit that changes a power supply potential in accordance with an output of the control circuit and supplies an operation power supply potential to the clock buffer. The potential generation circuit includes:
A clock generator for generating a clock signal;
A booster circuit that boosts and outputs a power supply potential according to the clock signal,
The semiconductor device according to claim 1, wherein the control circuit instructs the clock generation unit to decrease the frequency of the clock signal when the time constant is smaller than a predetermined value. The clock generator
The semiconductor device according to claim 6, further comprising a voltage controlled oscillator that changes an oscillation frequency according to an output of the control circuit and outputs the clock signal. The potential generation circuit includes:
A comparison circuit that changes the response speed according to the output of the control circuit and compares the internal potential with a target potential;
A clock generator for supplying the clock signal according to the output of the comparison circuit;
The semiconductor device according to claim 1, further comprising a booster circuit that boosts and outputs a power supply potential according to the clock signal. The potential generation circuit includes:
A voltage dividing resistor that receives the internal potential and outputs a divided potential;
A reference potential generating circuit for generating a reference potential,
The comparison circuit is
A first transistor that receives the divided potential at its gate;
A second transistor having a source connected to a source of the first transistor so that the reference potential is received at a gate and a differential amplification transistor pair is formed with the first transistor;
A third and a fourth transistor connected in parallel to limit a sum of currents flowing through the first and second transistors;
The semiconductor device according to claim 8, wherein the third transistor receives an output of the control circuit at a gate. The potential generation circuit includes:
A clock generator for generating complementary first and second clock signals;
A booster circuit that boosts and outputs a power supply potential according to the first and second clock signals;
The booster circuit includes:
A plurality of rectifying elements connected in series between the power supply node and the output node;
A plurality of variable capacitance circuits, each having one end connected to a plurality of connection nodes of the plurality of rectifying elements, and a capacitance value changing according to an output of the control circuit;
The other ends of the plurality of variable capacitance circuits connected to odd connection nodes among the plurality of connection nodes counted from the power supply node receive the first clock signal,
2. The semiconductor device according to claim 1, wherein the other end of the plurality of variable capacitance circuits connected to an even-numbered connection node among the plurality of connection nodes counted from the power supply node receives the second clock signal. . Each of the plurality of variable capacitance circuits includes:
A first capacitor connected between the one end and the other end;
A switch connected in series between the one end and the other end and a second capacitor;
The semiconductor device according to claim 10, wherein the control circuit switches the switch from the same state to a non-conductive state when the time constant is smaller than a predetermined value.

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