JP2005108931A - Display and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a display for forming a drive circuit in a CMOS configuration uniformly within surface, using a laminated TFT which uses a polycrystalline semiconductor. <P>SOLUTION: After forming a gate electrode 32 and a gate insulating film on a substrate 12, an active layer 34 made of a polycrystalline semiconductor film is formed by a reactive thermal CVD method. A p-type source/drain layer 37 is allowed to remain only at a p-type TFT region 12p by the reactive thermal CVD method via an etching stopper layer 35a, in a shape of the gate electrode 32 of a p-type TFT region 12n and a p-type TFT region 12p, and further the active layer 34 is patterned into an island shape. An n-type source/drain layer 40 is film-formed by the reactive thermal CVD method via an etching stopper layer 35a in a shape of the gate electrode 32 of the n-type TFT region 12n. The p-type/n-type source/drain layers 37, 40 are patterned to form p-type/n-type source/drains 37a, 37b, 40a, 40b. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a display device having a CMOS circuit as a driving element such as an active matrix type liquid crystal display device or an organic electroluminescence (hereinafter referred to as EL) display device, and a display device.

  A thin film transistor (TFT) is used as a driving element in an active matrix display device. Of these, stacked TFTs in which the active layer is formed in a layer different from the source / drain regions are compared with planar TFTs in which the source / drain regions and the channel portion are formed of the same semiconductor layer. The advantage is that the number of masks used in the manufacturing process is small. Hereinafter, an example of a manufacturing process of a multilayer TFT in a display device will be described.

FIG. 11 is a cross-sectional view of a bottom gate type stacked TFT. In order to form the bottom gate type laminated TFT shown in this figure, first, the gate electrode 102 is patterned on the substrate 101, and the gate insulating film 103 is further formed. Next, after forming a semiconductor thin film 104 made of amorphous silicon containing no impurities by CVD, the semiconductor thin film 104 is polycrystallized by irradiating laser light, and this semiconductor thin film 104 is further patterned to form an active layer. 104a. Next, an insulating protective pattern 105 is formed so as to cover the central portion of the active layer 104a made of polycrystalline silicon. Thereafter, a semiconductor thin film 106 made of amorphous silicon containing impurities is formed while doping impurities by plasma CVD, and a metal film 107 is further formed thereon. Thereafter, by patterning the metal film 107 and the semiconductor thin film 106, a source region 106a and a drain region 106b made of the semiconductor thin film 106, and electrodes 107a and 107b made of the metal film 107 are formed. TFT is obtained. In such a bottom-gate stacked TFT, a channel is formed at the interface between the gate insulating film 103 and the active layer 104a. In addition, by setting the impurity concentration of the active layer 104a to 10 ¹⁷ / cm ³ or less, the active layer 104a can function as an electric field relaxation region (see Patent Document 1 below).

JP 2001-102584 A (refer to FIG. 1 and paragraphs 0009 to 0013 in JP)

  By the way, among flat panel type display devices using TFTs as driving elements, display devices using organic EL elements as light emitting elements have many excellent features such as color reproducibility, wide viewing angle, high speed response, and high contrast. It has the characteristics. Since the organic EL element used in this display device is a current-driven element, the pixel transistor for driving the organic EL element is preferably a polycrystalline silicon TFT using polycrystalline silicon having excellent current driving capability. For this reason, in the above-described stacked TFT, a high current driving capability can be obtained by configuring the active layer and the source / drain with polycrystalline silicon. In particular, in a p-type TFT, when an amorphous silicon film is used for the source and drain, the resistance value becomes extremely high. For this reason, when a p-type TFT and a complementary (CMOS configuration) TFT using the p-type TFT are formed, it is preferable to use a polycrystalline silicon TFT.

  Here, in the conventional process for manufacturing a polycrystalline silicon TFT, as described above, an amorphous silicon film is irradiated with an excimer laser and melted and recrystallized to form a polycrystalline silicon film. However, in such a method, not only the crystallization process is added, but also the characteristics of the thin film transistor are varied due to the variation in laser energy.

In particular, in the formation of the source / drain, the dopant is implanted by an ion doping apparatus or an ion implantation apparatus, and the impurity is activated by a method such as thermal annealing or lamp annealing. However, these devices are limited to a so-called fourth generation substrate having a substrate size of at most about 730 × 920 mm ² , and it is extremely difficult to increase the size of the device beyond that, which is a factor that hinders the increase in size of the display. ing.

  Therefore, the present invention can uniformly form a driving circuit having a CMOS structure, which is advantageous for low power consumption, by using a stacked TFT using a polycrystalline semiconductor, which increases the size. It is an object of the present invention to provide a display device that can be manufactured and a display device obtained by the manufacturing method.

  In order to achieve such an object, a method for manufacturing a display device according to the present invention is a display device in which a pixel driving circuit comprising a first conductive type thin film transistor and a second conductive type thin film transistor is provided on a substrate. It is a manufacturing method. In particular, the first method is a manufacturing method using a bottom gate type thin film transistor, and the second method is a method using a top gate type thin film transistor.

  In the first method, first, in the first step, a gate electrode is formed on the substrate and covered with a gate insulating film, and then in the second step, reaction energies of a plurality of different gases are used on the gate insulating film. An active layer made of a polycrystalline semiconductor thin film is formed by the reactive thermal CVD method. Next, in the third step, an insulating etching stopper layer having a shape covering the first region portion for forming the first conductivity type thin film transistor and the gate electrode in the second region for forming the second conductivity type thin film transistor, Formed on the active layer. In the fourth step, the second conductive type source / drain layer made of the polycrystalline semiconductor thin film containing the second conductive type impurity is further formed by the reactive thermal CVD method so as to cover the etching stopper layer. A film is formed on top. In the next fifth step, the second conductivity type source / drain layer is patterned into a shape covering the second region by etching using the resist pattern covering the second region as a mask, and the resist pattern, the etching stopper layer, The active layer is patterned into a shape covering the first region and the second region by etching using a mask. Thereafter, in a sixth step, the etching stopper layer in the first region is patterned into a shape covering the gate electrode. In the next seventh step, the first conductivity type source / drain layer made of the polycrystalline semiconductor thin film containing the first conductivity type impurity is formed by the reactive thermal CVD method, the etching stopper layer and the second conductivity type. The film is formed so as to cover the source / drain layers. After the above, in the eighth step, the second conductivity type source / drain layer and the first conductivity type source / drain layer are patterned. Thereby, the first conductivity type source / drain composed of the first conductivity type source / drain layer is formed in the first region, and the first conductivity type is formed on the second conductivity type source / drain layer in the second region. A second conductivity type source / drain is formed by laminating type source / drain layers.

  On the other hand, in the second method, first, in the first step, a source / source composed of a polycrystalline semiconductor thin film containing a first conductivity type impurity is formed by a reactive thermal CVD method using reaction energies of a plurality of different gases. A drain layer is formed on the substrate and patterned to form a first conductivity type source / drain in a first region where a first conductivity type thin film transistor is to be formed. Next, in the second step, a source / drain layer made of a polycrystalline semiconductor thin film containing a second conductivity type impurity by reactive thermal CVD with the first conductivity type source / drain covered with a mask. Is formed on the substrate and patterned to form the second conductivity type source / drain in the second region where the second conductivity type thin film transistor is formed. After the above, in the third step, an active layer made of a polycrystalline semiconductor thin film is formed by reactive thermal CVD in a state of covering the first conductivity type source / drain and the second conductivity type source / drain. Next, in the fourth step, a gate insulating film is formed on the active layer, and in the fifth step, a gate electrode is formed on the gate insulating film between the first conductivity type source / drain and between the second conductivity type source / drain. Form.

  According to the first manufacturing method and the second manufacturing method, the active layer, the first conductivity type source / drain layer, and the second conductivity type source / drain layer are formed by the reactive thermal CVD method. Thus, a laminated thin film transistor in which these layers made of a semiconductor thin film having crystallinity are laminated in advance can be obtained without particularly performing the step of crystallizing the semiconductor thin film. Accordingly, the active layer and the source / drain layer are made of a crystalline semiconductor thin film while omitting a crystallization process, so that the operation speed is faster than the case of using an amorphous semiconductor thin film. A stacked thin film transistor (first conductivity type and second conductivity type) is obtained. Further, by omitting the step for crystallization, it is not necessary to worry about various variations caused by the crystallization step, so that the characteristics can be made uniform. Furthermore, since a crystalline semiconductor thin film into which impurities are introduced in advance is formed as the source / drain layer, it is not necessary to perform a step for introducing impurities after the film formation.

  In the first manufacturing method, the second conductivity type source / drain formed in the second region is formed by stacking the first conductivity type source / drain layer on the second conductivity type source / drain layer. Become. However, each source / drain layer containing a high concentration of impurities has a large number of defect levels, and the depletion layer does not spread, so that it becomes an ohm junction instead of a pn junction. Therefore, the second conductivity type source / drain functions without any problem as the conductivity type disposed on the active layer side, that is, the source / drain of the second conductivity type.

  The present invention is also a display device obtained by the first manufacturing method and the second manufacturing method described above. This display device is provided with a pixel driving circuit composed of a first conductive type thin film transistor and a second conductive type thin film transistor. In particular, each thin film transistor includes a gate electrode, a gate insulating film on a substrate. In addition, an active layer made of a semiconductor thin film and a source / drain are stacked in this order or in the reverse order. Each thin film transistor is characterized in that the active layer and each source / drain are formed of a polycrystalline semiconductor thin film formed by a reactive thermal CVD method using reaction energy of a plurality of different gases. .

  As described above, according to the method for manufacturing a display device of the present invention, the active layer, the first conductivity type source / drain layer, and the second conductivity type source / drain layer are formed by reactive thermal CVD. By using a polycrystalline semiconductor thin film having a high operating speed, the ON current can be increased without driving the process of crystallizing the semiconductor thin film or introducing impurities into the source / drain layer. It is possible to obtain a stacked type first-conductivity-type and second-conductivity-type thin film transistor in which the current is increased. As a result, it is possible to simplify the manufacturing process and reduce the manufacturing cost, and to form a CMOS circuit using the first conductivity type and second conductivity type thin film transistors from which variations caused by crystallization are eliminated. It becomes possible. In addition, as described above, it becomes possible to form a thin film transistor with uniform characteristics on a larger substrate by omitting the crystallization step and the impurity introduction step, thereby reducing power consumption. A large display device including a small CMOS circuit can be realized.

  According to the display device of the present invention, the source / drain of the first conductivity type thin film transistor, the source / drain of the second conductivity type thin film transistor, and the active layer of these thin film transistors are obtained by the reactive thermal CVD method. By using the polycrystalline semiconductor thin film thus formed, the stacked thin film transistors constituting the CMOS can be uniformly provided in a plane with respect to the large-sized substrate, and the power consumption can be reduced and the size can be increased.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following embodiments, the configuration of a processing apparatus used in the method for manufacturing a display device of the present invention will be described, and then the configuration of a pixel circuit of the display device manufactured here will be described, followed by the manufacture of the display device. The method and the display device formed by this manufacturing method will be described in this order.

<Processing device>
FIG. 1 is a configuration diagram illustrating an example of a processing apparatus used in the following embodiment. The processing apparatus 1 shown in this figure is a film forming processing apparatus, and includes a plurality of processing chambers 2 and 3 that are sealed so that the inside thereof is kept airtight. These processing chambers 2 and 3 communicate with each other via a transfer chamber 4 and are configured to be able to transfer the substrate W between the processing chamber 2 and the processing chamber 3 without releasing the atmosphere to the atmosphere. In addition, the processing chambers 2 and 3 can be formed by reactive thermal CVD. In particular, the processing chamber 2 can be formed by plasma CVD.

  These processing chambers 2 and 3 are provided with decompression means (for example, turbo molecular pump: TMP) and automatic pressure control means (APC), not shown here, so that the inside is maintained at a desired constant pressure. It is configured.

  Further, in each processing chamber 2, 3, a lower electrode 5 that also serves as a substrate holding means and an upper electrode 6 that also serves as a gas diffusing means disposed on the lower electrode 5 are provided. In particular, a high frequency power source (RF) 7 is connected between the lower electrode 5 and the upper electrode 6 in the processing chamber 2. Each lower electrode 5 also serving as a substrate holding means is provided with a heating means 8. The heating means 8 is, for example, a heater that is electrically heated, and can maintain the substrate W held by the lower electrode 5 at 200 ° C. to 600 ° C.

On the other hand, a gas supply means 9 for supplying a plurality of types of gases into the processing chamber 2 is connected to the upper electrode 6 that also serves as a gas diffusion means. A plurality of supply lines (not shown) are connected to the gas supply means 9 according to the type of gas required for film formation. For example, silane (SiH ₄ ), ammonia (NH ₃ ), nitrogen dinitride ( N ₂ O), disilane (Si ₂ H ₆ ), fluorine (F ₂ ), germanium tetrafluoride (GeF ₄ ), phosphine (PH ₃ ), diborane (B ₂ H ₆ ), arsine (AsH ₃ ), nitrogen ( ₂ ), film forming gases (source gas and dilution gas) G such as oxygen (O ₂ ), helium (He), argon (Ar), hydrogen (H ₂ ), etc., are contained in the processing chambers 2 and 3 respectively. It is a configuration to be supplied. Each gas supply means 9 is provided with a mass flow controller (MFC) 9a, and the gas supply amount into the processing chambers 2 and 3 is individually adjusted.

  And the sequence controller 10 which controls these is connected to the high frequency power supply (RF) 7 mentioned above, the power supply (heater power supply) of the heating means 8, and the mass flow controller 9a.

In the processing apparatus 1 having such a configuration, when an insulating film such as a silicon nitride film or a silicon oxide film is formed, for example, SiH ₄ , NH ₃ , N ₂ O, O _2, etc. are formed by the gas supply means 9. A deposition gas G is introduced into the processing chamber 2, and a high frequency is applied between the lower electrode 5 and the upper electrode 6 by a high frequency power source (RF) 7. Thus, these insulating films are formed by plasma CVD on the substrate W held on the lower electrode 5.

Further, when a semiconductor thin film such as a silicon thin film is formed, a gas supply means 9 introduces a film forming gas G such as Si ₂ H ₆ , F ₂ , Ar into the processing chambers 2 and 3, and the lower electrode 5. -A high frequency is not applied between the upper electrodes 6, and the lower electrode 5 is heated to about 450 ° C. Thus, the source gas is excited and decomposed using the chemical reactivity of the source gas itself, and a polycrystalline silicon film is formed on the substrate W heated on the lower electrode 5 and heated by reactive thermal CVD. The Further, when forming an n-type doped silicon thin film, Si ₂ H ₆ , F ₂ , Ar, and PH ₃ are introduced into the processing chambers 2 and ₃ as a film forming gas G. On the other hand, when forming a p-type doped silicon thin film, Si ₂ H ₆ , F ₂ , Ar, and B ₂ H ₆ are introduced into the processing chambers 2 and 3 as a film forming gas G. Thereby, a polycrystalline silicon film containing each dopant is formed by reactive thermal CVD.

Such Si ₂ H ₆ -F ₂ reactive thermal CVD film formation is a film formed by a kind of oxidation-reduction reaction, and Si ₂ H ₆ is oxidized by F ₂ to produce Si. In this reaction system, a film obtained with a crystallinity in a polycrystalline state having a crystal grain size of about 10 to 100 nm without containing hydrogen can be obtained. In addition, dopants such as P and B atoms are self-activated by being taken into the lattice positions of Si at the time of film formation, so that low resistance n-type simultaneously with film formation without requiring activation annealing or the like. Alternatively, a p-type polycrystalline silicon film is obtained.

  These film forming steps are continuously performed in the same processing chambers 2 and 3 by switching the gas type of the film forming gas G supplied from the gas supply means 9. The series of processing procedures is controlled by the sequence controller 10.

<Drive circuit>
FIG. 2 is a configuration diagram showing one configuration of a pixel circuit for one pixel in the display device 11 manufactured here. As shown in this figure, in the display area 12 a of the substrate 12 constituting the display device 11, a write scanning line 14 connected to the vertical driving circuit 13 and a signal line 16 connected to the horizontal driving circuit 15 are matrixed. The pixel circuit 17 including the organic EL element EL as a light emitting element is arranged at each intersection.

  Each of these pixel circuits 17 is an example of a current writing type pixel circuit in which luminance information is written in the form of current. In addition to the organic EL element EL, the capacitor element C, two p-channel TFTs (Tr1) , (Tr2), and two n-channel TFTs (Tr3), (Tr4) are combined in a CMOS circuit. The scanning line 14 and the signal line 16, and further the power supply line 18 and the erasing scanning line 19 It is provided in a connected state.

  Among these, the p-type TFTs (Tr1) and (Tr2) connected to the power supply line 18 constitute a current mirror circuit. The n-type TFT (Tr3) connected to the scanning line 14 and the signal line 16, and the n-type TFT (Tr4) connected to the n-type TFT (Tr3), the erasing scanning line 19 and the current mirror circuit are as follows. , Respectively, are transistors for writing and erasing.

  In the display device 11 having such a current writing type pixel circuit, the image data divided in time series is sequentially transferred to the plurality of pixel circuits 17 by the horizontal drive circuit 15 and the vertical drive circuit 13. In each pixel circuit 17, both the writing scanning line 14 and the erasing scanning line 19 are selected at the time of data writing, and a current proportional to the current of the signal line 16 is composed of p-type TFTs (Tr1) and (Tr2). It flows to the organic EL element EL through the current mirror circuit. By repeating such an operation, one image is displayed in one field. When erasing data, only the erase scanning line 19 is selected. 2 shows an example in which peripheral drive circuits including a horizontal drive circuit 15 and a vertical drive circuit 13 are also integrally formed on the same substrate 12 as the pixel circuit 17. In FIG. However, the peripheral drive circuit is connected to the pixel circuit 17 on the substrate 12 as an external integrated circuit by applying a COG (Chip-on-Glass) method or a TAB (Tape-Automated ≡ Bonding) method. It may be a thing.

<First Embodiment>
3 to 5 are views for explaining a first embodiment for manufacturing the display device having the circuit configuration of FIG. 2 using the processing apparatus of FIG. Here, a manufacturing method of a display device having a bottom gate type laminated TFT will be described using these cross-sectional process diagrams and, if necessary, a plan view corresponding to each cross-sectional process diagram. In addition, each cross-sectional process drawing shall respond | correspond to the AA 'cross section in a top view.

  First, as shown in FIG. 3A, an insulating substrate 12 is made of tantalum (Ta), molybdenum (Mo), tungsten (W), chromium (Cr), copper (Cu), or an alloy thereof. A conductive film to be formed is formed with a film thickness of about 50 to 250 nm, and then the conductive film is patterned to form the gate electrode 32. As shown in the plan view of FIG. 6, these gate electrodes 32 are provided in a connected state as necessary.

  Next, as shown in FIG. 3B, the silicon nitride film 33a is formed to a thickness of 30 to 50 nm and then the silicon oxide film 33b is formed to about 50 by a method such as plasma CVD, atmospheric pressure CVD, or low pressure CVD. A film is continuously formed with a film thickness of ˜200 m, and a gate insulating film 33 made of these laminated films is formed.

Next, from an i-type polycrystalline semiconductor such as polycrystalline silicon not containing impurities, polycrystalline silicon germanium, or a laminated film thereof, for example, by a reactive thermal CVD method using the processing apparatus described with reference to FIG. An active layer 34 is formed. The active layer 34 is formed with a film thickness of about 10 to 200 m, preferably 40 m. Here, for example, when the active layer 34 made of polycrystalline silicon is formed by the reactive thermal CVD method, the substrate temperature is kept at 450 to 600 ° C. Further, disilane (Si ₂ H ₆ ), fluorine (F ₂ ) as a film forming gas, an inert gas such as helium (He), nitrogen ( ₂ ), argon (Ar), krypton (Kr) as a dilution gas, or hydrogen Gas (H ₂ ) is used. For example, the gas flow rate is set to 20 sccm for disilane (Si ₂ H ₆ ), 0.8 sccm for fluorine (F ₂ ), 1000 to 4000 sccm for helium (He), and the gas pressure is maintained at about 600 Pa. As a result, Si ₂ H ₆ and F ₂ undergo a thermochemical reaction, and polycrystalline silicon is deposited at a deposition rate of about 0.2 nm / s. For example, when the active layer 34 made of polycrystalline silicon germanium is formed by a reactive thermal CVD method, germanium tetrafluoride (GeF ₄ ) is used instead of fluorine (F ₂ ). At this time, a polycrystalline silicon germanium thin film having various Si—Ge composition ratios can be obtained depending on the flow ratio of disilane (Si ₂ H ₆ ) and germanium tetrafluoride (GeF ₄ ). However, in order to adjust Vth of the laminated TFT formed here, a small amount of B ₂ H ₆ or the like may be added to the deposition gas.

  Subsequently, a silicon oxide thin film 35 with a thickness of 100 to 200 m is formed on the active layer 34 again using the plasma CVD method. Thereafter, annealing for removing the amorphous component may be performed as necessary.

  Next, as shown in FIG. 3C, a resist pattern 36 is formed on the silicon oxide film 35, and the silicon oxide film 35 is patterned by etching using the resist pattern 36 as a mask. Here, referring to the plan view of FIG. 7, in the n-type TFT region 12n of the first conductivity type (n-type or p-type, for example, n-type here), the entire region of the transistor is covered with the silicon oxide film 35. The silicon oxide film 35 is patterned so as to cover only the gate electrode 32 in the p-type TFT region 12p of the second conductivity type (for example, p-type here). Then, the other portions of the silicon oxide film 35 are removed by etching. Thereby, an etching stopper layer 35a made of the silicon oxide film 35 is formed. Then, after the etching stopper layer 35a is formed, the resist pattern 36 is removed.

  Next, as shown in FIG. 3D, the p-type made of polycrystalline silicon or polycrystalline silicon germanium containing impurities of the second conductivity type (for example, p-type here) in a state of covering the etching stopper layer 35a. The source / drain layer 37 is formed by a reactive thermal CVD method. The p-type source / drain layer 37 may be a single layer film or a laminated film of a polycrystalline silicon film containing impurities and polycrystalline silicon germanium containing impurities, and is a film of 10 to 200 m, preferably 100 m. The film is formed with a thickness.

Here, disilane (Si ₂ H ₆ ) and fluorine (F ₂ ) are used as the deposition gas, diborane (B ₂ H ₆ ) is used as the dopant gas, and helium (He), nitrogen ( ₂ ), and argon (Ar) as the dilution gas. ), An inert gas such as krypton (Kr), or hydrogen gas (H ₂ ). For example, the gas flow rate is set to 20 sccm for disilane (Si ₂ H ₆ ), 0.8 sccm for fluorine (F ₂ ), 1 sccm for diborane (B ₂ H ₆ ), and 1000 to 4000 sccm for helium (He) as a diluent gas, The gas pressure is maintained at about 600 Pa. Thus, Si ₂ H ₆ and F ₂ undergo a thermochemical reaction, and p-type polycrystalline silicon is deposited at a deposition rate of about 0.2 m / s. Since crystallization occurs simultaneously with the deposition of the thin film, the dopant is also activated simultaneously.

On the other hand, when the p-type source / drain layer 37 made of p-type polycrystalline silicon germanium is formed by a reactive thermal CVD method, germanium tetrafluoride (GeF ₄ ) is used instead of fluorine (F ₂ ). . At this time, p-type polycrystalline silicon germanium thin films having various Si—Ge composition ratios are obtained depending on the flow rate ratio of disilane (Si ₂ H ₆ ) and germanium tetrafluoride (GeF ₄ ).

  After the above, as shown in FIG. 4E, a resist pattern 38 is formed on the p-type source / drain layer 37, and the p-type source / drain layer 37 is etched by using the resist pattern 38 as a mask. Is patterned. Here, the p-type source / drain layer 37 is left only in the entire region of the p-type TFT region 12p, and the p-source / drain layer 37 portion in other regions is removed by etching.

  Subsequently, the active layer 34 is patterned by etching using the resist pattern 38 and the etching stopper layer 35a as a mask. Thereby, the active layer 34 is separated into islands in accordance with the n-type TFT region 12n and the p-type TFT region 12p. Then, after this etching, the resist pattern 38 is removed.

  Next, as shown in FIG. 4F, by performing backside exposure using the gate electrode 32 as a mask, a resist pattern 39 is formed on the etching stopper layer 35a in the n-type TFT region 12n, and the p-type is formed. A resist pattern 39 is formed on the p-type source / drain layer 37 in the TFT region 12p.

  Next, the etching stopper layer 35a made of silicon oxide is etched using the resist pattern 39 and the p-type source / drain 37 as a mask, so that the etching stopper layer 35a in the n-type TFT region 12n is formed into the shape of the gate electrode 32. Further patterning is performed. In this step, since the etching stopper layer 35a of the p-type TFT region 12p is covered with the p-type source / drain layer 37, it is not etched. Then, after this etching, the resist pattern 39 is removed.

Thereafter, as shown in FIG. 4G, an n-type source / drain layer 40 made of polycrystalline silicon or polycrystalline silicon germanium containing impurities of the first conductivity type (for example, n-type here) is formed on the substrate 12. Is formed by a reactive thermal CVD method. Like the p-type source / drain layer 37, the n-type source / drain layer 40 is a single layer film or a laminated film of a polycrystalline silicon film containing impurities and polycrystalline silicon germanium containing impurities. The film is formed with a thickness of 10 to 200 m, preferably 100 m. The n-type source / drain layer 40 is formed by the reactive thermal CVD method in the reactive thermal CVD film formation of the p-type source / drain layer 37 described with reference to FIG. As a dopant gas, phosphine (PH ₃ ) is used instead of diborane (B ₂ H ₆ ).

  Next, as shown in FIG. 4H, the n-type source / drain layer 40 and the p-type source / drain layer 37 are patterned to form the n-type TFT region 12n with the n-type source / drain layer 40. An n-type source 40a and an n-type drain 40b are formed, and a p-type source 37a and a p-type drain 37b made of a p-type source / drain layer 37 are formed in the p-type TFT region 12p.

  The n-type source 40a and the n-type drain 40b, the p-type source 37a and the p-type drain 37b are subjected to pattern etching so as to be separated on the etching stopper 35a. This prevents damage to the active layer 34 due to etching.

  In particular, the p-type source 37a and the p-type drain 37b are formed with the n-type source / drain layer 40 laminated thereon. However, in the state where the n-type source / drain layer 40 is stacked on the p-type source 37a and the p-type drain 37b, the impurities in each layer are high in concentration, so that there are many defect levels and the depletion layer is widened. Therefore, it is not a pn junction but an ohmic junction. Therefore, the p-type source 37a and the p-type drain 37b formed in the p-type TFT region 12p function without any problem as a p-type.

  Thus, an n-type stacked TFT (hereinafter referred to as an n-type TFT) 41 is formed in the n-type TFT region 12n, and a p-type stacked TFT (hereinafter referred to as a p-type TFT) 42 is formed in the p-type TFT region 12p. Form.

After the above, as shown in FIG. 5 (i), the silicon oxide film 43 (film thickness: 100 to 400 nm) and hydrogen on the upper part thereof are contained by plasma CVD in a state of covering the n-type TFT 41 and the p-type TFT. A silicon nitride film 44 (having a film thickness of 200 to 400 nm) is continuously formed as an interlayer insulating film. After film formation, hydrogenation annealing is performed at 350 to 400 ° C. for about 1 hour in a nitrogen gas (N ₂ ) atmosphere.

  Further, as shown in FIG. 5 (j), a connection hole is formed in the silicon nitride film 44 and the silicon oxide film 43, and a wiring electrode such as aluminum-silicon is sputtered and then patterned to obtain an n-type. Wiring electrodes 45 connected to the n-type source 40a and n-type drain 40b of the TFT 41 and the p-type source 37a and p-type drain 37b of the p-type TFT 42 are formed. However, the wiring electrode 45 may be connected to the p-type source region 37 a and the p-type drain region 37 b through the n-type source / drain layer 40.

  Next, the planarization insulating film 46 is formed by applying an acrylic organic resin, organic SOG, or the like at about 1 μm. Thereafter, a connection hole 46a reaching the wiring electrode 45 is formed in the planarization insulating film 46, and an electrode material film serving as an anode of Al, Cr, Mo or the like is formed by sputtering in a state of filling the connection hole 46. . Next, the pixel electrode 47 is formed by patterning this electrode material film.

Next, after annealing for 30 minutes in N ₂ at about 220 ° C., a hole transport layer 48, a light emitting layer 49, and an electron transport layer 50 are sequentially laminated thereon, and a transparent conductive cathode and The common electrode 51 is formed. Accordingly, an organic layer in which an organic layer in which a hole transport layer 48, a light emitting layer 49, and an electron transport layer 50 are stacked is sandwiched between an anode composed of the pixel electrode 47 and a cathode composed of the common electrode 51. An EL element 52 (EL) is obtained.

  After the above, although illustration is omitted here, a buffer layer is formed on the substrate 1 so as to cover the organic EL element 52, and a counter glass substrate is formed on the substrate 12 while sandwiching the organic EL element 52. To complete the display device. This display device has a top emission structure in which light emitted from the organic EL element 52 is extracted from the common electrode 51 side (opposite glass substrate side) opposite to the substrate 12.

  The display device is not limited to such a top emission structure, and the bottom emission that takes out the emitted light of the organic EL element 52 from the substrate 1 side by making the pixel electrode 47 of a transparent conductive material. A structure is also possible. Further, the pixel electrode 47 can be used as a cathode and the common electrode 51 can be used as an anode by changing the laminated state of the organic layer composed of the hole transport layer 48, the light emitting layer 49, the electron transport layer 50, and the like.

  In such a manufacturing method, the active layer 34, the p-type source / drain layer 37, and the n-type source / drain layer 40 constituting the n-type TFT 41 and the p-type TFT 42 are formed by a reactive thermal CVD method. As a result, stacked TFTs 41 and 42 in which these layers made of a semiconductor thin film having a crystalline structure are stacked in advance are obtained without particularly performing the step of crystallizing the semiconductor thin film. Accordingly, the source / drain layers 37 and 40 and the active layer 34 of the respective TFTs 41 and 42 are made of a crystalline semiconductor thin film while omitting a crystallization step, thereby forming an amorphous semiconductor thin film. The stacked n-type TFT 41 and p-type TFT 42 having a higher operation speed than the case of using the TFT can be obtained with a smaller number of masks (six pieces), and using these TFTs 41 and 42 is advantageous in reducing power consumption. A simple CMOS circuit is formed.

  As a result, the TFTs 41 and 42 capable of driving with low power consumption of the organic EL element LE whose driving current is increased by using a polycrystalline semiconductor thin film having a high operating speed are formed with a smaller number of processes. In addition, it is possible to obtain TFTs 41 and 42 from which variations caused by crystallization are eliminated. Further, as described above, by omitting the crystallization process and the impurity introduction process, it becomes possible to form TFTs 41 and 42 having uniform characteristics on a larger substrate. An increase in the size of the display device including the TFTs 41 and 42 that can be driven with low power consumption can be realized.

  In addition, the increase in the size of the display device as described above makes it possible to integrate selector switches in peripheral circuits and greatly reduce the number of connection terminals from external circuits, resulting in high reliability, low cost, and low power consumption. Contributes greatly to the realization of large display devices. And it has the big advantage that large displays, such as a large electroluminescent apparatus larger than 40 inches diagonal, can be manufactured with high productivity and low cost. In this embodiment, a display device using an organic EL element has been described as an example. However, the present invention is not limited to a display device using an organic EL element, and an inorganic EL element, a liquid crystal display element, or the like is used. It can be applied to all display devices.

  In particular, in the p-type TFT of the display device 11 thus obtained, an n-type source / drain layer 40 is laminated on the p-type source 37a and the p-type drain 37b. Since the wiring electrode 45 is connected via 40, the connection resistance can be reduced. Further, since the wiring electrode 45 is in contact only with the n-type source / drain layer 40, the conductor-semiconductor contact potential is always equal, so that electrolytic corrosion is unlikely to occur, and there is an effect that the selection range of conductors constituting the electrode is widened. This is the same when the upper layer is p-type.

  As the configuration of the bottom gate type laminated TFT, an n-type source 40a and an n-type drain 40b as shown in FIG. 8, and a wiring electrode 53 having the same pattern as the p-type source 37a and the p-type drain region 37b are provided. Even with such a configuration, the manufacturing method of the present invention can be applied. In this case, after forming the n-type source / drain layer 40 described with reference to FIG. 4G, a wiring electrode forming layer is provided on the n-type source / drain layer 40, and then the n-type source / drain layer 40 is formed. By simultaneously patterning the drain layer 40 and the p-type source / drain layer 37 and the formation layer of the wiring electrode 53, the number of masks can be further reduced as compared with the first embodiment described above.

  In this case, before or after the formation of the wiring electrode formation layer on the n-type source / drain layer 40, the active layer 34, p is formed by a method such as hydrogen plasma, hydrogen annealing, oxygen plasma, or water vapor annealing. The defect level in the layer made of polycrystalline silicon such as the type source / drain layer 37 and the n type source / drain layer 40 may be reduced.

Second Embodiment
9 to 10 are views for explaining a method for manufacturing the display device of the second embodiment. Here, a method for manufacturing a display device having a top-gate stacked TFT will be described using these cross-sectional process diagrams and, if necessary, a plan view corresponding to each cross-sectional process diagram.

  First, as shown in FIG. 9A, a silicon nitride (SiNx) film 61 and a silicon oxide (SiOx) film 62 are formed as buffer layers on the insulating substrate 12 in this order in thicknesses of about 50 nm to 400 nm. Form a film.

  After the above, from the polycrystalline silicon or polycrystalline silicon germanium containing the first conductivity type (n-type or p-type, for example, n-type here) impurity on the silicon oxide film 62 by the reactive thermal CVD method. An n-type source / drain layer 63 is formed. The reactive thermal CVD film formation of the n-type source / drain layer 63 is performed in the same manner as the film formation of the n-type source / drain layer (40) described with reference to FIG. 4G in the first embodiment.

  Next, the n-type source / drain layer 63 is etched using a resist pattern (not shown) as a mask, thereby forming an n-type source 63a and an n-type drain 63b in the n-type TFT region 12n. . After this etching is completed, the resist pattern is removed.

  Next, as shown in FIG. 9B, the n-type TFT region 12n is covered with a mask 64 such as a resist pattern. Then, an n-type source / drain layer 65 made of polycrystalline silicon or polycrystalline silicon germanium containing a second conductivity type (here, p-type) impurity is formed on the substrate 12 so as to cover the mask 64. To do. The reactive thermal CVD film formation of the p-type source / drain layer 65 is performed in the same manner as the film formation of the p-type source / drain layer (37) described with reference to FIG. 3D in the first embodiment.

  Next, the p-type source / drain layer 65 is etched using a resist pattern (not shown) as a mask, so that the p-type TFT region 12p has a p-type source 65a, a p-type drain 65b, Form. After this etching is completed, the resist pattern and the mask 64 are removed.

  Next, as shown in FIG. 9 (c), polycrystalline silicon containing no impurities in a state of covering the n-type source 63a and the n-type drain 63b, the p-type source 65a and the p-type drain 65b on the substrate 12, or An active layer 66 made of polycrystalline silicon germanium is formed. The active layer 25 is formed with a thickness of about 20 to 100 nm, preferably 40 nm, by a reactive thermal CVD method. This film formation is performed in the same manner as the film formation of the active layer (34) described with reference to FIG. 3B in the first embodiment. Further, in order to prevent cross contamination due to the dopant, it is formed in a processing chamber different from the formation of the polycrystalline n-type source / drain layer (63) and p-type source / drain layer (65) containing the impurities described above. A film treatment is performed.

  Thereafter, the active layer 66 is patterned by etching the active layer 66 using a mask so that both ends are overlapped on the ends of the n-type source 63a and the n-type drain 63b and the p-type source 65a and the p-type drain 65b. .

Next, as shown in FIG. 9D, the substrate 12 is moved to a processing chamber where plasma CVD film formation is possible, and a gate insulating film 67 made of silicon oxide (SiO _x ) is formed to a film thickness of 10 to 200 nm, preferably 100 nm. The film is formed with a thickness.

  Next, as shown in FIG. 10E, a gate electrode 68 is formed on the patterned active layer 66 through a gate insulating film 67. At this time, first, a conductive film made of tantalum (Ta), molybdenum (Mo), tungsten (W), chromium (Cr), copper (Cu), or an alloy thereof is formed to a thickness of about 50 to 250 nm. Then, the conductive film is patterned to form the gate electrode 68.

  In particular, both ends of the gate electrode 68 are overlapped on end portions of the n-type source 63a and the n-type drain 63b, the p-type source 65a and the p-type drain 65b via the gate insulating film 67 and the patterned active layer 66. It is preferable to be patterned into a different shape.

  Thus, an n-type stacked TFT (hereinafter referred to as an n-type TFT) 70 is formed in the n-type TFT region 12n, and a p-type stacked TFT (hereinafter referred to as a p-type TFT) 71 is formed in the p-type TFT region 12p. Form.

  Next, the process shown in FIG. 10F is performed in the same manner as described with reference to FIG. 5I in the first embodiment, and the silicon oxide film 43 and the n-type TFT 70 and the p-type TFT 71 are covered. A silicon nitride film 44 is continuously formed as an interlayer insulating film, and then hydrogenation annealing is performed.

  Next, the process shown in FIG. 10G is performed in the same manner as described with reference to FIG. 5J in the first embodiment, and the n-type source 63a and the n-type drain 63b, the p-type source 65a and the p-type drain are performed. A wiring electrode 45 connected to 65b, a planarization insulating film 46, and an organic EL element 52 (EL) connected to the wiring electrode 45 are formed, and a counter glass substrate is further bonded to complete the display device 11 ′.

  Even in such a manufacturing method, the active layer 66, the n-type source / drain layer 63, and the p-type source / drain layer 65 that constitute the n-type TFT 70 and the p-type TFT 71, as in the first embodiment described above. Is formed by a reactive thermal CVD method. Therefore, as in the first embodiment, TFTs 70 and 71 capable of driving with low power consumption of the organic EL element LE in which the driving current is increased by using a polycrystalline semiconductor thin film having a high operation speed, It is possible to obtain TFTs 70 and 71 that can be formed with a smaller number of steps and in which variations caused by crystallization are eliminated. Further, as described above, by omitting the crystallization step and the impurity introduction step, it becomes possible to form TFTs 70 and 71 having uniform characteristics on a larger substrate. An increase in the size of a display device including TFTs 70 and 71 that can be driven with low power consumption can be realized.

  In the first and second embodiments described above, the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type is p-type and the second conductivity type is It may be n-type. In the case of con, in the above description, n-type is read as p-type, and p-type is read as n-type.

It is a block diagram of the film-forming apparatus used for the manufacturing method of embodiment. It is a pixel circuit block diagram of the display apparatus demonstrated by embodiment. It is sectional process drawing (the 1) explaining a manufacturing method to 1st Embodiment. It is sectional process drawing (the 2) explaining the manufacturing method of 1st Embodiment. It is sectional process drawing (the 3) explaining the manufacturing method of 1st Embodiment. FIG. 4 is a plan view corresponding to FIG. FIG. 4 is a plan view corresponding to FIG. It is a figure explaining other structures of bottom gate type lamination TFT of a 1st embodiment. It is sectional process drawing (the 1) explaining a manufacturing method to 2nd Embodiment. It is sectional process drawing (the 2) explaining the manufacturing method of 2nd Embodiment. It is a figure explaining manufacture of the conventional bottom gate type laminated TFT.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11, 11 '... Display apparatus, 12 ... Board | substrate, 12n ... n-type TFT area | region, 12p ... p-type TFT area | region, 32, 68 ... Gate electrode, 33, 67 ... Gate insulating film, 34, 66 ... Active layer, 35a ... Etching stopper layer, 37, 65 ... p-type source / drain layer, 38 ... resist pattern, 40,63 ... n-type source / drain layer, 40a, 63a ... n-type source, 40b, 63b ... n-type drain, 37a, 65a ... p-type source, 37b, 65b ... p-type drain, 41, 54, 70 ... n-type TFT (first conductivity type thin film transistor), 42, 55, 71 ... p-type TFT (second conductivity type thin film transistor)

Claims (4)

A method of manufacturing a display device comprising a pixel driving circuit comprising a first conductive type thin film transistor and a second conductive type thin film transistor on a substrate,
Forming a gate electrode on the substrate and covering the gate electrode with a gate insulating film;
A second step of forming an active layer made of a polycrystalline semiconductor thin film on the gate insulating film by a reactive thermal CVD method using reaction energies of a plurality of different gases;
An insulating etching stopper layer having a shape covering the gate electrode in the first region part for forming the first conductivity type thin film transistor and the second region for forming the second conductivity type thin film transistor is formed on the active layer. A third step of forming
By the reactive thermal CVD method, a second conductivity type source / drain layer made of a polycrystalline semiconductor thin film containing a second conductivity type impurity is formed on the active layer so as to cover the etching stopper layer. A fourth step;
The second conductivity type source / drain layer is patterned into a shape covering the second region by etching using the resist pattern covering the second region as a mask, and further using the resist pattern and the etching stopper layer as a mask. A fifth step of patterning the active layer into a shape covering the first region and the second region by etching,
A sixth step of patterning the etching stopper layer in the first region into a shape covering the gate electrode;
Covering the etching stopper layer and the second conductivity type source / drain layer by the reactive thermal CVD method, covering the first conductivity type source / drain layer made of a polycrystalline semiconductor thin film containing the first conductivity type impurity. A seventh step of forming a film in a state;
By patterning the second conductivity type source / drain layer and the first conductivity type source / drain layer, a first conductivity type source / drain composed of the first conductivity type source / drain layer is formed in the first region. And an eighth step of forming a second conductivity type source / drain formed by laminating the first conductivity type source / drain layer on the second conductivity type source / drain layer in the second region. A display device manufacturing method. A method of manufacturing a display device comprising a pixel driving circuit comprising a first conductive type thin film transistor and a second conductive type thin film transistor on a substrate,
A source / drain layer made of a polycrystalline semiconductor thin film containing a first conductivity type impurity is formed on the substrate by a reactive thermal CVD method using reaction energies of a plurality of different gases and patterned. A first step of forming a first conductivity type source / drain in a first region for forming the first conductivity type thin film transistor;
With the first conductivity type source / drain covered with a mask, a source / drain layer made of a polycrystalline semiconductor thin film containing a second conductivity type impurity is formed on the substrate by the reactive thermal CVD method. Forming a second conductivity type source / drain in a second region for forming the second conductivity type thin film transistor by forming a film and patterning the film; and
A third step of forming an active layer made of a polycrystalline semiconductor thin film by the reactive thermal CVD method so as to cover the first conductivity type source / drain and the second conductivity type source / drain;
A fourth step of forming a gate insulating film on the active layer;
And a fifth step of forming a gate electrode on the gate insulating film between the first conductivity type source / drain and between the second conductivity type source / drain. A display device in which a pixel driving circuit including a first conductivity type thin film transistor and a second conductivity type thin film transistor is provided on a substrate,
Each thin film transistor has a stacked type in which a gate electrode, a gate insulating film, an active layer made of a semiconductor thin film, and a source / drain are stacked in this order or in reverse order on the substrate, The display device, wherein the active layer and the source / drain are formed of a polycrystalline semiconductor thin film formed by a reactive thermal CVD method using reaction energies of a plurality of different gases. The display device according to claim 3, wherein
Each thin film transistor includes a stacked type in which a gate electrode, a gate insulating film, an active layer made of a semiconductor thin film, and a source / drain are stacked in this order on the substrate,
The display device, wherein the source / drain of the second conductivity type thin film transistor is formed by stacking a source / drain of the first conductivity type on a source / drain layer of the second conductivity type.

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