JP2005094025A - Semiconductor device and transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly integrated memory capable of being manufactured at a low cost, having high-performance logics and memories in a mixed state, and capable of being operated in a further advanced state of miniaturization or a semiconductor device using the memory. <P>SOLUTION: The semiconductor device is configured so that charges injected or discharged via a write transistor can be read out by means of changes in a threshold voltage of the write transistor. The channel of the write transistor is formed of a semiconductor thin film on an insulation layer, and thereby reduction in leak current is enabled. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a field effect transistor, a semiconductor device, and more particularly to a semiconductor memory element and a manufacturing method thereof.

  With the spread of multimedia, the demands on data processing devices are becoming increasingly sophisticated. In particular, since voice and image processing needs to process a large amount of data in a short time, it is essential to improve the processing capability of the entire data processing apparatus. However, if the data processing device is configured with the logic chip and the memory chip as the main components of the data processing device separately, the data path between them may become a bottleneck and improve the overall processing capability. Have difficulty.

  In order to solve such a problem, a so-called DRAM embedded chip in which a logic circuit and a DRAM (dynamic random access memory) are integrated on one chip has been developed. As a document of such a technique, for example, H.C. Ishiuchi et al. , IEEE Internal Electron Devices Meeting, pp 33-36, 1997 (Non-patent Document 1). From the standpoint of the ease of mixed mounting, it can be said that an SRAM (static random access memory) capable of forming a memory cell with only a logic transistor is superior to a DRAM. However, since one cell is configured using six transistors, the cell area is large, and it is difficult to prepare a large capacity in terms of cost.

  In addition, a memory element structure called a gain cell has been proposed as a structure that can operate even when the accumulated charge of a DRAM cell is reduced. In this method, charge is injected into the storage node via the write transistor, and storage is performed by utilizing the threshold voltage of another read transistor provided by the accumulated charge. Further, as a technology related to the present invention, for example, H.264 using polycrystalline silicon for a writing transistor. Shichijo et al, Conference on Solid State Devices and Materials, pp 265-268, 1984 (Non-patent Document 2), and S. using polycrystalline silicon as a transistor for reading. Shukuri et al. , IEEE International Electric Devices Meeting, pp. 1006-1008, 1992 (Non-Patent Document 3).

  As another technique related to the present invention, K.K. Yano et al, IEEE International Electron Devices Meeting, pp 541-544, 1993 (Non-patent Document 4), and T.A. A single-electron memory using polycrystalline silicon described in Ishii et al, IEEE International Solid-State Circuits Conferences, pp 266-267, 1996 (Non-patent Document 5) can be given. This technique is a memory element that performs storage with one element. Although it differs from the present invention in terms of the operation principle and function of the device, it includes a general structure that can be considered as a TFT structure in which the channel portion is thinner than the source and drain. That is, the bottom surface of the source / drain region and the height of the channel thin film region are substantially aligned.

H. Ishiuchi et al. , IEEE Internal Electron Devices Meeting, pp 33-36, 1997 H. Shichijo et al, Conference on Solid State Devices and Materials, pp 265-268, 1984 S. Shukuri et al. , IEEE International Electric Devices Meeting, pp. 1006-1008, 1992 K. Yano et al, IEEE International Electron Devices Meeting, pp 541-544, 1993. T. T. et al. Ishii et al, IEEE International Solid-State Circuit Conferences, pp 266-267, 1996.

  Lowering the power consumption of devices is recognized as an important issue centering on battery-driven applications such as portable information terminals. Normally, the power consumption of a semiconductor device occupies a considerable portion of the power consumption of the entire device, and a reduction in power consumption is required. The current when the transistor is off is called a leakage current, which is related to all circuits, and causes an increase in power consumption of the entire chip regardless of logic and memory. Therefore, a transistor with low leakage current is required. The inventors have found that a leakage current of 10 minus 18 power can be realized with a polycrystalline silicon base TFT structure in which a channel portion is formed thin by original trial manufacture and evaluation. However, the TFT structure in which the channel portion is thinner than the source and drain is usually a structure in which the bottom surface of the source / drain region and the height of the channel thin film region are substantially aligned as in the prior art. In this structure, the gate insulating film is deposited by CVD. However, since a step is generated between the source and drain portions and the channel portion, electric field concentration tends to occur at the upper end of the step. For this reason, when the gate insulating film is thinned, the withstand voltage margin decreases. Further, since the film is thicker at the lower end of the step, there is a portion where the gate insulating film is substantially thickened. For this reason, there is a fear that the transistor performance is deteriorated and the short channel effect becomes remarkable.

  Accordingly, an object of the present invention is to provide a high-performance semiconductor element with low leakage. A further object is to provide a semiconductor device with low power consumption.

  As described above, a mixed technology of logic and DRAM has been developed and products already exist, but the problem is the compatibility of the logic process and the DRAM process. First, if there are few parts that can be shared in the manufacturing process, the number of masks and the number of processes increase, and the manufacturing cost increases. However, the capacitor fabrication process, which is the most complicated for DRAM fabrication, cannot be shared with the logic section. In addition, in order to emphasize high speed in the MOS transistor of the logic part, a technique of silicidizing the diffusion layer portion to reduce the resistance is commonly used. However, if the pass transistor of the DRAM memory cell is silicidized, the leakage current increases and the memory is increased. It is known that the retention time becomes extremely short. Therefore, in forming the MOS transistor, it is necessary to devise such as covering the DRAM portion when siliciding the logic portion, and the process is complicated.

Second, there is a problem of a high temperature process in the capacitor manufacturing process of DRAM. Since it is necessary to secure a signal amount in a DRAM, the amount of stored charge cannot be reduced while miniaturization proceeds. Therefore, it is necessary to introduce a high dielectric film in order to secure a capacity in a smaller area. The use of a three-dimensional structure as conventionally performed is difficult due to an increase in cost, and even if a three-dimensional structure is used, introduction of a high dielectric film is becoming indispensable. However, high temperature is required to form a high dielectric film. For example, when Ta ₂ O ₅ (tantalum pentoxide) is used, a high temperature treatment of about 750 ° C. is required for crystallization.

  On the other hand, the MOS transistor in the logic portion has a very shallow PN junction in the diffusion layer for miniaturization. The impurities in the diffusion layer are diffused by the heat treatment, and the characteristics of the MOS transistor are deteriorated. In some cases, the operation becomes impossible due to punch-through. Further, silicide materials such as cobalt silicide may be agglomerated at a high temperature. If a so-called trench capacitor structure is used in which a capacitor is formed by digging a groove in the substrate, the capacitor can be formed before the formation of the logic MOS transistor. And there is a problem that the aspect ratio must be further increased.

  The above-described problem of securing the amount of stored charge is not limited to a logic-embedded chip but is a problem related to DRAM in general. After 1 GbitRAM using a processing dimension of 0.18 μm to 0.14 μm, there is a fear that a new high dielectric material must be developed for each generation. Therefore, there is a need for a semiconductor memory with a small area that can operate stably even if the amount of stored charge is reduced and that can be integrated as high as a DRAM.

  As described above, an object of the present invention is to provide a semiconductor device in which high-performance logic and memory are mixedly mounted at low cost.

  The present invention can provide a highly integrated memory that can operate even when semiconductor devices are further miniaturized.

  The present invention is characterized in that charges injected and discharged through a writing transistor are read out by a threshold voltage change of the reading transistor. Since a new material for securing the capacitor capacity as in the case of DRAM is not required, it is easy to mix logic. The transistor of the present invention is very useful for such a semiconductor device.

  Specifically, the configuration of the semiconductor element according to the representative embodiment of the present invention basically has the following form.

  A typical first embodiment of the present invention has a source region, a drain region, a channel region made of a semiconductor material that connects the source region and the drain region, and a gate electrode that controls the potential of the channel region. The channel region is provided on an insulating film, and the channel region is arranged at the level of the upper surface of the source region and the drain region with respect to the substrate surface of the semiconductor device. The conductance of the channel is controlled by controlling the potential by the gate electrode.

  Here, a thin film semiconductor layer is used for the channel region according to the present invention. It is particularly preferable that the thickness is 5 nm or less. Since the channel region is an extremely thin film, an extremely low leakage current is secured. This configuration will be fully understood with reference to FIG.

  The second embodiment of the present application has the following configuration.

That is, this second form has a source region and a drain region made of a metal or semiconductor material,
The source region and the drain region are connected by a channel region made of a semiconductor material on an insulating film,
A first transistor structure (M2) having a gate electrode made of a metal or semiconductor material for controlling the potential of the channel region;
Having a source region and a drain region made of a metal or semiconductor material;
The source region and the drain region are connected by a channel region made of a semiconductor material,
A gate electrode made of a metal or semiconductor material for controlling the potential of the channel region;
A second transistor structure (M1) having a charge storage region made of a metal or semiconductor material coupled to the channel region by capacitance;
A source region of the second transistor structure is connected to a source line;
One end of the source region or drain region of the first transistor structure is connected to the charge storage region of the second transistor structure;
The other end of the source region or drain region of the first transistor structure is connected to a data line.

  In the present invention, the charge storage region (1) of the readout transistor and the control electrode (5) are stacked, and can be configured with a smaller area than a three-transistor gain cell. Further, since the channel of the writing transistor is made of a semiconductor thin film on the insulating film (134), a MOS using a normal bulk substrate is used as the writing transistor in order to completely deplete the channel (3) corresponding to the charge leakage path. Leakage current can be greatly reduced compared to the case of using it.

  Furthermore, the self-alignment processing with the word line (5) can be used for the memory region (1) processing or the channel (3) processing of the write transistor, which makes it possible to achieve both a simple manufacturing process and a small area cell. . In addition, in order to make an understanding easy, the reference code | symbol in the text has shown each site | part in FIG. 1 as a reference example.

  Other means, objects and features of the present invention will become apparent from the following embodiments.

  According to the present invention, it is possible to provide a low-cost, high-performance logic / memory mixed semiconductor device. In addition, the present invention can provide a highly integrated memory device that can operate even when miniaturization further progresses, or a semiconductor device using this memory device.

  Prior to describing specific embodiments, main aspects of the present invention are listed below.

The first form of the present application has a source region and a drain region made of a metal or semiconductor material,
The source region and the drain region are connected by a channel region made of a semiconductor material on an insulating film,
A first transistor having a gate electrode made of a metal or semiconductor material for controlling the potential of the channel region;
Having a source region and a drain region made of a metal or semiconductor material;
The source region and the drain region are connected by a channel region made of a semiconductor material,
A gate electrode made of a metal or semiconductor material for controlling the potential of the channel region;
The channel region and a second transistor having a charge storage region made of metal or semiconductor through a capacitance;
A source region of the second transistor is connected to a source line;
One end of either the source region or the drain region of the first transistor is connected to the charge storage region of the second transistor,
The other end of either the source region or the drain region of the first transistor is a semiconductor memory element connected to a data line. Various semiconductor devices can be provided by using the structure of the semiconductor memory element.

A second aspect of the present application is the semiconductor memory element or semiconductor device semiconductor memory element of the first aspect,
The distance between the source region or drain region of the first transistor structure connected to the data line and the source region of the second transistor structure is the source region or the source region of the first transistor structure connected to the data line. A semiconductor memory element or a semiconductor device characterized in that the distance is shorter than the distance between the drain region and the drain region of the second transistor structure.

  According to a third aspect of the present application, in the first or second semiconductor memory element, the width of the gate electrode of the second transistor structure is substantially equal to the width of the channel region of the first transistor structure. A semiconductor memory element or a semiconductor device. This mode is characterized by self-alignment processing using a read transistor electrode of a semiconductor memory element.

A fourth aspect of the present application is the semiconductor memory element according to any one of the first to third aspects,
The semiconductor memory element or the semiconductor device is characterized in that the width of the gate electrode of the second transistor structure is substantially equal to the width of the charge storage region of the second transistor structure.

The fifth embodiment of the present application has a field-effect type writing transistor and a reading transistor,
The channel of the write transistor is made of a semiconductor material,
The source region and drain region of the write transistor are made of a metal or semiconductor material and metal laminated structure,
One end (region A) of either the source or drain region of the write transistor has no conductive path other than the channel of the write transistor, and is coupled with the channel of the read transistor by the capacitance,
The other end (region B) of either the source or drain region of the write transistor is connected to the outside,
In a semiconductor memory element that stores information by changing a threshold voltage of a read transistor depending on the amount of charge accumulated in the region A of the write transistor,
The channel of the write transistor is a semiconductor memory element or a semiconductor device having this semiconductor memory element structure, characterized in that the channel of the write transistor is connected to the metal portion of the source and drain regions of the write transistor.

The sixth embodiment of the present application has a transistor composed of a gate insulating film having a thickness of at least two levels,
A peripheral circuit comprising a transistor having a gate insulating film that is not at least the thinnest insulating film of the gate insulating film;
Having a memory element composed of a field-effect write transistor and a read transistor on the same chip;
In the semiconductor device having the operation principle of reading out the amount of charge taken in and out through the write transistor by changing the threshold voltage of the read transistor,
The semiconductor device or the semiconductor device having the semiconductor memory element structure is characterized in that a gate insulating film thickness of a transistor constituting the peripheral circuit is equal to a gate insulating film thickness of a reading transistor of the memory element.

  A seventh aspect of the present invention is the semiconductor memory element or the semiconductor device according to any one of the first to sixth aspects, wherein the channel of the write transistor is provided on an insulating film.

  According to an eighth aspect of the present application, in the semiconductor memory element or semiconductor device according to the seventh aspect, the channel of the write transistor is provided at the same height as the upper end of the source or drain region of the write transistor. The semiconductor memory element or the semiconductor device is characterized.

  According to a ninth aspect of the present application, in the semiconductor memory element or the semiconductor device according to any one of the first to seventh aspects, a gate electrode of the write transistor and a gate electrode of the read transistor are common. A semiconductor memory element or a semiconductor device.

  According to a tenth aspect of the present application, in the semiconductor memory element or the semiconductor device according to any one of the first to eighth aspects, the channel thickness of the write transistor is 5 nm or less. Alternatively, it is a semiconductor device.

An eleventh aspect of the present application is a memory cell array in which the semiconductor memory elements according to any one of the first to tenth aspects are arranged in a matrix or the semiconductor according to any one of the first to tenth aspects. In the memory cell array in the device,
The layout of the element isolation region of the memory cell array has a rectangular shape substantially parallel to each other,
The layout of the word line connecting the gate electrode of the write transistor or read transistor of the semiconductor memory element is substantially in the shape of a rectangle arranged in parallel with each other,
A plurality of read transistors of the semiconductor memory element are connected to each other through a diffusion layer;
The layout of the diffusion layer connecting the plurality of read transistors has a rectangular shape substantially parallel to each other,
The rectangular element isolation regions arranged in parallel with each other and the rectangular diffusion layers arranged in parallel with each other are substantially parallel and arranged in parallel with the rectangular element isolation regions arranged in parallel with each other. The memory cell array is characterized in that the word lines are substantially perpendicular to each other.

An eleventh aspect of the present application is a memory cell array in which the semiconductor memory elements according to any one of the first to tenth aspects are arranged in a matrix, or the semiconductor device according to any one of the first to tenth aspects. In the memory cell array in
The layout of the element isolation region of the memory cell array has a rectangular shape substantially parallel to each other,
The layout of the word line connecting the gate electrode of the write transistor or read transistor of the semiconductor memory element is substantially in the shape of a rectangle arranged in parallel with each other,
A plurality of write transistors of the semiconductor memory element are connected to each other through a wiring of the same material as the gate electrode;
The rectangular element isolation regions arranged in parallel to each other and the word lines arranged in parallel to each other are substantially perpendicular to each other.
The wirings connecting the plurality of write transistors are parallel to each other and the rectangular element isolation regions arranged in parallel to each other,
Furthermore, the memory cell array is characterized in that wirings for connecting the plurality of write transistors are on the rectangular element isolation regions arranged in parallel to each other.

A twelfth aspect of the present application is a memory cell array in which the semiconductor memory elements according to any one of the first to tenth aspects are arranged in a matrix or the semiconductor device according to any one of the first to tenth aspects. In the memory cell array in
The layout of the element isolation region of the memory cell array has a rectangular shape substantially parallel to each other,
The layout of the word line connecting the gate electrode of the write transistor or read transistor of the semiconductor memory element is substantially in the shape of a rectangle arranged in parallel with each other,
Each read transistor of the semiconductor memory element has a structure sharing a diffusion layer of a drain region only with one adjacent cell,
The source lines of the plurality of read transistors are connected to each other by three or more cells by diffusion layer wiring or metal wiring,
The rectangular element isolation regions arranged in parallel with each other and the rectangular diffusion layers arranged in parallel with each other are substantially parallel and arranged in parallel with the rectangular element isolation regions arranged in parallel with each other. The memory cell array is characterized in that the word lines are substantially perpendicular to each other.

  A fourteenth aspect of the present application is a memory cell array in which the semiconductor memory elements according to any one of the first to thirteenth aspects are arranged in a matrix, or the semiconductor device according to any one of the first to thirteenth aspects. In this memory cell array, a semiconductor memory element or a semiconductor device is characterized in that information of 2 bits or more is stored in one cell.

  According to a fifteenth aspect of the present application, there is provided a memory cell array in which the semiconductor memory elements according to any one of the first to the fourteenth aspects are arranged in a matrix or the semiconductor device according to any one of the first to the fourteenth aspects. In a memory cell array, a semiconductor memory element or a semiconductor device is characterized in that a register capable of storing 2 bits or more is connected to a unit read data line.

  A sixteenth aspect of the present application is a memory cell array in which the semiconductor memory elements according to any one of the first to fifteenth aspects are arranged in a matrix, or the semiconductor device according to any one of the first to fifteenth aspects. In this memory cell array, a register capable of storing 2 bits or more is connected to the unit write data line.

  A seventeenth aspect of the present invention is a memory cell array in which the semiconductor memory elements according to any one of the first to sixteenth aspects are arranged in a matrix, or the semiconductor device according to any one of the first to sixteenth aspects. A first read operation step, and a second read step performed by driving the same word line and read data line as the first read operation step, and the first read operation The word line voltage of the second read operation is changed in accordance with the read result of...

  An eighteenth aspect of the present application is a memory cell array in which the semiconductor memory elements according to any one of the first to seventeenth aspects are arranged in a matrix, or the semiconductor device according to any one of the first to seventeenth aspects. In the memory cell array, the first read operation step includes a first read operation step, and a second read step performed by driving the same word line and read data line as the first read operation step. A method for controlling a semiconductor device, comprising means for setting a potential of a write data line in accordance with a combination of a read result in step 2 and a read result in a second read step.

  Next, embodiments of the present invention will be specifically described.

Example 1
In this example, a semiconductor memory device according to the present invention is formed on a semiconductor substrate. FIG. 1 shows a structure of an element and an equivalent circuit according to this embodiment. 1A is a cross-sectional view, FIG. 1B is a top view, and FIG. 1C is an equivalent circuit diagram. For ease of viewing, in FIG. 1 (b), the overlapping part of the outline of a certain region is described while being partially shifted. In addition, the element portions in FIGS. 1A to 1C are drawn so as to correspond to the left and right, respectively. The top view shows the arrangement relationship of the main parts of the semiconductor device, and is not a top view showing exactly the state of each stack. Hereinafter, explanation will be given while showing the correspondence with the equivalent circuit diagram.

  The structure of this example basically includes a transistor for writing information (commonly referred to as a writing transistor) (M2) and a transistor for reading written information (commonly referred to as a reading transistor) (M1). It is the structure made into. That is, this example is a so-called gain cell configuration using a thin film FET.

  The writing transistor (M2) has a thin film silicon channel FET (Field Effect Transistor) structure. The channel (3) of this FET has a low impurity concentration and is substantially intrinsic. Both ends (1) and (2) are laminated layers of polycrystalline silicon and W (tungsten) into which n-type impurities are introduced. Connected to the structure. One end (1) has no electric conduction path other than the channel (3), and serves as a charge storage section. This end portion (1) corresponds to an equivalent circuit diagram and a portion (1c) in FIG. On the other hand, the other end (2) is connected to a data line (34) for writing. The part of the other end (2) corresponds to the part (2c) of the equivalent circuit diagram. The laminated body of the polysilicon layer and the tungsten (W) layer itself is commonly used in the semiconductor field. In order to apply this laminate to the present invention, it is preferable to laminate the tungsten layer as if it is in contact with the channel. In this case, the effect of reducing the resistance by the tungsten layer is useful.

The portion (2) connected to the write data line is above the element isolation region (10). Here, an example of the film thickness of the channel (3) is 6 nm. On the channel (3), a gate electrode (5) having a laminated structure of p-type polycrystalline silicon and W is provided with a gate insulating film (4) made of SiO ₂ and having a thickness of 7 nm interposed therebetween. The insulating layer (4) is, SiO ₂ and thereafter the SiO ₂ formed on the upper is integrated which is initially formed. The dotted lines in the figure illustrate these two layers. In the following similar drawings, for the sake of simplicity, only an integrated insulating layer is shown.

  In the top view of FIG. 1B, the regions (1) and (2) corresponding to the source or drain and the region of the channel (3) are clearly shown.

  The read transistor (M1) is provided with a source (7) and a drain (6) of n-type impurities in a self-aligning manner using the charge storage portion (1) as a gate of a normal MOS transistor. ing. The source (7) of the read transistor (M1) is grounded via a source line (this grounded portion corresponds to (7c) in the equivalent circuit diagram). Although it is possible to operate the part (7) as a drain, it is preferable to use the part (7) as a source as described above because the storage is stable.

The drain (6) of the read transistor (M1) is connected to the read data line (33). The portion connected to the data line (33) corresponds to (6c) in the equivalent circuit diagram. The insulating film (9) between the charge storage portion (4) and the silicon substrate (8) is a SiO ₂ film having a thickness of 6 nm and a nitrided surface. The gate electrode (5) of the read transistor (M1) is common to the gate electrode of the write transistor (M2). This gate electrode corresponds to (5c) in the equivalent circuit diagram. Here, an n-channel transistor is used as the read transistor (M1), but a p-channel transistor may be used. In this case, the threshold voltage shift during charge accumulation, the sign of the applied voltage, and the magnitude relationship change, but it is essentially the same as in the case of the n channel. For simplification of description, in this embodiment and the following embodiments, the read transistor is an n-channel transistor, but a p-channel transistor may be used.

  Next, the operation of this embodiment will be described. (1) The gate electrode of the writing transistor (M2) is p-type, (2) the channel thickness of the writing transistor is thin, and (3) adjusting the channel impurity of the reading transistor (M1). Considering this, the threshold voltage of the writing transistor (M2) is set higher than the threshold voltage of the reading transistor (M1). The threshold voltage of the read transistor (M1) changes depending on the amount of charge accumulated in the charge accumulation region. Therefore, more specifically, the threshold voltage of the writing transistor is set higher than the second highest threshold voltage among the storage states to be used. In the case of simple 1-bit storage per cell, this means that the threshold voltage is higher than the low threshold voltage state in the storage state.

  When the voltage VWW is applied to the gate electrodes (5, 5c), the write transistor (M2) becomes conductive, and a current can flow through the channel (3) of the write transistor. At this time, different charge amounts are stored in the charge storage section (4) according to the potential of the write data line set in advance.

  In this embodiment, the write data line (34) and the read data line (33) are not shared but driven independently. When the write gate electrode (5, 5c) voltage VW is applied, the read transistor (M1) is in a conductive state. Therefore, when the data line is shared for write and read, a current flows through the read transistor. However, in this embodiment, this current can be reduced by opening the read data line or setting it to the same potential as the source end. Accordingly, power consumption of the transistor can be suppressed.

  When the data line is shared, the read transistor (M1) is turned on, so that the set potential of the write data line becomes the drain end (6, 6c) potential of the read transistor (M1). For this reason, the channel potential of the read transistor approaches this. As a result, when different voltages corresponding to the write data are set for the write data line, the case where the data line is driven independently and the write data line potential is substantially fixed to the source end potential is the same as that of the charge storage portion (4). Since the potential difference between the read transistor channels becomes large, the amount of accumulated charge due to write information can be greatly changed. As a result, the signal amount change at the same time of reading increases, and more stable information storage is possible.

  For setting the potential of the write data line, the use of two values corresponding to information “0” and “1” has the largest margin, but it is possible to store 2 bits by setting the voltage of four data lines, for example, more than that. The cost per storage capacity can be reduced.

  In this embodiment, the word line is common to the writing transistor and the reading transistor, but this may be provided separately. Compared to the common case, the area increases as the number of wirings increases, but the word line potential of the write transistor can be fixed during the read operation. Therefore, more stable operation is possible, and there is a feature that rewriting is not necessary immediately after reading. At the same time, the write operation can be performed while the read transistor is kept off, so that power consumption can be reduced.

  In reading, a positive voltage is applied to the gate electrode (5). The voltage VWR of this pulse is smaller than VWW, and almost no current flows through the channel (3) of the writing transistor. The information is held for a sufficiently long time with respect to the width.

  On the other hand, the threshold voltage of the read transistor changes according to the amount of stored charge, and the conductance when the read voltage is applied differs. This is sensed and information is read out. Compared with a DRAM that senses the change in potential by flowing the stored charge directly to the data line, the amount of stored charge becomes a threshold voltage change and is taken out of the memory cell in a form amplified by the read transistor. For this reason, in the present invention, the amount of accumulated charge can be reduced. Here, the source (7) of the read transistor is used below the write transistor and the potential is fixed, and the other end is used as the drain (6) for read precharge, thereby suppressing the potential change of the channel (3) of the write transistor. Stable retention of accumulated charge is realized.

  Thereafter, in order to compensate for a change in the amount of accumulated charge due to a slight current flowing through the writing transistor during the reading operation, writing is performed again according to the reading information. In the holding operation, the voltage of the gate electrode (5) is set to a voltage VW0 that is smaller than the read voltage VWR. Although the writing transistor is turned off, the leakage current between the source (1) and the drain (2) at this time is smaller than that of a normal MOS transistor because the channel (3) is thin and completely depleted. Furthermore, when a bulk silicon substrate is used, the leakage current of the PN junction flows through the substrate. However, in this structure, since there is no leakage path corresponding to this substrate, the leakage current is still small.

Next, the manufacturing process of the semiconductor device of this example will be described. 2 to 6 show a process and a layout in which the element structure of the present embodiment is arranged in a matrix. 2, 5, and 6, the left is a cross-sectional view and the right is a top view. In the left and right figures, the AA ′ cross section in the right figure corresponds to the left figure. In addition, the said top view shows only arrangement | positioning of the main site | part in the said process in order to avoid complexity, and does not correspond to an exact top view. Each cross-sectional view exemplifies a structure above the semiconductor layer forming the active region of the semiconductor device. This semiconductor layer is disposed on a semiconductor substrate or an SOI substrate, but this substrate portion is omitted for simplification of the drawings. Further, in FIG. 3B, FIG. 4, FIG. 5, and FIG. 6 relating to the following steps, the impurity region in the substrate is omitted. This region can be fully understood basically with reference to FIG.

  First, impurity ion implantation and annealing are performed on a p-type silicon substrate to produce a usual triple well structure of n well and p well. Also, a typical element isolation groove (12) embedded with an insulator is formed using the mask pattern (11) shown in the top view of FIG. 2 (b). That is, an element isolation groove (12) is formed in a region between the mask patterns (11). When a large number of elements are formed, a large number of the mask patterns (11) are arranged.

After the sacrificial oxidation of the substrate surface, an impurity for threshold voltage adjustment is implanted using a resist as a mask. After cleaning, the silicon surface is oxidized to form a peripheral circuit gate insulating film having a thickness of 5 nm. Next, the SiO ₂ film is etched using the resist pattern in which the transistor portion for the logic circuit is opened as a mask region.

Then, after removing the resist film, the silicon surface is oxidized to a thickness of 3 nm to form a gate insulating film for a logic circuit. After the surface of the gate insulating film is nitrided to increase the dielectric constant of the gate insulating film, polycrystalline silicon for a gate electrode is deposited, and impurities are implanted into the polycrystalline silicon using a resist as a mask. Further, a W film and a SiO ₂ film are deposited, and a gate electrode (14) is formed using the resist pattern (13) as a mask, as shown in FIG. At this time, in the repetitive pattern in the memory cell, it is possible to use a super-resolution technique such as phase shift exposure by making the distance between the gate electrodes substantially equal.

Here, a shallow diffusion layer (16) is formed by implanting low-energy impurities using the resist pattern and the gate electrode as a mask. FIG. 3A shows a shallow diffusion layer (16) in the semiconductor substrate (8). Thereafter, SiO ₂ or Si ₃ N ₄ is deposited, and sidewalls (15) are formed on the side surfaces of the gate electrode (14) by anisotropic dry etching. Again, using the gate electrode region with the resist pattern and the sidewall as a mask region, an impurity is implanted to form a diffusion layer (17). This state is shown in FIG.

  Before and after the impurity implantation, an impurity implantation having a polarity different from that of the diffusion layer may be obliquely performed to increase the well concentration at the end of the gate electrode (14) to suppress the short channel effect. Here, a silicidation process is performed to reduce the diffusion layer resistance. For example, titanium silicide or cobalt silicide is formed.

Subsequently, a SiO ₂ film (300) is deposited, and CMP (chemical mechanical polishing) is performed to planarize the upper end of the gate electrode (14) so as to be exposed ((b) of FIG. 3). ). In FIG. 3B, only the SiO ₂ film 300 left after the CMP is shown. FIG. 3C shows a planar pattern of the main part at this time.

After cleaning the semiconductor substrate thus prepared, an amorphous silicon film (18) having a thickness of 8 nm and a SiO ₂ film (19) having a thickness of 5 nm are deposited on the semiconductor substrate. Using the resist pattern (20) region shown in FIG. 4 (a) as a mask, the SiO ₂ film (19) and the amorphous silicon film (18) are dry etched (FIG. 4 (b)). The plane of the resist pattern (20) is formed using the mask pattern (23) shown in FIG.

Thereafter, a SiO ₂ film (25) is deposited, and further a p-type polycrystalline silicon, W, and SiO ₂ film (27) is deposited. A word line (26) is formed by dry etching using the resist pattern (23) as a mask ((b) of FIG. 5). The stacked body of the p-type polycrystalline silicon and W forms the word line (26). The reason why p-type polycrystalline silicon is used is to make the threshold value of the writing transistor positive. This word line (26) serves as both the gate electrode of the read transistor and the gate electrode of the write transistor. The SiO ₂ film (27) on the word line is made sufficiently thicker than the gate insulating film (25) of the write transistor.

Further, a resist having a hole pattern (28) as shown in FIG. 6B is subjected to dry etching of the SiO2 film in the mask region. At this time, the SiO ₂ film (27) on the word line remains even when the etching of the SiO ₂ film in the portion (29) not overlapping the word line (26) proceeds and the gate electrode (14) is exposed. Thereafter, the gate electrode (14) is etched, but it is possible to obtain a sufficient selection ratio between the SiO ₂ film (27) on the word line and the gate electrode (14). A cross-sectional view of a portion not overlapping the word line (26) is shown in FIG. As a result, only the portions (29) and (32) of the gate electrode (14) that do not overlap with the word line are not etched, and there is no charge storage region (where there is no charge outflow path other than the channel (21) of the write transistor). 30) is formed. Since the adjacent gate electrode (31) is not cut like this, it is conductive in the vertical direction of the drawing. This becomes the data line of the writing transistor. Due to such self-alignment processing, the width of the channel (21) and the charge storage region (30) of the writing transistor is substantially equal to the width of the word line (26). Thereafter, a desired wiring process is performed.

  Since the method of this example uses a lot of self-aligned processing as described above, the word lines can be arranged at the minimum pitch. That is, if the characteristic size of the technology to be used is expressed by F, it becomes 2F pitch. This size F means the size when the line width is F and the space width is F, that is, the line and space is 2F.

Further, since the data lines are paired for forming the write data line and the charge storage portion, the data lines have a pitch of about 4F. In this case, when the alignment margin of the write data line with respect to the element isolation region is increased or the width of the read data line is increased to reduce the resistance, the resistance is further increased. Eventually, the area of the unit memory cell is about 8F ² to 12F ² , and can be configured with a small area despite the structure in which transistors are arranged in a plane.

  FIG. 7 shows an equivalent circuit diagram of a memory cell array based on this memory element. Table 1 shows the set voltage during each operation. In this example, four memory cell portions arranged in a matrix are illustrated. The three were designated as MC1, MC2, and MC3. They shared columns that shared write data lines (DW1, DW2), read data lines (DR1, DR2), and source lines (SL1, SL2), and shared word lines (WL1, WL2). A row forms a matrix.

前記素子に即して、アレイでの電圧設定表を表１に示す。書込み動作においては、セルＭＣ１とセルＭＣ２のように、同一ワード線で駆動されるセルを同時に書込む。まず、データ・セット・ステップでは、ワード線（ＷＬ１）の電圧は書込みトランジスタが非導通の状態であるように設定したまま（例えば、ＶＷ０＝−１Ｖ）で、書込みデータ線（ＤＲ１）電圧を書込み情報「１」または「０」に応じて、ＶＤ１、ＶＤ０のいずれかに設定する。ここで読出しトランジスタをｎ型とし、ＶＤ１＜ＶＤ０とする。例えばＶＤ１＝０Ｖ、ＶＤ０＝２Ｖとする。この後、ワード線（ＷＬ１）に書込み電圧ＶＷＷ（例えば３Ｖ）の高さの書込みパルスを加え書込みトランジスタを導通させる。この時書込みトランジスタを、非飽和領域動作させることで、電荷蓄積領域が書込みデータ線（ＤＲ１）電圧とほぼ同電位になるまで電流が流れる。書込みパルス印加後に、電荷蓄積領域に蓄積される電荷はデータ線設定が高い（ＶＤ０）方が符号を含めた意味で大きく、従って、読出しトランジスタのしきい電圧は低くなる。この結果、読出し動作において読出しデータ線をプリチャージ電圧ＶＰＣ（例えば１Ｖ）に設定した後、ワード線に書込み電圧ＶＷＲを印加した際には、読出しトランジスタを流れる電流がより大きくなり、読出しデータ線のプリチャージ電位から急速に読出しトランジスタソース側電位（０Ｖ）に近づく。

Table 1 shows a voltage setting table in the array in accordance with the elements. In the write operation, cells driven by the same word line, such as cell MC1 and cell MC2, are simultaneously written. First, in the data set step, the write data line (DR1) voltage is written while the voltage of the word line (WL1) is set so that the write transistor is non-conductive (for example, VW0 = -1V). It is set to either VD1 or VD0 according to the information “1” or “0”. Here, the reading transistor is n-type, and VD1 <VD0. For example, VD1 = 0V and VD0 = 2V. Thereafter, a write pulse having a write voltage VWW (for example, 3V) is applied to the word line (WL1) to make the write transistor conductive. At this time, by operating the write transistor in the non-saturation region, a current flows until the charge accumulation region becomes substantially the same potential as the write data line (DR1) voltage. After application of the write pulse, the charge accumulated in the charge accumulation region is larger in the sense that the data line setting is higher (VD0) including the sign, and therefore the threshold voltage of the read transistor is lowered. As a result, when the write voltage VWR is applied to the word line after setting the read data line to the precharge voltage VPC (for example, 1 V) in the read operation, the current flowing through the read transistor becomes larger and the read data line The read transistor source side potential (0 V) is rapidly approached from the precharge potential.

  On the other hand, in the high threshold voltage state, the current flowing through the read transistor is small and remains almost at the precharge potential, and information on the selected cell can be read by detecting this difference using a sense amplifier. . When the positive precharge voltage VPC is used, the potential of the read data line becomes lower when the write data line potential is set higher (in this case, VD0). Therefore, in the rewriting of the read information, it is necessary to invert the voltage level of the read result and load it to the write data line. Therefore, a data path connected from the read data line to the read data line via the inverter is prepared. The word line voltage VW1 of the non-selected cell at the time of writing may be the same as the voltage VW0 at the time of holding, but if the adjacent word line of the selected cell is set to a lower voltage (VW1 <VW0), capacitive coupling It is possible to prevent charge loss due to an increase in the potential of the unselected word line due to.

Example 2
FIG. 8 shows a second embodiment of the present invention. FIG. 8A shows a cross-sectional structure of the device according to this example, and FIG. 8B shows a top view.

  The configuration is basically the same as that of the first embodiment, except that an SOI (silicon on insulator) substrate is used. Accordingly, the gate electrode structure of the read transistor, the formation method, and the channel thickness of the write transistor are different. This structure is characterized in that the number of steps common to the logic process is increased, and the number of additional steps for forming the memory is small. In addition, the leakage current of the write transistor is smaller than that of the first embodiment, and the memory retention characteristics are excellent.

  In FIG. 8, reference numeral 400 denotes a semiconductor substrate, and 48 denotes an insulating film. Thus, an SOI substrate is provided. An active region of the semiconductor device is formed above this. Reference numerals 41 and 42 are element isolation regions, 43 is a semiconductor region, 44 and 45 are deep diffusion layers, 47 is a shallow diffusion layer region, 40 is an insulating film (also serves as a gate insulating film of one FET), 35 and 36 And 38 are drain and source regions, 37 is a channel region, 300 is an insulating film, 39 is an insulating film, and 46 is a conductor layer. Here, the source and drain regions are preferably a stacked body of a metal layer and a polysilicon layer, for example, a stacked body of a tungsten layer and a polysilicon layer. Further, the metal layer is preferably disposed on the side in contact with the channel layer. In the drawing, details of this lamination are omitted. The same can be said for this laminate in other examples.

  The manufacturing process will be described focusing on differences from the first embodiment. 9 to 12 show a series of manufacturing steps. In these drawings, where the reference numerals of the respective parts are omitted, the geometrical shapes of these figures are considered to be the same part.

  Like a conventional SOI substrate, a predetermined semiconductor layer is formed on the buried insulating film (48) of the SOI substrate. In the following drawings, the structure above the semiconductor layer will be described. Accordingly, the region of the insulating substrate is generally omitted from the drawing. FIG. 8 shows the relationship between the SOI substrate and the parts mounted on the SOI substrate.

Element isolation regions (41) and (42) are formed in the silicon layer (43) provided on the buried insulating film (48) of the SOI substrate (400). Thereafter, a gate insulating film (50) is formed, and a dummy gate electrode-shaped member (49) made of a Si ₃ N ₄ material is further formed. Using this dummy gate member (49) as a mask, an extension region (47) forming implant is performed, and then, after forming the side wall (51), a diffusion layer forming implant is performed, whereby the source (45), drain ( 44). This state is shown in the cross-sectional view of FIG. The side wall is formed in the same manner as in Example 1. FIG. 8B corresponds to FIG.

  After depositing the insulating film (310) on the semiconductor substrate thus prepared, CMP is performed so that the upper surface of the dummy gate (49) is exposed (FIG. 9B).

  FIG. 10A shows the same state as FIG. 9B. In the drawing, a memory cell and a peripheral circuit portion are shown on the left, and a cross-sectional view of the logic portion is shown on the right. Regarding the manufacture of the semiconductor device of this embodiment, the impurity regions in the substrate are omitted in FIGS. 10, 11, and 12 related to the following steps. This region can be fully understood basically with reference to FIG.

  When the logic circuit portion and the memory circuit portion are mounted on the same substrate as in this example, gate insulation is required in the logic portion that pursues high speed, the memory cell that achieves low leakage, and the peripheral circuit portion that requires a certain withstand voltage. The film thickness is different. 10, 11, and 12, for the same semiconductor device, cross-sectional views of the memory cell and the peripheral circuit portion on the left and the logic portion on the right are shown. 13, 14, and 15 are top views, and for the same semiconductor device, memory cells and peripheral circuit portions are shown on the left, and logic portions are shown on the right. Further, for explaining how to make contact with the diffusion layer, a top view of four cells arranged vertically in FIGS. 16 to 18 and an equivalent circuit diagram corresponding thereto are shown in FIG.

  The dummy gate member (49) once formed is removed (FIG. 10 (b)), and a resist (55) is formed in the logic portion. Using this photoresist as a mask region, the dummy gate insulating film (50) in the memory cell readout transistor and peripheral circuit transistor portions is removed (FIG. 10C). At this time, the substrate (53) appears in the groove of the portion (53) which becomes the storage node of the memory cell and the gate (53) of the peripheral MOS, but the portion (54) where the write data line is formed later has an element isolation region. appear.

After the peripheral circuit gate insulating film 57 is formed again, a resist is formed in the peripheral circuit area. Using the formed resist (56) as a mask region, the dummy gate insulating film of the logic transistor portion (58) is then removed ((a) of FIG. 11).

  A gate insulating film (59) for a logic transistor is formed again (FIG. 11B), and then a metal gate material (60), for example, W is deposited on the semiconductor substrate thus prepared (FIG. 11). (C)). Further, the metal gate electrode is formed in the groove portion where the dummy gate member was formed by cutting the metal by CMP ((a) of FIG. 12). At this time, the write data line (70) of the memory cell, the logic and the gate electrode (72) of the peripheral circuit transistor are formed simultaneously. FIG. 13A shows the pattern of the upper surface at this time. For example, the data line (70) and the plane pattern of the gate electrode are shown on the left side. The cross section CC of FIG. 13A corresponds to FIG. 12A, and the DD ′ cross section of FIG. 13B corresponds to FIG.

  FIG. 16 shows a region (74) for providing a contact hole for the diffusion layer wiring (73) in the source region of the read transistor, and a region for providing a contact hole for the diffusion layer wiring (71) in the drain region of the read transistor. It is a top view which shows (72). In addition, a write data line (76) using the gate electrode layer and a line (75) parallel to the write data line (77) in the adjacent column are processed later to become a charge storage region.

Thereafter, an ultra-thin amorphous silicon (a-Si) film having a thickness of about 3 nm is deposited and a SiO ₂ film having a thickness of 10 nm is further deposited for channel formation of the writing transistor. Then, as shown in FIG. 12B, the SiO ₂ film (62) and the a-Si film (61) are etched using the resist pattern as a mask (65). FIG. 13B illustrates a plan view of the resist pattern (65) at this time.

  At this time, the logic part and the peripheral circuit part have a mask pattern without resist, and the thin film is removed by etching. In the present embodiment, the leak current can be suppressed to a low level by the same effect as in the first embodiment, the potential in the film is increased due to the quantum mechanical confinement energy in the film thickness direction, and the leak current is further reduced. . Further, in a region where the film is thin, there is a large potential change even with a slight change in the film thickness, and therefore the potential distribution in the film is not uniform and changes randomly. For this reason, even if there are multiple low potential portions in the film in the non-conducting state, it will be divided in the high potential region, and the grain boundary of the polycrystalline film also acts as a potential barrier, so that leakage is also reduced. is there.

  After this, the gate insulating film of the write transistor is formed, and further, with the resist as a mask, the logic layer and the diffusion layer of the peripheral transistor, the contact hole to the gate and the diffusion layer of the read transistor of the memory cell, the write data line, the read data line, A contact hole (66) to the source line is provided. An example of the arrangement of the contact hole (66), the element isolation regions (41, 42), and the region (72) in which the contact hole is provided is shown in FIG.

  After removing the resist, a metal material (64) is deposited on the entire surface including the inside of the contact hole, and an insulating film (64a) is formed thereon. Using the resist pattern as a mask, the insulating film (64a) and the metal (64) are processed, and simultaneously with the formation of the word line (67a) in the memory cell array, the logic part and peripheral circuit wiring (67b) are formed. The source line wiring of the memory cell array is also performed in this layer ((c) in FIG. 12). The planar arrangement of each pattern at this time is shown in FIG.

  Then, etching is performed using the photoresist for the hole pattern (68) shown in FIG. 15A and the word line (67a) of the memory cell as a mask region, and the channel ( 161). In FIG. 15B, the word line (67a) is shown by a broken line because the pattern overlaps with the word line (67a), the lower channel, and the charge accumulation region by self-alignment processing. At this time, the logic portion and the peripheral circuit portion are not etched because they are covered with a resist.

  FIG. 17 is a plan view of the first wiring layer of the semiconductor device. FIG. 17 shows a contact (83) for the source region diffusion layer wiring (73) of the reading transistor and a contact (81) for the drain region diffusion layer wiring (71) of the reading transistor at this time. . The positions of the contact (80) to the write data line (76) and the contact (81) to the write data line (77) in the adjacent column are shifted in the write data line direction. Therefore, the pitch in the column direction is made small. It is possible. A source line (78) is provided in parallel with the word line to connect different columns.

  Further, the portion (79) separated for forming the charge storage region has a sufficiently high impurity concentration in this portion (79), whereby the source region diffusion layer wiring (73) of the read transistor and the drain region diffusion of the read transistor are formed. Leakage between the layer wirings (71) is made sufficiently small. If necessary, impurity ion implantation may be performed at this stage to increase the threshold voltage of the separation portion (79).

  Thereafter, an insulating film is deposited and planarized. This insulating film becomes an insulating film of the first wiring layer and the second wiring layer of the semiconductor device. Next, as shown in FIG. 18, through holes (84) and (85) are formed using a resist as a mask. Then, a conductor material, for example, a metal material is deposited on the entire surface including the inside of these through holes, and a second layer wiring is performed by processing the resist into a mask. The conductor material in the through hole connects the first and second wiring layers. A write data line (86) and a read data line (87) are formed using this second layer wiring. The read data line uses a diffusion layer wiring (71) in a semiconductor substrate and generally has a high resistance because the line width and thickness are small. Therefore, the resistance can be reduced by backing with metal wiring as in this embodiment. FIG. 18 is a plan view of the second wiring layer of the semiconductor device. A cross-sectional view of the memory cell at this time is shown in FIG. In the second layer wiring, the write data (150) and the read data line (151) run in parallel. In the right part of FIG. 27, the logic part is a cross-sectional view of a portion overlapping the second-layer wiring, so the wiring cross section (153) is shown, but it goes without saying that it differs depending on the wiring pattern. In the present embodiment, the same wiring (86) is performed for the write data line (76), but this is not performed, and only the wiring of the gate electrode layer is used, and the data line pitch of the second-layer wiring is reduced. Alternatively, a cell array configuration with a smaller area is possible (FIG. 18). Referring to FIG. 28, since the write data line (151) is eliminated, the width of the read data line can be increased and the pitch between the lines can be increased.

  An equivalent circuit diagram at this stage is shown in FIG. A portion (88) surrounded by a solid line corresponds to FIGS. Each part of A, B, and C in FIG. 18 corresponds to the part of each symbol in FIG. Thereafter, the third and subsequent layers are wired by repeating the insulating film deposition, planarization, through-hole formation, metal material deposition, and processing.

  Another embodiment related to this example is shown in FIGS. 20 is a layout diagram, 21 is an equivalent circuit diagram, and each drawing corresponds to FIGS. 17 and 19 of the embodiment. The difference from the above embodiment is that a selection transistor (96) for the write data line (101) and a selection transistor (92) for the read data line (102) are provided. As a result, the data lines are hierarchized, and a smaller unit can be selectively driven instead of driving the entire array. For this reason, the capacity is reduced, which is effective in speeding up and reducing power consumption. The write data line (local write data line) (101) is connected to the global data line via the contact hole (97) via the selection transistor. The read data line (local read data line) (102) is also connected to the global data line via the select transistor and the contact hole (91). Here, the global data line corresponds to the data line wiring (86) (87) of the second layer in the embodiment. Further, wirings (95) and (100) for driving the local data line selection transistor are newly provided in parallel with the word lines.

Example 3
In the first embodiment and the second embodiment, the drain regions of the plurality of read transistors are connected by the diffusion layer. On the other hand, in this embodiment, a contact (113) is provided for each memory cell as illustrated below. This example is provided and connected to the upper layer read data line (109). This contact hole is shared by two cells. Although the cell area is smaller when the diffusion layer wiring is used, in this embodiment, since the parasitic resistance is small, the source line (114) that is quickly accessed is connected by the diffusion layer and wired in the direction parallel to the word line (106). .

  22 to 24 are views for explaining a third embodiment of the present invention. 22 is a sectional view, FIG. 23 is a layout diagram of a memory array, and FIG. 24 is an equivalent circuit diagram. The LL cross section in FIG. 23 is (a) in FIG. 22, and the MM ′ cross section is in (b) in FIG. FIG. 23 corresponds to a portion (115) surrounded by a solid line in FIG.

  The read transistor has a source (112) and a drain (111), and the drain region (111) is connected to an upper read data line (109) through a contact region (113). As described above, the contact region (113) is connected to the impurity regions of the two transistors in common. This state will be fully understood with reference to the equivalent circuit diagram shown in FIG. A charge storage region (105) of the writing transistor is provided through the insulating film (107), and a word line (106) is provided through the insulating film.

  The cross section shown to (a) of FIG. 22 is outlined. An element isolation region (108) provided on the semiconductor substrate is disposed. Above this, an FET transistor using a thin polycrystalline silicon film as a channel is provided. Semiconductor impurity regions (104, 105) are arranged on the thin polycrystalline silicon film (103). A word line region (106) is formed on this via an insulating film. Referring to the plan view of FIG. 23, the region (103) is a channel region of the transistor. Reference numeral (109) denotes the upper layer read data line (109) described with reference to FIG. The upper read data line (109) is connected to the lower semiconductor impurity region through the contact region (113).

  The operation principle of the element is the same as in the first and second embodiments. That is, according to the information to be written, the set voltage of the write data line (104) is changed, and the voltage is applied to the word line (106) to store the stored charge amount in the charge storage region (105). This is read as a threshold voltage change of the read transistor composed of the word line (106), the source (112), and the drain (111).

Example 4
In this example, the driving method is different. The element structure and the cell array configuration are the same as those in the second embodiment. Table 2 shows a voltage relationship applied to the write data line, the read data line, the source line, and the word line related to writing and reading.

本実施例では１セルに２ビットの記憶を行う。書込み動作時の書込みデータ線データセットの電圧設定を４通りとする。情報（０、１）（１、１）（０、０）（１、０）に対応して書込みデータ線電圧を各々ＶＤ１、ＶＤ２、ＶＤ３、ＶＤ４（但し、ＶＤ１＞ＶＤ２＞ＶＤ３＞ＶＤ４）に設定して書込みを行うと、読出しトランジスタは図２５のように書込みデータ線設定電圧と逆の大小関係のしきい電圧となる。図２５はワード線電圧と読み出しトランジスタのドレイン電流との関係を示す図である。尚、ＶＤＲはデータ線電圧、ＶＰＣはプリチャージ電圧、ＶＷＷは書き込み電圧、ＶＷＯは保持時の電圧、ＶＷ１は非選択セルのワード線電圧、ＶＷＲ１は第１の読み出し電圧、ＶＷＲ２は第２の読み出し電圧、ＶＷＲ３は第３の読み出し電圧を示す。

In this embodiment, 2 bits are stored in one cell. There are four voltage settings for the write data line data set during the write operation. Corresponding to the information (0, 1) (1, 1) (0, 0) (1, 0), the write data line voltages are set to VD1, VD2, VD3, VD4 (where VD1>VD2>VD3> VD4). When writing is performed with setting, the read transistor has a threshold voltage having a magnitude relationship opposite to the write data line setting voltage as shown in FIG. FIG. 25 is a diagram showing the relationship between the word line voltage and the drain current of the read transistor. VDR is a data line voltage, VPC is a precharge voltage, VWW is a write voltage, VWO is a holding voltage, VW1 is a word line voltage of an unselected cell, VWR1 is a first read voltage, and VWR2 is a second read. A voltage, VWR3, indicates a third read voltage.

  Although it is the same as that of a flash memory in that a threshold voltage change due to charge accumulation is read, a verify operation at the time of writing information is not required unlike the 2-bit / cell storage of the flash memory. This is because charge is injected through the write transistor, so that the amount of accumulated charge is determined with high accuracy according to the set voltage and capacitance, and write variation is small compared to the flash memory. For this reason, it is possible to store more bits in one cell using more write data line voltage settings.

  A read operation will be described. First, a read operation is performed in the same procedure as in the case of storing 1 bit. At this time, the read word line voltage VWR1 is set between the threshold voltages (1, 1) and (0, 0). As a result, it can be determined whether it is (0, 1) or (1, 1) or (0, 0) or (1, 0). This result is stored in a register, and the word voltages in the second read operation are set to VWR2 and VWR3, respectively, according to this result. By this second reading, it can be determined whether it is (0, 1) or (0, 0), (1, 1) or (1, 0). An output read result is output by performing a logical operation on this result and the result of the first read.

  Next, the configuration of the memory portion in this embodiment will be described together with the operation. FIG. 26 is a block diagram showing the memory portion and its peripheral circuit portion in this example.

  First, the reading operation from the memory will be described. In response to the requested address signal (116), the input / output interface generates a row address (117), a column address (118), and an upper / lower bit selection signal (135). The memory cell corresponding to the given row address (117) and column address (118) stores 2-bit information, which is stored in the register 1 and register 2 by the above-described reading procedure. Thereafter, selection is made by the up / down switching circuit (133) in accordance with the upper / lower bit selection signal (135), and data output (126) is performed. Next, the store operation to the memory will be described. The input / output interface generates a row address (117), a column address (118), and an upper / lower bit selection signal (135) according to the applied address signal (116). First, the row selected by the row decoder (132) is read. The result is stored in register 1 and register 2. Subsequently, the input data (124) is held in the register connected to the data line (129) selected by the column decoder (122). At this time, whether the register 1 or the register 2 is used is selected. The up / down switching circuit (133) is determined by the signal (135). At this time, the information is not retained in the register where the information is not written. Thereafter, the write data line (130) voltage is set based on the information stored in the register 1 (119) and the register 2 (120), and writing is performed by giving a write pulse to the word line (128). As a result, it is possible to rewrite only one bit out of the two bits stored in one cell (131).

  In addition, the above-described method allows reading and writing operations in bit units. However, if the memory is managed as a set of 2 bits and writing and reading of the upper bits and lower bits are performed simultaneously, the operation speed can be increased. This includes a management method in which input / output to / from the memory is set to 2 bits and the same address is allocated, and a management method in which processing is performed inside the memory. In the former case, data transfer between the data input / output interface (127) and the I / O control circuit (121) is also performed as a set of 2 bits, and the upper and lower bits are respectively registered in register 1 (119) and register 2 (120). It is easy because it is only stored in. In the latter case, in the write operation, the up / down switching circuit (133) distributes the 2-bit data of consecutive addresses to the register 1 and the register 2 of the same data line. Conversely, in the reading operation, the reading results held in the register 1 (119) and the register 2 (120) are continuously sent out as output data (126) by the up / down switching circuit (133). Of course, the function of the up / down switching circuit (133) may be assigned to the input / output interface (127). If such a method is used, it is not necessary to perform a read operation once as in the case of writing in units of 1 bit, and the write operation is speeded up. Further, since both the two bits read at the same time can be used for reading, the data output throughput is improved. The device for speeding up is effective because there are few 1-bit inputs / outputs in practice and most inputs / outputs are in units of several bits or several bytes. The hardware configuration is almost the same as that shown in FIG. 27, except that the upper / lower bit selection signal (135) is unnecessary.

Example 5
This example shows an example of a transistor using a thin semiconductor film such as a polycrystalline silicon film. The configuration is basically the same as that of the writing transistor shown in the above embodiments. This example is characterized in that the source, drain (200, 201), and channel layer are provided. FIG. 28A is a sectional structural view of an element according to this example, and FIG. 28B is a top view of the main part.

The element is formed on the insulating film (206). That is, for example, the upper part of the SIO substrate. The source region and the drain region are made of n-type polycrystalline silicon having a thickness of 60 nm, and the channel (202) is an intrinsic polycrystalline silicon thin film having a thickness of 5 nm. The gate electrode has a laminated structure of p-type polycrystalline silicon and W (tungsten). The gate insulating film (204) is an SiO ₂ film having a thickness of 8 nm. The polycrystalline silicon thin film is preferably an intrinsic crystal. In terms of the impurity concentration of the polycrystalline silicon thin film, 1 × 10 ¹⁷ cm ⁻³ or less, more preferably 1 × 10 ¹⁵ cm ⁻³ or less is often used.

  A gate electrode portion (203) is disposed on the gate insulating film (204). In the plan view of FIG. 28B, the portion constituting the channel in the channel layer (202) in the cross-sectional view of FIG.

  In this example, an insulating film (205) is provided under the thin film channel (202), and the upper surface of the source (200) and drain (201) portions and the channel portion (202) are substantially equal in height. . Therefore, the gate insulating film is formed on a substantially flat base in the portion under the gate. Therefore, compared with the case where there is a step, electric field concentration does not occur and the withstand voltage is good, so that the film can be made thinner. Further, when there is a step, the film thickness is increased at the end, but this structure can achieve a uniform film thickness and is excellent for the short channel effect. Further, since gate processing does not have to be performed on the steps, it is not necessary to perform over-etching, and a margin can be provided in the process, thereby improving the yield. Here, it is not necessary to use a silicon substrate as the substrate, and for example, a glass substrate may be used. The source and drain regions may be a p-type semiconductor, or may be a metal or a stacked structure of a semiconductor and a metal. In particular, since a metal or a stacked structure of a semiconductor and a metal has low resistance, wiring can be performed using this material. Since this element can block channel current by completely depleting the channel thin film portion, switching operation is possible even without a pn junction. A semiconductor other than Si, such as Ge or SiGe, may be used as the channel material, and the degree of freedom in design increases in terms of threshold voltage setting or mobility. The thickness of the thin semiconductor film according to the present invention is preferably 5 nm or less.

  The dependency of the drain current on the gate voltage of this element is the same as that of a normal n-type MOS transistor, but has a feature that the leakage current is very small. This is an experimental fact found by the inventors through original prototyping and evaluation, but there is no leakage path to the substrate because there is no substrate portion, and the channel is completely depleted because the film thickness is thin. In addition, it can be considered that the grain boundary that can be a leak path is one-dimensional. Since this semiconductor element can be formed on an insulating film with low leakage, it can be manufactured with low power consumption and low cost. A logic circuit may be formed using this semiconductor element, or an SRAM may be configured. Further, it may be used only for a portion of the logic circuit where low leakage is desired, or may be used for a resistance portion of the SRAM. Furthermore, a DRAM pass transistor can realize a memory with a long refresh cycle and low power consumption. Other memory applications will be described in other embodiments.

Next, the main part of the manufacturing process of the semiconductor device of this embodiment will be briefly described. On the insulating film, n-type polycrystalline silicon for forming a source and a drain is deposited. Etching is performed using the resist as a mask to form source and drain regions in desired shapes. As described in detail in another embodiment, the gate electrode of the transistor using the substrate surface and the source region and drain region of this element may be formed simultaneously. Thereafter, an insulating film is deposited. Then, the insulating film is removed using CMP (chemical mechanical polishing) so that the upper surfaces of the source and drain are exposed. A typical non-doped amorphous silicon film having a thickness of 5 nm to be a channel thin film is deposited, and a SiO ₂ film having a thickness of 5 nm is further deposited. Using the resist as a mask, the non-doped amorphous silicon film in the unnecessary portion is etched. Further, the basic structure of the device is formed by depositing a gate electrode material and etching using a resist as a mask.

Example 6
29 to 31 are diagrams for explaining the layout of the memory cell array according to the present embodiment together with the manufacturing process. A portion surrounded by a dotted line is an array unit structure including two cells, and the same structure is repeated in the X direction and the Y direction to realize a large-scale array. This embodiment is characterized by a channel processing method, and is effective in reducing the gate insulating film thickness and increasing the reliability. Below, a structure is demonstrated according to the manufacturing process of a present Example. A p-type silicon substrate is used as the substrate. First, a deep n-type well is formed by increasing the energy of ion implantation after sacrificial oxidation or extending the annealing time. A trench is dug in the element isolation region (207) and an insulating film is buried, followed by planarization. After sacrificial oxidation again, ion implantation and annealing are performed to form a p-type well. As a result, the p-type well is electrically separated from the p-type substrate by the n-type well. Therefore, different potentials can be applied between the p-type wells. Next, the substrate surface is oxidized to form a gate insulating film for the read transistor, and n-type polycrystalline silicon is deposited. This layer forms the source and drain of the writing transistor. Next, the polycrystalline silicon in the opening is removed using the resist of the hole pattern (208) as a mask (FIG. 29A). This groove width defines the channel length of the writing transistor.

  After an insulating film is deposited and planarized, an amorphous silicon thin film that becomes a channel is deposited. An insulating film to be a gate insulating film of the writing transistor is deposited thereon, p-type polycrystalline silicon is deposited as a gate electrode material of the writing transistor, and impurity activation annealing is performed. Using the resist pattern (210) for forming the gate electrode of the writing transistor as a mask, the gate electrode material of the writing transistor, the gate insulating film of the writing transistor, the channel thin film, and the n-type polycrystalline silicon film are etched (FIG. 29B). )). As a result, the channel of the write transistor is formed in the overlapping portion (211) of the opening portion of the previous hole pattern (208) and the resist pattern (210) for the gate. Further, an n-type impurity is implanted using the gate pattern of the formed write transistor as a mask to form an extension region. Thereafter, an insulating film is deposited and etched back to form a sidewall. Further, n-type impurities are implanted at a high concentration to form a diffusion layer region of the read transistor. Here, Ti (titanium) is deposited on the substrate surface, and annealing is performed to reduce the resistance of the substrate surface. Thereafter, the gate electrodes are partially etched using a predetermined hole pattern (212), and the gate electrodes of the upper and lower cells are separated. At this time, the gate insulating film and the n-type polycrystalline silicon film of the writing transistor thereunder are not etched. Here, unlike the other embodiments, there is a feature that the step of processing the channel thin film does not enter before the gate insulating film of the writing transistor is deposited. Therefore, the formation of an insulating film for protecting the channel thin film can be omitted.

  In another embodiment, the protective film is damaged by the channel processing process, and thus a gate insulating film is further formed thereon. However, in this embodiment, only one deposition is required and the gate insulating film is not damaged. The film thickness can be reduced, so that the write transistor operating voltage can be lowered and the performance can be improved. Next, after depositing and planarizing an insulating film, a contact hole is opened using the resist pattern as a mask (FIG. 30A). In addition to the contact hole (215) for the drain region of the reading transistor common to two cells, the contact hole (213) for the drain region of the writing transistor common to two cells, and the contact hole (214) to the writing transistor gate / reading transistor gate In addition, contact holes to the gates and diffusion layer regions of peripheral circuits and logic circuits can be formed at the same time. The source regions (220) and (221) of the two-cell read transistors are different and wired in the X direction using diffusion layer wiring having titanium silicide on the surface. Thereafter, a metal material such as W is deposited, and the first-layer metal wiring is performed by processing the resist into a mask (FIG. 30B). A word line (216) is formed by this line, and the cell write / read transistor gate of the cell is wired in the X direction. Also, a pad (217) in which the drain of the read transistor is pulled up by this metal layer and a pad (222) in which the drain of the write transistor is pulled up are formed. Further, after depositing and planarizing an insulating film, through-holes (218) and (224) are opened using a resist as a mask, and a second metal layer is deposited and processed to perform second-layer wiring (FIG. 31). . In this layer, the read data line (219) and the write data line (223) are wired in the Y direction. Here, the normal writing transistor has a small current flow because it needs to charge and discharge with a small capacity. The write data line (223) can be made thinner than the read data line (219).

FIG. 1 is a diagram for explaining a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a diagram for explaining the method of manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a diagram illustrating a method for manufacturing a write transistor of the semiconductor device according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view illustrating a channel processing method for the write transistor according to the first embodiment of the present invention. FIG. 5 is a diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is a diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 7 is a diagram showing an array configuration of the semiconductor device according to the first embodiment of the present invention. FIG. 8 is a diagram for explaining a manufacturing process for the semiconductor device according to the second embodiment of the present invention. It is sectional drawing explaining the manufacturing process of the semiconductor memory element of Example 2 of this invention. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to Example 2 of the present invention. FIG. 11 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to Example 2 of the present invention. FIG. 12 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to Example 2 of the present invention. FIG. 13 is a top view for explaining the method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 14 is a top view for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention. FIG. 15 is a top view for explaining the manufacturing process for the semiconductor device according to Embodiment 2 of the present invention. FIG. 16 is a top view for explaining the memory cell array configuration of the semiconductor device according to the second embodiment of the present invention. FIG. 17 is a top view for explaining the memory cell array configuration of the semiconductor device according to the second embodiment of the present invention. FIG. 18 is a top view for explaining the memory cell array configuration of the semiconductor device according to the second embodiment of the present invention. FIG. 19 is an equivalent circuit diagram for explaining the memory cell array configuration of the semiconductor device according to the second embodiment of the present invention. FIG. 20 is a top view for explaining a memory cell array configuration of another embodiment of the semiconductor device according to Example 2 of the present invention. FIG. 21 is an equivalent circuit diagram for explaining a memory cell array configuration of another embodiment of the semiconductor device according to Example 2 of the present invention. FIG. 22 is a cross-sectional view showing a process for manufacturing a semiconductor device in Example 3 of the present invention. FIG. 23 is a top view for explaining the memory cell array configuration of the semiconductor device according to the third embodiment of the present invention. FIG. 24 is an equivalent circuit diagram for explaining the memory cell array configuration of the semiconductor device according to the third embodiment of the present invention. FIG. 25 is a diagram illustrating current-voltage characteristics in each storage state of the memory cell of the semiconductor device according to the fourth embodiment of the present invention. FIG. 26 is a diagram showing the configuration of the memory portion including the peripheral circuit of the semiconductor device according to the fourth embodiment of the present invention. FIG. 27 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment of the present invention. FIG. 28 is a diagram showing a basic configuration of a transistor described in the fifth embodiment of the present invention. FIG. 29 is a plan view showing the basic configuration of the transistor described in the fifth embodiment of the present invention. FIG. 30 is a top view showing a process for manufacturing a semiconductor device described in Example 6 of the present invention. FIG. 31 is a top view showing a manufacturing process of a semiconductor device described in Embodiment 6 of the present invention.

Explanation of symbols

1: source region, 2: drain region, 3: channel region, 4: insulating layer, 5: control electrode, 6: drain region, 7: source region, 8: silicon substrate, 9: insulating film, 1
0: element isolation region, M1: read transistor, M2: write transistor, 12: element isolation region, 13: resist pattern, 14: gate electrode, 15: sidewall insulating film, 16: shallow diffusion layer, 17: diffusion layer 18: Amorphous silicon film,
19: Insulating film, 20: Resist, 21: Channel of writing transistor, 23:
Resist pattern, 25: insulating film, 26: word line, 27: insulating film, 28: hole pattern, 41, 42: element isolation region, 43: semiconductor layer, 44: drain region, 4
5: Source area.

Claims (6)

A transistor comprising a gate insulating film of at least two levels of thickness;
The peripheral circuit of the semiconductor device includes a transistor having a gate insulating film that is not at least the thinnest insulating film of the gate insulating film,
A memory element portion having a field effect transistor for writing and a field effect transistor for reading on the same chip,
In the semiconductor device in which the memory element portion can read out the amount of charge taken in / out through the field effect transistor for writing by changing the threshold voltage of the field effect transistor for reading,
A semiconductor device, wherein a gate insulating film thickness of a transistor constituting the peripheral circuit is equal to a gate insulating film thickness of a reading transistor of the memory element. 2. The semiconductor device according to claim 1, wherein a channel of the writing transistor is provided on an insulating film. 3. The semiconductor memory according to claim 2, wherein a channel of the write transistor is provided at the same height as an upper end of a source or drain region of the write transistor. The film thickness of the channel of the field effect transistor for writing is
The semiconductor device according to claim 1, wherein the semiconductor device is 5 nm or less. The film thickness of the channel of the field effect transistor for writing is
The semiconductor device according to claim 2, wherein the semiconductor device is 5 nm or less. The film thickness of the channel of the field effect transistor for writing is
The semiconductor device according to claim 3, wherein the semiconductor device is 5 nm or less.

Images